Pixel driving circuit and display device

Abstract

A pixel driver circuit and display device are disclosed. In the pixel driver circuit, opposite ends of the n-th row of pixels along the column direction are a first wiring area and a second wiring area, respectively. The second wiring area is located between the n-th row of pixels and the n+1-th row of pixels. A scan line in the m+1-th row extends in a square waveform along the row direction and passes between two adjacent first sub-pixels. The portion of the scan line in the m+1-th row located in the first wiring area is located between the first sub-pixel and the m-th row of scan lines, and the portion of the scan line in the m+1-th row located in the second wiring area is located between the first sub-pixel and the m+2-th row of scan lines. This pixel driver circuit can resolve the problem of excessively large differences in scan line coupling capacitance in pixel driver circuits.

Description

Technical Field

[0001] The present application relates to the technical field of display devices, and in particular to a pixel driving circuit and a display device. Background Art

[0002] In the field of display technology, DRD (Dual Rate Driving) is an important driver technology with unique characteristics and advantages in its pixel structure. The DRD pixel structure doubles the number of gate drive stages, thereby reducing the number of source driver ICs, gate driver ICs, COFs, and PCBAs, thereby lowering costs. This driver design is currently gaining increasing adoption.

[0003] However, existing DRD panels still have shortcomings. For example, for products with a refresh rate of 60Hz, the environment in which each pixel of the DRD panel is located is different from that of 1G1D products, and the loading is also different, resulting in different pixel charging and discharging conditions. This sometimes causes the image quality of the DRD panel to be poor, such as a rough and unsophisticated picture. The main reason for this problem is that the distance between the scan lines on two adjacent rows of pixels is different, resulting in different coupling capacitance between the scan lines, which leads to different charging and discharging conditions between the pixels in the rows. Therefore, how to solve the different coupling capacitance caused by the scan line spacing becomes the key. Summary of the Invention

[0004] The purpose of the present application is to provide a pixel driving circuit and a display device to solve the problem of excessively large differences in coupling capacitance between scanning lines in the pixel driving circuit.

[0005] To achieve the purpose of this application, this application provides the following technical solutions:

[0006] In a first aspect, the present invention provides a pixel driving circuit, comprising: an n-th row pixel region, an n+1-th row pixel region, an m-th row scan line, an m+1-th row scan line, and an m+2-th row scan line; wherein the n-th row pixel region comprises a plurality of first sub-pixels sequentially spaced along a row direction; the n+1-th row pixel region comprises a plurality of second sub-pixels sequentially spaced along the row direction; the m-th row scan line and the m+1-th row scan line are connected to the first sub-pixels, and the m+2-th row scan line is connected to the second sub-pixels; wherein the n-th row pixel region is arranged along a column direction. The two opposite ends are respectively a first wiring area and a second wiring area, the second wiring area is located between the n-th row pixel area and the n+1-th row pixel area, the m+1-th row scan line extends in a square waveform along the row direction and passes between two adjacent first sub-pixels, the portion of the m+1-th row scan line located in the first wiring area is located between the first sub-pixel and the m-th row scan line, and the portion of the m+1-th row scan line located in the second wiring area is located between the first sub-pixel and the m+2-th row scan line, and n and m are both positive integers.

[0007] In one embodiment, the mth row scan line extends in a square waveform along the row direction and passes between two adjacent first sub-pixels, and the portion of the mth row scan line located in the second wiring area is located between the first sub-pixel and the m+1th row scan line.

[0008] In one embodiment, the nth row of pixel areas includes adjacent first and second sub-pixel areas, the mth row of scan lines includes a first segment and a second segment, the m+1th row of scan lines includes a third segment and a fourth segment, the first segment and the third segment are located in the first wiring area, and the second segment and the fourth segment are located in the second wiring area; along the row direction, the first segment passes through the first sub-pixel area and at least part of the second sub-pixel area, the second segment passes through the second sub-pixel area, the third segment passes through the first sub-pixel area, and the fourth segment passes through the second sub-pixel area.

[0009] In one embodiment, the number of the first sub-pixel areas and the second sub-pixel areas is multiple, and along the row direction, one second sub-pixel area is located between two adjacent first sub-pixel areas; the number of the first segments and the second segments is multiple, and along the row direction, one second segment is located between two adjacent first segments; the number of the third segments and the fourth segments is multiple, and along the row direction, one fourth segment is located between two adjacent third segments.

[0010] In one embodiment, the first sub-pixel area includes q first sub-pixels, and the second sub-pixel area includes p×q first sub-pixels, where q is an integer greater than or equal to 1, and p is an integer greater than or equal to 1. The first segment and the second segment respectively connect part of the first sub-pixels in the second sub-pixel area, the fourth segment connects another part of the first sub-pixels in the second sub-pixel area, and the third segment connects at least part of the first sub-pixels in the first sub-pixel area.

[0011] In one embodiment, q is equal to 1, p is equal to 3, the first sub-pixel area includes the i-th sub-pixel, the second sub-pixel area includes the i+1-th sub-pixel, the i+2-th sub-pixel and the i+3-th sub-pixel arranged in sequence along the row direction, the third segment connects the i-th sub-pixel, the first segment connects the i+1-th sub-pixel, the second segment connects the i+2-th sub-pixel, and the fourth segment connects the i+3-th sub-pixel, and i is a positive integer.

[0012] In one embodiment, q is equal to 6, p is equal to 3, the third segment and the m+2th row scan line connect the first sub-pixel in the first sub-pixel area, the second sub-pixel area includes the jth pixel segment, the j+1th pixel segment and the j+2th pixel segment arranged in sequence along the row direction, the first segment and the fourth segment connect the first sub-pixel in the jth pixel segment, the second segment connects part of the first sub-pixel in the j+1th pixel segment, and the fourth segment also connects part of the first sub-pixel in the j+2th pixel segment, and j is a positive integer.

[0013] In one embodiment, the pixel driving circuit further includes an m+3th row of scan lines, the m+3th row of scan lines extending along the row direction, the m+3th row of scan lines connecting the second sub-pixel; the side of the n+1th row of pixel regions facing away from the nth row of pixel regions is a third wiring area, the m+2th row of scan lines extending in a square waveform along the row direction and passing between two adjacent second sub-pixels, the portion of the m+2th row of scan lines located in the second wiring area being located between the second sub-pixel and the m+1th row of scan lines, and the portion of the m+2th row of scan lines located in the third wiring area being located between the second sub-pixel and the m+3th row of scan lines.

[0014] In one embodiment, the (m+3)th row of scan lines extends in a square waveform along the row direction and passes between two adjacent second sub-pixels. The portion of the (m+3)th row of scan lines located in the second wiring area is located between the second sub-pixel and the (m+2)th row of scan lines.

[0015] In one embodiment, the pixel driving circuit further includes an m-1th row scan line and an m+4th row scan line, the nth row pixel area and the n+1th row pixel area are both located between the m-1th row scan line and the m+4th row scan line, the m-1th row scan line and the m+4th row scan line extend in a square waveform along the row direction, the m-1th row scan line connects to the other part of the first sub-pixel in the j+1th pixel segment, and the m+4th row scan line connects to the second sub-pixel.

[0016] In one embodiment, q is equal to 6, p is equal to 6, the number of the first sub-pixel regions is two, and along the row direction, the two first sub-pixel regions are located on both sides of the second sub-pixel region.

[0017] In a second aspect, the present invention provides a display device, comprising a pixel driving circuit, a display panel, a panel frame, a power supply module and a data receiving module as described in any one of the embodiments of the first aspect; the pixel driving circuit is arranged on the display panel, the display panel is mounted on the panel frame, the power supply end of the display panel is connected to the power supply module, and the signal receiving end of the display panel is connected to the data receiving module.

[0018] The pixel driving circuit provided by the present invention sets the m+1th row of scan lines to extend along a square waveform, so that the m+1th row of scan lines protrudes toward the first wiring area. The portion of the m+1th row of scan lines in the first wiring area is close to the mth row of scan lines, thereby reducing the distance between the m+1th row of scan lines and the mth row of scan lines, thereby increasing the capacitance between the m+1th row of scan lines and the mth row of scan lines. This makes the m+1th row of scan lines more similar to the influence of the previous level of Gateline, and the charging conditions of the m+1th row of scan lines are more similar, thereby achieving the purpose of more uniform display of the DRD panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the implementation methods of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the implementation methods or the description of the prior art. Obviously, the drawings described below are only some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0020] Figure 1 is a schematic diagram of a DRD pixel structure in the prior art;

[0021] Figure 2 is a schematic diagram of a pixel driving circuit according to an embodiment;

[0022] Figure 3is a schematic diagram of a pixel driving circuit according to another embodiment;

[0023] Figure 4 yes Figure 3 A schematic diagram of the second sub-pixel region;

[0024] Figure 5 is a schematic diagram of a pixel driving circuit according to yet another embodiment.

[0025] Description of reference numerals:

[0026] Pixel area of ​​the nth row -110, first subpixel -111, first subpixel area -1101, i-th subpixel -1111, second subpixel area -1102, i+1-th subpixel -1112, i+2-th subpixel -1113, i+3-th subpixel -1114, j-th pixel segment -1102a, j+1-th pixel segment -1102b, j+2-th pixel segment -1102c, cyclic units -S1, S2, S3, S4, S5, S6, S7, S8;

[0027] Pixel area -120 in the (n+1)th row, second sub-pixel -121;

[0028] The mth scan line is G1, the first segment is G1a, and the second segment is G1b;

[0029] Scan line m+1 - G2, third segment - G2a, fourth segment - G2b;

[0030] Scan line m+2 - G3;

[0031] Scan line m+3 - G4;

[0032] Scan line m+4 - G5;

[0033] Scan line m-1 - G0;

[0034] First wiring area - 130, second wiring area - 140, third wiring area - 150;

[0035] Top row pixel area -200, display row pixel area -100, bottom row pixel area -300;

[0036] Row direction - X, first column direction - Y1, second column direction - Y2. DETAILED DESCRIPTION

[0037] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0038] It should be noted that when a component is referred to as being "fixed to" another component, it may be directly on the other component or there may be an intermediate component. When a component is referred to as being "connected to" another component, it may be directly connected to the other component or there may be an intermediate component.

[0039] Unless otherwise defined, all technical and scientific terms used in this application have the same meanings as commonly understood by those skilled in the art to which this application belongs. The terms used in this specification are for the purpose of describing specific embodiments only and are not intended to limit this application. The term "and / or" as used in this application includes any and all combinations of one or more of the relevant listed items.

[0040] The following describes some embodiments of the present application in detail with reference to the accompanying drawings. In the absence of conflict, the following embodiments and features therein may be combined with each other.

[0041] In the prior art, the DRD pixel structure has been increasingly used due to its unique characteristics and advantages. Figure 1 As shown, it specifically includes sub-pixels arranged in an array ( Figure 1 Multiple pixels are driven by multiple row scan lines and column data lines. Subpixels in the same column have the same color, and each subpixel can be turned on by one of the two row scan lines at either end. The number of data lines is half the number of column scan lines, with each data line connected to two column scan lines. When a row scan line is selected, the data line connected to it simultaneously provides signals to both subpixels. However, because the regular scan lines G1 and G2 are far apart, the capacitance C between them is G1G2 The line spacing between the conventional scanning line G3 and the conventional scanning line G2 is small, and the capacitance C between the two is small. G2G3 Large. Because the capacitor C G1G2 with C G2G3 The difference makes the regular scan line G1 (odd scan line) and the regular scan line G2 (even scan line) affected differently by the previous scan line, which ultimately leads to the poor image quality of the DRD panel, such as rough and not delicate pictures.

[0042] In view of the problems in the above-mentioned prior art embodiments, the present invention provides a pixel driving circuit, which can solve the problem of large difference in coupling capacitance of scanning lines in the pixel driving circuit by setting a wiring method of scanning lines, such as Figure 2-Figure 5 .

[0043] In one embodiment, please refer to Figure 2 The pixel driving circuit includes: an n-th row pixel area 110, an n+1-th row pixel area 120, an m-th row scan line G1, an m+1-th row scan line G2, and an m+2-th row scan line G3; wherein, the n-th row pixel area 110 includes a plurality of first sub-pixels 111 sequentially spaced along the row direction X; the n+1-th row pixel area 120 includes a plurality of second sub-pixels 121 sequentially spaced along the row direction X; the m-th row scan line G1 and the m+1-th row scan line G2 are connected to the first sub-pixels 111, and the m+2-th row scan line G3 is connected to the second sub-pixels 121; the n-th row pixel area 110 is spaced along the column direction Y The two opposite ends are respectively a first wiring area 130 and a second wiring area 140. The second wiring area 140 is located between the n-th row pixel area 110 and the n+1-th row pixel area 120. The m+1-th row scan line G2 extends in a square waveform along the row direction X and passes between two adjacent first sub-pixels 111. The portion of the m+1-th row scan line G2 located in the first wiring area 130 is located between the first sub-pixel 111 and the m-th row scan line G1. The portion of the m+1-th row scan line G2 located in the second wiring area 140 is located between the first sub-pixel 111 and the m+2-th row scan line G3. Both n and m are positive integers.

[0044] Specifically, the pixel driving circuit includes multiple rows of pixel regions, each row of pixel regions includes a plurality of independent sub-pixels; in a specific embodiment, the number of sub-pixels in each row of pixel regions is the same. Each row of pixel regions includes at least three sub-pixels of different colors, namely, red sub-pixels, green sub-pixels, and blue sub-pixels. In a specific embodiment, the red sub-pixels, green sub-pixels, and blue sub-pixels are arranged along a row direction X, and adjacent red sub-pixels, green sub-pixels, and blue sub-pixels together constitute a pixel, and each row of pixel regions includes multiple pixels.

[0045] Among them, the multiple rows of pixel areas include the n-th row pixel area 110 and the n+1-th row pixel area 120 that are adjacently arranged along the column direction Y. The side of the n-th row pixel area 110 facing away from the n+1-th row pixel area 120 is the first wiring area 130, and the second wiring area 140 is between the n-th row pixel area 110 and the n+1-th row pixel area 120. Among them, the m+1-th row scan line G2 extends along the row direction X in the second wiring area 140, and the m+1-th row scan line G2 at least partially protrudes toward the first wiring area 130, so that the m+1-th row scan line G2 forms a square waveform extension. It can be understood that the m+1-th row scan line G2 passes between two first sub-pixels 111 into the first wiring area 130, and then passes between the other two first sub-pixels 111 back to the second wiring area 140. It should be noted that, Figure 2 D1-D6 are data lines.

[0046] In a specific embodiment, the column direction Y includes a first column direction Y1 and a second column direction Y2. The first column direction Y1 is the direction from the pixel region 120 in the (n+1)th row toward the pixel region 110 in the (n+1)th row, and the second column direction Y2 is the direction from the pixel region 110 in the (n+1)th row toward the pixel region 120 in the (n+1)th row (i.e., the opposite direction of the first column direction Y1). The (m+1)th row scan line G2 protrudes along the first column direction Y1 and forms a peak segment and a valley segment. The peak segment is located between the first sub-pixel 111 and the scan line G1 in the (m+2)th row, and the valley segment is located between the first sub-pixel 111 and the scan line G3 in the (m+2)th row. The peak segment is close to the scan line G1 in the (m+1)th row, with a spacing A between them. The valley segment is close to the scan line G3 in the (m+2)th row, with a spacing B between them. The similar spacings A and B result in the coupling capacitances of the two being the same or similar.

[0047] The pixel driving circuit provided by the present invention arranges the m+1th row of scan lines G2 to extend along a square waveform, so that the m+1th row of scan lines G2 protrudes toward the first wiring area 130. The portion of the m+1th row of scan lines G2 in the first wiring area 130 is close to the mth row of scan lines G1, thereby reducing the distance between the m+1th row of scan lines G2 and the mth row of scan lines G1, thereby increasing the capacitance between the m+1th row of scan lines G2 and the mth row of scan lines G1. This allows the m+1th row of scan lines G2 to be more closely affected by the level of the previous level of scan lines, resulting in more similar charging conditions, thereby achieving a more uniform display on the DRD panel.

[0048] In one embodiment, please refer to Figure 2 The mth row scan line G1 extends in a square waveform along the row direction X and passes between two adjacent first sub-pixels 111. The portion of the mth row scan line G1 located in the second wiring area 140 is located between the first sub-pixel 111 and the (m+1)th row scan line G2.

[0049] Specifically, the m-th row of scan line G1 extends in the first wiring area 130 along the row direction X, and at least a portion of the m-th row of scan line G1 protrudes toward the second wiring area 140, thereby forming a square waveform. It can be understood that the m-th row of scan line G1 passes between two first sub-pixels 111 into the second wiring area 140, and then passes between another two first sub-pixels 111 back to the first wiring area 130.

[0050] In a specific embodiment, the m-th row scan line G1 is recessed along the second column direction Y2, forming a peak segment and a trough segment. The trough segment is located between the first sub-pixel 111 and the m+1-th row scan line G2, and the peak segment is located on the side of the m+1-th row scan line G2 (the portion located in the first arrangement line area 130) facing away from the first sub-pixel 111. The trough segment is close to the m+1-th row scan line G2, and the spacing C, A, and C between the two are similar, so that the coupling capacitances of the two are the same or similar. It should be noted that the peak segment and trough segment of the m+1-th row scan line G2, as well as the peak segment and trough segment of the m-th row scan line G1, are the shapes observed from two directions in the column direction Y, respectively, and are not observed from the same column direction Y.

[0051] By setting the m-th row scan line G1 to also extend in a square waveform along the row direction X, the distance between the m+1-th row scan line G2 and the m-th row scan line G1 is reduced, and the capacitance between the m+1-th row scan line G2 and the m-th row scan line G1 is further balanced, so that the m+1-th row scan line G2 is more closely affected by the level of the previous level scan line, and the charging condition is more similar, thereby achieving the purpose of more uniform display of the DRD panel.

[0052] In one embodiment, please refer to Figure 2 The n-th row pixel area 110 includes an adjacent first sub-pixel area 1101 and a second sub-pixel area 1102, the m-th row scan line G1 includes a first segment G1a and a second segment G1b, the m+1-th row scan line G2 includes a third segment G2a and a fourth segment G2b, the first segment G1a and the third segment G2a are located in the first wiring area 130, and the second segment G1b and the fourth segment G2b are located in the second wiring area 140; along the row direction X, the first segment G1a passes through the first sub-pixel area 1101 and at least part of the second sub-pixel area 1102, the second segment G1b passes through the second sub-pixel area 1102, the third segment G2a passes through the first sub-pixel area 1101, and the fourth segment G2b passes through the second sub-pixel area 1102.

[0053] Specifically, the mth scan line G1 includes a first segment G1a and a second segment G1b, wherein the first segment G1a is the peak segment of the mth scan line G1 in the above embodiment, and the second segment G1b is the trough segment of the mth scan line G1 in the above embodiment. The m+1th scan line G2 includes a third segment G2a and a fourth segment G2b, wherein the third segment G2a is the peak segment of the m+1th scan line G2 in the above embodiment, and the fourth segment G2b is the trough segment of the m+1th scan line G2 in the above embodiment.

[0054] In a specific embodiment, the (m+1)th scan line G2 divides the pixel region 110 in the nth row into a first sub-pixel region 1101 and a second sub-pixel region 1102, wherein along the row direction X, the first sub-pixel region 1101 is located to the left of the second sub-pixel 121. The first sub-pixel region 1101 and the second sub-pixel region 1102 each independently include at least one first sub-pixel 111. Therefore, the (m+1)th scan line G2 can be used as a standard for distinguishing the first sub-pixel region 1101 from the second sub-pixel region 1102. The first sub-pixel region 1101 corresponds to the third segment G2a (the peak segment of the (m+1)th scan line G2), and the (m)th scan line G1 forms the second segment G1b (the trough segment of the (m)th scan line G1) in the second sub-pixel region 1102.

[0055] It can be understood that, in the first sub-pixel region 1101, since the third segment G2a is closer to the first sub-pixel 111, the third segment G2a connects at least a portion of the first sub-pixels 111 in the first sub-pixel region 1101. In the second sub-pixel region 1102, the second segment G1b is closer to the first sub-pixel 111, so the second segment G1b connects at least a portion of the first sub-pixels 111 in the second sub-pixel region 1102, and further portions of the first sub-pixels 111 in the second sub-pixel region 1102 can be connected by the first segment G1a and the fourth segment G2b.

[0056] By setting the m-th row scan line G1 and the m+1-th row scan line G2 to include the first to fourth segments respectively, the two scan lines are extended in a square wave shape, and the sub-pixel area range passed by the first to fourth segments also ensures that the two scan lines will not cross-interfere when implementing the square wave extension.

[0057] In one embodiment, please refer to Figure 2 There are multiple first sub-pixel areas 1101 and multiple second sub-pixel areas 1102. Along the row direction X, one second sub-pixel area 1102 is located between two adjacent first sub-pixel areas 1101. There are multiple first segments G1a and second segments G1b. Along the row direction X, one second segment G1b is located between two adjacent first segments G1a. There are multiple third segments G2a and fourth segments G2b. Along the row direction X, one fourth segment G2b is located between two adjacent third segments G2a.

[0058] It can be understood that the m+1th row scan line G2 extends in a square waveform, so the nth row of pixels can be divided into a plurality of first sub-pixels 111 and second sub-pixel areas 1102, wherein the first sub-pixel areas 1101 and the second sub-pixel areas 1102 are arranged in an intermittent periodic manner along the row direction X. Moreover, the corresponding mth row scan line G1 also has a plurality of peaks and troughs. Therefore, the first wiring area 130 includes a plurality of first segments G1a and third segments G2a with a spacing A, and the second wiring area 140 includes a plurality of second segments G1b and fourth segments G2b with a spacing C, as well as a fourth segment G2b with a spacing B and the m+2th row scan line G3. In this way, the capacitance C between the mth row scan line G1 and the m+1th row scan line G2 is GmGm+1 =C Gm+1Gm+2 .

[0059] In one embodiment, please refer to Figure 1 The first sub-pixel area 1101 includes q first sub-pixels 111, and the second sub-pixel area 1102 includes p×q first sub-pixels 111, where q is an integer greater than or equal to 1, and p is an integer greater than or equal to 1. The first segment G1a and the second segment G1b are respectively connected to part of the first sub-pixels 111 in the second sub-pixel area 1102, the fourth segment G2b is connected to another part of the first sub-pixels 111 in the second sub-pixel area 1102, and the third segment G2a is connected to at least part of the first sub-pixels 111 in the first sub-pixel area 1101.

[0060] In the specific embodiment, please refer to Figure 2 The first sub-pixel region 1101 may include one first sub-pixel 111, i.e., q = 1, and the second sub-pixel region 1102 may include three first sub-pixels 111, i.e., p = 3. However, each peak segment of the scan line (or a valley segment for the m-th scan line G1) increases the scan line length because the scan line length passing between two first sub-pixels 111 is increased. Each increase in scan line length increases the circuit loading. Therefore, to reduce the scan line length and thus the circuit loading in the present invention, q > 1 and p > 1 can be set.

[0061] In the specific embodiment, please refer to Figure 3, the first sub-pixel area 1101 may include six first sub-pixels 111, that is, q=6, and the second sub-pixel area may include eighteen first sub-pixels 111, that is, p=3. In addition, it can be set that the first sub-pixel area 1101 may include twelve first sub-pixels 111, that is, q=12, and the second sub-pixel area may include thirty-six first sub-pixels 111, that is, p=3. In addition, it can be set that the first sub-pixel area 1101 may include eighteen first sub-pixels 111, that is, q=18, and the second sub-pixel area may include fifty-four first sub-pixels 111, that is, p=3. In addition, it can be set that the first sub-pixel area 1101 may include twenty-four first sub-pixels 111, that is, q=24, and the second sub-pixel area may include seventy-two first sub-pixels 111, that is, p=3, and so on, which will not be repeated.

[0062] By setting the first sub-pixel area 1101 to include q first sub-pixels 111 and the second sub-pixel area 1102 to include p×q first sub-pixels 111, the solution provided by the present invention is designable and the frequency of the scan line square wave extension, that is, the frequency of the peak (or trough) can be designed according to the size of the actually required pixel driving structure.

[0063] In one embodiment, please refer to Figure 2 , q is equal to 1, p is equal to 3, the first sub-pixel area 1101 includes the i-th sub-pixel 1111, the second sub-pixel area 1102 includes the i+1-th sub-pixel 1112, the i+2-th sub-pixel 1113 and the i+3-th sub-pixel 1114 arranged in sequence along the row direction X, the third segment G2a connects the i-th sub-pixel 1111, the first segment G1a connects the i+1-th sub-pixel 1112, the second segment G1b connects the i+2-th sub-pixel 1113, and the fourth segment G2b connects the i+3-th sub-pixel 1114, where i is a positive integer.

[0064] Specifically, in the first row of pixel areas, four first sub-pixels 111 correspond to one cycle of the (m+1)th row of scan line G2. Figure 2As shown, along the row direction X, from left to right, it includes a red subpixel (the i-th subpixel 1111), a green subpixel (the i+1-th subpixel 1112), a blue subpixel (the i+2-th subpixel 1113), and another red subpixel (the i+3-th subpixel 1114). The red subpixel on the left is the first subpixel region 1101, and the green subpixel, the blue subpixel, and the red subpixel on the right are the second subpixel region 1102. The third segment G2a corresponds to the red subpixel on the left, where the m+1-th scan line G2 forms a peak. To prevent the m+1-th scan line G2 from overlapping or crossing the m-th scan line G1, the second segment G1b is configured to correspond to the blue subpixel, where the m-th scan line G1 forms a valley. In addition, the green sub-pixel and the red sub-pixel on the right are both located between the m-th scan line G1 and the m+1-th scan line G2, so the two sub-pixels can be connected to the m-th scan line G1 and the m+1-th scan line G2, respectively. The first sub-pixel region 1101 and the second sub-pixel region 1102 in the next cycle also follow this connection rule.

[0065] The above embodiment illustrates that the solution provided by the present invention is applicable to an arrangement in which the period q is equal to 1 and p is equal to 3, and the capacitance between the scan line G2 of the m+1th row and the scan line G1 of the mth row is balanced, so that the scan line G2 of the m+1th row is more closely affected by the scan line of the previous level, and the charging conditions are more similar, thereby achieving a more uniform display on the DRD panel.

[0066] In one embodiment, please refer to Figure 3 and Figure 4 , q is equal to 6, p is equal to 3, the third segment G2a and the (m+2)th scan line G3 are connected to the first sub-pixel 111 in the first sub-pixel region 1101, the second sub-pixel region 1102 includes the j-th pixel segment 1102a, the j+1-th pixel segment 1102b, and the j+2-th pixel segment 1102c sequentially arranged along the row direction X, the first segment G1a and the fourth segment G2b are connected to the first sub-pixel 111 in the j-th pixel segment 1102a, the second segment G1b is connected to a portion of the first sub-pixel 111 in the j+1-th pixel segment 1102b, and the fourth segment G2b is also connected to a portion of the first sub-pixel 111 in the j+2-th pixel segment 1102c, where j is a positive integer. Figure 3 The data lines extend in the middle column direction.

[0067] Specifically, in the first row of pixel regions, twenty-four first sub-pixels 111 correspond to one cycle of the (m+1)th row of scan line G2. The first sub-pixel region 1101 includes six first sub-pixels 111, and the second sub-pixel region 1102 includes eighteen first sub-pixels 111. The second sub-pixel region 1102 can be divided into three pixel segments, namely, the j-th pixel segment 1102a, the j+1-th pixel segment 1102b, and the j+2-th pixel segment 1102c. The j-th pixel segment 1102a includes six first sub-pixels 111, the j+1-th pixel segment 1102b includes six first sub-pixels 111, and the j+2-th pixel segment 1102c includes six first sub-pixels 111. It is understandable that in order to ensure the same coupling capacitance, the j+1th pixel segment 1102b (ie, the middle pixel segment) can be mapped to the second segment G1b, that is, a valley segment is formed on the mth scan line at the position of the j+1th pixel segment 1102b.

[0068] In a specific embodiment, Figure 3 and Figure 4 As shown, along the row direction X, from left to right, red sub-pixels (i-th sub-pixel 1111), green sub-pixels (i+1-th sub-pixel 1112), and blue sub-pixels (i+2-th sub-pixel 1113) are arranged in a periodic row pattern, totaling twenty-four sub-pixels. The first six first sub-pixels 111 (two pixels) constitute a first sub-pixel region 1101 and are referred to as cyclic unit S1. The six first sub-pixels 111 following cyclic unit S1 constitute a j-th pixel segment 1102a (j is 1) and are referred to as cyclic unit S2. The six first sub-pixels 111 following cyclic unit S2 constitute a j+1-th pixel segment 1102b (j is 1) and are referred to as cyclic unit S3. The six first sub-pixels 111 following cyclic unit S3 constitute a j+2-th pixel segment 1102c (j is 1) and are referred to as cyclic unit S4. By setting q equal to 6 and p equal to 3, the routing length of the scan line can be reduced, that is, the frequency of peaks (or troughs) can be reduced, thereby reducing the loading of the circuit.

[0069] In one embodiment, please refer to Figure 3 The pixel driving circuit further includes an m+3th row scan line G4, which extends along the row direction X and is connected to the second sub-pixel 121. The side of the n+1th row pixel region 120 facing away from the nth row pixel region 110 is the third wiring area 150. The m+2th row scan line G3 extends in a square waveform along the row direction X and passes between two adjacent second sub-pixels 121. The portion of the m+2th row scan line G3 located in the second wiring area 140 is located between the second sub-pixel 121 and the m+1th row scan line G2. The portion of the m+2th row scan line G3 located in the third wiring area 150 is located between the second sub-pixel 121 and the m+3th row scan line G4.

[0070] Specifically, based on the above embodiment, the (m+2)th scan line G3 extends in a square waveform along the row direction X, and the (m+2)th scan line G3 can extend in the same manner as the (m)th scan line G1, i.e., have the same period. Furthermore, based on the above embodiment, the (m+2)th scan line G3 is further connected to the first sub-pixel 111 in the (n)th pixel region 110, and the (m+1)th scan line G2 is further connected to the second sub-pixel 121 in the (n+1)th pixel region 120.

[0071] In the specific embodiment, please refer to Figure 3 , when q is equal to 6 and p is equal to 3, based on the above embodiment, the three first sub-pixels 111 in the cyclic unit S1 can be connected to the m+1th row scan line G2, and the other three first sub-pixels 111 can be connected to the m+2th row scan line G3. Specifically, in the cyclic unit S1, the red sub-pixel and the blue sub-pixel in the first pixel are connected to the m+1th row scan line G2, and the green sub-pixel in the first pixel is connected to the m+2th row scan line G3; the red sub-pixel and the blue sub-pixel in the second pixel are connected to the m+2th row scan line G3, and the green sub-pixel in the first pixel is connected to the m+1th row scan line G2.

[0072] In the specific embodiment, please refer to Figure 3 , when q is equal to 6 and p is equal to 3, based on the above embodiment, the three first sub-pixels 111 in the cyclic unit S2 can be connected to the m-th row scan line G1, and the other three first sub-pixels 111 can be connected to the m+1-th row scan line G2. The three first sub-pixels 111 in the cyclic unit S4 can be connected to the m-th row scan line G1, and the other three first sub-pixels 111 can be connected to the m+1-th row scan line G2.

[0073] In the specific embodiment, please refer to Figure 3 , when q is equal to 6 and p is equal to 3, based on the above embodiment, the n+1-th row pixel region 120 can also refer to the configuration method of the n-th row pixel region 110, that is, the n+1-th row pixel region 120 is also divided into four cyclic units. The three first sub-pixels 111 in the cyclic unit S3 of the n+1-th row pixel region 120 can be connected to the m+1-th row scan line G2, and the other three first sub-pixels 111 can be connected to the m+2-th row scan line G3. Similarly, the cyclic unit S3 in the n-th row pixel region 110 can also follow this connection method.

[0074] It can be understood that the DRD pixel structure reduces costs by doubling the number of gate drive levels, thereby reducing the number of source driver ICs, gate driver ICs, COFs, and PCBAs. The above design method also conforms to the scan line connection method of the DRD pixel structure, that is, in the pixel area of ​​the xth row, the first type of sub-pixel is connected to the row scan line of the 2x-1th row, and the second type of sub-pixel is connected to the row scan line of the 2xth row. The first type of sub-pixel is a sub-pixel in either the odd-bit pixel sub-area or the even-bit pixel sub-area, and the second type of sub-pixel is a sub-pixel in the other pixel sub-area.

[0075] In one embodiment, please refer to Figure 3 The (m+3)th scan line G4 extends in a square waveform along the row direction X and passes between two adjacent second sub-pixels 121. The portion of the (m+3)th scan line G4 located in the second wiring area 140 is located between the second sub-pixel 121 and the (m+2)th scan line G3.

[0076] Specifically, based on the above embodiment, the (m+3)th scan line G4 extends in a square waveform along the row direction X. The (m+3)th scan line G4 can extend in the same manner as the (m+1)th scan line G2, i.e., have the same period. Furthermore, the connection between the (m+3)th scan line G4 and the second sub-pixels 121 in the second row of pixel regions can be similar to that of the (m+1)th scan line G2 in the above embodiment, and will not be further described here.

[0077] In one embodiment, please refer to Figure 3 The pixel driving circuit further includes an m-1th scan line G0 and an m+4th scan line G5. The nth pixel area 110 and the n+1th pixel area 120 are both located between the m-1th scan line G0 and the m+4th scan line G5. The m-1th scan line G0 and the m+4th scan line G5 extend in a square waveform along the row direction X. The m-1th scan line G0 is connected to the other part of the first sub-pixel 111 in the j+1th pixel segment 1102b, and the m+4th scan line G5 is connected to the second sub-pixel 121.

[0078] Specifically, the multiple rows of pixel areas may include a top row pixel area 200 (top Dummy pixel row), a display row pixel area 100, and a bottom row pixel area 300 (bottom Dummy pixel row), wherein the display row pixel area 100 is a valid display pixel area, the top row pixel area 200 and the bottom row pixel area 300 are located on both sides of the display row pixel area 100, and the top row pixel area 200 and the bottom row pixel area 300 may not provide a display function. Therefore, in order to ensure that all sub-pixels in the pixel driving circuit can be driven normally, a scan line may be set at the top row pixel area 200 to connect the sub-pixels of the next row of display row pixel area 100, and a scan line may be set at the bottom row pixel area 300 to connect the sub-pixels of the previous display row pixel area 100.

[0079] In the specific embodiment, please refer to Figure 3 There are two display row pixel regions 100, namely the nth row pixel region 110 and the n+1th row pixel region 120. The n-1th row pixel region is the top row pixel region 200, and the n+2th row pixel region is the bottom row pixel region 300. The m-1th row scan line G0 extends in a square waveform along the row direction X, and is partially located in the first wiring region 130; the m+4th row scan line G5 extends in a square waveform along the row direction X, and is partially located in the third wiring region 150.

[0080] In one embodiment, please refer to Figure 5 , q equals 6, p equals 6, there are two first sub-pixel regions 1101, and along the row direction X, the two first sub-pixel regions 1101 are located on both sides of the second sub-pixel region 1102. Specifically, based on the above embodiment, the scan lines in the pixel driving circuit can be symmetrically arranged, that is, a symmetrical design or symmetrical display is achieved on the left and right sides of the display device. Figure 5 The data lines extend in the middle column direction.

[0081] In a specific embodiment, Figure 5As shown, along the row direction X, from left to right, a red sub-pixel (i-th sub-pixel 1111), a green sub-pixel (i+1-th sub-pixel 1112), and a blue sub-pixel (i+2-th sub-pixel 1113) are arranged in a periodic row pattern, totaling forty-eight sub-pixels. The first six first sub-pixels 111 (two pixels) form a first sub-pixel region 1101, designated as cyclic unit S1. The six first sub-pixels 111 following cyclic unit S1 form the j-th pixel segment 1102a (j is 1), designated as cyclic unit S2. This includes the j+5 pixel segments, i.e., cyclic units S2 through S7. To the side of the second sub-pixel region 1102 is another first sub-pixel region 1101, designated as cyclic unit S8. The first sub-pixels 111 in each cyclic unit can be connected to the scan lines in the same manner as described in the aforementioned embodiment, conforming to the scan line connection method in the DRD pixel structure.

[0082] The present application also provides a display device, including the pixel driving circuit, display panel, panel frame, power module and data receiving module provided in the above embodiment; the pixel driving circuit is arranged on the display panel, the display panel is installed on the panel frame, the power supply end of the display panel is connected to the power module, and the signal receiving end of the display panel is connected to the data receiving module.

[0083] The technical solution of the present application can be widely used in driving circuits of various display panels, such as the driving circuit of TN (Twisted Nematic) display panel, the driving circuit of IPS (In-Plane Switching) display panel, the driving circuit of VA (Vertical Alignment) display panel, and the driving circuit of MVA (Multi-Domain Vertical Alignment) display panel. Of course, it can also be the driving circuit of other types of display panels, such as the driving circuit of OLED (Organic Light-Emitting Diode) display panel, to which the above solution can be applied.

[0084] In the description of the embodiments of the present application, it should be noted that the orientation or positional relationship of terms such as "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", and "outside" are based on the orientation or positional relationship of the accompanying drawings, which is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application.

[0085] It should be noted that the limitations on the steps involved in this solution do not limit the order of the steps without affecting the implementation of the specific solution. The steps written in front can be executed first, later, or even simultaneously. As long as this solution can be implemented, it should be deemed to fall within the scope of protection of this application.

[0086] The above disclosure is only a preferred embodiment of the present application, and certainly cannot be used to limit the scope of rights of the present application. Ordinary technicians in this field can understand that all or part of the processes of the above embodiment and equivalent changes made in accordance with the claims of the present application are still within the scope covered by the present application.

Claims

1. A pixel driving circuit, characterized in that: include: The n-th row pixel area includes a plurality of first sub-pixels sequentially spaced apart along the row direction; The n+1th row of pixel areas includes a plurality of second sub-pixels sequentially spaced apart along the row direction; an m-th scan line, an m+1-th scan line, and an m+2-th scan line, wherein the m-th scan line and the m+1-th scan line are connected to the first sub-pixel, and the m+2-th scan line is connected to the second sub-pixel; The n-th row pixel region has two opposite ends along the column direction, namely a first wiring region and a second wiring region, the second wiring region is located between the n-th row pixel region and the n+1-th row pixel region, the m+1-th row scan line extends in a square waveform along the row direction and passes between two adjacent first sub-pixels, the portion of the m+1-th row scan line located in the first wiring region is located between the first sub-pixel and the m-th row scan line, and the portion of the m+1-th row scan line located in the second wiring region is located between the first sub-pixel and the m+2-th row scan line, and n and m are both positive integers; the pixel driving circuit is a DRD pixel structure, and the pixel driving circuit further includes a data line, the data line extends along the column direction, and the two first sub-pixels on both sides of the data line are connected to different scan lines.

2. The pixel driving circuit according to claim 1, wherein: The mth row of scan lines extends in a square waveform along the row direction and passes between two adjacent first sub-pixels. The portion of the mth row of scan lines located in the second wiring area is located between the first sub-pixels and the m+1th row of scan lines.

3. The pixel driving circuit according to claim 2, wherein: The n-th row of pixel areas includes adjacent first and second sub-pixel areas, the m-th row of scan lines includes a first segment and a second segment, the m+1-th row of scan lines includes a third segment and a fourth segment, the first segment and the third segment are located in the first wiring area, and the second segment and the fourth segment are located in the second wiring area; Along the row direction, the first segment passes through the first sub-pixel area and at least part of the second sub-pixel area, the second segment passes through the second sub-pixel area, the third segment passes through the first sub-pixel area, and the fourth segment passes through the second sub-pixel area.

4. The pixel driving circuit according to claim 3, wherein: There are multiple first sub-pixel areas and multiple second sub-pixel areas, and along the row direction, one second sub-pixel area is located between two adjacent first sub-pixel areas; there are multiple first segments and multiple second segments, and along the row direction, one second segment is located between two adjacent first segments; there are multiple third segments and multiple fourth segments, and along the row direction, one fourth segment is located between two adjacent third segments.

5. The pixel driving circuit according to claim 3, wherein: The first sub-pixel area includes q first sub-pixels, and the second sub-pixel area includes p×q first sub-pixels, where q is an integer greater than or equal to 1, and p is an integer greater than or equal to 1. The first segment and the second segment respectively connect part of the first sub-pixels in the second sub-pixel area, the fourth segment connects another part of the first sub-pixels in the second sub-pixel area, and the third segment connects at least part of the first sub-pixels in the first sub-pixel area.

6. The pixel driving circuit according to claim 5, wherein: The q is equal to 1, the p is equal to 3, the first sub-pixel area includes the i-th sub-pixel, the second sub-pixel area includes the i+1-th sub-pixel, the i+2-th sub-pixel and the i+3-th sub-pixel arranged in sequence along the row direction, the third segment connects the i-th sub-pixel, the first segment connects the i+1-th sub-pixel, the second segment connects the i+2-th sub-pixel, the fourth segment connects the i+3-th sub-pixel, and i is a positive integer.

7. The pixel driving circuit according to claim 5, wherein: The q is equal to 6, the p is equal to 3, the third segment and the (m+2)th row scan line connect the first sub-pixel in the first sub-pixel area, the second sub-pixel area includes the j-th pixel segment, the j+1-th pixel segment and the j+2-th pixel segment arranged in sequence along the row direction, the first segment and the fourth segment connect the first sub-pixel in the j-th pixel segment, the second segment connects part of the first sub-pixel in the j+1-th pixel segment, and the fourth segment also connects part of the first sub-pixel in the j+2-th pixel segment, and j is a positive integer.

8. The pixel driving circuit according to claim 7, wherein: The pixel driving circuit also includes an m+3th row of scan lines, which extend along the row direction and are connected to the second sub-pixel; the side of the n+1th row of pixel areas facing away from the nth row of pixel areas is a third wiring area, the m+2th row of scan lines extends in a square waveform along the row direction and passes between two adjacent second sub-pixels, a portion of the m+2th row of scan lines located in the second wiring area is located between the second sub-pixel and the m+1th row of scan lines, and a portion of the m+2th row of scan lines located in the third wiring area is located between the second sub-pixel and the m+3th row of scan lines.

9. The pixel driving circuit according to claim 8, wherein: The (m+3)th scan line extends in a square waveform along the row direction and passes between two adjacent second sub-pixels. The portion of the (m+3)th scan line located in the second wiring area is located between the second sub-pixel and the (m+2)th scan line.

10. The pixel driving circuit according to claim 7, wherein: The pixel driving circuit further includes an m-1th row of scan lines and an m+4th row of scan lines, the nth row of pixel regions and the n+1th row of pixel regions are both located between the m-1th row of scan lines and the m+4th row of scan lines, the m-1th row of scan lines and the m+4th row of scan lines extend in a square waveform along the row direction, the m-1th row of scan lines connects to another portion of the first sub-pixels in the j+1th pixel segment, and the m+4th row of scan lines connects to the second sub-pixels.

11. The pixel driving circuit according to claim 5, wherein: The q is equal to 6, the p is equal to 6, the number of the first sub-pixel regions is two, and along the row direction, the two first sub-pixel regions are located on both sides of the second sub-pixel region.

12. A display device, characterized in that: It includes a pixel driving circuit, a display panel, a panel frame, a power supply module and a data receiving module as described in any one of claims 1 to 11; the pixel driving circuit is arranged on the display panel, the display panel is mounted on the panel frame, the power supply end of the display panel is connected to the power supply module, and the signal receiving end of the display panel is connected to the data receiving module.

Images