Substrate processing method

Abstract

A method of processing a substrate in a reaction chamber is provided, and more particularly, a method of increasing a wet etch rate of a SiCN layer to reduce protrusions from the SiCN layer formed on a stepped structure is provided. The method includes simultaneously supplying a carbon-containing silicon source and nitrogen while applying power followed by post-processing wherein the wet etch rate of the SiCN layer is adjusted by the amount of nitrogen source supplied.

Description

Technical Field

[0001] The present disclosure relates to a method of processing a substrate in a reaction chamber, and more particularly, to a method of removing a protrusion from a film layer formed on a step structure. Background Art

[0002] As the line width of semiconductor device circuits continues to shrink, 3D (three-dimensional) structures are introduced into non-volatile semiconductor devices to achieve high integration. For example, by vertically stacking multiple gate structures, a highly integrated NAND semiconductor device can be realized in a limited space on a substrate. The gate electrode of each gate of a 3D NAND semiconductor device is connected to a word line via a through-hole contact hole. To this end, the 3D gate electrode is shaped in the form of a step, and each gate electrode is connected to a word line through the end of each step and a through-hole contact hole.

[0003] FIG. 1A to FIG. 1I A conventional method of forming a gate structure of a 3D NAND semiconductor device on the stepped structure 10 is shown.

[0004] exist Figure 1A In the embodiment, a stack including insulating layers 100 (100a, 100b, 100c, and 100d) and first sacrificial layers 110 (110a, 110b, 110c, and 110d) may be alternately formed and stacked. The insulating layers 100 and the first sacrificial layers 110 may be formed by CVD (chemical vapor deposition) or PECVD (plasma enhanced chemical vapor deposition). The insulating layer may include SiO2, and the first sacrificial layer may include SiN.

[0005] exist Figure 1B In the embodiment of the present invention, a step structure 10 may be formed. The step structure 10 may be formed by, for example, reactive ion etching and resist thinning to a stack. The step structure 10 may include an upper surface 120, a lower surface 160, and a side surface 140 connecting the upper surface 120 and the lower surface 160.

[0006] exist Figure 1C In the embodiment of the present invention, the second sacrificial layer 200 may be uniformly formed on the step structure 10. The second sacrificial layer 200 may include SiN. The second sacrificial layer 200 may be formed using in-situ plasma by applying power to a reaction chamber. For example, the second sacrificial layer may be formed by PEALD (Plasma Enhanced Atomic Layer Deposition). The second sacrificial layer 200 may be a contact pad for the through-hole contacts 230 (230a, 230b, 230c, and 230d), such as Figure 1G shown.

[0007] exist Figure 1DIn the embodiment of the present invention, the third sacrificial layer 210 may be uniformly formed on the second sacrificial layer 200. The third sacrificial layer 210 may include SiCN. The third sacrificial layer 210 may be formed by applying power to the reaction chamber using in-situ plasma. For example, the third sacrificial layer 210 may be formed by PEALD (Plasma Enhanced Atomic Layer Deposition).

[0008] The third sacrificial layer 210 may be a mask layer to prevent the via contact from being formed in the Figure 2 In the subsequent process shown, the contact pad (ie, the second sacrificial layer 200) is penetrated into the first sacrificial layer and another first sacrificial layer (eg, Figure 2 110b and 110c in FIG. 1 ). Therefore, the third sacrificial layer 210 may be harder than the second sacrificial layer 200. For example, the third sacrificial layer 210 may have a lower wet etching rate than the second sacrificial layer 200.

[0009] As is known to all, the SiCN layer is harder than the SiN layer. Therefore, the wet etching selectivity between the SiCN layer (ie, the third sacrificial layer) and the SiN layer (ie, the second sacrificial layer) can be maintained.

[0010] exist Figure 1E In the embodiment of the present invention, isotropic etching can be performed. For example, wet etching can be performed. As described above, in-situ plasma can be applied to form the second sacrificial layer 200 and the third sacrificial layer 210. Due to the directivity of plasma species such as ions, the layer positioned perpendicular to the ion movement direction can be densified and hardened by ion bombardment. That is, the layer formed on the upper surface and the layer formed on the lower surface of the step structure can be densified and hardened.

[0011] In contrast, layers positioned transversely to the direction of ion movement may be less densified and less hardened. That is, layers formed on the side surfaces of the stepped structure may be less densified and less hardened than layers formed on the upper and lower surfaces. Figure 1E As shown, due to wet etching selectivity during wet etching, the layers formed on the upper and lower surfaces may remain, while the layers formed on the side surfaces may be removed.

[0012] The third sacrificial layer 210 is a mask layer to protect the second sacrificial layer 200 from being penetrated by the through-hole contacts 230 (230a, 230b, 230c, and 230d). Figure 2 In other words, the third sacrificial layer 210 may be denser and harder than the second sacrificial layer 200. Therefore, during wet etching, the wet etching selectivity between the two layers may result in a protrusion at the end of the third sacrificial layer 210, such as Figure 1E As shown in A.

[0013] exist Figure 1FIn the embodiment, an interlayer insulating layer 220 may be formed on the stepped structure 10. The interlayer insulating layer 220 may include SiO2, and may be formed by CVD (Chemical Vapor Deposition) or PECVD (Plasma Enhanced Chemical Vapor Deposition).

[0014] exist Figure 1G In the embodiment, the through-hole contacts 230 (230a, 230b, 230c and 230d) can be formed from the upper surface of the interlayer insulating layer 220 through the mask layer 210 (i.e., the third sacrificial layer 210) formed on the contact pad 200 (i.e., the second sacrificial layer 200). The through-hole contacts can be formed by etching or patterning. Since the mask layer 210 is dense and hard, the through-hole contacts 230 may not penetrate into the contact pad 200.

[0015] exist Figure 1H In the embodiment, the first sacrificial layer 110 (110a, 110b, 110c, and 110d), the second sacrificial layer 200, and the third sacrificial layer 210 may be etched to form spaces 240 (240a, 240b, 240c, and 240d) therein.

[0016] exist Fig. 1I In the embodiment of the present invention, the space 240 may be filled with a conductive layer 250 (250a, 250b, 250c, 250d). Therefore, the gate channel (not shown here) may be electrically connected to the word line (not shown here) via the through-hole contact 230. The conductive layer 250 may be at least one of polysilicon, aluminum, copper, and tungsten or a mixture thereof.

[0017] However, the third sacrificial layer 210 is formed as Figure 3A The protrusion B shown (or Figure 1E The protrusion A) shown may contact an adjacent through-hole contact, such as Figure 3B As shown, this results in a short circuit between the via contacts as shown in C, and electrical failure of the semiconductor device after the via contacts 230 are filled with the conductive layer 250 . Summary of the invention

[0018] The present disclosure relates to a method of processing a substrate in a reaction chamber, and more particularly, to a method of increasing a wet etching rate of a SiCN mask layer to reduce a protrusion from the SiCN mask layer formed on a step structure.

[0019] In one or more embodiments, a method for processing a substrate in a reaction chamber includes providing a substrate into a reaction chamber, forming a stack including an insulating layer and a first sacrificial layer on the substrate, wherein the insulating layer may include a SiO2 layer, the first sacrificial layer may include a SiN layer, forming a step structure on the stack, wherein the step structure includes an upper surface, a lower surface, and a side surface connecting the upper surface and the lower surface, forming a second sacrificial layer on the step structure, forming a third sacrificial layer on the second sacrificial layer, and wet etching the second sacrificial layer and the third sacrificial layer, wherein the second sacrificial layer may be a SiN layer, and the third sacrificial layer may be a SiCN layer, wherein the second sacrificial layer and the third sacrificial layer may be removed from the side surfaces of the step structure after wet etching and remain on the upper and lower surfaces of the step structure, wherein the wet etching rate of the third sacrificial layer may be adjusted by supplying a nitrogen source during the formation of the third sacrificial layer.

[0020] In one or more embodiments, the second sacrificial layer may be formed by repeating a cycle including supplying a first silicon source to the substrate, supplying a nitrogen source to the substrate as a reactant, and applying a first power to the reaction chamber to activate the nitrogen source, thereby forming a SiN layer on the substrate, wherein the first silicon source may include a carbon-free component.

[0021] In one or more embodiments, the first silicon source may include at least one of: TSA, (SiH3)3N; DSO, (SiH3)2; SiCl4; HCD, Si2Cl6; Si3H8; DCS, SiH2Cl2; SiHI3; SiH2I2 or a mixture thereof.

[0022] In one or more embodiments, the nitrogen source may include at least one of: N2, NH3, NH4, N2H2, N2H4 or a mixture thereof.

[0023] In one or more embodiments, the third sacrificial layer may be formed by repeating a cycle including simultaneously supplying a second silicon source and a nitrogen source to the substrate to form a SiCN layer and adjusting its wet etching rate, while applying a second power to the reaction chamber, and performing post-processing by applying a third power to the reaction chamber, wherein the second silicon source may include a carbon component.

[0024] In one or more embodiments, the second silicon source may include at least one of aminosilane, alkoxysilane, alkylsilane, or a mixture thereof.

[0025] In one or more embodiments, during the wet etching, protrusions may be reduced from corners of the step structure where the upper surface and the side surface meet.

[0026] In one or more embodiments, the wet etching rate of the third sacrificial layer may increase as the flow rate of the nitrogen source increases.

[0027] In one or more embodiments, the nitrogen source supplied to form the third sacrificial layer may be between about 100 sccm and about 20,000 sccm, and more specifically, between about 1,000 sccm and about 5,000 sccm.

[0028] In one or more embodiments, a wet etch rate ratio of the third sacrificial layer to the second sacrificial layer may be between about 1:2 and about 1:300, and more specifically, between about 1:10 and about 1:100.

[0029] In one or more embodiments, the wet etching rate of the second sacrificial layer may be about / second and approx. / second, more specifically, between about / second and approx. / second.

[0030] In one or more embodiments, the wet etching rate of the third sacrificial layer may be about / second and approx. / second, more specifically, between about / second and approx. / second.

[0031] In one or more embodiments, the method of processing a substrate in a reaction chamber may also include forming an interlayer insulating layer on the stepped structure, forming a through-hole contact through the interlayer insulating layer to a third sacrificial layer, etching the first sacrificial layer, the second sacrificial layer, and the third sacrificial layer, and filling the space formed by the etching and the through-hole contact with a conductive layer, wherein the conductive layer filling the space is connected to a word line. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] FIG. 1A to FIG. 1I A conventional method of forming a gate structure of a 3D NAND semiconductor device on a stepped structure is shown.

[0033] Figure 2 A through-hole contact is shown penetrating a contact pad (ie, a second sacrificial layer) into a first sacrificial layer and another first sacrificial layer through an insulating layer.

[0034] Figure 3A A protrusion formed on the third sacrificial layer is shown.

[0035] Figure 3B A via contact is shown contacting an adjacent via contact, resulting in a short circuit in the gate structure.

[0036] Figure 4 A substrate processing method according to an embodiment of the present disclosure is shown.

[0037] Figure 5AShown are protrusions formed when a SiCN layer is formed by a PEALD method and then etched according to a conventional method.

[0038] Figure 5B Shown is a protrusion formed when a SiCN layer is formed by a pulsed PECVD method and then etched according to an embodiment of the present disclosure.

[0039] Fig. 6A A method for forming the second sacrificial layer is shown.

[0040] Figure 6B Shows Fig. 6A Timing diagram of .

[0041] Fig. 7A A method for forming the third sacrificial layer is shown.

[0042] Figure 7B Shows Fig. 7A Timing diagram of .

[0043] Figure 8 The growth rates of SiCN layers formed by conventional PEALD method and pulsed PECVD method are shown.

[0044] Fig. 9A The relationship between the carbon content and the wet etching rate of the SiCN layer prepared by the PEALD method and the SiN layer prepared by the PEALD method is shown.

[0045] Fig. 9B The relationship between the carbon content and the wet etching rate of the SiCN layer prepared by the pulsed PECVD method according to an embodiment of the present disclosure and the SiN layer prepared by the PEALD method is shown. DETAILED DESCRIPTION

[0046] Although certain embodiments and examples are disclosed below, it will be appreciated by those skilled in the art that the invention extends beyond the specifically disclosed embodiments and / or uses of the invention and their obvious modifications and equivalents. Therefore, it is intended that the scope of the disclosed invention should not be limited by the specifically disclosed embodiments described below.

[0047] As used herein, the term "substrate" may refer to any one or more underlying materials, including any one or more underlying materials that may be modified or on which a device, circuit, or film may be formed. A "substrate" may be continuous or non-continuous; rigid or flexible; solid or porous; and combinations thereof. A substrate may be in any form, such as a powder, a plate, or a workpiece. A plate-like substrate may include wafers of various shapes and sizes. A substrate may be made of semiconductor materials, including, for example, silicon, silicon germanium, silicon oxide, gallium arsenide, gallium nitride, and silicon carbide.

[0048] The continuous substrate may extend beyond the boundaries of the processing chamber in which the deposition process occurs. In some processes, the continuous substrate may be moved through the processing chamber so that the process continues until the end of the substrate is reached. The continuous substrate may be provided from a continuous substrate feed system to allow the continuous substrate to be manufactured and output in any suitable form.

[0049] The illustrations presented herein are not meant to be actual views of any particular material, structure, or device but are merely idealized representations used to describe embodiments of the present disclosure.

[0050] The specific embodiments shown and described are illustrations of the present invention and its best mode and are not intended to limit the scope of these aspects and embodiments in any way. In fact, for the sake of brevity, the traditional manufacturing, connection, preparation and other functional aspects of the system may not be described in detail. In addition, the connecting lines shown in the various figures are intended to represent exemplary functional relationships and / or physical connections between various elements. Many alternative or additional functional relationships or physical connections may exist in actual systems, and / or may not exist in some embodiments.

[0051] It should be understood that the configuration and / or method described herein are exemplary in nature, and these specific embodiments or examples should not be considered restrictive, because many variations are possible. The specific routine or method described herein can represent one or more of any number of processing strategies. Therefore, the various actions shown can be performed in the order shown, in other orders, or omitted in some cases.

[0052] The subject matter of the present disclosure includes all novel and nonobvious combinations and subcombinations of the various processes, systems and configurations, and other features, functions, acts and / or properties disclosed herein, and any and all equivalents thereof.

[0053] Figure 4 A substrate processing method according to an embodiment of the present disclosure is shown.

[0054] In step 400, a substrate is provided into a reaction chamber. The substrate may include complex structures, such as recesses and 3D gate structures, etc. The reaction chamber may be provided with a gas supply unit (e.g., a shower head) and a substrate support unit (e.g., a heating block on which a pedestal is mounted (not shown here)). The substrate support unit may be arranged opposite to the gas supply unit, facing the gas supply unit. A power generator and a matching network may also be provided and connected to at least one of the gas supply unit and the substrate support unit. Therefore, in order to form a film layer on the substrate, an in-situ plasma process may be performed in the reaction chamber.

[0055] In step 410, if Figure 1AAs shown, a stack may be formed on a substrate. In the stack, an insulating layer and a first sacrificial layer may be alternately formed. The insulating layer may include a SiO2 layer, and the first sacrificial layer may include a SiN layer. The stack may be formed by CVD or PECVD. In a subsequent subsequent process, the first sacrificial layer may be etched away, and the space in which the first sacrificial layer is formed may be filled with a conductive layer, such as Figure 1H and Fig. 1I shown.

[0056] In step 420, a stepped structure may be formed on the stack, such as Figure 1B As shown. The step structure 10 can be formed by, for example, reactive ion etching and resist thinning to a stack. The step structure may include an upper surface 120 , a lower surface 160 , and a side surface 140 connecting the upper surface 120 and the lower surface 160 .

[0057] In step 430, a second sacrificial layer may be formed on the stepped structure, such as Figure 1C As shown. The second sacrificial layer 200 may include a SiN layer. The second sacrificial layer 200 may be formed by applying power to the reaction chamber using in-situ plasma. For example, the second sacrificial layer may be conformally formed on the stepped structure by PEALD (plasma enhanced atomic layer deposition). Figure 1G As shown, the second sacrificial layer 200 may be a contact pad for via contacts 230 ( 230 a , 230 b , 230 c , and 230 d ) later.

[0058] In one embodiment of the present disclosure, the second sacrificial layer can be formed by alternately and sequentially supplying a first silicon source and a nitrogen source activated by power, wherein the first silicon source can include a carbon-free component. Since the first silicon source includes a carbon-free component, the SiN layer (i.e., the second sacrificial layer) can include a carbon-free component.

[0059] The first silicon source may include at least one of: TSA, (SiH3)3N; DSO, (SiH3)2; SiCl4; HCD, Si2Cl6; Si3H8; DCS, SiH2Cl2; SiHI3; SiH2I2 or a mixture thereof.

[0060] The nitrogen source for forming the second sacrificial layer may include at least one of: N2, NH3, NH4, N2H2, N2H4 or a mixture thereof.

[0061] In step 440, a third sacrificial layer may be formed on the sacrificial layer, such as Figure 1D As shown. The third sacrificial layer 210 may include SiCN. The third sacrificial layer 210 may be formed using in-situ plasma by applying power to the reaction chamber. In an embodiment of the present disclosure, the third sacrificial layer 210 may be formed by pulsed PECVD (pulsed plasma enhanced chemical vapor deposition).

[0062] In an embodiment of the present disclosure, the third sacrificial layer 210 may be formed by simultaneously supplying a second silicon source and a nitrogen source while applying power, wherein the second silicon source may include a carbon component to form a SiCN layer when reacting with the nitrogen source.

[0063] The second silicon source may include at least one of aminosilane, alkoxysilane, alkylsilane, or a mixture thereof. More specifically, the second silicon source may include at least one of the following: DSMA, (SiH3)2NMe; DSEA, (SiH3)2NEt; DSIPA, (SiH3)2N(iPr); DSTBA, (SiH3)2N(tBu); DEAS, SiH3NEt2; DTBAS, SiH3N(tBu)2; BDEAS, SiH2(NEt2)2; BDMAS, SiH2(NMe2)2; BTBAS, SiH2(NHtBu)2; BITS, SiH2(NHSiMe3)2; DIPAS, SiH3N(iPr)2; TEOS, Si(OEt)4; 3DMAS, SiH(N(Me)2)3; BEMAS, SiH2[N(Et)(Me)]2; AHEAD, Si2(NHEt)6; TEAS, Si(NHEt)4; 4MS, Si(CH3)4 or a mixture thereof.

[0064] The nitrogen source for forming the third sacrificial layer may include at least one of: N2, NH3, NH4, N2H2, N2H4 or a mixture thereof.

[0065] The present disclosure finds that nitrogen supplied simultaneously with the second silicon source can adjust the wet etching rate of the SiCN layer. That is, as the flow rate of the nitrogen source increases, the wet etching rate of the SiCN layer increases. In one embodiment of the present disclosure, the nitrogen source can be supplied between about 100 sccm and about 20,000 sccm, more specifically, between about 1,000 sccm and about 5,000 sccm.

[0066] It is speculated that nitrogen can replace the carbon component of the SiCN layer and reduce its carbon content, thereby reducing the difference in wet etching rate between the SiN layer (i.e., the second sacrificial layer) and the SiCN layer (i.e., the third sacrificial layer). Therefore, as the nitrogen source flow rate increases, the wet etching rate of the SiCN layer increases.

[0067] The increase in the wet etching rate of the SiCN layer may result in a low wet etching selectivity between the SiCN layer (ie, the third sacrificial layer) and the SiN layer (ie, the second sacrificial layer). Therefore, the overhang may be reduced accordingly during the subsequent wet etching.

[0068] Optionally, after forming the SiCN layer, a post-processing may be further performed. The post-processing may be performed by supplying power to the reaction chamber and activating the process gas. In one embodiment of the present disclosure, an activated nitrogen source may be supplied as the process gas to further reduce the carbon content and control the density of the SiCN layer.

[0069] The SiN layer (second sacrificial layer) and the SiCN layer (third sacrificial layer) may be wet-etched in step 450. The wet-etching may be performed by immersing the substrate in a wet etching solution (eg, 1:100 dHF (diluted hydrogen fluoride)).

[0070] like Figure 1E As shown, the SiN / SiCN stack can be removed from the side surface of the step and remain on the upper and lower surfaces of the step. These two layers are formed by in-situ plasma. Compared with the layers on the side surfaces, the layers on the upper and lower surfaces can be dense and hard by ion bombardment. Therefore, it is faster to remove these layers from the side surfaces than from the upper and lower surfaces.

[0071] In step 460, an insulating layer may be formed on the Figure 1F The insulating layer 220 may include SiO2 and may be formed by CVD (chemical vapor deposition) or PECVD (plasma enhanced chemical vapor deposition).

[0072] In step 470, the Figure 1G The through-hole contacts 230 (230a, 230b, 230c, 230d) can be formed by etching or patterning through the SiCN layer (third sacrificial layer) from the upper surface of the interlayer insulating layer. The SiCN layer can prevent the through-hole contacts 230 from over-etching the contact pads (SiN, the second sacrificial layer) and can be formed as shown in FIG. Figure 2 The lower step is shown penetrating into the insulating layer 100 and the first sacrificial layer 110 .

[0073] In step 480, the Figure 1H The etching shown includes sacrificial layers of the first sacrificial layer 100, the second sacrificial layer 200, and the third sacrificial layer 210. Therefore, a space 240 (240a, 240b, 240c, 240d) can be formed from a gate channel (not shown here) to a through-hole contact to a word line (not shown here) of a 3D NAND gate structure.

[0074] In step 490, the space between the etched sacrificial layer and the via contact may be filled with a conductive layer 250 (250a, 250b, 250c, 250d), such as Fig. 1IAs shown. Therefore, the gate channel can be electrically connected to the word line via the via contact 230. The conductive layer 250 can be at least one of the following: polysilicon, aluminum, copper, tungsten, or a mixture thereof.

[0075] Figure 5A Shows the protrusions formed when the SiCN layer 210 is formed by the PEALD method and then etched according to a conventional method.

[0076] Figure 5B Shows the protrusions formed when the SiCN layer 210 is formed by the pulsed PECVD method and then etched according to an embodiment of the present disclosure.

[0077] Compare Figure 5A and Figure 5B , the protrusion O' formed on the SiCN layer 210 in Figure 5B is less protruding than the protrusion O formed on the SiCN layer 210 in Figure 5A (d' < d). Therefore, the technical advantage provided by the present disclosure is that the contact between the protrusion and the via contact as shown in Figure 3A and the short circuit between the via contacts as shown in Figure 3B can be prevented.

[0078] Fig. 6A Shows a method for forming the second sacrificial layer, i.e., the SiN layer, corresponding to Figure 4 step 430.

[0079] In step 600, a first silicon source can be supplied to the substrate provided to the reaction chamber. The first silicon source can contain a carbon-free component. For example, the first silicon source can include at least one of the following: TSA, (SiH3)3N; DSO, (SiH3)2; SiCl4; HCD, Si2Cl6; Si3H8; DCS, SiH2Cl2; SiHI3; SiH2I2, or a mixture thereof.

[0080] In step 610, a nitrogen source can be supplied. The nitrogen source can include at least one of the following: N2, NH3, NH4, N2H2, N2H4, or a mixture thereof.

[0081] In step 620, a first power can be applied to the reaction chamber to activate the nitrogen source and generate nitrogen plasma. The first silicon source and the activated nitrogen source can react to form a SiN layer on the substrate.

[0082] The first power may include a high frequency RF power (HRF). Optionally, the first power may also include a low frequency RF power (LRF), i.e., a dual frequency RF power. For high frequency, at an RF frequency between about 10 MHz and about 100 MHz, the HRF may be between about 30 W and about 1200 W, more specifically between about 50 W and about 250 W. At an RF frequency between about 10 kHz and about 250 kHz, the LRF may be between about 30 W and about 1200 W, more specifically between about 50 W and about 250 W.

[0083] Steps 610 and 620 may be performed simultaneously or sequentially. Steps 600 to 620 may be repeated multiple times until the target thickness is reached.

[0084] Figure 6B Shows Fig. 6A Timing diagram of Figure 6B In the embodiment, a purge gas such as an inert gas (i.e., Ar, He) can be continuously supplied throughout the entire cycle from T1 to T4. Steps T1 to T4 can be repeated multiple times (M times). Alternatively, a nitrogen source can be continuously supplied throughout the entire cycle from T1 to T4. Figure 6B In the embodiment, LRF may be further applied optionally.

[0085] Fig. 7A A method for forming a third sacrificial layer, namely a SiCN layer, is shown, corresponding to Figure 4 Step 440

[0086] In step 700, while applying a second power to the reaction chamber, a second silicon source and a nitrogen source may be simultaneously supplied to a substrate provided to the reaction chamber. The second silicon source may include a carbon component. For example, the second silicon source may include at least one of aminosilane, alkoxysilane, alkylsilane, or a mixture thereof. More specifically, the second silicon source may include at least one of the following: DSMA, (SiH3)2NMe; DSEA, (SiH3)2NEt; DSIPA, (SiH3)2N(iPr); DSTBA, (SiH3)2N(tBu); DEAS, SiH3NEt2; DTBAS, SiH3N(tBu)2; BDEAS, SiH2(NEt2)2; BDMAS, SiH2(NMe2)2; BTBAS, SiH2(NHtBu)2; BITS, SiH2(NHSiMe3)2; DIPAS, SiH3N(iPr)2; TEOS, Si(OEt)4; 3DMAS, SiH(N(Me)2)3; BEMAS, SiH2[N(Et)(Me)]2; AHEAD, Si2(NHEt)6; TEAS, Si(NHEt)4; 4MS, Si(CH3)4 or a mixture thereof.

[0087] The nitrogen source supplied in step 700 may include at least one of N2, NH3, NH4, N2H2, N2H4 or a mixture thereof. The nitrogen source may be supplied between about 100 sccm and about 20,000 sccm, more specifically, between about 1,000 sccm and about 5,000 sccm.

[0088] The second power applied in step 700 may include a high frequency RF power (HRF). Optionally, the second power may also include a low frequency RF power (LRF), i.e., a dual frequency RF power. For high frequency, at an RF frequency between about 10 MHz and about 100 MHz, the HRF may be between about 30 W and about 1200 W, more specifically between about 50 W and about 300 W. At an RF frequency between about 10 kHz and about 500 kHz, the LRF may be between about 30 W and about 1200 W, more specifically between about 50 W and about 300 W.

[0089] In step 710, post-processing may be performed. In an embodiment of the present disclosure, the post-processing may be performed by applying a third power to the reaction chamber while supplying a process gas. In an embodiment of the present disclosure, an activated nitrogen source may be supplied as the process gas.

[0090] The third power applied in step 710 may include high frequency RF power (HRF). Optionally, the third power may also include low frequency RF power (LRF), that is, dual frequency RF power. The third power may be the same as the second power, or greater than the second power.

[0091] For high frequencies, at RF frequencies between about 10 MHz and about 100 MHz, the HRF may be between about 30 W and about 1200 W, more specifically between about 50 W and about 500 W. At RF frequencies between about 10 kHz and about 500 kHz, the LRF may be between about 30 W and about 1200 W, more specifically between about 50 W and about 500 W.

[0092] Figure 7B Shows Fig. 7A Timing diagram of Figure 7B In the embodiment, a purge gas such as an inert gas (i.e., Ar, He) may be continuously supplied throughout the entire cycle from T1 to T4. Steps T1 to T4 may be repeated multiple times (N times). Alternatively, nitrogen may be supplied throughout the entire cycle from T1 to T4. Figure 7B In , LRF can be further applied optionally. Figure 7B In the embodiment, the SiCN layer can be formed at T1 and then post-processed at T3.

[0093] Figure 8The growth rate of SiCN layer formed by conventional PEALD method and pulsed PECVD method is shown. Figure 8 Compared to the conventional PEALD method shown, the pulsed PECVD method according to the present disclosure may have another advantage of a high growth rate of the SiCN layer. Therefore, the substrate processing speed (eg, throughput) may be increased.

[0094] Fig. 9A The relationship between the carbon content and the wet etching rate of the SiCN layer (ie, the third sacrificial layer) prepared by the PEALD method and the SiN layer (ie, the second sacrificial layer) prepared by the PEALD method is shown.

[0095] exist Fig. 9A The SiCN layer contains about 48% carbon and its wet etching rate is about / sec. In contrast, the SiN layer contains about 0% carbon and its wet etching rate is about / sec. Therefore, wide wet etching selectivity (i.e. / second / sec) may result in protrusions on the SiCN layer after wet etching.

[0096] Fig. 9B The relationship between the carbon content and the wet etching rate of the SiCN layer (ie, the third sacrificial layer) prepared by the pulsed PEALD method according to an embodiment of the present disclosure and the SiN layer (ie, the second sacrificial layer) prepared by the PEALD method is shown.

[0097] exist Fig. 9B In FIG. 5 , as the nitrogen flow rate increases from 0 sccm to 20000 sccm, the carbon content of the SiCN layer decreases from 40% to 3.5%, and the wet etching rate of the SiCN layer decreases from / second increases to / sec. and the wet etching rate is Compared with the wet etching rate of the SiN layer, the wet etching rate of the SiCN layer increases to / sec, which is almost 50% of the wet etching rate of the SiN layer.

[0098] therefore, Fig. 9A and Fig. 9B It is shown that, compared with the conventional PEALD method, by supplying a nitrogen source according to the pulsed PECVD method of the present disclosure, the wet etching rate of the SiCN layer (i.e., the third sacrificial layer) can be more effectively increased. In other words, the difference in wet etching selectivity between the SiCN layer and the SiN layer can be more effectively reduced. Therefore, the protrusion can be more effectively reduced from the SiCN layer, and interference with the contact of the adjacent through hole can be prevented.

[0099] In an embodiment according to the present disclosure, a wet etching ratio of the SiCN layer, i.e., the third sacrificial layer, to the SiN layer, i.e., the second sacrificial layer may be between about 1:2 and about 1:300, more specifically between about 1:10 and 1:100, so as to reduce the protrusion and the interference between the protrusion and the adjacent through-hole contact.

[0100] In an embodiment according to the present disclosure, the wet etching rate of SiN, i.e., the second sacrificial layer, can be about / second and approx. / second, more specifically about / second and approx. / second. The wet etching rate of SiCN, i.e., the third sacrificial layer, can be about / second and approx. / second, more specifically about / second and approx. / second.

[0101] Table 1 is the test conditions for forming a SiN layer, ie, the second sacrificial layer, and Table 2 is the test conditions for forming a SiCN layer, ie, the third sacrificial layer, followed by post-processing according to an embodiment of the present disclosure.

[0102] Table 1 - Test conditions for forming a SiN layer according to an embodiment of the present disclosure

[0103]

[0104] Table 2 - Test conditions for forming SiCN layers followed by post-processing according to embodiments of the present disclosure

[0105]

[0106]

Claims

1. A method for processing a substrate in a reaction chamber, comprising: providing a substrate into a reaction chamber; forming a stack including an insulating layer and a first sacrificial layer on a substrate, forming a step structure on the stack, wherein the step structure includes an upper surface, a lower surface, and a side surface connecting the upper surface and the lower surface; forming a second sacrificial layer on the stepped structure; forming a third sacrificial layer on the second sacrificial layer; as well as performing wet etching to remove the second sacrificial layer and the third sacrificial layer from the side surfaces and remain on the upper and lower surfaces, wherein the wet etching rate of the third sacrificial layer is adjusted by supplying a nitrogen source during the formation of the third sacrificial layer, The insulating layer is a SiO2 layer, and the first sacrificial layer is a SiN layer.

2. The method according to claim 1, wherein: The second sacrificial layer is a SiN layer formed by repeating a cycle, the cycle comprising: supplying a first silicon source to the substrate; supplying the nitrogen source as a reactant to the substrate; and applying a first power to the reaction chamber to activate a nitrogen source, The first silicon source includes a carbon-free component.

3. The method according to claim 2, wherein: The first silicon source includes at least one of the following: TSA, (SiH3)3N; DSO, (SiH3)2; SiCl4; HCD, Si2Cl6; Si3H8; DCS, SiH2Cl2; SiHI3; SiH2I2 or a mixture thereof.

4. The method according to claim 2, wherein: The nitrogen source includes at least one of the following: N2, NH3, NH4, N2H2, N2H4 or a mixture thereof.

5. The method according to claim 2, wherein: The first power is a high frequency power between about 30W and about 1200W.

6. The method according to claim 1, wherein: The third sacrificial layer is a SiCN layer formed by repeating a cycle, wherein the cycle comprises: When a second power is applied to the reaction chamber, a second silicon source and the nitrogen source are simultaneously supplied to the substrate to form a SiCN layer, wherein the second silicon source includes a carbon component, and the wet etching rate of the SiCN layer is adjusted by reducing the carbon component by supplying a nitrogen source; and performing post-processing by applying a third power to the reaction chamber, Therein, a nitrogen source is further supplied during post-treatment.

7. The method according to claim 6, wherein: During the formation of the SiCN layer, the nitrogen source is supplied at between about 100 sccm and about 20,000 sccm.

8. The method according to claim 6, wherein: Protrusions are reduced from the stepped structure.

9. The method according to claim 6, wherein: The second silicon source includes at least one of aminosilane, alkoxysilane, alkylsilane or a mixture thereof.

10. The method according to claim 9, wherein: The second silicon source includes at least one of the following: DSMA, (SiH3)2NMe; DSEA, (SiH3)2NEt; DSIPA, (SiH3)2N(iPr); DSTBA, (SiH3)2N(tBu); DEAS, SiH3NEt2; DTBAS, SiH3N(tBu)2; BDEAS, SiH2(NEt2)2; BDMAS, SiH2(NMe2)2; BTBAS, SiH2(NHtBu)2; BITS, SiH2(NHSiMe3)2; DIPAS, SiH3N(iPr)2; TEOS, Si(OEt)4; 3DMAS, SiH(N(Me)2)3; BEMAS, SiH2[N(Et)(Me)]2; AHEAD, Si2(NHEt)6; TEAS, Si(NHEt)4; 4MS, Si(CH3)4 or a mixture thereof.

11. The method according to claim 6, wherein: The nitrogen source includes at least one of the following: N2, NH3, NH4, N2H2, N2H4 or a mixture thereof.

12. The method according to claim 6, wherein: The second power is between about 30W and about 1200W.

13. The method according to claim 6, wherein: The third power is between about 30W and about 1200W.

14. The method according to claim 6, wherein: The second power and the third power include high-frequency power and low-frequency power.

15. The method according to claim 1, wherein: A wet etching rate ratio of the third sacrificial layer to the second sacrificial layer is between about 1:2 and about 1:

300.

16. The method according to claim 15, wherein: A wet etching rate ratio of the third sacrificial layer to the second sacrificial layer is between about 1:10 and about 1:

100.

17. The method according to claim 1, wherein: The wet etching rate of the second sacrificial layer is about / second and approx. / second.

18. The method according to claim 1, wherein: The wet etching rate of the third sacrificial layer is about / second and / second. 19 . The method of claim 1 , further comprising continuously supplying an inert gas to purge the reaction chamber while forming the second sacrificial layer and the third sacrificial layer.

20. The method of claim 1, further comprising: forming an interlayer insulating layer on the stepped structure; forming a through-hole contact through the interlayer insulating layer to the third sacrificial layer; etching the first sacrificial layer, the second sacrificial layer and the third sacrificial layer; as well as Fill the spaces created by etching and via contacts with a conductive layer, The conductive layer includes at least one of the following: polysilicon, aluminum, copper and tungsten or a mixture thereof.

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