Wafer and packaging method

Abstract

The invention discloses a wafer and a packaging method. The wafer comprises a substrate; the dielectric layer is located on the substrate, and the surface, opposite to one side of the substrate, of the dielectric layer is a bonding surface; the first bonding layer is located in the dielectric layer of the central chip area, the bonding surfaces are exposed out of the first bonding layer, and the first bonding layer is used for achieving bonding between the bonding surfaces of the wafers; and the second bonding layer is located in the dielectric layer of the edge chip area, the second bonding layer exposes the bonding surface, the second bonding layer is used for realizing bonding among the bonding surfaces of a plurality of wafers, and the size of the second bonding layer is larger than that of the first bonding layer. When a plurality of wafers are bonded to form the bonded wafer, the probability that the contact area between the second bonding layers is smaller than the contact area between the first bonding layers due to the fact that the second bonding layers of the bonded wafer are affected by alignment precision errors can be reduced, and therefore the bonding strength of the edge chip area of the bonded wafer can be guaranteed.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a wafer and a packaging method. Background Art

[0002] Three-Dimensional Integrated Circuit (3D IC) is made by using advanced chip stacking technology, which stacks chips with different functions into integrated circuits with a three-dimensional structure. Compared with two-dimensional integrated circuits, the stacking technology of three-dimensional integrated circuits can not only shorten the signal transmission path of three-dimensional integrated circuits, but also speed up the operation of three-dimensional integrated circuits, thereby meeting the needs of semiconductor devices for higher performance, smaller size, lower power consumption and more functions.

[0003] Among them, hybrid bonding is a technology that simultaneously bonds the metal electrode and dielectric insulating layer on the wafer / chip, eliminating the microbumps and further reducing the bonding interconnection pitch. Therefore, high-density integration can be achieved using hybrid bonding technology, which plays an irreplaceable role in 3D packaging.

[0004] In the packaging field, after bonding between wafers is achieved, the back side of the wafer is usually thinned and trimmed.

[0005] However, the reliability and yield of packaging between wafers still need to be improved. Summary of the invention

[0006] The problem solved by the embodiments of the present invention is to provide a wafer and a packaging method, which are beneficial to further improve the packaging reliability and packaging yield of the wafer.

[0007] To solve the above problems, an embodiment of the present invention provides a wafer, comprising a central chip area and an edge chip area surrounding the central chip area, the wafer comprising: a substrate; a dielectric layer located on the substrate, the surface of the dielectric layer facing away from the substrate being a bonding surface; a first bonding layer located in the dielectric layer of the central chip area, the first bonding layer exposing the bonding surface, the first bonding layer being used to achieve bonding between bonding surfaces of multiple wafers; a second bonding layer located in the dielectric layer of the edge chip area, the second bonding layer exposing the bonding surface, the second bonding layer being used to achieve bonding between bonding surfaces of multiple wafers, and the size of the second bonding layer being larger than the size of the first bonding layer.

[0008] Optionally, the edge chip area includes a plurality of sub-edge chip areas surrounding the central chip area in a circumferential direction; one or more second bonding layers are located in the sub-edge chip area, and when the number of second bonding layers in the sub-edge chip area is multiple, the plurality of second bonding layers are arranged in a matrix along the first direction and the second direction, and the first direction and the second direction are perpendicular to each other.

[0009] Optionally, when there are multiple second bonding layers in the sub-edge chip region, distances between adjacent second bonding layers in the first direction are the same, and distances between adjacent second bonding layers in the second direction are the same.

[0010] Optionally, a distance between adjacent second bonding layers in the first direction is 0.1 micrometer to 200 micrometers; a distance between adjacent second bonding layers in the second direction is 0.1 micrometer to 200 micrometers.

[0011] Optionally, the size of the first bonding layer is 0.1 micron to 200 microns; the size of the second bonding layer is 0.1 micron to 200 microns.

[0012] Optionally, a size of the second bonding layer is greater than a size of the first bonding layer in a range of 0.1 micrometer to 200 micrometers.

[0013] Optionally, a pitch between adjacent first bonding layers is equal to a pitch between adjacent second bonding layers.

[0014] Optionally, one or more of the first bonding layers are located in the central chip area, and when there are multiple first bonding layers in the central chip area, the multiple first bonding layers are arranged in a matrix along the first direction and the second direction, and the first direction and the second direction are perpendicular to each other.

[0015] Optionally, the wafer further includes: a first interconnect structure located in the dielectric layer, the first bonding layer and the second bonding layer located on top of the first interconnect structure, the first interconnect structure electrically connected to the first bonding layer, and the first interconnect structure electrically connected to the second bonding layer.

[0016] Optionally, the wafer further includes: an interconnection through-hole structure located in the dielectric layer between the first bonding layer and the first interconnection structure, and in the dielectric layer between the second bonding layer and the first interconnection structure.

[0017] Correspondingly, an embodiment of the present invention also provides a packaging method, including: providing multiple wafers provided by the embodiments of the present invention, the wafers including a first wafer and a second wafer; bonding the first wafer and the second wafer so that the bonding surfaces of the first wafer and the second wafer are relatively arranged, the first bonding layers of the first wafer and the second wafer are relatively arranged and bonded, and the second bonding layers of the first wafer and the second wafer are relatively arranged and bonded, the dielectric layers of the first wafer and the second wafer are relatively arranged and bonded, and the size of the second bonding layer is larger than the size of the first bonding layer.

[0018] Optionally, in the step of bonding the first wafer and the second wafer, the first bonding layers of the first wafer and the second wafer are arranged opposite to each other up and down, the second bonding layers of the first wafer and the second wafer are arranged opposite to each other up and down, and the shape, position, length and width of the first bonding layers in the first wafer and the second wafer are the same, and the shape, position, length and width of the second bonding layers in the first wafer and the second wafer are the same.

[0019] Optionally, the process of bonding the first wafer and the second wafer includes a hybrid bonding process.

[0020] Optionally, after bonding the first wafer and the second wafer, the packaging method further includes: thinning a surface of the first wafer facing away from the bonding surface; or thinning a surface of the second wafer facing away from the bonding surface.

[0021] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0022] An embodiment of the present invention provides a wafer, the wafer comprising a central chip area and an edge chip area surrounding the central chip area, a dielectric layer is located on the substrate, a surface of the dielectric layer facing away from the substrate is a bonding surface, a first bonding layer is located in the dielectric layer of the central chip area, and the first bonding layer exposes the bonding surface, the first bonding layer is used to achieve bonding between bonding surfaces of multiple wafers, a second bonding layer is located in the dielectric layer of the edge chip area, the second bonding layer exposes the bonding surface, the second bonding layer is used to achieve bonding between bonding surfaces of multiple wafers, and the size of the second bonding layer is larger than the size of the first bonding layer, accordingly, in the back When multiple wafers are bonded to form a bonded wafer, the probability that the contact area between the second bonding layers is smaller than the contact area between the first bonding layers due to the error in overlay accuracy (overlay accuracy refers to the fact that during the formation of the bonded wafer, the bonded wafer is prone to expansion after being heated, and the expansion easily causes the second bonding layer to move toward the edge of the bonded wafer) of the second bonding layer of the bonded wafer can be reduced, thereby ensuring the bonding strength of the edge chip area of ​​the bonded wafer. In the subsequent thinning process of the bonded wafer, the probability of gaps in the edge chip area of ​​the bonded wafer is reduced, thereby improving the packaging reliability and packaging yield of the wafer. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a structural schematic diagram corresponding to a packaging structure;

[0024] Figures 2 to 5 It is a structural schematic diagram of a wafer embodiment of the present invention;

[0025] Figures 6 to 9 It is a schematic structural diagram corresponding to each step in an embodiment of a packaging method of the present invention. DETAILED DESCRIPTION

[0026] At present, the packaging reliability and packaging yield of wafers still need to be improved. This paper analyzes the reasons why its performance needs to be improved in combination with a packaging structure.

[0027] Figure 1 It is a structural schematic diagram corresponding to a packaging structure.

[0028] The packaging structure includes: a bonding wafer 22, including a first wafer 20 and a second wafer 21 arranged opposite to and bonded thereto, wherein the first wafer 20 and the second wafer 21 both include a central chip area 20A and an edge chip area 20B surrounding the central chip area 20A; a first bonding layer 28, located in the central chip area 20A of the first wafer 20 and the second wafer 21, and the first bonding layers 28 of the first wafer 20 and the second wafer 21 are arranged opposite to and bonded; a second bonding layer 27, located in the edge chip area 20B of the first wafer 20 and the second wafer 21, and the second bonding layers 27 of the first wafer 20 and the second wafer 21 are arranged opposite to and bonded.

[0029] Research has found that during the formation process of the bonded wafer 22, the bonded wafer 22 is prone to expand after being heated, and the expansion easily causes the second bonding layer 27 to move toward the edge of the bonded wafer 22, thereby causing the contact area between the second wafer 21 in the edge chip area 20B of the bonded wafer 22 to become smaller, resulting in insufficient bonding strength between the edge chip areas 20B of the bonded wafer 22. Accordingly, in the subsequent thinning process of the bonded wafer 22, the probability of gaps appearing in the edge chip area 20B of the bonded wafer 22 is increased, thereby affecting the packaging reliability and packaging yield of the wafer.

[0030] In order to solve the technical problem, an embodiment of the present invention provides a wafer, comprising a central chip area and an edge chip area surrounding the central chip area, the wafer comprising: a substrate; a dielectric layer located on the substrate, the surface of the dielectric layer facing away from the substrate being a bonding surface; a first bonding layer located in the dielectric layer of the central chip area, the first bonding layer exposing the bonding surface, the first bonding layer being used to achieve bonding between bonding surfaces of multiple wafers; a second bonding layer located in the dielectric layer of the edge chip area, the second bonding layer exposing the bonding surface, the second bonding layer being used to achieve bonding between bonding surfaces of multiple wafers, and the size of the second bonding layer being larger than the size of the first bonding layer.

[0031] An embodiment of the present invention provides a wafer, the wafer comprising a central chip area and an edge chip area surrounding the central chip area, a dielectric layer is located on the substrate, a surface of the dielectric layer facing away from the substrate is a bonding surface, a first bonding layer is located in the dielectric layer of the central chip area, and the first bonding layer exposes the bonding surface, the first bonding layer is used to achieve bonding between bonding surfaces of multiple wafers, a second bonding layer is located in the dielectric layer of the edge chip area, the second bonding layer exposes the bonding surface, the second bonding layer is used to achieve bonding between bonding surfaces of multiple wafers, and the size of the second bonding layer is larger than the size of the first bonding layer, accordingly, in the back When multiple wafers are bonded to form a bonded wafer, the probability that the contact area between the second bonding layers is smaller than the contact area between the first bonding layers due to the error in overlay accuracy (overlay accuracy refers to the fact that during the formation of the bonded wafer, the bonded wafer is prone to expansion after being heated, and the expansion easily causes the second bonding layer to move toward the edge of the bonded wafer) of the second bonding layer of the bonded wafer can be reduced, thereby ensuring the bonding strength of the edge chip area of ​​the bonded wafer. In the subsequent thinning process of the bonded wafer, the probability of gaps in the edge chip area of ​​the bonded wafer is reduced, thereby improving the packaging reliability and packaging yield of the wafer.

[0032] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0033] refer to Figures 2 to 5 , shows a schematic diagram of the structure of a wafer according to an embodiment of the present invention. Figure 2 This is a top view of the wafer. Figure 3 yes Figure 2 A partial enlarged schematic diagram of the label A. Figure 4 yes Figure 2 The enlarged schematic diagram of the part marked with B in the middle. Figure 5 yes Figure 2 Schematic diagram of the cross-sectional structure of the wafer along the CC direction.

[0034] In this embodiment, the wafer 130 includes a central chip area 100A and an edge chip area 100B surrounding the central chip area 100A; the wafer 130 includes: a substrate 193; a dielectric layer 194, located on the substrate 193, and the surface of the dielectric layer 194 facing away from the substrate 193 is a bonding surface 195; a first bonding layer 180, located in the dielectric layer 194 of the central chip area 100A, and the first bonding layer 180 exposes the bonding surface 195, and the first bonding layer 180 is used to achieve bonding between the bonding surfaces 195 of multiple wafers 130; a second bonding layer 170, located in the dielectric layer 194 of the edge chip area 100B, and the second bonding layer 170 exposes the bonding surface 195, and the second bonding layer 170 is used to achieve bonding between the bonding surfaces 195 of multiple wafers 130, and the size of the second bonding layer 170 is larger than the size of the first bonding layer 180.

[0035] In this embodiment, the wafer 130 is manufactured using integrated circuit manufacturing technology.

[0036] In this embodiment, the wafer 130 includes a central chip area 100A and an edge chip area 100B surrounding the central chip area 100A. Specifically, the central chip area 100A is used to set multiple chips and a first bonding layer 180 , and the edge chip area 100B is used to set multiple chips and a second bonding layer 170 .

[0037] As an example, the edge chip region 100B includes a plurality of sub-edge chip regions 160 surrounding the central chip region 100A in a circumferential direction.

[0038] Specifically, the sub-edge chip area 160 is used to arrange a plurality of chips, and a cutting street 120 is provided between adjacent sub-edge chip areas 160 , which facilitates the subsequent division of the wafer 130 into a plurality of chips through the cutting street 120 .

[0039] It should be noted that the first bonding layer 180 is located in the dielectric layer 194 of the central chip area 100A, and the first bonding layer 180 exposes the bonding surface 195, and the first bonding layer 180 is used to achieve bonding between the bonding surfaces 195 of multiple wafers 130, and the second bonding layer 170 is located in the dielectric layer 194 of the edge chip area 100B, and the second bonding layer 170 exposes the bonding surface 195, and the second bonding layer 170 is used to achieve bonding between the bonding surfaces 195 of multiple wafers 130, and the size of the second bonding layer 170 is larger than the first bonding layer 170. The size of the bonding layer 180 can accordingly reduce the probability that the contact area between the second bonding layers 170 of the bonded wafer is smaller than the contact area between the first bonding layers 180 due to the influence of the overlay accuracy error when multiple wafers 130 are subsequently bonded to form a bonded wafer, thereby ensuring the bonding strength of the edge chip area 100B of the bonded wafer. In the subsequent thinning process of the bonded wafer, the probability of gaps in the edge chip area 100B of the bonded wafer is reduced, thereby improving the packaging reliability and packaging yield of the wafer 130.

[0040] The substrate 193 is used to provide a process platform for manufacturing the wafer 130 .

[0041] As an example, the substrate 193 of the wafer 130 is a silicon substrate 193. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as a silicon on insulator substrate or a germanium on insulator substrate.

[0042] The dielectric layer 194 is used to provide a process basis for setting the first bonding layer 180 and the second bonding layer 170 , and is also used to electrically isolate adjacent first bonding layers 180 and adjacent second bonding layers 170 .

[0043] In this embodiment, the exposed surface of the dielectric layer 194 is the bonding surface 195 , that is, when different wafers 130 are subsequently bonded, the dielectric layers 194 of different wafers 130 are arranged relatively and bonded.

[0044] Specifically, the bonding surface 195 is the top surface of the dielectric layer 194 , and the bonding surface 195 is the surface for bonding the wafer 130 . After the bonding between the wafers 130 is achieved, the electrical connection between the circuit structure layers of the wafer 130 can be achieved, thereby realizing the normal function of the packaging structure.

[0045] In the present embodiment, the material of the dielectric layer 194 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride.

[0046] A circuit structure is also formed in the dielectric layer 194 . The dielectric layer 194 is also used to provide a process basis for forming the circuit structure and to isolate adjacent circuit structures.

[0047] The circuit structure is used to electrically lead out the devices in the wafer 130 so as to achieve electrical connection with external circuits or other structures.

[0048] The first bonding layer 180 is used to realize electrical connection between the wafer 130 and an external circuit.

[0049] As an example, when achieving bonding between different wafers 130 , the first bonding layer 180 located in the central chip area 100A is relatively arranged and bonded to achieve bonding between different wafers 130 . Correspondingly, electrical connection between different wafers 130 can also be achieved through the first bonding layer 180 .

[0050] In this embodiment, the material of the first bonding layer 180 includes one or more of copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc and chromium, which is conducive to obtaining better conductive properties.

[0051] In this embodiment, one or more first bonding layers 180 are located in the central chip region 100A. As an example, Figure 4 The central chip region 100A in FIG. 1 has a plurality of first bonding layers 180 .

[0052] Specifically, multiple first bonding layers 180 are located in the central chip area 100A. When multiple wafers 130 are subsequently bonded to form a bonded wafer, the bonding strength of the central chip area 100A of the bonded wafer can be enhanced. In the subsequent process of back thinning of the bonded wafer, the risk of breakage or cracks on the bonding surface 195 of the bonded wafer can be reduced.

[0053] As an example, in the case where there are multiple first bonding layers 180 in the central chip region 100A, the multiple first bonding layers 180 are arranged along the first direction (eg Figure 4 X direction) and the second direction (as shown in Figure 4 The first and second directions are arranged in a matrix (as shown in the Y direction), and the first and second directions are perpendicular to each other.

[0054] In other embodiments, the plurality of first bonding layers 180 may also be arranged in a matrix at intervals along a certain angle.

[0055] Specifically, in the process of forming the first bonding layer 180 , multiple first bonding layers 180 are arranged in a matrix along the first direction and the second direction, which reduces the process difficulty of forming the first bonding layer 180 and reduces the probability of contact between adjacent first bonding layers 180 .

[0056] In this embodiment, the distances between adjacent first bonding layers 180 are equal. Specifically, the distances between adjacent first bonding layers 180 are equal, and in the subsequent process of bonding multiple wafers 130 to form a bonded wafer, the bonding strength of each area of ​​the central chip area 100A of the bonded wafer can be made consistent, reducing the probability of uneven bonding strength between the bonding surfaces 195 of the bonded wafer, and reducing the risk of cracks or gaps on the bonding surfaces 195 of the bonded wafer, thereby improving the packaging reliability and packaging yield of the wafer 130.

[0057] In other embodiments, the distances between adjacent first bonding layers may also be unequal.

[0058] It should be noted that the distance d1 between adjacent first bonding layers 180 should not be too large or too small. If the distance d1 between adjacent first bonding layers 180 is too large, after the subsequent bonding of multiple wafers 130 to form a bonded wafer, the bonding strength of the central chip area 100A of the bonded wafer cannot meet the packaging requirements, and in the subsequent process of back thinning of the bonded wafer, the risk of cracks or gaps on the bonding surface 195 of the bonded wafer is increased; if the distance d1 between adjacent first bonding layers 180 is too small, in the subsequent process of bonding multiple wafers 130 to form a bonded wafer, the process difficulty of the first bonding layer 180 of the central chip area 100A of the bonded wafer is increased, thereby increasing the probability of the first bonding layer 180 being short-circuited with the first bonding layer 180 on the lower side, thereby affecting the packaging yield of the bonded wafer. For this reason, in this embodiment, the distance d1 between adjacent first bonding layers 180 is 0.1 microns to 200 microns.

[0059] It should also be noted that the size of the first bonding layer 180 should not be too large or too small. If the size of the first bonding layer 180 is too large, it is easy to cause the first bonding layer 180 to occupy too much area of ​​other circuit structures in the dielectric layer 194; if the size of the first bonding layer 180 is too small, in the subsequent process of bonding multiple wafers 130 to form a bonded wafer, the process difficulty of the first bonding layer 180 in the central chip area 100A of the bonded wafer is increased, thereby increasing the probability of the first bonding layer 180 being short-circuited with the first bonding layer 180 on the lower side, thereby affecting the packaging yield of the bonded wafer. For this reason, in this embodiment, the size of the first bonding layer 180 is 0.1 microns to 200 microns.

[0060] Specifically, the size of the first bonding layer 180 refers to the size of the first bonding layer 180 in the first direction and the second direction.

[0061] As an example, the shape of the first bonding layer 180 is a rectangle. In other embodiments, the shape of the first bonding layer can also be one or more of a polygon, a circle, and an ellipse.

[0062] It should be noted that the second bonding layer 170 is used to achieve bonding between the bonding surfaces 195 of multiple wafers 130, and the size of the second bonding layer 170 is larger than the size of the first bonding layer 180. Accordingly, when multiple wafers 130 are subsequently bonded to form a bonded wafer, the probability that the second bonding layer 170 of the bonded wafer is affected by the overlay accuracy error and the contact area between the second bonding layers 170 is smaller than the contact area between the first bonding layers 180 can be reduced, thereby ensuring the bonding strength of the edge chip area 100B of the bonded wafer. In the subsequent thinning process of the bonded wafer, the probability of gaps in the edge chip area 100B of the bonded wafer is reduced, thereby improving the packaging reliability and packaging yield of the wafer 130.

[0063] It should also be noted that the second bonding layer 170 is also used to achieve electrical connection between the wafer 130 and an external circuit.

[0064] As an example, when bonding between different wafers 130 is achieved, the second bonding layer 170 located in the edge chip area 100B is relatively arranged and bonded to achieve bonding between different wafers 130. Correspondingly, electrical connection between different wafers 130 can also be achieved through the second bonding layer 170.

[0065] In this embodiment, the material of the second bonding layer 170 includes one or more of copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc and chromium, which is conducive to obtaining better conductive properties.

[0066] In this embodiment, one or more second bonding layers 170 are located in the edge chip region 100B. As an example, Figure 3 The edge chip region 100B has a plurality of second bonding layers 170 .

[0067] Specifically, multiple second bonding layers 170 are located in the edge chip area 100B. When multiple wafers 130 are subsequently bonded to form a bonded wafer, the bonding strength of the edge chip area 100B of the bonded wafer can be further enhanced. In the subsequent process of back thinning of the bonded wafer, the risk of breakage or cracks on the bonding surface 195 of the bonded wafer can be reduced.

[0068] As an example, when there are multiple second bonding layers 170 in the edge chip region 100B, the multiple second bonding layers 170 are arranged along the first direction (eg Figure 3 X direction) and the second direction (as shown in Figure 3 The first and second directions are arranged in a matrix (as shown in the Y direction), and the first and second directions are perpendicular to each other.

[0069] Specifically, in the process of forming the second bonding layer 170 , multiple second bonding layers 170 are arranged in a matrix along the first direction and the second direction, which reduces the process difficulty of forming the second bonding layer 170 and reduces the probability of contact between adjacent second bonding layers 170 .

[0070] As an example, when there are multiple second bonding layers 170 in the sub-edge chip area 160 , the distances between adjacent second bonding layers 170 in the first direction are the same, and the distances between adjacent second bonding layers 170 in the second direction are the same.

[0071] Specifically, the distance between adjacent second bonding layers 170 in the first direction is the same, and the distance between adjacent second bonding layers 170 in the second direction is the same. In the subsequent process of bonding multiple wafers 130 to form a bonded wafer, the bonding strength of each area of ​​the edge chip area 100B of the bonded wafer can be made consistent, thereby reducing the probability of uneven bonding strength between the bonding surfaces 195 of the bonded wafers, and reducing the risk of breakage or gaps on the bonding surfaces 195 of the bonded wafers, thereby improving the packaging reliability and packaging yield of the wafer 130.

[0072] It should be noted that the distance D1 between adjacent second bonding layers 170 in the first direction should not be too large or too small. If the distance D1 between adjacent second bonding layers 170 in the first direction is too large, after multiple wafers 130 are bonded to form a bonded wafer, the bonding strength of the edge chip area 100B of the bonded wafer in the first direction cannot meet the packaging requirements, and in the subsequent process of back thinning of the bonded wafer, the risk of chipping or cracking of the bonding surface 195 of the bonded wafer is increased; if the distance D1 between the second bonding layers 170 in the first direction is too small, in the subsequent process of bonding multiple wafers 130 to form a bonded wafer, the process difficulty of the second bonding layers 170 in the edge chip area 100B of the bonded wafer is increased, the contact area between the second bonding layers 170 is reduced, and the bonding strength of the edge chip area 100B of the bonded wafer in the first direction is reduced. At the same time, the probability of the second bonding layer 170 being short-circuited with the second bonding layer 170 on the lower side is increased, thereby affecting the packaging yield of the bonded wafer. To this end, in this embodiment, the distance D1 between adjacent second bonding layers 170 in the first direction is 0.1 micrometer to 200 micrometers.

[0073] It should also be noted that the distance D2 between adjacent second bonding layers 170 in the second direction should not be too large or too small. If the distance D2 between adjacent second bonding layers 170 in the second direction is too large, after multiple wafers 130 are bonded to form a bonded wafer, the bonding strength of the edge chip area 100B of the bonded wafer in the second direction cannot meet the packaging requirements, and in the subsequent process of back thinning of the bonded wafer, the risk of chipping or cracking of the bonding surface 195 of the bonded wafer is increased; if the distance D2 between the second bonding layers 170 in the second direction is too small, in the subsequent process of bonding multiple wafers 130 to form a bonded wafer, the process difficulty of the second bonding layers 170 in the edge chip area 100B of the bonded wafer is increased, the contact area between the second bonding layers 170 is reduced, and the bonding strength of the edge chip area 100B of the bonded wafer in the second direction is reduced. At the same time, the probability of the second bonding layer 170 being short-circuited with the second bonding layer 170 on the lower side is increased, thereby affecting the packaging yield of the bonded wafer. To this end, in this embodiment, the distance D2 between adjacent second bonding layers 170 in the second direction is 0.1 micrometer to 200 micrometers.

[0074] Specifically, the size of the second bonding layer 170 should not be too large or too small. If the size of the second bonding layer 170 is too large, it is easy to cause the second bonding layer 170 to occupy too much area of ​​other circuit structures in the dielectric layer 194; if the size of the second bonding layer 170 is too small, in the process of bonding multiple wafers 130 to form a bonded wafer, the process difficulty of the second bonding layer 170 in the central chip area 100A of the bonded wafer is increased, thereby increasing the probability of the second bonding layer 170 and the second bonding layer 170 on the lower side being short-circuited, thereby affecting the packaging yield of the bonded wafer. For this reason, in this embodiment, the size of the second bonding layer 170 is 0.1 microns to 200 microns.

[0075] It should be noted that during the formation process of the bonded wafer, the second bonding layer 170 is prone to expand after being heated, and the expansion easily causes the second bonding layer 170 to move toward the edge of the wafer, and the distance the second bonding layer 170 moves is greater than the distance the first bonding layer 180 moves. Therefore, the size of the second bonding layer 170 is greater than the size of the first bonding layer 180. When multiple wafers 130 are subsequently bonded to form a bonded wafer, the probability that the contact area between the second bonding layers 170 of the bonded wafers is smaller than the contact area between the first bonding layers 180 can be reduced, thereby ensuring the bonding strength of the edge chip area 100B of the bonded wafer. In the subsequent thinning process of the bonded wafer, the probability of gaps in the edge chip area 100B of the bonded wafer is reduced, thereby improving the packaging reliability and packaging yield of the wafer 130.

[0076] Specifically, the size of the second bonding layer 170 should not be too large or too small compared to the size of the first bonding layer 180 . If the size of the second bonding layer 170 is larger than the size of the first bonding layer 180, when the size of the first bonding layer 180 meets the process requirements, it is easy for the second bonding layer 170 to occupy too much of the spatial area of ​​the sub-edge chip area 160, which is not conducive to setting other circuit structures in the sub-edge chip area 160, thereby affecting the function of the chip in the sub-edge chip area 160; if the size of the second bonding layer 170 is larger than the size of the first bonding layer 180, when multiple wafers 130 are subsequently bonded to form a bonded wafer, the probability that the contact area between the second bonding layers 170 of the bonded wafers is smaller than the contact area between the first bonding layers 180 is increased, so that the bonding strength of the edge chip area of ​​the bonded wafer is smaller than the bonding strength of the central chip area 100A, so that the bonding strength of the edge chip area 100B cannot be guaranteed, and in the subsequent thinning process of the bonded wafer, the probability of gaps in the edge chip area 100B of the bonded wafer is reduced, thereby reducing the packaging reliability and packaging yield of the wafer 130. To this end, in this embodiment, the size of the second bonding layer 170 is greater than the size of the first bonding layer 180 in a range of 0.1 micrometer to 200 micrometers.

[0077] In this embodiment, a pitch between adjacent second bonding layers 170 is equal to a pitch between adjacent first bonding layers 180 .

[0078] Specifically, in the semiconductor manufacturing process, for a wafer, there are multiple chips distributed on it, and the circuits and functions between the chips are the same. For example, a chip at the edge and a chip at the center are actually chips with the same function. Therefore, although the size of the second bonding layer 170 is inconsistent with the size of the first bonding layer 180, the pitch between adjacent second bonding layers 170 is equal to the pitch between adjacent first bonding layers 180.

[0079] In other embodiments, the pitch between adjacent second bonding layers may be unequal to the pitch between adjacent first bonding layers.

[0080] As an example, the second bonding layer 170 is in a rectangular shape. In other embodiments, the second bonding layer may be in a polygonal shape, a circular shape, or an elliptical shape.

[0081] In this embodiment, the wafer 130 also includes: a first interconnection structure 191, located in the dielectric layer 194, the first bonding layer 180 and the second bonding layer 170 are located on the top of the first interconnection structure 191, the first interconnection structure 191 is electrically connected to the first bonding layer 180, and the first interconnection structure 191 is electrically connected to the second bonding layer 170.

[0082] Specifically, the first interconnect structure 191 is electrically connected to the first bonding layer 180 and to the second bonding layer 170. When multiple wafers 130 are subsequently bonded to form a bonded wafer, the first interconnect structures 191 in the multiple wafers 130 can be electrically connected to each other through the first bonding layer 180 and the second bonding layer 170, thereby transmitting electrical signals in the bonded wafer.

[0083] The material of the first interconnect structure 191 is a conductive material, and the conductive material includes one or both of copper and aluminum. As an example, the material of the first interconnect structure 191 is copper.

[0084] In this embodiment, the wafer 130 further includes: an interconnection via structure 192 located in the dielectric layer 194 between the first bonding layer 180 and the first interconnection structure 191 , and in the dielectric layer 194 between the second bonding layer 170 and the first interconnection structure 191 .

[0085] Specifically, the interconnection via structure 192 is used to electrically connect the first bonding layer 180 and the first interconnection structure 191 , and to electrically connect the second bonding layer 170 and the first interconnection structure 191 .

[0086] As an example, the material of the interconnect via structure 192 includes one or both of copper and aluminum.

[0087] Aluminum and copper have lower resistivity, which is beneficial for lowering the resistance value generated by the interconnection through-hole structure 192 . At the same time, aluminum and copper have faster electron mobility and higher conductivity, thereby improving the performance of the wafer 130 .

[0088] Correspondingly, an embodiment of the present invention also provides a packaging method. Figures 6 to 9 The following is a schematic diagram of the structure corresponding to each step in an embodiment of the packaging method of the present invention. The packaging method of this embodiment is described in detail in conjunction with the accompanying drawings.

[0089] refer to Figure 6 to Figure 7 , provide a plurality of wafers provided in the aforementioned embodiments, including a first wafer 200 and a second wafer 201 .

[0090] A plurality of wafers provided in the above-mentioned embodiments are provided so as to subsequently bond the first wafer 200 and the second wafer 201 .

[0091] For a detailed description of the wafer of this embodiment, please refer to the corresponding description in the aforementioned embodiment, and this embodiment will not be repeated here.

[0092] refer to Figure 8, bond the first wafer 200 and the second wafer 201 so that the bonding surfaces 295 of the first wafer 200 and the second wafer 201 are arranged relative to each other, the first bonding layers 280 of the first wafer 200 and the second wafer 201 are arranged relative to each other and bonded, and the second bonding layers 270 of the first wafer 200 and the second wafer 201 are arranged relative to each other and bonded, the dielectric layers 294 of the first wafer 200 and the second wafer 201 are arranged relative to each other and bonded, and the size of the second bonding layer 270 is larger than the size of the first bonding layer 280.

[0093] It should be noted that the second bonding layer 270 is used to achieve bonding between the bonding surfaces 295 of multiple wafers, and the size of the second bonding layer 270 is larger than the size of the first bonding layer 280. Accordingly, when multiple wafers are bonded to form a bonded wafer 202, the probability that the second bonding layer 270 of the bonded wafer 202 is affected by the overlay accuracy error and the contact area between the second bonding layers 270 is smaller than the contact area between the first bonding layers 280 can be reduced, thereby ensuring the bonding strength of the edge chip area 200B of the bonded wafer 202. In the subsequent thinning process of the bonded wafer 202, the probability of gaps in the edge chip area 200B of the bonded wafer 202 is reduced, thereby improving the packaging reliability and packaging yield of the wafer.

[0094] In this embodiment, in the step of bonding the first wafer 200 and the second wafer 201, the first bonding layers 280 of the first wafer 200 and the second wafer 201 are arranged opposite to each other up and down, the second bonding layers 270 of the first wafer 200 and the second wafer 201 are arranged opposite to each other up and down, and the shape, position, length and width of the first bonding layers 280 in the first wafer 200 and the second wafer 201 are the same, and the shape, position, length and width of the second bonding layers 270 in the first wafer 200 and the second wafer 201 are the same. The length and width are the same so that the first bonding layers 280 of the first wafer 200 and the second wafer 201 can be aligned vertically, and the second bonding layers 270 of the first wafer 200 and the second wafer 201 can be aligned vertically, so that the contact area between the first bonding layers 280 and the contact area between the second bonding layers 270 can meet the process requirements, thereby increasing the bonding strength of the edge chip area 200B of the bonded wafer 202, and improving the bonding strength and firmness of the bonded wafer 202.

[0095] In this embodiment, the step of bonding the first wafer 200 and the second wafer 201 includes: bonding the bonding surfaces 295 of the first wafer 200 and the second wafer 201 relative to each other, the central chip areas 200A of the first wafer 200 and the second wafer 201 are arranged relative to each other up and down, and the edge chip areas 200B of the first wafer 200 and the second wafer 201 are arranged relative to each other up and down, so that the first bonding layers 280 of the first wafer 200 and the second wafer 201 are in relative contact, and the second bonding layers 270 of the first wafer 200 and the second wafer 201 are in relative contact.

[0096] The first bonding layers 280 of the first wafer 200 and the second wafer 201 are in relative contact, and the second bonding layers 270 of the first wafer 200 and the second wafer 201 are in relative contact, so that the first bonding layer 280 and the second bonding layer 270 can both bond to each other, thereby allowing the first wafer 200 and the second wafer 201 to be bonded to form a bonded wafer 202.

[0097] It should also be noted that, in the present embodiment, the dielectric layers 294 in the first wafer 200 and the second wafer 201 are arranged relatively to each other and bonded, and the dielectric layers 294 in the first wafer 200 and the dielectric layers 294 in the second wafer 201 are both dielectric materials, and the dielectric layers 294 in the first wafer 200 and the second wafer 201 play a role of mutual bonding, so that the first wafer 200 and the second wafer 201 can be bonded to form a bonded wafer 202, making it difficult for the first wafer 200 and the second wafer 201 to fall off.

[0098] In this embodiment, the process of bonding the first wafer 200 and the second wafer 201 includes a hybrid bonding process.

[0099] Specifically, in the hybrid bonding process, the bonding interface has not only the bonding between dielectric layers but also the bonding between metals, so that the total bonding area 295 between the first wafer 200 and the second wafer 201 is increased. Accordingly, the bonded wafer 202 formed after the first wafer 200 and the second wafer 201 are bonded to each other is not easy to fall off. At the same time, the hybrid bonding process has the characteristics of fewer process steps and low process cost, and there is no need to form a bonding dielectric layer on the surface of the first wafer 200 and the surface of the second wafer 201.

[0100] refer to Fig. 9 After bonding the first wafer 200 and the second wafer 201 , the packaging method further includes: thinning a surface of the first wafer 200 that is opposite to the bonding surface 295 .

[0101] Specifically, the thinning process provides a process basis for subsequent wafer stacking.

[0102] It should be noted that the bonding strength of the edge chip area 200B of the bonded wafer 202 is guaranteed, making the bonding strength of the edge chip area 200B of the bonded wafer 202 stronger. During the thinning process, the probability of generating gaps on the bonding surface 295 of the edge chip area 200B of the bonded wafer 202 is reduced, thereby reducing the probability of the gaps extending into the central chip area 200A, and reducing the probability of the central chip area 200A being damaged, thereby improving the packaging reliability and packaging yield of the wafer.

[0103] As an example, the thinning process may be performed by first performing rough grinding and then fine grinding, wherein the rough grinding is performed quickly using a rough grinding machine, and the fine grinding is performed using a chemical mechanical grinding process.

[0104] In other embodiments, after the first wafer and the second wafer are bonded together, the packaging method may further include: thinning the surface of the second wafer that is opposite to the bonding surface.

[0105] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A wafer, characterized in that: The wafer comprises a central chip area and an edge chip area surrounding the central chip area, and the wafer comprises: substrate; A dielectric layer is located on the substrate, wherein the surface of the dielectric layer facing away from the substrate is a bonding surface; A first bonding layer, located in the dielectric layer of the central chip area, and the first bonding layer exposes the bonding surface, and the first bonding layer is used to achieve bonding between bonding surfaces of multiple wafers; The second bonding layer is located in the dielectric layer of the edge chip area, the second bonding layer exposes the bonding surface, the second bonding layer is used to achieve bonding between bonding surfaces of multiple wafers, and the size of the second bonding layer is larger than the size of the first bonding layer.

2. The wafer according to claim 1, characterized in that: The edge chip area includes a plurality of sub-edge chip areas surrounding the central chip area in a circumferential direction; One or more second bonding layers are located in the sub-edge chip area, and when the number of second bonding layers in the sub-edge chip area is multiple, the multiple second bonding layers are arranged in a matrix along the first direction and the second direction, and the first direction and the second direction are perpendicular to each other.

3. The wafer according to claim 2, characterized in that: When there are multiple second bonding layers in the sub-edge chip region, the distances between adjacent second bonding layers in the first direction are the same, and the distances between adjacent second bonding layers in the second direction are the same.

4. The wafer according to claim 2, characterized in that: The distance between adjacent second bonding layers in the first direction is 0.1 micrometer to 200 micrometers; The distance between adjacent second bonding layers in the second direction is 0.1 micrometer to 200 micrometers.

5. The wafer according to claim 1, wherein: The size of the first bonding layer is 0.1 micrometer to 200 micrometers; The size of the second bonding layer is 0.1 micrometer to 200 micrometers.

6. The wafer according to claim 1, wherein: The size of the second bonding layer is greater than that of the first bonding layer in a range of 0.1 micrometer to 200 micrometers.

7. The wafer according to claim 1, wherein: A pitch between adjacent first bonding layers is equal to a pitch between adjacent second bonding layers.

8. The wafer according to claim 1, wherein: One or more of the first bonding layers are located in the central chip area, and when there are multiple first bonding layers in the central chip area, the multiple first bonding layers are arranged in a matrix along the first direction and the second direction, and the first direction and the second direction are perpendicular to each other.

9. The wafer according to claim 1, characterized in that: The wafer further includes: a first interconnect structure located in the dielectric layer, the first bonding layer and the second bonding layer located on top of the first interconnect structure, the first interconnect structure electrically connected to the first bonding layer, and the first interconnect structure electrically connected to the second bonding layer.

10. The wafer according to claim 9, characterized in that: The wafer further includes an interconnect via structure in the dielectric layer between the first bonding layer and the first interconnect structure, and in the dielectric layer between the second bonding layer and the first interconnect structure.

11. A packaging method, characterized in that: include: Providing a plurality of wafers according to any one of claims 1 to 10, wherein the wafers include a first wafer and a second wafer; The first wafer and the second wafer are bonded so that the bonding surfaces of the first wafer and the second wafer are arranged relative to each other, the first bonding layers of the first wafer and the second wafer are arranged relative to each other and bonded, and the second bonding layers of the first wafer and the second wafer are arranged relative to each other and bonded, the dielectric layers of the first wafer and the second wafer are arranged relative to each other and bonded, and the size of the second bonding layer is larger than the size of the first bonding layer.

12. The packaging method according to claim 11, characterized in that: In the step of bonding the first wafer and the second wafer, the first bonding layers of the first wafer and the second wafer are arranged opposite to each other up and down, the second bonding layers of the first wafer and the second wafer are arranged opposite to each other up and down, and the shape, position, length and width of the first bonding layers in the first wafer and the second wafer are the same, and the shape, position, length and width of the second bonding layers in the first wafer and the second wafer are the same.

13. The packaging method according to claim 11, characterized in that: The process of bonding the first wafer to the second wafer includes a hybrid bonding process.

14. The packaging method according to claim 11, characterized in that: After bonding the first wafer to the second wafer, the packaging method further comprises: thinning a surface of the first wafer that is opposite to the bonding surface; Alternatively, a thinning process is performed on a surface of the second wafer which is opposite to the bonding surface.

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