Stacked chip packaging method for stacked packaging

Abstract

The invention discloses a stacked chip packaging method for stacked packaging, and the method comprises the steps: providing a support plate, and providing a plurality of bare chips with conductive columns; the top ends of the conductive columns are exposed in a staggered manner, and the top surfaces of the conductive columns are equal in height; forming a packaging monomer in which the bare crystal and the conductive column are plastically packaged on the carrier plate, and exposing the top surface of the conductive column; superposing conductive columns on the exposed conductive columns of the packaging single body, and sequentially stacking one or more bare chips or another independent packaging single body on the packaging single body in a staggered manner, wherein the conductive columns are staggered, and the top surfaces of the conductive columns are equal in height; forming another packaging single body on the carrier plate and exposing the top surface of the conductive column, and repeating the steps until a preset number of bare chips or packaging single bodies are superposed; manufacturing a rewiring layer on the upper surface of the packaging monomer; and welding pins are manufactured on the rewiring layer so as to manufacture the stacked chip packaging structure. The invention has the advantages of thin thickness and high yield.

Description

Technical Field

[0001] The present invention relates to semiconductor packaging, and in particular to chip stacking packaging. Background Art

[0002] Nowadays, the advanced packaging industry is booming, and the thickness of bare die packaging is required to be thinner and thinner. However, the bare die packaging thickness achieved by the existing traditional wire bonding packaging has reached the limit of technology and equipment. It is urgent to use new interconnection methods to make thinner packaging structures. 1) Traditional packaging is to stack bare die on a substrate and then make electrical connections to the metal on the substrate through leads. A certain gap needs to be left between the highest point of the top bare die lead and the plastic cover. 2) Traditional wire bonding packaging still uses substrates as carriers, and the minimum thickness of the substrate has reached the process limit; 3) The gap between the top bare crystal and the plastic cover and the minimum processing thickness of the substrate have reached their limits. If ultra-thin bare crystal packaging is required, the thickness of a single bare crystal must be lower. The thinner the thickness of a single bare crystal, the more difficult it is to ensure the production yield; this limits the production of ultra-thin packaging.

[0003] Therefore, there is an urgent need for a bare die packaging method that can solve the above problems. Summary of the invention

[0004] The purpose of the present invention is to provide a stacked chip packaging method with a superimposed package, which has a thin thickness and a high yield rate.

[0005] In order to achieve the above-mentioned purpose, the present invention provides a stacked chip packaging method of stacking packaging, comprising: step 1, providing a carrier board, providing a plurality of bare crystals with conductive columns, wherein the conductive columns are electrically connected to the electrodes of the bare crystals; step 2, stacking one of the bare crystals on the carrier board or stacking a plurality of the bare crystals on the carrier board in a staggered manner, and the top ends of the conductive columns on all the bare crystals are staggered and exposed and the top surfaces are at the same height; step 3, forming a packaging monomer on the carrier board that plastic-seales the bare crystals and the conductive columns, so that the top surfaces of all the conductive columns are exposed on the upper surface of the packaging monomer; step 4, stacking conductive columns of a preset height on the top surfaces of the conductive columns exposed in the packaging monomer, and stacking one or more bare crystal conductive columns upward in a staggered manner on the packaging monomer in sequence, or stacking the conductive columns of another independent packaging monomer in a staggered manner. The top surface of the column is offset and stacked upward on the original packaging monomer, and the conductive columns of all the packaging monomers are staggered with the conductive columns exposed on the original packaging body and the top surfaces are at the same height; step 5, forming another packaging monomer on the carrier board, which plastic-encapsulates the original packaging monomer, the stacked conductive columns and the bare crystal or packaging monomer stacked on the original packaging monomer, and the top surfaces of all the conductive columns are exposed on the upper surface of the packaging monomer, repeating steps 4 to 5 until a preset number of bare crystals are stacked on the carrier board; step 6, making a redistribution layer electrically connected to the conductive columns on the upper surface of the finally formed packaging monomer; step 7, making a solder foot on the side of the redistribution layer away from the packaging monomer to form a stacked chip packaging structure; step 8, debonding the carrier board and the stacked chip packaging structure.

[0006] Preferably, the independent packaging unit is manufactured by steps 1 to 3, or steps 1 to 5, and the independent packaging unit is a packaging unit debonded from the carrier.

[0007] Preferably, the structure of another independent packaging unit superimposed on the original packaging unit is the same as or different from that of the original packaging unit.

[0008] Preferably, the electrode of the bare die is located on one side of the symmetry line of the bare die, and the conductive pillar is formed on the electrode of the bare die, so that all the electrodes and the conductive pillars thereon are staggered during staggered stacking.

[0009] Preferably, multiple bare die are sequentially staggered and stacked on the carrier or the package monomer, and the number of the bare die is 2 or 3. This solution makes the structure in each package monomer stable, and the height of the conductive pillars on the bare die is controlled, which is easy to manufacture and has a high yield.

[0010] Preferably, in step 5, the newly formed packaging monomer is superimposed on the original packaging monomer or wraps the original packaging monomer.

[0011] Preferably, providing a bare crystal with a conductive column specifically includes: providing a wafer, making a conductive column on an electrode of the wafer by an electroplating process, and thinning the substrate on the back of the wafer, and cutting the thinned wafer to obtain a number of bare crystals with a conductive column, wherein the bare crystal is a thinned bare core.

[0012] Preferably, another independent package monomer superimposed on the original package monomer has multiple staggered stacked bare dies, and the package monomer encapsulating the bare dies is encapsulated once or multiple times, and each time the number of staggered unencapsulated bare dies is 1 or 2. This solution makes the structure of each package monomer stable, and the height of the conductive pillars on the bare dies is controlled, which is easy to manufacture and has a high yield rate.

[0013] Preferably, in step 4, a conductive column of a preset height is manufactured on the top surface of the conductive column of the package unit by electroplating, so that the connection stability between the stacked conductive column and the original conductive column is high.

[0014] Preferably, in step 4, the preset height of the stacked conductive columns matches the thickness of the structure to be stacked in step 5, so that when the corresponding structure (bare crystal with conductive columns or new packaging structure) is stacked in step 5, the top surface of the stacked conductive columns is directly the same height as the top surface of the conductive columns on top of them, without the need for further grinding or etching.

[0015] Preferably, in step 10, when the plurality of bare chips are stacked in sequence on the carrier or the packaging unit in an offset manner, the height difference of the conductive pillars on the plurality of bare chips matches the thickness of the bare chips, so that the tops of all the conductive pillars are at the same height after the plurality of bare chips are stacked in sequence.

[0016] Preferably, on the carrier, all the bare crystals are stacked in a staggered manner in a first direction from bottom to top, and the electrodes of the bare crystals are located in a second direction of the symmetry line of the bare crystals, and the second direction is opposite to the first direction.

[0017] Preferably, before step 2, a temporary bonding layer is formed on the carrier, a black insulating layer is formed on the temporary bonding layer, and one or more bare crystals are stacked on the black insulating layer. This solution can effectively prevent the temporary bonding and debonding processes from damaging the stacked bare cores, and sometimes the surface of the bare crystal is damaged when laser debonding is used. Of course, it is not limited to this, and a temporary bonding layer of opaque (light absorbing, light shielding, light reflecting) material can be directly used to replace the temporary bonding layer and the black insulating layer.

[0018] Specifically, a black insulating layer is formed on the temporary bonding adhesive layer by pasting a black film on the temporary bonding adhesive layer, which is simple to operate, low in cost and makes the bonding surface of the temporary bonding flat, thereby improving the yield rate.

[0019] Preferably, forming a packaging monomer on the carrier board to plastic-encapsulate the bare crystal and the conductive pillar specifically includes: plastic-encapsulating on the carrier board to form a plastic-encapsulated body that fully encapsulates the bare crystal and the conductive pillar, and grinding the plastic-encapsulated body on a side away from the carrier board until the top surface of the conductive pillar is exposed; forming another packaging monomer on the carrier board to plastic-encapsulate the original packaging monomer, the superimposed conductive pillar, and the bare crystal or packaging monomer stacked on the original packaging monomer specifically includes: plastic-encapsulating on the carrier board to form a plastic-encapsulated body that fully encapsulates the original packaging monomer, the superimposed conductive pillar, and the bare crystal or packaging monomer stacked on the original packaging monomer, and grinding the plastic-encapsulated body on a side away from the carrier board until the top surface of the conductive pillar is exposed.

[0020] Compared with the prior art, the present invention first forms a conductive column on a bare core, then stacks and packages the bare core with the conductive column to form a packaged monomer with the conductive column exposed, and then directly forms a rewiring layer on the packaged monomer, which not only allows the conductive column to be closer to the packaged monomer, effectively thinning the package structure, but also during packaging, first packages to form a packaged monomer, and then stacks the conductive column and bare core / packaged monomer on the packaged monomer for secondary packaging, so that many layers of bare cores can be packaged in the final package structure, and the package has high structural stability and high yield. Furthermore, the present invention uses conductive columns instead of traditional wiring methods, which not only eliminates the gap between the top bare core and the top surface of the package body, but also effectively reduces the signal transmission distance between the electrode of the bare core and the output end of the package structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figures 1 to 4 It is a flow chart of the stacked chip packaging method of stacking packaging in Example 1 of the present invention.

[0022] Figure 5 The present invention is a flow chart of manufacturing a bare die with conductive pillars.

[0023] Figure 6 It is a flow chart of the present invention for processing the carrier before stacking the bare wafers.

[0024] Figures 7 and 8 It is a partial flow chart of the stacked chip packaging method of stacking packaging in Example 2 of the present invention.

[0025] Fig. 9 It is another flow chart of manufacturing a bare die with conductive pillars according to the present invention.

[0026] Fig.10 FIG. 1 is a partial flow chart of a stacked chip packaging method of stacking packaging in another embodiment of the present invention.

[0027] Figures 11 to 13 It is a partial flow chart of the stacked chip packaging method of stacking packaging in Example 3 of the present invention.

[0028] Figures 14 to 16 It is a partial flow chart of the stacked chip packaging method of stacking packaging in Example 4 of the present invention. DETAILED DESCRIPTION

[0029] In order to explain the technical content, structural features, achieved objectives and effects of the present invention in detail, the following is a detailed description in conjunction with the implementation methods and the accompanying drawings.

[0030] Embodiment 1: refer to Figures 1 to 4 The present invention discloses a stacked chip packaging method of stacking packaging, including steps S11 to S25.

[0031] S11, reference Figure 1 , provide a carrier 10, provide a plurality of bare crystals 20 with conductive pillars 30, the electrodes of the bare crystals 20 are located on one side of the symmetry line of the bare crystals, and the conductive pillars 30 are protruding on the electrodes of the bare crystals 20.

[0032] refer to Figure 5 Providing a bare die 20 having a conductive pillar 30 includes steps S111 to S114.

[0033] S111, providing a wafer 20a, the surface of the wafer 20a already has a surface electrode, and a passivation insulating layer is formed around the electrode.

[0034] S112, manufacturing a conductive pillar 30 on the electrode of the wafer 20a by an electroplating process.

[0035] Specifically, a copper electroplating seed layer is formed on the electrode surface of the wafer 20a by sputtering or other deposition processes. A photoresist layer is prepared on the electroplating seed layer, and the photoresist layer exposes the area that needs subsequent electroplating. Copper column electroplating is performed on the electroplating seed layer exposed on the photoresist layer to prepare a copper column of a preset height as the conductive column 30, and the photoresist layer and the excess electroplating seed layer are removed.

[0036] S113, thinning the substrate on the back side of the wafer 20a.

[0037] S114, cutting the thinned wafer 20b to obtain a plurality of bare crystals 20 with conductive pillars 30. The upper surface of the bare crystal 20 has an electrode, and the electrode is located on one side of the bare core symmetry line.

[0038] S12, reference Figure 1 , stacking one of the bare chips 20 on the carrier 10 .

[0039] Among them, reference Figure 6, before stacking one of the bare die 20 on the carrier 10, it also includes steps S121 to S122. S121, providing a carrier 10, forming a temporary bonding adhesive layer 11 on the carrier 10, and forming a black insulating layer 12 on the temporary bonding adhesive layer 11. In step S12, one of the bare die 20 is stacked on the black insulating layer 12. Preferably, forming the black insulating layer 12 on the temporary bonding adhesive layer 11 is specifically: pasting a black insulating film on the temporary bonding adhesive layer 11.

[0040] The bare die 20 is adhered and fixed on the black insulating layer 12 .

[0041] S13, Ref. Figure 1 A packaging unit 40 a is formed on the carrier 10 to plastic-encapsulate the bare die 20 and the conductive pillars, so that the top surfaces of all the conductive pillars 30 are exposed on the upper surface of the packaging unit 40 a.

[0042] Specifically, the carrier 10 is plastic-sealed and cured to form a plastic-sealed body, which fully encapsulates the bare die 20 and the conductive pillars 30. At this time, the plastic-sealed body encapsulates the top surface of the piglet 30, and the side of the plastic-sealed body away from the carrier 10 is thinned by a grinding process to expose the conductive pillars 30 on the bare die 20, so as to form a package monomer. The package monomer includes the bare die 20, the conductive pillars 30 and the thinned plastic-sealed body.

[0043] S14, reference Figure 1 A conductive column 31 with a preset height is stacked on the conductive column 30 exposed by the packaging unit 40a.

[0044] The height of the stacked conductive pillars 31 is determined according to the subsequently stacked bare crystal 20 and the height of the conductive pillars 30 thereon. In this embodiment, the height of the stacked conductive pillars 31 is equal to the thickness of the bare crystal 20 plus the height of the conductive pillars 31 thereon plus the thickness of the adhesive layer used during stacking.

[0045] The conductive pillar 31 is superimposed on the top surface of the conductive pillar 30 exposed by the package monomer 40a by using an electroplating process. Specifically, it includes: a copper electroplating seed layer is made on the surface of the package monomer 40a by sputtering or other deposition processes. A photoresist layer is prepared on the electroplating seed layer, and the photoresist layer exposes the area that needs subsequent electroplating. Copper pillars are electroplated on the electroplating seed layer exposed on the photoresist layer to prepare copper pillars of a preset height as the conductive pillars 31, and the photoresist layer and the excess electroplating seed layer are removed.

[0046] S15, reference Figure 1 A bare die 20 carrying a conductive pillar 30 is staggered and stacked on the package monomer 40a, and the conductive pillar 31 stacked on the package monomer 40a is staggered with the conductive pillar 30 of the stacked bare die 20 and has the same top surface height.

[0047] The bare die 20 carrying the conductive pillars 30 is offsetly pasted on the package monomer 40 a through an adhesive layer. Specifically, the adhesive layer can be formed by curing an insulating adhesive or an insulating adhesive film.

[0048] S16, reference Figure 2 A packaging monomer 40b is formed on the carrier 10, which plastic-encapsulates the original packaging monomer 40a, the stacked conductive pillars 31, the bare die 20 stacked on the original packaging monomer 40a, and the conductive pillars 30, and the top surfaces of all the conductive pillars 30 and 31 are exposed on the upper surface of the packaging monomer 40b.

[0049] Specifically, the carrier 10 is plastic-sealed and cured to form a plastic-sealed body, which plastic-sealed the two bare crystals 20, the two conductive pillars 30, and a superimposed conductive pillar 31. At this time, the plastic-sealed body wraps the top surfaces of the conductive pillars 30 and 31; the side of the plastic-sealed body away from the carrier 10 is thinned by a grinding process to expose the conductive pillars 30 and the superimposed conductive pillars 31 on the bare crystal 20, so as to form a package monomer 40b. The package monomer 40b includes two bare crystals 20, two conductive pillars 30, a superimposed conductive pillar 31, and two thinned plastic-sealed bodies. Figure 2 It can be clearly seen that in this embodiment, a plastic package body is injection molded on the packaging monomer 40a to form another packaging monomer 40b, and the new plastic package body is directly formed on the previous packaging monomer 40a.

[0050] S17, reference Figure 2 , a conductive pillar 31 of a preset height is stacked on the conductive pillars 30 and 31 exposed by the packaging monomer 40b. The details are the same as step S14.

[0051] S18, Ref. Figure 2 , a bare die 20 carrying a conductive pillar 30 is staggered and stacked on the package monomer 40b, and the conductive pillars 31 stacked on the package monomer 40b are staggered with the conductive pillars 30 of the stacked bare die 20 and have the same top surface height. The details are the same as step S15.

[0052] S19, reference Figure 2 , a packaging unit 40c is formed on the carrier 10, which plastic-encapsulates the original packaging unit 40b, the stacked conductive pillars 31, the bare die 20 stacked on the original packaging unit 40b, and the conductive pillars 30, and the top surfaces of all the conductive pillars 30 and 31 are exposed on the upper surface of the packaging unit 40c. The details are the same as step S16.

[0053] S20, reference Figure 3, a conductive column 31 of a preset height is stacked on the conductive columns 30 and 31 exposed by the packaging unit 40c. The details are the same as step S14.

[0054] S21, Reference Figure 3 , a bare die 20 carrying a conductive pillar 30 is staggered and stacked on the package monomer 40c, and the conductive pillars 31 stacked on the package monomer 40c are staggered with the conductive pillars 30 of the stacked bare die 20 and have the same top surface height. The details are the same as step S15.

[0055] S22, Ref. Figure 3 , a packaging unit 40d is formed on the carrier 10, which plastic-encapsulates the original packaging unit 40c, the stacked conductive pillars 31, the bare die 20 stacked on the original packaging unit 40b, and the conductive pillars 30, and the top surfaces of all the conductive pillars 30 and 31 are exposed on the upper surface of the packaging unit 40d. The details are the same as step S16.

[0056] The above steps S14 to S16 are repeated multiple times to stack the four bare dies 20 together in a staggered manner.

[0057] When the bare die 20 are stacked as above, the bare die 20 are stacked on the carrier 10 in a staggered manner in one direction.

[0058] S23, Ref. Figure 4 A redistribution layer 50 electrically connected to the conductive pillars 30 and 31 is formed on the upper surface of the finally formed package monomer 40d. The redistribution layer 50 has a pad 51 on one side adjacent to the package monomer 40d, and the pad 51 is electrically connected to the conductive pillars 30 and 31 exposed on the surface of the package monomer 40d.

[0059] S24, reference Figure 4 A solder foot 60 is made on the side of the redistribution layer 50 away from the package unit 40d to form a stacked chip package structure. The solder foot 60 can be a solder ball or a solder block. In this embodiment, the solder foot 60 is a solder ball.

[0060] S25, reference Figure 4 , debonding the carrier board 10 and the stacked chip packaging structure.

[0061] The temporary bonding layer 11 is a structure of laser debonding, etc., where a laser is used to penetrate the carrier 10 and act on the temporary bonding layer 11, so that the temporary bonding layer 11 is dissociated, and the carrier 10 is removed from the stacked chip packaging structure.

[0062] Embodiment 2: refer to Figures 7 and 8 The present invention discloses a stacked chip packaging method of stacking packaging, including steps S11a to S19a.

[0063] S11a, ref. Figure 7 Provide a carrier 10, provide a plurality of bare crystals 20 with conductive pillars 30 of a first height, and provide a bare crystal 20 with conductive pillars 32 of a second height. The electrodes of the bare crystals 20 are located on one side of the bare crystal symmetry line, and the conductive pillars 30 and 32 are respectively protruded on the electrodes corresponding to the bare crystals 20.

[0064] refer to Figure 5 , is a flow chart of providing a bare die 20 having a conductive pillar 30 of a first height, which specifically includes steps S111 to S114.

[0065] S111, providing a wafer 20a, the surface of the wafer 20a already has a surface electrode, and a passivation insulating layer is formed around the electrode.

[0066] S112, a conductive column 30 of a first height is produced on the electrode of the wafer 20a by an electroplating process. Specifically, a copper electroplating seed layer is produced on the electrode surface of the wafer 20a by sputtering or other deposition processes. A photoresist layer is prepared on the electroplating seed layer, and the photoresist layer exposes the area that needs subsequent electroplating. Copper column electroplating is performed on the electroplating seed layer exposed on the photoresist layer to prepare a copper column of a first height as the conductive column 30, and the photoresist layer and the excess electroplating seed layer are removed.

[0067] S113, thinning the substrate on the back side of the wafer 20a.

[0068] S114, cutting the thinned wafer 20b to obtain a plurality of bare crystals 20 with conductive pillars 30. The upper surface of the bare crystal 20 has an electrode, and the electrode is located on one side of the bare core symmetry line.

[0069] refer to Fig. 9 , is a flow chart of providing a bare die 20 having a conductive pillar 32 of a second height, which specifically includes steps S115 to S118.

[0070] S115, providing a wafer 20a, the surface of the wafer 20a already has a surface electrode, and a passivation insulating layer is formed around the electrode.

[0071] S116, a conductive column 32 of a second height is produced on the electrode of the wafer 20a by an electroplating process. Specifically, a copper electroplating seed layer is produced on the electrode surface of the wafer 20a by sputtering or other deposition processes. A photoresist layer is prepared on the electroplating seed layer, and the photoresist layer exposes the area that needs subsequent electroplating. Copper column electroplating is performed on the electroplating seed layer exposed on the photoresist layer to prepare a copper column of a second height as the conductive column 32, and the photoresist layer and the excess electroplating seed layer are removed.

[0072] S117, thinning the substrate on the back side of the wafer 20a.

[0073] S118, cutting the thinned wafer 20b to obtain a plurality of bare crystals 20 with conductive pillars 32. The upper surface of the bare crystal 20 has an electrode, and the electrode is located on one side of the bare core symmetry line.

[0074] S12a, ref. Figure 7 , a bare die 20 with a conductive pillar 30 of a first height and a bare die 20 with a conductive pillar 32 of a second height are sequentially stacked on the carrier 10, and the top surfaces of the conductive pillars 30 and the conductive pillars 32 are made equal in height after stacking. The bare die 20 with the conductive pillars 30 of the first height is stacked first, and then the bare die 20 with the conductive pillars 32 of the second height is staggeredly stacked on the bare die 20 with the conductive pillars 30 of the first height. The height difference between the conductive pillars 32 and the conductive pillars 30 matches the thickness of the bare die 20, for example, the height difference is equal to the sum of the thickness of the bare die 20 and the thickness of the adhesive layer used during stacking.

[0075] Among them, reference Figure 6 , before stacking the two bare crystals 20 on the carrier 10, it also includes steps S121 to S122. S121, providing a carrier 10, forming a temporary bonding adhesive layer 11 on the carrier 10, and forming a black insulating layer 12 on the temporary bonding adhesive layer 11. In step S12, one of the bare crystals 20 is stacked on the black insulating layer 12. Preferably, forming the black insulating layer 12 on the temporary bonding adhesive layer 11 is specifically: pasting a black insulating film on the temporary bonding adhesive layer 11. Among them, the bare crystal 20 is pasted and fixed on the black insulating layer 12.

[0076] In this embodiment, two bare dies 30 with conductive pillars are sequentially staggered and stacked on the carrier 10 , but the present invention is not limited thereto. Three or four bare dies 30 may also be sequentially staggered and stacked on the carrier 10 at one time.

[0077] S13a, ref. Figure 7 A packaging monomer 41 a is formed on the carrier 10 to plastic-encapsulate the bare die 20 and the conductive pillars, so that the top surfaces of all the conductive pillars 30 and 32 are exposed on the upper surface of the packaging monomer 41 a.

[0078] Specifically, the carrier 10 is plastic-sealed and cured to form a plastic-sealed body, which fully encapsulates the two bare dies 20, the conductive pillars 30, and the conductive pillars 32, and the plastic-sealed body encapsulates the top surfaces of the conductive pillars 30 and 32; the side of the plastic-sealed body away from the carrier 10 is thinned by a grinding process to expose the conductive pillars 30 and 32 on the bare dies 20, so as to form a package monomer. The package monomer includes two bare dies 20, the conductive pillars 30, the conductive pillars 33, and the thinned plastic-sealed body.

[0079] S14a, reference Figure 7 A conductive pillar 33 of a preset height is stacked on the conductive pillars 30 and 32 exposed by the packaging monomer 41 a.

[0080] The height of the stacked conductive pillars 33 is determined according to the subsequently stacked bare crystals 20 and the height of the conductive pillars 30 thereon. In this embodiment, the height of the stacked conductive pillars 33 is equal to the thickness of the two bare crystals 20 plus the height of the conductive pillars 30 thereon plus the thickness of the adhesive layer used during stacking.

[0081] The conductive pillar 33 is superimposed on the top surface of the conductive pillars 30 and 32 exposed by the package monomer 41a by using an electroplating process. Specifically, it includes: a copper electroplating seed layer is made on the surface of the package monomer 41a by sputtering or other deposition processes. A photoresist layer is prepared on the electroplating seed layer, and the photoresist layer exposes the area that needs subsequent electroplating. Copper pillars are electroplated on the electroplating seed layer exposed on the photoresist layer to prepare copper pillars of a preset height as the conductive pillars 33, and the photoresist layer and the excess electroplating seed layer are removed.

[0082] S15a, ref. Figure 7 A bare crystal 20 with a conductive column 30 of a first height and a bare crystal 20 with a conductive column 32 of a second height are stacked on the original package monomer 41a in sequence, and the conductive column 33 stacked on the package monomer 41a is staggered with the conductive columns 30 and 31 of the stacked bare crystal 20 and has the same top surface height.

[0083] The bare die 20 carrying the conductive pillars 30 is offsetly pasted on the package monomer 41 a through an adhesive layer. Specifically, the adhesive layer can be formed by curing an insulating adhesive or a cured insulating adhesive film.

[0084] S16a, ref. Figure 8 A packaging monomer 41b is formed on the packaging monomer 41a to plastic-encapsulate the bare die 20 and the conductive pillars 30 and 32, and the top surfaces of all the conductive pillars 30, 33, and 32 are exposed on the upper surface of the packaging monomer 41b.

[0085] Specifically, the plastic package is formed on the carrier 10 and cured to form a plastic package body, which fully encapsulates the four bare chips 20 and the related conductive pillars 30, 32, 33, and the side of the plastic package body away from the carrier 10 is thinned by a grinding process to expose the top surface of the conductive pillars 30, 32, 33, so as to form a package monomer 41b. Figure 8It can be clearly seen that in this embodiment, a plastic encapsulation body is plastic-encapsulated on the encapsulation monomer 41a to form another encapsulation monomer 41b, and the new plastic encapsulation body is directly formed on the previous encapsulation monomer 41a. Of course, different from this, refer to Fig.10 In another embodiment, the new packaging unit 41c directly wraps the previous packaging unit 41a.

[0086] S17a, ref. Figure 8 A redistribution layer 50 electrically connected to the conductive pillars 30, 33 and 32 is formed on the upper surface of the finally formed package monomer 41b. The redistribution layer 50 has a pad 51 on one side adjacent to the package monomer 41b, and the pad 51 is electrically connected to the conductive pillars 30, 33 and 32 exposed on the surface of the package monomer 41b.

[0087] S18a, ref. Figure 8 A solder foot 60 is made on the side of the redistribution layer 50 away from the package monomer 41b to form a stacked chip package structure. The solder foot 60 can be a solder ball or a solder block. In this embodiment, the solder foot 60 is a solder ball.

[0088] S19a, ref. Figure 8 , debonding the carrier board 10 and the stacked chip packaging structure.

[0089] The temporary bonding layer 11 is a structure of laser debonding, etc., where laser or ultraviolet light is used to penetrate the carrier 10 and act on the temporary bonding layer 11, so that the temporary bonding layer 11 is dissociated, and the carrier 10 is removed from the stacked chip packaging structure.

[0090] Embodiment 3: refer to Figures 11 to 13 The present invention discloses a stacked chip packaging method of stacking packaging, including steps S11a to S22b.

[0091] S11a, ref. Figure 7 Provide a carrier 10, provide a plurality of bare crystals 20 with conductive pillars 30 of a first height, and provide a bare crystal 20 with conductive pillars 32 of a second height. The electrodes of the bare crystals 20 are located on one side of the bare crystal symmetry line, and the conductive pillars 30 and 32 are respectively protruded on the electrodes corresponding to the bare crystals 20.

[0092] refer to Figure 5 , is a flow chart of providing a bare die 20 having a conductive pillar 30 of a first height, which specifically includes steps S111 to S114.

[0093] S111, providing a wafer 20a, the surface of the wafer 20a already has a surface electrode, and a passivation insulating layer is formed around the electrode.

[0094] S112, a conductive column 30 of a first height is produced on the electrode of the wafer 20a by an electroplating process. Specifically, a copper electroplating seed layer is produced on the electrode surface of the wafer 20a by sputtering or other deposition processes. A photoresist layer is prepared on the electroplating seed layer, and the photoresist layer exposes the area that needs subsequent electroplating. Copper column electroplating is performed on the electroplating seed layer exposed on the photoresist layer to prepare a copper column of a first height as the conductive column 30, and the photoresist layer and the excess electroplating seed layer are removed.

[0095] S113, thinning the substrate on the back side of the wafer 20a.

[0096] S114, cutting the thinned wafer 20b to obtain a plurality of bare crystals 20 with conductive pillars 30. The upper surface of the bare crystal 20 has an electrode, and the electrode is located on one side of the bare core symmetry line.

[0097] refer to Fig. 9 , is a flow chart of providing a bare die 20 having a conductive pillar 32 of a second height, which specifically includes steps S115 to S118.

[0098] S115, providing a wafer 20a, the surface of the wafer 20a already has a surface electrode, and a passivation insulating layer is formed around the electrode.

[0099] S116, a conductive column 32 of a second height is produced on the electrode of the wafer 20a by an electroplating process. Specifically, a copper electroplating seed layer is produced on the electrode surface of the wafer 20a by sputtering or other deposition processes. A photoresist layer is prepared on the electroplating seed layer, and the photoresist layer exposes the area that needs subsequent electroplating. Copper column electroplating is performed on the electroplating seed layer exposed on the photoresist layer to prepare a copper column of a second height as the conductive column 32, and the photoresist layer and the excess electroplating seed layer are removed.

[0100] S117, thinning the substrate on the back side of the wafer 20a.

[0101] S118, cutting the thinned wafer 20b to obtain a plurality of bare crystals 20 with conductive pillars 32. The upper surface of the bare crystal 20 has an electrode, and the electrode is located on one side of the bare core symmetry line.

[0102] S12a, ref. Fig.11, a bare die 20 with a conductive pillar 30 of a first height and a bare die 20 with a conductive pillar 32 of a second height are sequentially stacked on the carrier 10, and the top surfaces of the conductive pillars 30 and 32 are made equal in height after stacking. The bare die 20 with the conductive pillars 30 of the first height is stacked first, and then the bare die 20 with the conductive pillars 32 of the second height is staggeredly stacked on the bare die 20 with the conductive pillars 30 of the first height. The height difference between the conductive pillars 32 and the conductive pillars 33 matches the thickness of the bare die 20, for example, the height difference is equal to the sum of the thickness of the bare die 20 and the thickness of the adhesive layer used during stacking.

[0103] Among them, reference Figure 6 , before stacking the two bare crystals 20 on the carrier 10, it also includes steps S121 to S122. S121, providing a carrier 10, forming a temporary bonding adhesive layer 11 on the carrier 10, and forming a black insulating layer 12 on the temporary bonding adhesive layer 11. In step S12, one of the bare crystals 20 is stacked on the black insulating layer 12. Preferably, forming the black insulating layer 12 on the temporary bonding adhesive layer 11 is specifically: pasting a black insulating film on the temporary bonding adhesive layer 11. Among them, the bare crystal 20 is pasted and fixed on the black insulating layer 12.

[0104] In this embodiment, two bare dies 30 with conductive pillars are sequentially staggered and stacked on the carrier 10 , but the present invention is not limited thereto. Three or four bare dies 30 may also be sequentially staggered and stacked on the carrier 10 at one time.

[0105] S13a, ref. Fig.11 A packaging monomer 41 a is formed on the carrier 10 to plastic-encapsulate the bare die 20 and the conductive pillars, so that the top surfaces of all the conductive pillars 30 and 32 are exposed on the upper surface of the packaging monomer 41 a.

[0106] Specifically, the carrier 10 is plastic-sealed and cured to form a plastic-sealed body, which fully encapsulates the two bare dies 20, the conductive pillars 30, and the conductive pillars 32, and the side of the plastic-sealed body away from the carrier 10 is thinned by a grinding process to expose the conductive pillars 30 and 32 on the bare dies 20, so as to form a package monomer. The package monomer includes the two bare dies 20, the conductive pillars 30, the conductive pillars 33, and the thinned plastic-sealed body.

[0107] S14a, reference Fig.11 A conductive pillar 33 of a preset height is stacked on the conductive pillars 30 and 32 exposed by the packaging monomer 41 a.

[0108] The height of the stacked conductive pillars 33 is determined according to the subsequently stacked bare crystals 20 and the height of the conductive pillars 30 thereon. In this embodiment, the height of the stacked conductive pillars 33 is equal to the thickness of the two bare crystals 20 plus the height of the conductive pillars 30 thereon plus the thickness of the adhesive layer used during stacking.

[0109] The conductive pillar 33 is superimposed on the top surface of the conductive pillars 30 and 32 exposed by the package monomer 41a by using an electroplating process. Specifically, it includes: a copper electroplating seed layer is made on the surface of the package monomer 41a by sputtering or other deposition processes. A photoresist layer is prepared on the electroplating seed layer, and the photoresist layer exposes the area that needs subsequent electroplating. Copper pillars are electroplated on the electroplating seed layer exposed on the photoresist layer to prepare copper pillars of a preset height as the conductive pillars 33, and the photoresist layer and the excess electroplating seed layer are removed.

[0110] S15b, ref. Fig.11 , the top surface of the conductive pillar 33 of another package monomer 41a is facing upward and is offset and stacked on the original package monomer 41a, so that the exposed conductive pillar 33 on the other package monomer 41a is offset from the stacked conductive pillar 33 on the original package monomer 41a and the top surface is at the same height.

[0111] Another packaging monomer 41a is offset and pasted on the original packaging monomer 41a through an adhesive layer. Specifically, the adhesive layer can be formed by curing an insulating adhesive or a cured insulating adhesive film.

[0112] S16c, ref. Fig.11 A packaging monomer 42a is formed on the carrier 10, which plastic-seales the original packaging monomer 41a, the superimposed packaging monomer 41a and the conductive column 33, and the top surfaces of all the conductive columns 30, 33 and 32 are exposed on the upper surface of the packaging monomer 42a.

[0113] S17b, ref. Fig.12 A redistribution layer 50 electrically connected to the conductive pillars 30, 33 and 32 is formed on the upper surface of the finally formed package monomer 42a. The redistribution layer 50 has a pad 51 on one side adjacent to the package monomer 41d, and the pad 51 is electrically connected to the conductive pillars 30, 33 and 32 exposed on the surface of the package monomer 41d.

[0114] S18b, ref. Fig.12 , the top surface of the conductive pillar 33 of another package monomer 41a is facing upward and is offset and stacked on the original package monomer 42a, so that the conductive pillar 33 exposed on the other package monomer 41a is offset from the conductive pillar 33 stacked on the original package monomer 42a and the top surface is at the same height.

[0115] Another packaging unit 41a is offset and pasted on the original packaging unit 42a through an adhesive layer. Specifically, the adhesive layer can be formed by curing an insulating adhesive or a cured insulating adhesive film.

[0116] S19b, ref. Fig.12A packaging monomer 42b is formed on the carrier 10, which plastic-seales the original packaging monomer 42a, the superimposed packaging monomer 41a and the conductive column 33, and the top surfaces of all the conductive columns 30, 33 and 32 are exposed on the upper surface of the packaging monomer 42a.

[0117] S20b, ref. Fig.13 A redistribution layer 50 connected to the conductive pillars 30, 33 and 32 is formed on the upper surface of the finally formed package monomer 42b. The redistribution layer 50 has a pad 51 on one side adjacent to the package monomer 42b, and the pad 51 is electrically connected to the conductive pillars 30, 33 and 32 exposed on the surface of the package monomer 42b.

[0118] S21b, ref. Fig.13 A solder foot 60 is made on the side of the redistribution layer 50 away from the package monomer 42b to form a stacked chip package structure. The solder foot 60 can be a solder ball or a solder block. In this embodiment, the solder foot 60 is a solder ball.

[0119] S22b, ref. Fig.13 , debonding the carrier board 10 and the stacked chip packaging structure.

[0120] The temporary bonding layer 11 is a structure of laser debonding, etc., where laser or ultraviolet light is used to penetrate the carrier 10 and act on the temporary bonding layer 11, so that the temporary bonding layer 11 is dissociated, and the carrier 10 is removed from the stacked chip packaging structure.

[0121] Embodiment 4: refer to Figures 14 to 16 The present invention discloses a stacked chip packaging method of stacking packaging, including steps S11a to S21c.

[0122] S11a, ref. Figure 7 , providing a carrier 10, providing a plurality of bare crystals 20 having conductive pillars 30 of a first height, and providing a bare crystal 20 having conductive pillars 32 of a second height. The electrodes of the bare crystal 20 are located on one side of the bare crystal symmetry line, and the conductive pillars 30, 32 are respectively protruded on the electrodes corresponding to the bare crystal 20. The bare crystal 20 in this embodiment is a thinned bare crystal 20.

[0123] refer to Figure 5 , is a flow chart of providing a bare die 20 having a conductive pillar 30 of a first height, which specifically includes steps S111 to S114.

[0124] S111, providing a wafer 20a, the surface of the wafer 20a already has a surface electrode, and a passivation insulating layer is formed around the electrode.

[0125] S112, a conductive column 30 of a first height is produced on the electrode of the wafer 20a by an electroplating process. Specifically, a copper electroplating seed layer is produced on the electrode surface of the wafer 20a by sputtering or other deposition processes. A photoresist layer is prepared on the electroplating seed layer, and the photoresist layer exposes the area that needs subsequent electroplating. Copper column electroplating is performed on the electroplating seed layer exposed on the photoresist layer to prepare a copper column of a first height as the conductive column 30, and the photoresist layer and the excess electroplating seed layer are removed.

[0126] S113, thinning the substrate on the back side of the wafer 20a.

[0127] S114, cutting the thinned wafer 20b to obtain a plurality of bare crystals 20 with conductive pillars 30. The upper surface of the bare crystal 20 has an electrode, and the electrode is located on one side of the bare core symmetry line.

[0128] refer to Fig. 9 , is a flow chart of providing a bare die 20 having a conductive pillar 32 of a second height, which specifically includes steps S115 to S118.

[0129] S115, providing a wafer 20a, the surface of the wafer 20a already has a surface electrode, and a passivation insulating layer is formed around the electrode.

[0130] S116, a conductive column 32 of a second height is produced on the electrode of the wafer 20a by an electroplating process. Specifically, a copper electroplating seed layer is produced on the electrode surface of the wafer 20a by sputtering or other deposition processes. A photoresist layer is prepared on the electroplating seed layer, and the photoresist layer exposes the area that needs subsequent electroplating. Copper column electroplating is performed on the electroplating seed layer exposed on the photoresist layer to prepare a copper column of a second height as the conductive column 32, and the photoresist layer and the excess electroplating seed layer are removed.

[0131] S117, thinning the substrate on the back side of the wafer 20a.

[0132] S118, cutting the thinned wafer 20b to obtain a plurality of bare crystals 20 with conductive pillars 32. The upper surface of the bare crystal 20 has an electrode, and the electrode is located on one side of the bare core symmetry line.

[0133] S12a, ref. Fig.11, a bare die 20 with a conductive pillar 30 of a first height and a bare die 20 with a conductive pillar 32 of a second height are sequentially stacked on the carrier 10, and the top surfaces of the conductive pillars 30 and the conductive pillars 32 are made equal in height after stacking. The bare die 20 with the conductive pillars 30 of the first height is stacked first, and then the bare die 20 with the conductive pillars 32 of the second height is staggeredly stacked on the bare die 20 with the conductive pillars 30 of the first height. The height difference between the conductive pillars 32 and the conductive pillars 30 matches the thickness of the bare die 20, for example, the height difference is equal to the sum of the thickness of the bare die 20 and the thickness of the adhesive layer used during stacking.

[0134] Among them, reference Figure 6 , before stacking the two bare crystals 20 on the carrier 10, it also includes steps S121 to S122. S121, providing a carrier 10, forming a temporary bonding adhesive layer 11 on the carrier 10, and forming a black insulating layer 12 on the temporary bonding adhesive layer 11. In step S12, one of the bare crystals 20 is stacked on the black insulating layer 12. Preferably, forming the black insulating layer 12 on the temporary bonding adhesive layer 11 is specifically: pasting a black insulating film on the temporary bonding adhesive layer 11. Among them, the bare crystal 20 is pasted and fixed on the black insulating layer 12.

[0135] In this embodiment, two bare dies 30 with conductive pillars are sequentially staggered and stacked on the carrier 10 , but the present invention is not limited thereto. Three or four bare dies 30 may also be sequentially staggered and stacked on the carrier 10 at one time.

[0136] S13a, ref. Fig.14 A packaging monomer 41 a is formed on the carrier 10 to plastic-encapsulate the bare die 20 and the conductive pillars, so that the top surfaces of all the conductive pillars 30 and 32 are exposed on the upper surface of the packaging monomer 41 a.

[0137] Specifically, the carrier 10 is plastic-encapsulated and cured to form a plastic-encapsulated body, which encapsulates the two bare dies 20, the conductive pillars 30, and the conductive pillars 32, and the side of the plastic-encapsulated body away from the carrier 10 is thinned by a grinding process to expose the conductive pillars 30 and 32 on the bare die 20, so as to form a package monomer. The package monomer includes the two bare dies 20, the conductive pillars 30, the conductive pillars 32, and the thinned plastic-encapsulated body.

[0138] S14c, ref. Fig.14 A conductive pillar 31 of a first height is stacked on the conductive pillars 30 and 32 exposed by the packaging monomer 41 a.

[0139] Among them, the conductive pillar 31 is superimposed on the top surface of the conductive pillars 30 and 32 exposed by the package monomer 41a by using an electroplating process. Specifically, it includes: a copper electroplating seed layer is made on the surface of the package monomer 41a by sputtering or other deposition processes. A photoresist layer is prepared on the electroplating seed layer, and the photoresist layer exposes the area that needs subsequent electroplating. Copper pillars are electroplated on the electroplating seed layer exposed on the photoresist layer to prepare copper pillars of a preset height as the conductive pillars 31, and the photoresist layer and the excess electroplating seed layer are removed.

[0140] S15c, ref. Fig.14 A bare die 20 carrying a conductive pillar 30 is staggered and stacked on the package monomer 41 a, and the conductive pillar 31 stacked on the package monomer 41 a is staggered with the conductive pillar 30 of the stacked bare die 20 and has the same top surface height.

[0141] S16d, ref. Fig.14 A packaging monomer 43a is formed on the carrier 10, which plastic-encapsulates the original packaging monomer 41a, the stacked conductive pillars 31, the bare die 20 stacked on the original packaging monomer 41a, and the conductive pillars 30, and the top surfaces of all the conductive pillars 30 and 31 are exposed on the upper surface of the packaging monomer 43a.

[0142] S17c, ref. Fig.15 A conductive column 34 of a third height is stacked on the top surface of the conductive columns 30 and 32 exposed in the package monomer 43a. The height of the conductive column 34 matches the thickness of the package monomer 43a. Specifically, the height of the conductive column 34 is equal to the thickness of the package monomer 43a plus the thickness of an adhesive layer.

[0143] S18c, ref. Fig.15 , the top surface of the conductive pillar of another package monomer 43a is facing upward and is staggered and stacked on the original package monomer 43a, so that the conductive pillars 30 and 31 exposed on the other package monomer 43a are staggered with the conductive pillars 34 stacked on the original package monomer 43a and the top surfaces are at the same height. The other package monomer 43a is pasted and stacked on the original package monomer 43a through an adhesive layer.

[0144] Among them, another packaging unit 43a can be Fig.14 The step S16d of step S11a is formed, and after being debonded from the carrier 10, an independent package monomer 43a is formed. Of course, another package monomer 43a with the same structure can be stacked on the original package monomer 43a, and package monomers with different structures can also be stacked thereon, such as stacking independent package monomers 41a, 41b, etc.

[0145] S19c, ref. Fig.15, plastic-encapsulated and cured on the carrier 10 to form a packaging monomer 43b that plastic-encapsulates the original packaging monomer 43a, the superimposed packaging monomer 43a and the conductive column 34, and the top surfaces of all the conductive columns 30, 34 and 31 are exposed on the upper surface of the packaging monomer 43b.

[0146] S20c, ref. Fig.16 A redistribution layer 50 electrically connected to the conductive pillars 30, 34 and 31 is formed on the upper surface of the finally formed package monomer 43b. The redistribution layer 50 has a pad 51 on one side adjacent to the package monomer 41d, and the pad 51 is electrically connected to the conductive pillars 30, 34 and 31 exposed on the surface of the package monomer 43b.

[0147] S20c, ref. Fig.16 A solder foot 60 is made on the side of the redistribution layer 50 away from the package monomer 43b to form a stacked chip package structure. The solder foot 60 can be a solder ball or a solder block. In this embodiment, the solder foot 60 is a solder ball.

[0148] S21c, ref. Fig.16 , debonding the carrier board 10 and the stacked chip packaging structure.

[0149] The temporary bonding layer 11 is a structure of laser debonding, etc., where laser or ultraviolet light is used to penetrate the carrier 10 and act on the temporary bonding layer 11, so that the temporary bonding layer 11 is dissociated, and the carrier 10 is removed from the stacked chip packaging structure.

[0150] The above disclosure is only the preferred embodiment of the present invention, which certainly cannot be used to limit the scope of rights of the present invention. Therefore, equivalent changes made according to the scope of the patent application of the present invention are still within the scope covered by the present invention.

Claims

1. A stacked chip packaging method for stacking packaging, characterized in that: include: Step 1, providing a carrier board and providing a plurality of bare crystals having conductive pillars, wherein the conductive pillars are electrically connected to electrodes of the bare crystals; Step 2, stacking one of the bare die on the carrier or stacking a plurality of the bare die on the carrier in a staggered manner, and the tops of the conductive pillars on all the bare die are staggered and exposed and the top surfaces are at the same height; Step 3, forming a packaging unit on the carrier board to plastic-encapsulate the bare die and the conductive pillars, so that the top surfaces of all the conductive pillars are exposed on the upper surface of the packaging unit; Step 4, stacking a conductive column of a preset height on the top surface of the conductive column exposed on the package monomer, stacking one or more bare crystal conductive columns on the package monomer in sequence with the top surface facing upward, or stacking the top surface of the conductive column of another independent package monomer on the original package monomer with the top surface facing upward, and making the conductive columns of all the package monomers staggered with the conductive columns exposed on the original package body and having the same top surface height; Step 5, forming another packaging unit on the carrier board, which plastic-encapsulates the original packaging unit, the stacked conductive pillars, and the bare die or packaging unit stacked on the original packaging unit, and makes the top surfaces of all the conductive pillars exposed on the upper surface of the packaging unit, and repeating steps 4 to 5 until a preset number of bare die layers are stacked on the carrier board; Step 6, forming a redistribution layer electrically connected to the conductive pillar on the upper surface of the finally formed packaging unit; Step 7, making solder fillets on a side of the redistribution layer away from the package monomer to form a stacked chip package structure; Step 8: debonding the carrier and the stacked chip packaging structure.

2. The stacked chip packaging method of claim 1, wherein: The independent packaging unit is manufactured by step 1 to step 3, or step 1 to step 5, and the independent packaging unit is a packaging unit debonded from the carrier.

3. The stacked chip packaging method of overlay packaging according to claim 1, characterized in that: The structure of another independent packaging unit superimposed on the original packaging unit is the same as or different from that of the original packaging unit.

4. The stacked chip packaging method of overlay packaging according to claim 1, characterized in that: The electrode of the bare die is located on one side of the symmetry line of the bare die, and the conductive column is formed on the electrode of the bare die.

5. The stacked chip packaging method of claim 1, wherein: Multiple bare dies are stacked in sequence on the carrier or the packaging unit in a staggered manner, and the number of the bare dies is 2 or 3.

6. The stacked chip packaging method of overlay packaging as claimed in claim 1, characterized in that: In step 5, the newly formed packaging unit is superimposed on the original packaging unit or wraps the original packaging unit.

7. The stacked chip packaging method of claim 1, wherein: Providing a bare crystal with a conductive column specifically includes: providing a wafer, making a conductive column on an electrode of the wafer by an electroplating process, thinning the substrate on the back of the wafer, and cutting the thinned wafer to obtain a number of bare crystals with a conductive column, wherein the bare crystal is a thinned bare core.

8. The stacked chip packaging method of overlay packaging as claimed in claim 1, characterized in that: In step 4, a conductive column of a preset height is manufactured on the top surface of the conductive column of the package unit by an electroplating process.

9. The stacked chip packaging method of claim 1, wherein: In step 4 , the preset height of the stacked conductive pillars matches the thickness of the structure to be stacked in step 5 .

10. The stacked chip packaging method of claim 1, wherein: In step 10, when the plurality of bare die are stacked in sequence on the carrier or the package unit in an offset manner, the height difference of the conductive pillars on the plurality of bare die matches the thickness of the bare die, so that the tops of all the conductive pillars are at the same height after the plurality of bare die are stacked in sequence.

11. The stacked chip packaging method of claim 1, wherein: On the carrier, all the bare crystals are stacked in a staggered manner in a first direction from bottom to top, and the electrodes of the bare crystals are located in a second direction of the bare crystal symmetry line, and the second direction is opposite to the first direction.

12. The stacked chip packaging method of claim 1, wherein: Before step 2, a temporary bonding adhesive layer is formed on the carrier, a black insulating layer is formed on the temporary bonding adhesive layer, and one or more bare dies are stacked on the black insulating layer.

13. The stacked chip packaging method of claim 12, wherein: The black insulating layer is formed on the temporary bonding adhesive layer by pasting a black film on the temporary bonding adhesive layer.

14. The stacked chip packaging method of claim 1, wherein: Forming a packaging unit on the carrier board to encapsulate the bare die and the conductive pillars specifically includes: encapsulating the carrier board to form a plastic encapsulation body that fully encapsulates the bare die and the conductive pillars, and polishing a side of the plastic encapsulation body away from the carrier board until the top surface of the conductive pillar is exposed; Forming another packaging monomer on the carrier board that plastic-encapsulates the original packaging monomer, the superimposed conductive pillars, and the bare die or packaging monomer stacked on the original packaging monomer specifically includes: plastic-encapsulating on the carrier board to form a plastic-encapsulated body that fully encapsulates the original packaging monomer, the superimposed conductive pillars, and the bare die or packaging monomer stacked on the original packaging monomer, and polishing the side of the plastic-encapsulated body away from the carrier until the top surface of the conductive pillar is exposed.

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