High-power TVS packaging structure and packaging method thereof

Abstract

The invention discloses a high-power TVS (Transient Voltage Suppressor) packaging structure and a packaging method thereof. The process comprises the following steps: chip packaging: mounting a chip on a substrate electroplated with pins, packaging the chip, and grinding and packaging the top surface until the output end of the front surface of the chip is exposed; drilling and electroplating: vertically drilling on the top surface of the encapsulation until the pins are exposed, and electroplating stand columns in drilled holes; a circuit layer is electroplated on the top surface of the encapsulation, the circuit layer electrically connects the output end of the chip with the stand column, the circuit layer, the front output end of the chip and the stand column are electroplated into a whole, the circuit layer comprises a thin and narrow section, encapsulation is continued, the circuit layer is completely encapsulated, and when the circuit input power is larger than the rated power of the chip, the thin and narrow section is disconnected; according to the packaging body, abnormal overvoltage exceeding the breakdown voltage of the packaging body occurs in the circuit, heat accumulation occurs at the thin and narrow section of the packaging body, the packaging body is fused into an open circuit, and the situation that fire disasters are caused by burning of the packaging body is avoided.

Description

Technical Field

[0001] The present invention belongs to the technical field of chip packaging, and in particular relates to a high-power TVS packaging structure and a packaging method thereof. Background Art

[0002] TVS (Transient Voltage Suppressor) is a semiconductor device used to quickly suppress transient overvoltage and protect electronic equipment from voltage transients and surges. It is also called transient voltage suppression diode. It is a new product developed on the basis of voltage regulator technology. When the two ends of the TVS tube are subjected to a momentary high-energy impact, it can suddenly reduce its impedance at an extremely high speed, while absorbing a large current, clamping the voltage between its two ends to a predetermined value, thereby ensuring that the subsequent circuit components are protected from damage by transient high-energy impacts; TVS chips can be divided into high-power TVS and low-power TVS according to the power size. Generally speaking, peak pulse power ≥3000W is defined as high-power TVS.

[0003] TVS usually adopts a diode-type axial lead packaging structure. The core unit of TVS is the chip. The main material of the chip is a semiconductor silicon wafer or a selenium wafer. During packaging, the electrode of the chip is electrically led out and then the chip and the electrical lead-out circuit are encapsulated using an encapsulation material encapsulation process. The encapsulation shell plays the role of placing, fixing, sealing, protecting the chip and enhancing the electrical and thermal performance. The interface for electrical installation outside the encapsulation body is the pin. The pin establishes an electrical connection with other devices through the wires on the printed board, and is a bridge between the internal world of the chip and the external circuit of the encapsulation body.

[0004] After the high-power TVS chip is packaged, it is connected in parallel with the protected device. When the circuit is working normally, the TVS chip is in the cut-off state and does not affect the circuit operation. When an abnormal overvoltage occurs in the circuit and reaches the breakdown voltage of the TVS chip, the chip fails directly, and the TVS diode changes from a high-resistance state to a low-resistance state, becoming a conducting circuit. In this case, the TVS tube will release high energy, damage the protected electronic components, and even cause a fire. Summary of the invention

[0005] In order to solve the above problems in the prior art, the present invention provides a high-power TVS packaging structure and a packaging method thereof.

[0006] To achieve the above object, the present invention proposes a high-power TVS packaging method, comprising the following steps: Chip packaging: mount the chip on a substrate with electroplated pins, encapsulate the chip and grind the top surface of the encapsulation until the front output terminal of the chip is exposed; Drilling and plating: vertically drill holes on the top surface of the package until the pins are exposed, and electroplate the pillars in the drilled holes; Circuit layer electroplating: The circuit layer is electroplated on the top surface of the package. The circuit layer electrically connects the chip output end with the pillar. The circuit layer, the chip front output end and the pillar are electroplated as a whole. The circuit layer contains a narrow section. Continue to encapsulate and completely encapsulate the circuit layer. When the circuit input power is greater than the rated power of the chip, the narrow section is disconnected; Product unitization: Peel off the substrate to obtain the package product unit.

[0007] Furthermore, in the chip packaging step, a substrate is provided, on which pads and pins are electroplated. After encapsulation, the pads and pin top surfaces are exposed by grinding, and the back side of the chip is mounted on the pads and encapsulated again, so that the chip, pads and pins are completely encapsulated.

[0008] Furthermore, in the circuit layer electroplating step, a film block is mounted on the corresponding position of the package top surface that exposes the chip front output end before the circuit layer is electroplated, and then the circuit layer is electroplated, and a thin and narrow section of the circuit layer is formed by passing through the film block and the position where the film block is mounted.

[0009] Furthermore, the film block is a photoresist film.

[0010] Furthermore, in the circuit layer electroplating step, the portion of the circuit layer close to the pillar is thinned by etching to form a thin and narrow section of the circuit layer.

[0011] Furthermore, in the circuit layer electroplating step, the circuit layer is horizontally laid and extended along the top surface of the package that is polished and exposed to expose the front output terminal of the chip, and the electrical properties of the front output terminal of the chip are transmitted to the pin through the circuit layer and the column.

[0012] Furthermore, in the product unitization step, after the substrate is peeled off, the pads and pins are flush with the bottom surface of the package and exposed.

[0013] A high-power TVS packaging structure includes a packaging body, wherein the packaging body encapsulates: A pad and a pin, wherein the pad is arranged on one side of the pin; The chip is mounted with the back side facing the pad and the front side of the chip is provided with an output terminal; Posts, posts are plated vertically on the pins; Circuit layer: The circuit layer electrically connects the front output terminal of the chip with the column. The circuit layer, the front output terminal of the chip and the column are electroplated as a whole. The circuit layer includes a narrow section. When the circuit input power is greater than the rated power of the chip, the narrow section is disconnected.

[0014] Furthermore, the pads and pins are formed by simultaneous electroplating on a substrate, and are polished after encapsulation to expose the pads and the top surfaces of the pins. The back side of the chip is mounted on the pads and encapsulated again, and polished to expose the front output terminal of the chip. A hole is drilled in the encapsulation surface to expose the top surface of the pin, and the column is formed by electroplating in the hole.

[0015] Furthermore, the circuit layer is horizontally laid and extended along the top surface of the package that is polished to expose the chip front output terminal. The electrical properties of the chip front output terminal are transmitted to the pins through the circuit layer and the column, and the circuit layer is continued to be encapsulated to form a package as a whole.

[0016] Furthermore, before the circuit layer is electroplated, a film block is mounted on the corresponding position of the package top surface that exposes the chip front output end, and then the circuit layer is electroplated, and a thin and narrow section of the circuit layer is formed at the position where the film block is mounted.

[0017] Furthermore, the film block is a photoresist film.

[0018] Furthermore, the portion of the circuit layer close to the pillar is thinned by etching to form a thin and narrow section of the circuit layer.

[0019] Furthermore, after the package is peeled off the substrate, the pads and pins are flush with the bottom surface of the package and exposed.

[0020] The present invention thins the circuit layer locally into a narrow section of a certain size while electroplating the circuit layer. When the package is connected in parallel to the circuit of the protected device, an abnormal overvoltage exceeding the breakdown voltage of the package appears in the circuit, and heat accumulates at the narrow section of the package, which is melted to an open circuit, thereby avoiding the burning of the package and causing a fire. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1-Figure 6 A cross-sectional view of a chip packaging step of a high-power TVS packaging method of the present invention; Figure 7-Figure 8 A cross-sectional view of a drilling and electroplating step of a high-power TVS packaging method of the present invention; Figure 9-13 It is a cross-sectional view of a circuit layer electroplating step of a high-power TVS packaging method according to an embodiment of the present invention; Figure 14-17 It is a cross-sectional view of a second embodiment of a circuit layer electroplating step of a high-power TVS packaging method of the present invention; Fig.18 This is a product cross-sectional view of Embodiment 1 of a high-power TVS packaging structure of the present invention; Fig.19 This is a product cross-sectional view of Example 2 of a high-power TVS packaging structure of the present invention.

[0022] In the figure: 1. Package; 2. Chip; 3. Pillar; 4. Circuit layer; 5. Pad; 6. Pin; 7. Narrow section. DETAILED DESCRIPTION

[0023] The content of the present invention will be explained below in conjunction with specific embodiments, examples of which are shown in the accompanying drawings, wherein the same or similar numbers throughout represent the same or similar components or components with the same or similar functions.

[0024] The directional terms mentioned in the present invention, such as: up, down, left, right, front, back, inside, outside, front, back, side, etc., are only reference directions of the drawings. The embodiments described below with reference to the drawings and the directional terms used are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention. In addition, the various specific process and material examples provided in the present invention are all those skilled in the art who can recognize the application of other processes and / or the use of other materials.

[0025] In order to better understand the purpose, structure and function of the present invention, the following is a further detailed description of a high-power TVS packaging method proposed by the present invention in conjunction with the accompanying drawings. The process includes the following steps: Chip 2 packaging: mount the chip 2 on the substrate plated with pins 6, encapsulate the chip 2 and grind the top surface of the encapsulation until the front output terminal of the chip 2 is exposed; Drilling and electroplating: vertically drill holes on the top surface of the package until the pins 6 are exposed, and electroplate the pillars 3 in the drilled holes; Circuit layer 4 electroplating: Circuit layer 4 is electroplated on the top surface of the package. Circuit layer 4 electrically connects the output end of chip 3 with pillar 3. Circuit layer 4, the front output end of chip 2 and pillar 3 are electroplated as a whole. Circuit layer 4 includes a narrow section 7. Continue encapsulation to completely encapsulate circuit layer 4. When the circuit input power is greater than the rated power of chip 2, narrow section 7 is disconnected. Product unitization: Peel off the substrate to obtain the package 1 product unit.

[0026] Among them, Figure 1-Figure 6 As shown, in the chip 2 packaging step, a substrate is provided, and pads 5 and pins 6 (such as Figure 1 As shown in the figure, the space arrangement is reasonably carried out according to the surface size of the substrate to set the number of groups of the electroplated pads 5 and pins 6, and each group is provided with a pad 5 and a pin 6. After the electroplating is completed, the pads 5 and the pins 6 are encapsulated on the substrate with an encapsulation material (as shown in the figure). Figure 2 As shown), and grind the package surface horizontally by mechanical grinding until the top surface of pad 5 and pin 6 is exposed (as shown Figure 3 Then, the chip 2 is placed with its back facing toward the pad 5 and adhered to the pad 5 by adhesive (as shown in FIG. Figure 4As shown), the functional surfaces of the front and back sides of the chip 2 are designed according to the actual situation. The chip 2 involved in this application has no output terminal on the back side of the chip 2, which can also be called the non-functional side of the chip 2. After the mounting is completed, the front side (functional side) of the chip 2 faces upward, and a chip 2 is mounted on each pad 5; the chip 2 transfers the heat to the pad 5 through the thermal conductive insulating adhesive on the back side and then dissipates it to the outside of the package 1, with high heat dissipation efficiency. If the chip 2 also has an output terminal on the back side, the adhesive is a thermal conductive and electrically conductive adhesive, which can transfer heat and realize electrical connection; after the chip 2 is mounted, the encapsulation material is continued to be used on the encapsulation surface of the encapsulation pad 5 and the pin 6 to completely encapsulate the chip 2 (such as Figure 5 As shown in the figure), continue to use mechanical horizontal grinding to encapsulate the top surface until the front output terminal of chip 2 is exposed, and pin 6 is also completely encapsulated (as shown in the figure). Figure 6 as shown).

[0027] In the present application, chip 2 is a unidirectional transient voltage suppressor (TVS) chip 2, which is an electronic circuit protection device used to protect electronic equipment from voltage transients and surges. Its internal diode has a reverse characteristic. In the electronic circuit, the positive pole of the diode is connected to the low potential end and the negative pole is connected to the high potential end. The high potential and low potential in electricity refer to high potential charges and low potential charges. The potential is low at the position far from the positive charge, which is a low potential, and the potential is high at the position close to the positive charge, which is a high potential. Therefore, the potential gradually decreases along the direction of the electric field line. At this time, almost no current flows through the diode, and the diode is in the cut-off state. This connection method is called reverse bias. When the reverse voltage at both ends of the diode increases to a certain value, the reverse current will increase sharply, and the diode loses its unidirectional conductive characteristics and conducts in the reverse direction.

[0028] Among them, Figure 7-Figure 8 As shown, in the drilling and plating step, in the chip 2 packaging step, after the chip 2 is mounted, the chip 2 is encapsulated and polished to expose the horizontal flat package surface of the front output end of the chip 2, and a hole is drilled vertically on the package surface at the corresponding position to remove part of the encapsulation material above the pin 6, so that the top surface of the pin 6 is exposed at the bottom of the drill hole (such as Figure 7 As shown in the figure, in this application, the drilling method is laser drilling, but this is not limited; and the metal-plated column 3 in the drilled hole, the pin 6 and the column 3 are made of the same material, so the column 3 is integrated with the pin 6 after electroplating, and the column 3 is electroplated to fill the drilled hole (such as Figure 8 as shown).

[0029] Among them, Figure 9-13 As shown, it is a schematic diagram of the first embodiment of the circuit layer 4 electroplating step. In the circuit layer 4 electroplating step of this embodiment, before the circuit layer 4 is electroplated, a film block (such as Fig. 9 As shown), the corresponding position here in the present application refers to the position close to the column 3, after which the circuit layer 4 is electroplated and passes through the membrane block, and the circuit layer 4 covers but does not wrap the membrane block (such as Fig.10 As shown in the figure, the two ends of the plated circuit layer 4 are connected to the front output end of the chip 2 and the pillar 3 as a whole, and the circuit layer 4 is horizontally laid and extended along the top surface of the package where the front output end of the chip 2 is exposed by grinding. The electrical properties of the front output end of the chip 2 are transmitted to the pin 6 by the circuit layer 4 and the pillar 3. The film block is a photoresist film. When the circuit layer 4 is electroplated, it is also necessary to mount a photoresist film on the top surface of the package that is not electroplated for protection. After the electroplating is completed, the photoresist film needs to be completely peeled off (as shown in the figure). Fig.11 As shown in FIG. 1 ), since the film block is also a photoresist film, it can be removed together in the subsequent electroplating process, saving the process flow. After removing the film block, the position of the film block forms a narrow section 7 of the circuit layer 4. After the electroplating of the circuit layer 4 is completed, the encapsulation material is used to continue encapsulation, so that the circuit layer 4 is completely encapsulated. The encapsulation material also fills the gap below the narrow section 7 of the circuit layer 4 after the film block is removed (as shown in FIG. 1 ). Fig.12 As shown in FIG. 1 ), the narrow section 7 becomes thinner due to the reduced electroplating under the part of the circuit layer 4. By this time, the encapsulation process is completed. Since the same encapsulation material is used, the encapsulation material becomes a complete encapsulation after multiple encapsulations. After the encapsulation is completed, the encapsulation material is cut at the cutting path position to separate it into product units, and the substrate is peeled off. The bottom surface of the pad 5 and the pin 6 is flush with the package body 1 and exposed (as shown in FIG. 1 ). Fig.13 as shown).

[0030] In this embodiment, before electroplating the circuit layer 4, a photoresist film is mounted on the top surface of the package that does not need to be electroplated for protection. This is a common method in the electroplating process in the art. At the same time, a small piece of photoresist film is also mounted on the position near the column 3 where the circuit layer 4 is electroplated. The film block is smaller than the photoresist film of other normal protective parts. After electroplating, the photoresist film is removed to form the circuit layer 4 and the narrow section 7 of the circuit layer 4. In the electroplating process, the small film block is embedded in the electroplating route, without adding or changing the process flow, and the process is simple and efficient. The narrow section 7 of the circuit layer 4 is reduced in electroplating and becomes thinner under part of the circuit layer 4, that is, the top surface of the narrow section 7 is flat and the bottom surface is concave. The size of the mounting film block is controllable, so that the size control of the narrow section 7 is more accurate. If an abnormal overvoltage occurs in the circuit, the package 1 can respond faster and eliminate the danger in time.

[0031] Among them, Figure 14-17 , which is a schematic diagram of the second embodiment of the electroplating step of the circuit layer 4. In the electroplating step of the circuit layer 4 of this embodiment, after the electroplating of the circuit layer 4 is completed (such as Fig.14 As shown in FIG. 1 ), the portion of the circuit layer 4 close to the pillar 3 is thinned by etching to form a thin narrow section 7 of the circuit layer 4, and the thin narrow section 7 is thinned by etching above a portion of the circuit layer 4 (as shown in FIG. 1 ). Fig.15 As shown, and then the encapsulation material is used to continue encapsulation, so that the circuit layer 4 is completely encapsulated (as shown Fig.16As shown in the figure, by this time, the encapsulation process is completely completed. Since the same encapsulation material is used, the encapsulation material becomes a complete encapsulation after multiple encapsulations. After the encapsulation is completed, the encapsulation material is cut at the cutting path position to separate it into product units, and the substrate is peeled off. The bottom surface of the pad 5 and the pin 6 is flush with the package body 1 and exposed (as shown in the figure). Fig.17 as shown).

[0032] In this embodiment, after the circuit layer 4 is electroplated, the part of the circuit layer 4 close to the pillar 3 is etched to form a narrow section 7, and the encapsulation material fills the etched part to avoid the situation where the encapsulation material is not filled sufficiently, causing voids and separation, and the structure is more stable and effective; The narrow section 7 of the circuit layer 4 is etched and becomes thinner above part of the circuit layer 4, that is, the bottom surface of the narrow section 7 is flat and the top surface is concave. The etching condition is adjusted by controlling the etching immersion time and parameters such as the etching flow rate and concentration, which makes it easy to observe the etching progress and achieve precise control of the etching size of the narrow section 7.

[0033] Among them, in the product unitization step, after the circuit layer 4 is completely encapsulated, the encapsulation process is completed. The number of groups of pads 5 and pins 6 is set according to the size of the substrate, that is, the number of product units that are encapsulated and processed by the process at one time is set. This application takes the encapsulation of two groups as an example. Each product unit in this application includes a chip 2, pads 5, pins 6, columns 3, circuit layers 4 and narrow sections 7. Therefore, after the process is completed, the encapsulation material needs to be cut through a cutting process to divide it into product units. Each product unit is a package body 1. The cutting path is reserved when the substrate is set. Only encapsulation material exists in the cutting path to ensure that the product unit is complete after cutting. After cutting into product units, the substrate is removed by mechanical stripping. The pads 5 and pins 6 are flush with the bottom surface of the package body 1 and exposed. The chip 2, circuit layer 4, column 3 and narrow section 7 are all encapsulated in the package body 1, and the package body 1 is a high-power TVS package device.

[0034] The package 1 of the unidirectional TVS in the present application is connected in parallel with the device to be protected, and the diode is reverse biased. When the circuit is working normally, the TVS is in the cut-off state and does not affect the circuit operation. At this time, the voltage on the negative electrode of the TVS does not exceed its reverse stand-off voltage (VRWM), which is slightly higher than the normal working voltage of the circuit, VRWM ≥ 1.1 × working voltage; when the circuit has an abnormal overvoltage and reaches the TVS breakdown voltage (breakdown voltage refers to the maximum rated voltage that the TVS can withstand: Breakdown Voltage) (VBR), which is usually 10%-15% higher than VRWM, the TVS changes from a high-resistance state to a low-resistance state, and discharges the instantaneous overcurrent caused by the abnormal overvoltage to the ground; at the same time, the abnormal overvoltage is clamped at a lower level (the set threshold), that is, the clamping voltage (Clamping Voltage Voltage (Vc) must be lower than the maximum withstand voltage of the protected device, thereby protecting the subsequent circuit from damage by abnormal overvoltage; if an abnormal overvoltage occurs in the circuit, the current passing through the TVS is too large, exceeding the surge it can withstand, or a very large DC source is mistakenly added to both ends of the TVS, causing the TVS to accumulate heat due to continuous current, leading to burning and short circuit. Although the back-end circuit is guaranteed, the TVS tube will release high energy, which will affect the protected electronic equipment and devices in the back-end circuit, and even cause a fire. The protected electronics and devices will be damaged. Equipment and devices such as temperature-sensitive sensor ICs, etc. The package 1 of the present application is a high-power TVS with a peak pulse power ≥3000W. The circuit layer 4 encapsulated in the package 1 is partially thinned into a narrow section 7, and the package 1 is connected in parallel with the protected electronic equipment and devices. When the abnormal overvoltage in the circuit directly breaks down the package 1 and fails, the narrow section 7 of the circuit layer 4 inside the package 1 is disconnected to form an open circuit, which can prevent the package 1 from becoming a low-resistance state, the instantaneous overcurrent from being discharged, and the package 1 from accumulating high heat, which may lead to greater dangers such as burning and fire.

[0035] Voltage relationship between TVS and protected device: 1. The normal operating voltage of the protected device should be ≤ the reverse shutdown voltage of the TVS, so that the TVS will not conduct during normal operation and will not affect the circuit; 2. The clamping voltage of the TVS must be less than the maximum tolerable voltage of the protected device, so that in a transient event, the TVS limits the voltage to the clamping voltage, and the clamping voltage must be low enough to protect the device; 3. The breakdown voltage of TVS should be higher than the reverse turn-off voltage of TVS, so that TVS will not conduct under normal working voltage. Usually the breakdown voltage of TVS is the voltage defined under a specific test current; 4. Voltage hierarchy order: Normal operating voltage of the protected device ≤ TVS reverse shutdown voltage ≤ TVS breakdown voltage ≤ TVS clamping voltage ≤ maximum withstand voltage of the protected device.

[0036] Taking the protected device as an on-board power function module as an example, package 1 is connected in parallel with the protected device, the working voltage of the protected device is 24V, assuming that the maximum voltage that the protected device can withstand is 60V, and the reverse shutdown voltage of TVS is ≥26.4V, then the clamping voltage of TVS needs to be ≤50V, and the breakdown voltage of TVS is ≈29.04V-30.36V; when an abnormal overvoltage occurs in the circuit, but the abnormal overvoltage is within the breakdown voltage range of TVS, the TVS will work normally and discharge current, but when the abnormal overvoltage of the circuit exceeds T VS breakdown voltage, the current passing through the TVS is too large, exceeding the surge it can withstand, and the heat accumulated by the TVS, that is, the heat accumulated on the circuit layer inside the package 1, causes the narrow section 7 to melt and form a short circuit, thereby preventing the TVS from burning and causing a fire, etc. However, the short circuit cannot protect the protected device, which may cause the protected device to be exposed to the risk of overvoltage. A TVS warning device can be connected to the actual circuit. When the TVS is short-circuited, it warns of abnormalities in the device, so that the TVS can be replaced in time to prevent damage to the protected device. The present invention is not limited to this.

[0037] The electroplated circuit layer 4 and its narrow segment 7 are both made of metal materials, such as copper. The TVS performance selection of the package 1 is set according to the specific type and functional requirements of the protected device. It can be seen that the maximum breakdown voltage of the package 1 is U. At a temperature of 25°C, L is the line length of the narrow segment 7, W is the line width of the narrow segment 7, and A is the cross-sectional area of ​​the narrow segment 7.

[0038] The relationship between the fusing of the narrow section 7 of the electroplated circuit layer 4 and the current can be calculated by the following formula and steps: 1. Fusing current calculation (adiabatic model): At pulse current duration t pulse Internal, fuse current I fuse The relationship with the cross-sectional area A is: Formula 1:

[0039] Parameter description: ρm: Density of copper (8960 kg / m³) c: Specific heat capacity of copper (385 J / (kg·K)) ΔT: The temperature difference between the melting point and the ambient temperature (1060 K corresponds to a melting point of 1085°C) L: Latent heat of fusion of copper (209,000 J / kg) ρ: Resistivity of copper (1.68×10⁻ 8 Ω·m) t pulse : Pulse time (seconds) 2. Resistance and voltage drop: the resistance R and voltage V of the conductor drop for: Formula 2: R = ρL / A, V drop =IR=IρL / A Known breakdown voltage U = V drop , assuming the pulse time t pulse Based on the test, and by substituting into Formula 1 and Formula 2, the line length L can be obtained, and the fusing current I can be obtained fuse According to the current-voltage relationship, the cross-sectional area A of the narrow segment 7 can be obtained, and the size of the narrow segment is set according to the cross-sectional area, and the cross-sectional area A=wt, w is the width, t is the thickness. By setting the width, thickness and length of the narrow segment 7, the narrow segment 7 reaches the maximum cross-sectional area. When an abnormal overvoltage greater than the breakdown voltage range of the package 1 occurs in the circuit, heat accumulates at the narrow segment 7 and it is melted to prevent burning or even fire.

[0040] A high-power TVS packaging structure can be obtained by the above-mentioned high-power TVS packaging method. Fig.18 FIG. 1 is a cross-sectional view of the first embodiment of the packaging structure, wherein the packaging body 1 encapsulates: A pad 5 and a pin 6, wherein the pad 5 is arranged on one side of the pin 6; Chip 2, the back of chip 2 is mounted toward pad 5, and the front of chip 2 is provided with an output terminal; Pillar 3, pillar 3 is vertically plated on pin 6; Circuit layer 4, circuit layer 4 electrically connects the front output end of chip 2 with pillar 3, circuit layer 4, the front output end of chip 2 and pillar 3 are electroplated as a whole, circuit layer 4 includes a narrow section 7, when the circuit input power is greater than the rated power of the chip, the narrow section 7 is disconnected.

[0041] The pad 5 and the pin 6 are formed by electroplating on a substrate at the same time. After encapsulation, the pad 5 and the top surface of the pin 6 are exposed by grinding. The back of the chip 2 is mounted on the pad 5 for encapsulation again, and the front output end of the chip 2 is exposed by grinding. A hole is drilled on the package surface to expose the top surface of the pin 6. The column 3 is formed by electroplating in the hole. The circuit layer 4 is horizontally laid and extended along the top surface of the package that exposes the front output end of the chip 2. The electrical property of the front output end of the chip 2 is transferred from the circuit layer 4 and the column 3 to the pin 6. The circuit layer 4 is continuously encapsulated. The encapsulation as a whole constitutes the package 1. Before the circuit layer 4 is electroplated, a film block is mounted on the corresponding position of the top surface of the package that exposes the front output end of the chip 2. The circuit layer 4 is then electroplated and passes through the film block. A narrow section 7 of the circuit layer 4 is formed at the position where the film block is mounted. The film block is a photoresist film. After the electroplating of the circuit layer 4 is completed, the film block is peeled off and the circuit layer 4 is encapsulated. The encapsulation material fills the gap after the film block is removed. After the package 1 is peeled off the substrate, the pad 5 and the pin 6 are flush with the bottom surface of the package 1 and exposed.

[0042] In this embodiment, before the circuit layer 4 is electroplated, a photoresist film is mounted on the top surface of the package that does not need to be electroplated for protection. At the same time, a small piece of photoresist film is also mounted on the position near the pillar 3 where the circuit layer 4 is electroplated. The film block is smaller than the photoresist film of other normal protective parts. After electroplating, the photoresist film is removed to form the circuit layer 4 and the narrow section 7 of the circuit layer 4. No additional process flow is added or changed, and the process is simple and efficient. The narrow section 7 of the circuit layer 4 is reduced in electroplating and becomes thinner under part of the circuit layer 4, that is, the top surface of the narrow section 7 is flat and the bottom surface is concave. The size of the mounting film block is controllable, so that the size control of the narrow section 7 is more accurate. If an abnormal overvoltage occurs in the circuit, the package 1 can respond faster and eliminate the danger in time.

[0043] like Fig.19 , which is a cross-sectional view of the second embodiment of the packaging structure. The difference between this embodiment and the first embodiment is that the portion of the circuit layer 4 close to the pillar 3 is thinned by etching to form a narrow section 7 of the circuit layer 4 .

[0044] After the circuit layer 4 is electroplated, the part of the circuit layer 4 close to the pillar 3 is etched to form a narrow section 7, and the encapsulation material fills the etched part to avoid the situation where the encapsulation material is not filled sufficiently, causing a void and detachment, and the structure is more stable and effective; The narrow section 7 of the circuit layer 4 is etched and becomes thinner above part of the circuit layer 4, that is, the bottom surface of the narrow section 7 is flat and the top surface is concave. The etching condition is adjusted by controlling the etching immersion time and parameters such as the etching flow rate and concentration, which makes it easy to observe the etching progress and achieve precise control of the etching size of the narrow section 7.

[0045] In all the encapsulation steps of the present invention, the encapsulation material used is a plastic encapsulation material, and the specific material can be epoxy resin, cyanate, polyimide, etc., which has low cost and good curing performance. The packaging process plays an important role in the field of semiconductor manufacturing, mainly in terms of protection, connection, support, reliability and promotion of technological progress. The encapsulation method is the commonly used molding and injection molding method in this field.

[0046] All post-encapsulation grinding processes of the present invention use a grinding machine commonly used in the technical field to perform surface treatment on the package surface, that is, horizontal mechanical grinding on the top surface of the package, and finally the grinding surface is horizontal and flat after grinding, and the outer surface of the entire packaging structure is flat and smooth.

[0047] All the steps of the electroplating process of the present invention are to first use a photoresist film to form electroplating protection on the surface through exposure and development photolithography technology, protect the places that do not need electroplating with a photoresist film, expose the areas that need electroplating, and then form a metal seed layer in the area to be electroplated by sputtering or copper deposition or other appropriate methods. The metal seed layer is copper or other metal materials. The metal seed layer is to ensure the bonding force between the metals and metals and between the metals and the encapsulation materials in the subsequent electroplating, and at the same time provide a surface for the electroplating to attach conductive ions to ensure the electroplating effect. The entire steps in the electroplating process and the materials used are also technical common sense in the field. The metals electroplated in all the electroplating processes of the present invention are all made of metallic copper.

[0048] The present invention: by locally thinning the circuit layer 4 into a narrow section 7 of a certain size while electroplating it, when the package 1 is connected in parallel to the circuit of the protected device, an abnormal overvoltage exceeding the breakdown voltage of the package 1 occurs in the circuit, and heat accumulates at the narrow section 7 of the package 1, which is melted to an open circuit, thereby avoiding the situation where the package 1 is burned and causes a fire. The narrow section 7 is reduced in size by electroplating or etching after electroplating, and the process is simple, efficient and reliable.

[0049] It is to be understood that the present invention is described by some embodiments, and it is known to those skilled in the art that various changes or equivalent substitutions may be made to these features and embodiments without departing from the spirit and scope of the present invention. In addition, under the teachings of the present invention, these features and embodiments may be modified to adapt to specific circumstances and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of the present invention are within the scope of protection of the present invention.

Claims

1. A high-power TVS packaging method, characterized in that: The following steps are involved: Chip packaging: mount the chip on a substrate with electroplated pins, encapsulate the chip and grind the top surface of the encapsulation until the front output terminal of the chip is exposed; Drilling and plating: vertically drill holes on the top surface of the package until the pins are exposed, and electroplate the pillars in the drilled holes; Circuit layer electroplating: The circuit layer is electroplated on the top surface of the package. The circuit layer electrically connects the chip output end with the pillar. The circuit layer, the chip front output end and the pillar are electroplated as a whole. The circuit layer contains a narrow section. Continue to encapsulate and completely encapsulate the circuit layer. When the circuit input power is greater than the rated power of the chip, the narrow section is disconnected; Product unitization: Peel off the substrate to obtain the package product unit.

2. The high-power TVS packaging method according to claim 1, characterized in that: In the chip packaging step, a substrate is provided, on which pads and pins are electroplated. After encapsulation, the pads and pins are exposed by grinding, and the back of the chip is mounted on the pads and encapsulated again, so that the chip, pads and pins are completely encapsulated.

3. The high-power TVS packaging method according to claim 1, characterized in that: In the circuit layer electroplating step, a film block is mounted on the corresponding position of the package top surface of the exposed chip front output terminal before the circuit layer is electroplated, and then the circuit layer is electroplated, and a thin and narrow section of the circuit layer is formed at the position where the film block is mounted.

4. The high-power TVS packaging method according to claim 3, characterized in that: In the circuit layer electroplating step, the film block is a photoresist film.

5. The high-power TVS packaging method according to claim 1, characterized in that: In the circuit layer electroplating step, the portion of the circuit layer close to the pillar is thinned by etching to form a thin and narrow section of the circuit layer.

6. The high-power TVS packaging method according to claim 3 or 5, characterized in that: In the circuit layer electroplating step, the circuit layer is horizontally laid and extended along the top surface of the package where the front output terminal of the chip is exposed by grinding, and the electrical properties of the front output terminal of the chip are transmitted to the pin through the circuit layer and the column.

7. The high-power TVS packaging method according to claim 2, characterized in that: In the product unitization step, after the substrate is peeled off, the pads and pins are flush with the bottom surface of the package and exposed.

8. A high-power TVS packaging structure, comprising a packaging body, characterized in that: The package contains: A pad and a pin, wherein the pad is arranged on one side of the pin; The chip is mounted with the back side facing the pad and the front side of the chip is provided with an output terminal; Posts, posts are plated vertically on the pins; Circuit layer: The circuit layer electrically connects the front output terminal of the chip with the column. The circuit layer, the front output terminal of the chip and the column are electroplated as a whole. The circuit layer includes a narrow section. When the circuit input power is greater than the rated power of the chip, the narrow section is disconnected.

9. The high-power TVS packaging structure according to claim 8, characterized in that: The pads and pins are formed by simultaneous electroplating on a substrate, and are exposed by grinding after encapsulation. The back of the chip is mounted on the pads and encapsulated again, and the front output end of the chip is exposed by grinding. A hole is drilled on the encapsulation surface to expose the top surface of the pin, and the column is formed by electroplating in the hole.

10. The high-power TVS packaging structure according to claim 9, characterized in that: The circuit layer is horizontally laid and extended along the top surface of the package that exposes the front output terminal of the chip. The electrical properties of the front output terminal of the chip are transmitted to the pins through the circuit layer and the column, and the circuit layer is continuously encapsulated to form a package as a whole.

11. The high-power TVS packaging structure according to claim 10, characterized in that: Before the circuit layer is electroplated, a film block is mounted on the corresponding position of the package top surface where the output end of the front side of the chip is exposed, and then the circuit layer is electroplated and passes through the film block. The position where the film block is mounted forms a thin and narrow section of the circuit layer.

12. The high-power TVS packaging structure according to claim 11, characterized in that: The film block is a photoresist film.

13. The high-power TVS packaging structure according to claim 8, characterized in that: The portion of the circuit layer close to the pillar is thinned by etching to form a thin and narrow section of the circuit layer.

14. The high-power TVS packaging structure according to claim 9, characterized in that: After the package is peeled off from the substrate, the pads and pins are flush with the bottom surface of the package and exposed.

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