A wafer acceptance test method with low test escape rate

Abstract

The present invention discloses a wafer acceptance test method with a low test escape rate, and the method is as follows: (1) Find out the key WAT electrical parameters in the current batch that have a great influence on the test escape rate from the WAT electrical parameters; (2) When performing a wafer acceptance test on the test wafers of the current batch, test the key WAT electrical parameters of each die on the wafers to be tested, and detect abnormal dies based on the key WAT electrical parameters. First, evaluate the importance of the WAT electrical parameter characteristics to the escape rate, and then determine the key WAT electrical parameters that have a greater influence on the escape rate. Only test the key WAT electrical parameters for the wafers to be tested in the current batch, which can greatly reduce the detection task amount of the wafers to be tested while not affecting the escape rate of the wafer detection.

Description

Technical Field

[0001] The present invention belongs to the technical field of wafer acceptance testing. More specifically, the present invention relates to a wafer acceptance testing method with a low test escape rate. Background Art

[0002] In the production process of wafers, wafer acceptance test (WAT) is a pre-step of wafer test (Circuit Probe, CP). Its main purpose is to detect the process conditions of each wafer product by testing the electrical parameters of specific structures on the wafer, so as to evaluate the quality and stability of the semiconductor chip manufacturing process. During the wafer testing process, in the automated test equipment (ATE), the probe card in the wafer probe test is used to detect each die in the wafer to identify and eliminate defective or abnormal dies that are not suitable for packaging, which requires a lot of time and expensive device costs. Since WAT can predict the wafer yield, experienced engineers use WAT prediction to reduce the production time and production cost in the CP process. Processing the dies with abnormal WAT data in advance is the key to improving the wafer yield.

[0003] In the wafer manufacturing process, during the production of wafers by ATE, WAT electrical parameters of various test items will be generated, such as output current, logic signal, power supply voltage, and operating voltage, etc. When the collected WAT electrical parameters exceed the reasonable parameter range given by the detection equipment, it is determined that the detection point corresponding to the die is abnormal, and the rest are normal dies. After the above method for identifying abnormal dies is used to detect the wafers to be tested, there are still some defective dies that are not captured during the test and are determined to be qualified dies (normal detection points), that is, escape detection points, and thus directly enter the chip packaging and functional testing. Some defective dies escape the test screening until they are packaged as chip products and have an increased number of failures during use, resulting in a decline in quality. Summary of the Invention

[0004] The present invention provides a wafer acceptance testing method with a low test escape rate, aiming to improve the above problems.

[0005] The present invention is implemented as follows. A wafer acceptance testing method with a low test escape rate is as follows:

[0006] (1) Find out the key WAT electrical parameters in the current batch that have a great influence on the test escape rate from the WAT electrical parameters;

[0007] (2) When performing wafer acceptance test (WAT) on the test wafers of the current batch, test the key WAT electrical parameters of each die on the wafers to be tested, and detect abnormal dies based on the key WAT electrical parameters.

[0008] Furthermore, the process of obtaining the key WAT electrical parameters is as follows:

[0009] (11) Test the WAT electrical parameters of multiple wafers to be tested in the current batch and identify abnormal detection points;

[0010] (12) Determine the escape detection points among the normal detection points, and determine the key WAT electrical parameters that have a great impact on escape based on the abnormal WAT electrical parameters in the abnormal detection points and the escape detection points.

[0011] Furthermore, the process of identifying the escape detection points is as follows:

[0012] (121) Detect the escape detection points among the normal detection points based on dynamic partial average testing and interquartile range detection;

[0013] (122) Calculate the degree of abnormality of each current escape detection point, determine the neighborhood range affected by the escape detection point based on the degree of abnormality, test the WAT electrical parameters of the detection points within the neighborhood range, and detect the escape detection points again based on step (121).

[0014] Furthermore, the process of identifying the escape detection points based on dynamic partial average testing is as follows:

[0015] First, determine the upper limit value UCL and the lower limit value LCL of each WAT electrical parameter. If the WAT electrical parameter exceeds the upper limit value UCL or the lower limit value LCL, it is considered an abnormal WAT electrical parameter, and the corresponding die is considered an escape detection point. Among them, the upper limit value UCL of the i-th type of WAT electrical parameter i , the lower limit value LCL i The calculation formulas are as follows:

[0016] UCL i = μ i + Kσ i ;

[0017] LCL i = μ i - Kσ i ;

[0018] Among them, μ i represents the mean value of the i-th type of WAT electrical parameter, σ i represents the standard deviation of the i-th type of WAT electrical parameter, and K represents a robust constant, K = 3.

[0019] Furthermore, the method for identifying the escape detection points based on interquartile range detection is as follows:

[0020] Calculate the interquartile range IQR of the i-th type of WAT electrical parameter i, represents the upper quartile of the electrical parameters of the i-th type of WAT, represents the lower quartile of the electrical parameters of the i-th type of WAT;

[0021] Based on the interquartile range IQR i determine the boundary of the outliers of the electrical parameters of the i-th type of WAT. If the electrical parameters of the i-th type of WAT at the normal detection point are lower than or higher than then the corresponding WAT electrical parameter is identified as an abnormal WAT electrical parameter, and the corresponding grain is identified as an escape detection point.

[0022] Furthermore, count the number of abnormal WAT electrical parameters in each escape detection point. The more the number of abnormal WAT electrical parameters, the higher the degree of abnormality, and the larger the affected neighborhood range; the lower the degree of abnormality, the smaller the affected neighborhood range.

[0023] Furthermore, divide the degree of abnormality into four levels. The first level has the lowest degree of abnormality, and the fourth level has the highest degree of abnormality.

[0024] Furthermore, if the proportion of the number of abnormal WAT electrical parameters in the escape detection point is greater than or equal to b1, it is identified as the fourth level of abnormality, and a neighborhood range of 7x7 is formed centered on the escape detection point; if the proportion of the number of abnormal WAT electrical parameters in the escape detection point is in the range of (b1, b2], it is identified as the third level of abnormality, and a neighborhood range of 5x5 is formed centered on the escape detection point; if the proportion of the number of abnormal WAT electrical parameters in the escape detection point is in the range of (b2, b3], it is identified as the second level of abnormality, and a neighborhood range of 3x3 is formed centered on the escape detection point; if the proportion of the number of abnormal WAT electrical parameters in the escape detection point is lower than b3, it is identified as the first level of abnormality, and the escape detection point itself is used as the neighborhood range, where b1 > b2 > b3.

[0025] Furthermore, the determination process of the key WAT electrical parameters is as follows:

[0026] (123) Extract the abnormal WAT electrical parameters in all abnormal detection points, classify the extracted abnormal WAT electrical parameters, and perform normalization processing on each type of abnormal WAT electrical parameter;

[0027] (124) Input each type of abnormal WAT electrical parameter processed in step (123) into the NSGA-II algorithm, and determine the Shapely value of each type of WAT electrical parameter based on the NSGA-II algorithm. The Shapely value reflects the influence degree of each type of WAT electrical parameter on the escape rate;

[0028] (125) Select several WAT electrical parameters that have a great impact on the escape rate based on the Shapely values of various WAT electrical parameters as the key WAT electrical parameters of the wafers in the current batch.

[0029] The wafer acceptance test method with low test escape rate proposed by the present invention has the following beneficial technical effects:

[0030] (1) Use dynamic average testing and interquartile range to perform anomaly detection on the WAT electrical data of the generated die, which is beneficial to reducing the escape rate of wafer detection;

[0031] (2) Determine the affected neighborhood range based on the anomaly degree of the escaped die. The higher the anomaly degree, the larger the affected range. Retest through the local neighborhood range to further reduce the escape rate of wafer detection;

[0032] (3) Use the Shapely value to evaluate the importance of the WAT electrical parameter characteristics to the escape rate, and determine the key WAT electrical parameters that have a greater impact on the escape rate. Only test the key WAT electrical parameters of the wafers to be tested in the current batch, which can greatly reduce the detection task volume of the wafers to be tested while not affecting the escape rate of wafer detection. Description of the Drawings

[0033] Figure 1 It is a flowchart of the wafer acceptance test method with low test escape rate provided by an embodiment of the present invention. Embodiment

[0034] The following will further describe in detail the specific embodiments of the present invention with reference to the accompanying drawings through the description of the embodiments, so as to help those skilled in the art have a more complete, accurate and in-depth understanding of the inventive concept and technical solution of the present invention.

[0035] Figure 1 It is a flowchart of the wafer acceptance test method with low test escape rate provided by an embodiment of the present invention, and the method is as follows:

[0036] (1) Find the key WAT electrical parameters in the current batch that have a great impact on the test escape rate from the WAT electrical parameters;

[0037] (2) When performing wafer acceptance test (WAT) on the test wafers in the current batch, test the key WAT electrical parameters of each die on the wafers to be tested, and perform detection of abnormal die based on the key WAT electrical parameters.

[0038] Since there are significant differences in the WAT electrical parameters of the wafers to be tested in different batches, it is necessary to determine the key WAT electrical parameters of each batch of wafers to be tested, eliminate the WAT electrical parameters that have little impact on the test escape rate, and only test the key WAT electrical parameters of each die on the test wafer, while reducing the test cost and the test escape rate. Based on steps (121) and (122), the detection of abnormal dies is carried out. The dies determined to be normal are the escape dies or escape detection points in the present invention.

[0039] The process of obtaining the key WAT electrical parameters will be described in detail below. The process of obtaining the key WAT electrical parameters is as follows:

[0040] (11) Test the WAT electrical parameters of multiple wafers to be tested in the current batch and identify the abnormal detection points;

[0041] Since the abnormal detection points are identified based on the reasonable parameter range given by the detection equipment, and the identification process is existing, the present invention will not elaborate on it here.

[0042] (12) Determine the escape detection points among the normal detection points, and determine the key WAT electrical parameters that have a great impact on escape based on the abnormal WAT electrical parameters among the abnormal detection points and the escape detection points.

[0043] In the embodiment of the present invention, the escape detection point refers to the abnormal detection point determined to be a normal detection point. The detection process of the escape detection point is as follows:

[0044] (121) Detect the escape detection points among the normal detection points based on the dynamic partial average test and the interquartile range detection;

[0045] In the embodiment of the present invention, if a normal detection point is identified as an abnormal detection point in the dynamic partial average test or the interquartile range detection, the corresponding detection points are all escape detection points.

[0046] In the dynamic partial average test process, it is necessary to first determine the upper limit value UCL and the lower limit value LCL of each WAT electrical parameter. If the WAT electrical parameter exceeds the upper limit value UCL or the lower limit value LCL, it is determined as an escape detection point. The upper limit value UCL of the i-th type of WAT electrical parameter i and the lower limit value LCL i are determined based on formulas (1) and (2). Formulas (1) and (2) are as follows:

[0047] UCL i = μ i + Kσ i (1)

[0048] LCL i = μ i-Kσ i (2)

[0049] wherein, respectively, μ i represents the mean value of the electrical parameters of the i-th type of WAT, and σ i represents the standard deviation of the electrical parameters of the i-th type of WAT. K represents a robustness constant. Usually, K = 3. If the electrical parameter of the i-th WAT at a detection point exceeds the range corresponding to the lower limit value and the upper limit value, then the detection point is an escape detection point.

[0050] In the embodiment of the present invention, the mean value μ i and the standard deviation σ i of the electrical parameter of the i-th WAT are calculated respectively using formula (3) and formula (4). The specific formulas of formula (3) and formula (4) are as follows:

[0051]

[0052] wherein, n represents the total number of types of electrical parameters of WAT, and X i represents the test value of the electrical parameter of the i-th type of WAT.

[0053] Dynamic Part Average Testing (DPAT) is a quality control method used to detect outliers in product parameters during the manufacturing process, identify and eliminate abnormal products in production to ensure the overall product quality. However, since DPAT can only detect a limited number of outliers, some deviated error data may not be detected. Therefore, it is necessary to add the Interquartile Range (IQR) detection to the DPAT technology to identify escape detection points among normal detection points. The interquartile range is more robust when dealing with non-normal or skewed distribution data and provides a more reliable measure of dispersion. It reduces the influence of extreme values (outliers) and more accurately reflects the central tendency and dispersion degree of the data.

[0054] In the embodiment of the present invention, the interquartile range IQR i of the electrical parameter of the i-th type of WAT is calculated, and based on the interquartile range IQR i the boundaries of the outliers of the electrical parameter of the i-th type of WAT are determined. represents the upper quartile of the electrical parameter of the i-th type of WAT, represents the lower quartile of the electrical parameter of the i-th type of WAT, then If the electrical parameter of the i-th type of WAT at a normal detection point is lower than or higher than [[ID=4A]] then the corresponding normal detection point is identified as an escape detection point.

[0055] (122) Calculate the abnormality degree of each current escape detection point, determine the domain range affected by the escape detection point based on the abnormality degree, test the WAT electrical parameters of the detection points within the neighborhood range, and perform escape detection again based on step (121).

[0056] In the embodiment of the present invention, count the number of abnormal WAT electrical parameters in each escape detection point. The more the number of abnormal WAT electrical parameters, the higher the abnormality degree, and the larger the neighborhood range it affects; the lower the abnormality degree, the smaller the neighborhood range it affects. The detection points within the neighborhood range are affected by the escape detection point and may also show abnormalities. Therefore, the detection points within the neighborhood range have a relatively high risk of escape. Performing escape detection on the detection points within the neighborhood range again can greatly reduce the escape risk.

[0057] In the embodiment of the present invention, the abnormality degree is divided into four levels. The first level has the lowest abnormality degree, and the fourth level has the highest abnormality degree. When the proportion of the number of abnormal WAT electrical parameters in the escape detection point is greater than or equal to b1, it is determined as the fourth-level abnormality degree, and a neighborhood range of 7x7 size is formed with the escape detection point as the center; when the proportion of the number of abnormal WAT electrical parameters in the escape detection point is in the range of (b1, b2], it is determined as the third-level abnormality degree, and a neighborhood range of 5x5 size is formed with the escape detection point as the center; when the proportion of the number of abnormal WAT electrical parameters in the escape detection point is in the range of (b2, b3], it is determined as the second-level abnormality degree, and a neighborhood range of 3x3 size is formed with the escape detection point as the center; when the proportion of the number of abnormal WAT electrical parameters in the escape detection point is lower than b3, it is determined as the first-level abnormality degree, and the escape detection point itself is used as the neighborhood range, where b1 > b2 > b3.

[0058] In the present invention, n = 6, that is, each detection point has 6 types of WAT electrical parameters. When there are six WAT electrical parameter abnormalities in the escape detection point, a neighborhood range of 7x7 size is formed with the escape detection point as the center; when there are four or five WAT electrical parameter abnormalities in the escape detection point, a neighborhood range of 5x5 size is formed with the escape detection point as the center; when there are two or three WAT electrical parameter abnormalities in the escape detection point, a neighborhood range of 3x3 size is formed with the escape detection point as the center; and when there is only one WAT electrical parameter abnormality in the escape detection point, the neighborhood range is only the escape detection point itself. The above method not only reduces the risk of overtesting, but also reduces the cost of WAT and the risk of escape at the same time.

[0059] In the embodiment of the present invention, the process of determining the key WAT electrical parameters is specifically as follows:

[0060] (123)Extract the abnormal WAT electrical parameters among all the anomaly detection points, classify the extracted abnormal WAT electrical parameters, and perform normalization processing on each category of abnormal WAT electrical parameters;

[0061] (124)Input each category of abnormal WAT electrical parameters processed in step (123) into the NSGA-II algorithm, and determine the Shapely value of each category of WAT electrical parameters within the boundary range based on the NSGA-II algorithm. The Shapely value reflects the degree of influence of each category of WAT electrical parameters on the escape rate;

[0062] In the embodiment of the present invention, the boundary range is: g(X i ) = φ(X i ) * l i , g(X i ) ≤ 0, where φ(X i ) is the Shapely value calculation model of the i-th category of abnormal WAT electrical parameters, and l i is the contribution coefficient, determined based on the number of the i-th category of abnormal WAT electrical parameters. The more the number, the larger the value of l i , and the value is between 0 and 1.

[0063] (125)Select several WAT electrical parameters with a large influence on the escape rate based on the Shapely values of each category of WAT electrical parameters as the key WAT electrical parameters of the current batch of wafers. For subsequent wafers to be tested, only the key WAT electrical parameters need to be detected to identify the anomaly detection points, greatly reducing the test volume and lowering the escape rate during the test process.

[0064] The wafer acceptance test method with a low test escape rate proposed by the present invention has the following beneficial technical effects:

[0065] (1)Adopt dynamic average testing and interquartile range to perform anomaly detection on the WAT electrical data of the generated die, which is beneficial to reducing the escape rate of wafer detection;

[0066] (2)Determine the affected neighborhood range based on the anomaly degree of the escaped die. The higher the anomaly degree, the larger the influence range. By re-testing through the local neighborhood range, the escape rate of wafer detection is further reduced;

[0067] (3)Utilize the Shapely value (Shapley value) to evaluate the importance of the WAT electrical parameter characteristics to the escape rate, and determine the key WAT electrical parameters with a large influence on the escape rate. Only test the key WAT electrical parameters for the wafers to be tested in the current batch, which does not affect the escape rate of wafer detection while greatly reducing the detection task volume of the wafers to be tested.

[0068] The present invention has been described by way of example. Obviously, the specific implementation of the present invention is not limited by the above-mentioned manner. As long as various non-substantive improvements are made by adopting the method concept and technical solution of the present invention, or the concept and technical solution of the present invention are directly applied to other occasions without improvement, they are all within the protection scope of the present invention.

Claims

1. A wafer acceptance test method with a low test escape rate, characterized in that, The method is specifically as follows: (1) Find out the key WAT electrical parameters in the current batch that have a great influence on the test escape rate from the WAT electrical parameters. (2) When performing wafer acceptance testing on the test wafers of the current batch, test the key WAT electrical parameters of each die on the wafers to be tested, and detect abnormal dies based on the key WAT electrical parameters. The process of obtaining the key WAT electrical parameters is specifically as follows: (11) Test the WAT electrical parameters of multiple wafers to be tested in the current batch, and identify abnormal detection points. (12) Determine the escape detection points among the normal detection points, and determine the key WAT electrical parameters that have a great influence on escape based on the abnormal WAT electrical parameters in the abnormal detection points and the escape detection points. The process of identifying the escape detection points is specifically as follows: (121) Detect the escape detection points among the normal detection points based on dynamic partial average testing and interquartile range detection. (122) Calculate the degree of abnormality of each current escape detection point, determine the neighborhood range affected by the escape detection point based on the degree of abnormality, test the WAT electrical parameters of the detection points within the neighborhood range, and detect the escape detection points again based on step (121).

2. The method for testing wafers with a low test escape rate according to claim 1, wherein The process of identifying the escape detection points based on dynamic partial average testing is specifically as follows: First, determine the upper limit value UCL and the lower limit value LCL of each WAT electrical parameter. If the WAT electrical parameter exceeds the upper limit value UCL or the lower limit value LCL, it is identified as an abnormal WAT electrical parameter, and the corresponding die is identified as an escape detection point. Among them, the upper limit value UCL of the i-th type of WAT electrical parameter i , the lower limit value LCL i The calculation formulas are as follows: UCL i = μ i + Kσ i ; LCL i = μ i - Kσ i ; where, μ i represents the mean of the electrical parameters of the i-th type of WAT, and σ i represents the standard deviation of the electrical parameters of the i-th type of WAT, and K represents the robustness constant, where K = 3.

3. The method for testing wafers with a low test escape rate as described in claim 1, wherein, The method of identifying the escape detection points based on interquartile range detection is specifically as follows: Calculate the interquartile range IQR of the electrical parameters of the i-th type of WAT i , represents the upper quartile of the electrical parameters of the i-th type of WAT, represents the lower quartile of the electrical parameters of the i-th type of WAT; Based on the interquartile range IQR i Determine the boundary of the outliers of the electrical parameters of the i-th type of WAT. If the electrical parameters of the i-th type of WAT at the normal detection points are lower than or higher than then the corresponding WAT electrical parameters are identified as abnormal WAT electrical parameters, and the corresponding crystal grains are identified as escape detection points.

4. The wafer acceptance test method with a low test escape rate as described in claim 1, wherein Count the number of abnormal WAT electrical parameters in each escape detection point. The more the number of abnormal WAT electrical parameters, the higher the degree of abnormality, and the larger the affected neighborhood range; the lower the degree of abnormality, the smaller the affected neighborhood range.

5. The wafer acceptance test method with a low test escape rate as described in claim 4, characterized in that, The degree of abnormality is divided into four levels. The first level has the lowest degree of abnormality, and the fourth level has the highest degree of abnormality.

6. The method for testing wafers with low test escape rate as claimed in claim 5, wherein If the proportion of the number of abnormal WAT electrical parameters in the escape detection point is greater than or equal to b1, it is determined to be the fourth level of abnormality, and a neighborhood range of 7x7 is formed centered on the escape detection point; if the proportion of the number of abnormal WAT electrical parameters in the escape detection point is in (b1, b2], it is determined to be the third level of abnormality, and a neighborhood range of 5x5 is formed centered on the escape detection point; if the proportion of the number of abnormal WAT electrical parameters in the escape detection point is in (b2, b3], it is determined to be the second level of abnormality, and a neighborhood range of 3x3 is formed centered on the escape detection point; if the proportion of the number of abnormal WAT electrical parameters in the escape detection point is less than b3, it is determined to be the first level of abnormality, and the escape detection point itself is used as the neighborhood range, where b1 > b2 > b3.

7. The wafer acceptance test method with low test escape rate as described in claim 1, characterized in that, The process of determining the key WAT electrical parameters is specifically as follows: (123) Extract the abnormal WAT electrical parameters in all abnormal detection points, classify the extracted abnormal WAT electrical parameters, and perform normalization processing on each type of abnormal WAT electrical parameters. (124) Input each type of abnormal WAT electrical parameters processed in step (123) into the NSGA-II algorithm, and determine the Shapely value of each type of WAT electrical parameter based on the NSGA-II algorithm. The Shapely value reflects the influence degree of each type of WAT electrical parameter on the escape rate. (125) Select several WAT electrical parameters that have a great impact on the escape rate based on the Shapely values of various WAT electrical parameters as the key WAT electrical parameters of the current batch of wafers.

Images