Double-sided packaging structure for low parasitic inductance of power device

Abstract

The invention discloses a low parasitic inductance double-sided packaging structure for a power device, which is characterized in that a plurality of conductor layers, via holes and metal layers are respectively arranged on the upper surface and the lower surface of a first insulating layer, so that the parasitic inductance of the double-sided packaging structure is reduced, routing on a ceramic substrate can be laminated, the parasitic inductance is further reduced, and the reliability of the packaging structure is improved. Different from a traditional DBC ceramic substrate with only an upper conductor participating in electric conduction, the inner conductor layer of the multi-layer insulating layer can also participate in electric conduction and is connected with the upper conductor through a via hole, the double-face packaging structure and the power device chip are connected in a double-face mode, under the condition that multiple devices are connected in parallel, the double faces can be connected with a cooling fin, and the heat dissipation efficiency is improved. And the heat dissipation of the power device chip is greatly increased, so that the working reliability of the double-sided packaging structure is improved.

Description

Technical Field

[0001] The invention belongs to the technical field of power semiconductor chip packaging technology, and in particular relates to a low parasitic inductance double-sided packaging structure for a power device. Background Art

[0002] Power electronic devices are developing in the direction of modularization and intelligence. The emergence of large-scale and ultra-large-scale integrated circuits has led to higher and higher integration of power electronic devices, and the number and density of various chips assembled on the substrate have also increased. To reduce the size of power electronic modules and further increase the power density, it is required that the power modules have good electrical and thermal performance and working reliability under both steady-state and transient conditions. All these lead to the chips being subjected to more and more high temperatures or temperature drifts during use. High temperatures have a great impact on the reliability and rapid aging of power electronic products, while excessive temperatures and temperature cycles often directly lead to premature product failure. Therefore, effective thermal management has become a major challenge for the future development of power electronics, and has put forward higher requirements for the research and development and progress of packaging technology and packaging materials.

[0003] Traditional power electronic packaging is as follows Figure 1 As shown, the power device chip is directly soldered to the DBC substrate (copper-clad ceramic substrate), and then the DBC substrate with the chip attached is connected to the heat sink. This packaging form is called single-sided packaging. The heat dissipation channel of the single-sided package is mainly for the heat generated by the chip to be transferred to the DBC board through the adhesive layer, and then transferred to the heat sink through another adhesive layer. Finally, the heat sink and air convection heat transfer or water cooling dissipates the heat. In the single-sided cooling packaging form, the direction of heat transfer is from the chip to the heat sink in a single direction. Although it is possible to use connection materials with higher thermal conductivity or design heat sinks with better heat dissipation capabilities to increase the overall heat dissipation capacity of the structure, there is still very limited room for improvement. In today's pursuit of greater power input and packaging density, single-sided cooling packaging can no longer meet the needs of high-power electronic packaging. Therefore, a double-sided cooling packaging technology has emerged. Usually the form of a double-sided cooling device is as follows Figure 2 In the symmetrical structure shown, the chip is soldered between the upper and lower DBC substrates, and the upper and lower DBC boards are connected to the heat sink through connecting materials.

[0004] The parasitic inductance inside the module is an important indicator of the power module packaging design. When the power semiconductor device is turned off, the energy stored in the parasitic inductance will cause voltage spikes and oscillations, and may increase losses. Therefore, in order to ensure the performance and safe operation of power devices and power electronic systems, it is necessary to reduce the packaging parasitic inductance when designing the power module packaging. Therefore, it is urgent to provide a low parasitic inductance double-sided packaging structure for power devices to solve the above-mentioned technical problems. Summary of the invention

[0005] In view of this, the present invention provides a low parasitic inductance double-sided packaging structure for a power device, using a multi-layer ceramic substrate so that the wiring on the ceramic substrate can be stacked, thereby further reducing the parasitic inductance. Unlike the traditional DBC ceramic substrate where only the upper conductor participates in conduction, the inner conductor of the multi-layer ceramic substrate can also participate in conduction and be connected to the upper conductor through vias, which is specifically achieved by the following technical solution.

[0006] The present invention provides a low parasitic inductance double-sided packaging structure for a power device, the double-sided packaging structure comprising: a first insulating layer; A first conductor layer formed on the upper surface of the first insulating layer, second insulating layers arranged at intervals on the upper surface of the first conductor layer, and a first via hole located between the second insulating layers; a second conductor layer filled in the first via hole and a third conductor layer located on the upper surface of the second insulating layer; A first metal layer formed on the upper surface of the second conductor layer, a second metal layer on one side of the third conductor layer, and a first power device chip on the other side of the third conductor layer, wherein the first power device chip is connected to the second conductor layer via a first metal connection; A fourth conductor layer formed on the lower surface of the first insulating layer, third insulating layers arranged at intervals on the lower surface of the fourth conductor layer, and second via holes located between the third insulating layers and arranged corresponding to the first via holes; a fifth conductor layer filled in the second via hole, and a sixth conductor layer located on the lower surface of the third insulating layer and arranged corresponding to the third conductor layer; A third metal layer is formed on the lower surface of the fifth conductor layer, a fourth metal layer is formed on one side of the sixth conductor layer, and a second power device chip is formed on the other side of the sixth conductor layer. The second power device chip is connected to the fifth conductor layer through a second metal connection.

[0007] As a preferred embodiment of the above technical solution, the projected area of ​​the third conductive layer on the first insulating layer is smaller than the projected area of ​​the second insulating layer on the first insulating layer, and the projected area of ​​the sixth conductive layer on the first insulating layer is smaller than the projected area of ​​the third insulating layer on the first insulating layer.

[0008] As a preferred embodiment of the above technical solution, the thickness of the first conductor layer, the third conductor layer, the fourth conductor layer and the sixth conductor layer is between 0.1 and 0.5 mm.

[0009] As a preferred embodiment of the above technical solution, the thickness of the first insulating layer, the second insulating layer and the third insulating layer is between 0.2 and 1 mm.

[0010] As a preferred embodiment of the above technical solution, the first metal layer, the second metal layer and the first power device chip are flush with each other, and the third metal layer, the fourth metal layer and the second power device chip are flush with each other.

[0011] As a preferred embodiment of the above technical solution, the double-sided packaging structure further includes: A first heat dissipation component, the first heat dissipation component comprising a first heat sink, a first adhesive layer and a first DBC substrate stacked in sequence, the first DBC substrate being close to the first power device chip, and the first heat sink being far away from the first power device chip; The second heat dissipation component includes a second DBC substrate, a second adhesive layer and a second heat sink stacked in sequence, the second DBC substrate is close to the second power device chip, and the second heat sink is far away from the second power device chip.

[0012] As a preferred embodiment of the above technical solution, when the first metal layer inputs a first current of a first current density, the first current sequentially passes through the second conductor layer, the first conductor layer, the second conductor layer, the first metal connection, the first power device chip, the third conductor layer and the second metal layer to form a first current branch; When the fourth metal layer inputs a second current of a second current density, the second current passes through the sixth conductor layer, the second power device chip, the second metal connection, the fourth conductor layer and the fifth metal layer in sequence to form a second current branch, the first current density is the same as the second current density, and the currents of the first current branch and the second current branch are equal and in opposite directions.

[0013] As a preferred embodiment of the above technical solution, the first insulating layer, the second insulating layer and the third insulating layer are all insulating ceramics, and the first conductor layer, the second conductor layer, the third conductor layer, the fourth conductor layer, the fifth conductor layer and the sixth conductor layer are all made of copper.

[0014] As a preferred embodiment of the above technical solution, the preparation process of the double-sided packaging structure includes: Providing a first insulating layer, and growing a first conductor layer and a fourth conductor layer on the upper surface and the lower surface of the first insulating layer respectively; Etching the first conductor layer and the fourth conductor layer to produce a completely mirrored current path; A second insulating layer is formed on the upper surface of the first conductor layer and a third insulating layer is formed on the lower surface of the fourth conductor layer; Etching via holes on both sides of the insulating ceramic, etching the second insulating layer and the third insulating layer to form a first via hole and a second via hole respectively; Filling the first via hole with a second conductor layer and forming a third conductor layer on the upper surface of the second insulating layer, and filling the second via hole with a fifth conductor layer and forming a sixth conductor layer on the lower surface of the third insulating layer corresponding to the third conductor layer; The first power device chip is bonded to one side of the third conductor layer and the second power device chip is bonded to one side of the sixth conductor layer; A first metal layer is formed on the upper surface of the second conductor layer, a second metal layer is formed on the other side of the third conductor layer, a third metal layer is formed on the lower surface of the fifth conductor layer, and a fourth metal layer is formed on the other side of the sixth conductor layer. The first power device chip is connected to the second conductor layer through a first metal connection, and the second power device chip is connected to the fifth conductor layer through a second metal connection.

[0015] As a preferred embodiment of the above technical solution, double-sided DBC covering is used to form a first heat dissipation component located above the first power device chip and a second heat dissipation component located below the second power device chip, and the first heat dissipation component and the second heat dissipation component are symmetrically arranged about the first insulating layer.

[0016] The present invention provides a low parasitic inductance double-sided packaging structure for a power device. By respectively arranging a plurality of conductor layers, vias and metal layers on the upper surface and the lower surface of a first insulating layer, the parasitic inductance of the double-sided packaging structure is reduced, so that the wiring on the ceramic substrate can be stacked, thereby further reducing the parasitic inductance. Different from the traditional DBC ceramic substrate in which only the upper conductor participates in the conduction, the inner conductor layer of the multi-layer insulating layer can also participate in the conduction and is connected to the upper conductor through the via. The double-sided packaging structure is connected to the power device chip on both sides. When multiple devices are connected in parallel, both sides can be connected to the heat sink, which greatly increases the heat dissipation of the power device chip and improves the working reliability of the double-sided packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 It is a schematic diagram of the structure of the power electronic packaging form of the prior art; Figure 2 It is a structural schematic diagram of a double-sided cooling device in the prior art; Figure 3 A schematic diagram of the double-sided packaging structure provided by the present invention; Figure 4 A schematic diagram of the working current of the double-sided packaging structure provided by the present invention; Figure 5 A schematic diagram of the structure of the first heat dissipation component and the second heat dissipation component provided by the present invention; Figure 6 This is a flow chart of the method for preparing the double-sided packaging structure provided by the present invention.

[0019] The main component symbols are described as follows: 1-power device chip; 2-DBC substrate; 3-heat sink; 4-adhesion layer; 10-first insulating layer; 11-first conductor layer; 12-second insulating layer; 13-first via hole; 14-second conductor layer; 15-third conductor layer; 16-first metal layer; 17-second metal layer; 18-first power device chip; 19-first metal connection; 20-fourth conductor layer; 21-third insulating layer; 22-second via hole; 23-fifth conductor layer; 24-sixth conductor layer; 25-third metal layer; 26-fourth metal layer; 27-second power device chip; 28-second metal connection; 30-first heat sink; 31-first adhesion layer; 32-first DBC substrate; 34-second DBC substrate; 35-second adhesion layer; 36-second heat sink. DETAILED DESCRIPTION

[0020] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0021] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. In contrast, when an element is referred to as being "directly on" another element, there is no intermediate element. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only.

[0022] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0023] See also Figure 3 The present invention provides a low parasitic inductance double-sided packaging structure for a power device, the double-sided packaging structure comprising: A first insulating layer 10; A first conductor layer 11 formed on the upper surface of the first insulating layer 10, second insulating layers 12 arranged at intervals on the upper surface of the first conductor layer 11, and first vias 13 located between the second insulating layers 12; a second conductor layer 14 filled in the first via hole 13 and a third conductor layer 15 located on the upper surface of the second insulating layer 12; A first metal layer 16 formed on the upper surface of the second conductor layer 14, a second metal layer 17 on one side of the third conductor layer 15, and a first power device chip 18 on the other side of the third conductor layer 15, wherein the first power device chip 18 is connected to the second conductor layer 14 via a first metal connection 19; A fourth conductor layer 20 formed on the lower surface of the first insulating layer 10, third insulating layers 21 arranged at intervals on the lower surface of the fourth conductor layer 20, and second via holes 22 located between the third insulating layers 21 and arranged corresponding to the first via holes 13; a fifth conductor layer 23 filled in the second via hole 22, and a sixth conductor layer 24 located on the lower surface of the third insulating layer 21 and arranged corresponding to the third conductor layer 15; A third metal layer 25 is formed on the lower surface of the fifth conductor layer 23 , a fourth metal layer 26 is formed on one side of the sixth conductor layer 24 , and a second power device chip 27 is formed on the other side of the sixth conductor layer 24 . The second power device chip 27 is connected to the fifth conductor layer 23 via a second metal connection 28 .

[0024] In this embodiment, the projection area of ​​the third conductive layer 15 on the first insulating layer 10 is smaller than the projection area of ​​the second insulating layer 12 on the first insulating layer 10, and the projection area of ​​the sixth conductive layer 24 on the first insulating layer 10 is smaller than the projection area of ​​the third insulating layer 21 on the first insulating layer 10. The thickness of the first conductor layer 11, the third conductor layer 15, the fourth conductor layer 20 and the sixth conductor layer 24 is between 0.1 and 0.5 mm, the thickness of the first insulating layer 10, the second insulating layer 12 and the third insulating layer 21 is between 0.2 and 1 mm, the first metal layer 16, the second metal layer 17 and the first power device chip 18 are flush, and the third metal layer 25, the fourth metal layer 26 and the second power device chip 27 are flush. The double-sided packaging structure also includes: a first heat dissipation component, which includes a first heat sink 30, a first adhesive layer 31 and a first DBC substrate 32 stacked in sequence, the first DBC substrate 32 is close to the first power device chip 18, and the first heat sink 30 is far away from the first power device chip 18; a second heat dissipation component, which includes a second DBC substrate 34, a second adhesive layer 35 and a second heat sink 36 stacked in sequence, the second DBC substrate 34 is close to the second power device chip 27, and the second heat sink 36 is far away from the second power device chip 27.

[0025] It should be noted that when the first metal layer 16 inputs a first current of a first current density, the first current sequentially passes through the second conductor layer 14, the first conductor layer 11, the second conductor layer 14, the first metal connection 19, the first power device chip 18, the third conductor layer 15 and the second metal layer 17 to form a first current branch; when the fourth metal layer 26 inputs a second current of a second current density, the second current sequentially passes through the sixth conductor layer 24, the second power device chip 27, the second metal connection 28, the fourth conductor layer and the fifth metal layer to form a second current branch, the first current density is the same as the second current density, and the currents of the first current branch and the second current branch are equal and opposite in direction. The first insulating layer, the second insulating layer and the third insulating layer are all insulating ceramics, and the materials of the first conductor layer 11, the second conductor layer 14, the third conductor layer 15, the fourth conductor layer 20, the fifth conductor layer 23 and the sixth conductor layer 24 are all copper. Preferably, the thicknesses of the first conductor layer 11, the third conductor layer 15, the fourth conductor layer 20 and the sixth conductor layer 24 are equal, the thicknesses of the first insulating layer 10, the second insulating layer 12 and the third insulating layer 21 are equal, and the thicknesses of the second conductor layer 14 and the fifth conductor layer 23 are equal, which can improve the working stability of the double-sided packaging structure.

[0026] It should be understood, refer again Figure 2 As the switching speed of power semiconductor devices has become faster and faster in recent years, the parasitic inductance problem of the package has become more prominent. In traditional power modules, the package parasitic inductance mainly consists of the following parts: (1) the current loop on the DBC; (2) the bonding wire on the surface of the chip; (3) the power connection terminal. There are three main methods to reduce the package parasitic inductance: 1) reduce the parasitic inductance of the DBC trace through DBC layout design; 2) reduce the parasitic inductance of the terminal through the design of the connection terminal; 3) use a new connection method to replace the chip surface bonding wire to reduce the parasitic inductance introduced by the bonding wire. The main purpose of the lower conductive layer of the traditional DBC (ceramic) substrate 2 is to facilitate the design of the trace, that is, the metal layer and the metal connection, to facilitate the control of the trace current and direction, thereby reducing the parasitic inductance and also reducing the resistance. The present invention adopts an improved double-sided packaging structure to further reduce the parasitic inductance of the module package, and uses a multi-layer ceramic substrate so that the wiring on the ceramic substrate can also be stacked, thereby further reducing the parasitic inductance. Unlike the traditional DBC ceramic substrate where only the upper conductor participates in the conduction, the inner conductors (first conductor layer, fourth conductor layer) of the multi-layer ceramic substrate can also participate in the conduction and are connected to the upper conductors (third conductor layer, sixth conductor layer) through vias. Since the ceramic substrate is thin, the loop area is small, which reduces the parasitic inductance. In other words, by respectively arranging multiple conductor layers, vias and metal layers on the upper surface and the lower surface of the first insulating layer 10, the parasitic inductance of the double-sided packaging structure is reduced, so that the wiring on the ceramic substrate can be stacked, thereby further reducing the parasitic inductance. Unlike the traditional DBC ceramic substrate in which only the upper conductor participates in conduction, the inner conductor layer of the multi-layer insulating layer can also participate in conduction and is connected to the upper conductor through vias. The double-sided packaging structure and the power device chip are connected on both sides. When multiple devices are connected in parallel, both sides can be connected to the heat sink, which greatly increases the heat dissipation of the power device chip and improves the working reliability of the double-sided packaging structure.

[0027] Specifically, the first power device chip 18 and the second power device chip 27 adopt vertical power device chips, and are double-sided packaged on a new multi-layer insulating layer (ceramic substrate). The size of the first via 13 and the second via 22 can be as large as possible based on the ceramic substrate to reduce the path resistance. The material of the first metal layer 16, the second metal layer 17, the third metal layer 25 and the fourth metal layer 26 is copper, which has low internal resistance and can be directly bonded to the DBC. The first metal connection 19 and the second metal connection 28 can be connected to the gate lead of the first power device chip 18 and the second power device chip 27, or the electrode lead of the control circuit part. The material of the conductor layer is preferably a material with good thermal conductivity. The height of the first metal layer 16, the second metal layer 17, the third metal layer 25 and the fourth metal layer 26 is close to the thickness of the first power device chip 18 or the second power device chip 27, and the edges of the first metal layer 16, the second metal layer 17, the third metal layer 25 and the fourth metal layer 26 cover the first DBC substrate 32 or the second DBC substrate 34 (DBC layer).

[0028] Specifically, the power device chips on the front side (upper surface of the first insulating layer 10) and the back side (lower surface of the first insulating layer 10) are connected in parallel, and the operating current is shown as follows: Figure 4 As shown, opposite current directions and the same current density can greatly reduce the parasitic inductance of the package. In theory, the magnetic field between traces with equal and opposite current directions can be weakened, and the parasitic inductance can be offset, that is, the currents of the first current branch (light arrow input to dark arrow output) and the second current branch (dark arrow input to light arrow output) are equal and opposite, which can reduce the parasitic inductance of the double-sided package structure. In other words, multiple conductor layers and insulation layers are staggered and stacked to achieve multi-layer wiring and facilitate routing, control the current size and direction of the routing, and eliminate parasitic inductance. In addition, as Figure 5 As shown, after filling insulating plastic on the front and back sides according to actual application needs, a heat sink can be added to the double-sided packaging structure to improve the heat dissipation performance of the power device chip after packaging.

[0029] See also Figure 6 Optionally, the preparation process of the double-sided packaging structure includes: S1: providing a first insulating layer 10, and growing a first conductor layer 11 and a fourth conductor layer 20 on the upper surface and the lower surface of the first insulating layer 10 respectively; S2: etching the first conductor layer 11 and the fourth conductor layer 20 to produce a completely mirrored current path; S3: forming a second insulating layer 12 on the upper surface of the first conductor layer 11 and forming a third insulating layer 21 on the lower surface of the fourth conductor layer 20; S4: etching via holes on both sides of the insulating ceramic, etching the second insulating layer 12 and the third insulating layer 21 to form a first via hole 13 and a second via hole 22 respectively; S5: filling the first via hole 13 with a second conductor layer 14 and forming a third conductor layer 15 on the upper surface of the second insulating layer 12, and filling the second via hole 22 with a fifth conductor layer 23 and forming a sixth conductor layer 24 on the lower surface of the third insulating layer 21 corresponding to the third conductor layer 15; S6: The first power device chip 18 is bonded to one side of the third conductor layer 15 and the second power device chip 27 is bonded to one side of the sixth conductor layer 24; S7: A first metal layer 16 is formed on the upper surface of the second conductor layer 14, a second metal layer 17 is formed on the other side of the third conductor layer 15, a third metal layer 25 is formed on the lower surface of the fifth conductor layer 23, and a fourth metal layer 26 is formed on the other side of the sixth conductor layer 24. The first power device chip 18 is connected to the second conductor layer 14 through the first metal connection 19, and the second power device chip 27 is connected to the fifth conductor layer 23 through the second metal connection 28.

[0030] In this embodiment, double-sided DBC covering is used to form a first heat dissipation component located above the first power device chip 18 and a second heat dissipation component located below the second power device chip 27, and the first heat dissipation component and the second heat dissipation component are symmetrically arranged about the first insulating layer 10. The preparation process of the double-sided packaging structure includes: growing a conductor layer on both sides of the central insulating ceramic; etching the front and back conductor layers to make a completely mirrored current path; double-sided covering and filling insulating ceramics; double-sided etching of vias in insulating ceramics; double-sided production of covering conductor layers, and double-sided etching of conductor layers; high-temperature smelting; bonding of power device chips; production of metal leads (metal layers) and metal connections; and double-sided DBC covering.

[0031] In all examples shown and described herein, any specific values ​​should be interpreted as merely exemplary and not as limiting, and thus other examples of the exemplary embodiments may have different values.

[0032] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0033] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the present invention. It should be pointed out that for ordinary technicians in this field, several modifications and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention.

Claims

1. A low parasitic inductance double-sided packaging structure for a power device, characterized in that: The double-sided packaging structure comprises: a first insulating layer; A first conductor layer formed on the upper surface of the first insulating layer, second insulating layers arranged at intervals on the upper surface of the first conductor layer, and a first via hole located between the second insulating layers; a second conductor layer filled in the first via hole and a third conductor layer located on the upper surface of the second insulating layer; A first metal layer formed on the upper surface of the second conductor layer, a second metal layer on one side of the third conductor layer, and a first power device chip on the other side of the third conductor layer, wherein the first power device chip is connected to the second conductor layer via a first metal connection; A fourth conductor layer formed on the lower surface of the first insulating layer, third insulating layers arranged at intervals on the lower surface of the fourth conductor layer, and second via holes located between the third insulating layers and arranged corresponding to the first via holes; a fifth conductor layer filled in the second via hole, and a sixth conductor layer located on the lower surface of the third insulating layer and arranged corresponding to the third conductor layer; A third metal layer is formed on the lower surface of the fifth conductor layer, a fourth metal layer is formed on one side of the sixth conductor layer, and a second power device chip is formed on the other side of the sixth conductor layer. The second power device chip is connected to the fifth conductor layer through a second metal connection.

2. The low parasitic inductance double-sided packaging structure for power devices according to claim 1, characterized in that: The projected area of ​​the third conductive layer on the first insulating layer is smaller than the projected area of ​​the second insulating layer on the first insulating layer, and the projected area of ​​the sixth conductive layer on the first insulating layer is smaller than the projected area of ​​the third insulating layer on the first insulating layer.

3. The low parasitic inductance double-sided packaging structure for power devices according to claim 2, characterized in that: The thickness of the first conductor layer, the third conductor layer, the fourth conductor layer and the sixth conductor layer is between 0.1 mm and 0.5 mm.

4. The low parasitic inductance double-sided packaging structure for power devices according to claim 2, characterized in that: The thickness of the first insulating layer, the second insulating layer and the third insulating layer is between 0.2 and 1 mm.

5. The low parasitic inductance double-sided packaging structure for power devices according to claim 1, characterized in that: The first metal layer, the second metal layer and the first power device chip are flush with each other, and the third metal layer, the fourth metal layer and the second power device chip are flush with each other.

6. The low parasitic inductance double-sided packaging structure for power devices according to claim 1, characterized in that: The double-sided packaging structure also includes: A first heat dissipation component, the first heat dissipation component comprising a first heat sink, a first adhesive layer and a first DBC substrate stacked in sequence, the first DBC substrate being close to the first power device chip, and the first heat sink being far away from the first power device chip; The second heat dissipation component includes a second DBC substrate, a second adhesive layer and a second heat sink stacked in sequence, the second DBC substrate is close to the second power device chip, and the second heat sink is far away from the second power device chip.

7. The low parasitic inductance double-sided packaging structure for a power device according to claim 1, characterized in that: When the first metal layer inputs a first current of a first current density, the first current sequentially passes through the second conductor layer, the first conductor layer, the second conductor layer, the first metal connection line, the first power device chip, the third conductor layer and the second metal layer to form a first current branch; When the fourth metal layer inputs a second current of a second current density, the second current passes through the sixth conductor layer, the second power device chip, the second metal connection, the fourth conductor layer and the fifth metal layer in sequence to form a second current branch, the first current density is the same as the second current density, and the currents of the first current branch and the second current branch are equal and in opposite directions.

8. The low parasitic inductance double-sided packaging structure for power devices according to claim 1, characterized in that: The first insulating layer, the second insulating layer and the third insulating layer are all made of insulating ceramics, and the first conductor layer, the second conductor layer, the third conductor layer, the fourth conductor layer, the fifth conductor layer and the sixth conductor layer are all made of copper.

9. The low parasitic inductance double-sided packaging structure for a power device according to claim 1, characterized in that: The preparation process of the double-sided packaging structure includes: Providing a first insulating layer, and growing a first conductor layer and a fourth conductor layer on the upper surface and the lower surface of the first insulating layer respectively; Etching the first conductor layer and the fourth conductor layer to produce a completely mirrored current path; A second insulating layer is formed on the upper surface of the first conductor layer and a third insulating layer is formed on the lower surface of the fourth conductor layer; Etching via holes on both sides of the insulating ceramic, etching the second insulating layer and the third insulating layer to form a first via hole and a second via hole respectively; Filling the first via hole with a second conductor layer and forming a third conductor layer on the upper surface of the second insulating layer, and filling the second via hole with a fifth conductor layer and forming a sixth conductor layer on the lower surface of the third insulating layer corresponding to the third conductor layer; The first power device chip is bonded to one side of the third conductor layer and the second power device chip is bonded to one side of the sixth conductor layer; A first metal layer is formed on the upper surface of the second conductor layer, a second metal layer is formed on the other side of the third conductor layer, a third metal layer is formed on the lower surface of the fifth conductor layer, and a fourth metal layer is formed on the other side of the sixth conductor layer. The first power device chip is connected to the second conductor layer through a first metal connection, and the second power device chip is connected to the fifth conductor layer through a second metal connection.

10. The low parasitic inductance double-sided packaging structure for a power device according to claim 1, characterized in that: Also includes: Double-sided DBC covering forms a first heat dissipation component located above the first power device chip and a second heat dissipation component located below the second power device chip, wherein the first heat dissipation component and the second heat dissipation component are symmetrically arranged with respect to the first insulating layer.

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