Semiconductor package and method of manufacturing the same

Abstract

A semiconductor package and a method of manufacturing the semiconductor package are provided. The semiconductor package includes: a middleware; a semiconductor chip disposed on the middleware; a lower bump metal (UBM) pad disposed between the middleware and the semiconductor chip and including an upper UBM pad and a lower UBM pad; and a connection member disposed between the UBM pad and the semiconductor chip, in which the connection member is in contact with the UBM pad and a side surface of the middleware.

Description

Technical Field

[0001] The inventive concept relates to a semiconductor package and a method of manufacturing the same, and more particularly, to a semiconductor package including an intermediate member and a method of manufacturing the same. Background Art

[0002] According to the rapid development of the electronics industry and user needs, electronic devices have become more compact and multifunctional. Therefore, the demand for miniaturization and multifunctionality of semiconductor chips used in electronic devices has also increased. For this reason, semiconductor chips with micro-pitch connection terminals are required, and small-sized electrode pads are required to install large-capacity semiconductor chips in the limited structure of semiconductor packages. For this reason, a structure and method for electrically connecting connection terminals to small-sized electrode pads included in semiconductor packages are required. Summary of the invention

[0003] The inventive concept provides a semiconductor package having improved electrical characteristics and a method of manufacturing the semiconductor package.

[0004] The technical problems to be solved by the present inventive concept are not limited to the above-mentioned problems, and other unmentioned problems will be clearly understood by those skilled in the art through the following description.

[0005] According to one aspect of the present invention, a semiconductor package is provided, which includes: an intermediate member; a semiconductor chip arranged on the intermediate member; an under bump metal (UBM) pad, which is arranged between the intermediate member and the semiconductor chip and includes an upper UBM pad and a lower UBM pad; and a connecting member, which is arranged between the UBM pad and the semiconductor chip, wherein the connecting member contacts the UBM pad and the side surface of the intermediate member.

[0006] According to another aspect of the inventive concept, a method of manufacturing a semiconductor package is provided, the method comprising: forming an intermediate member; forming a UBM pad on the intermediate member; forming a plating layer on the UBM pad; and attaching a connection member to the UBM pad, wherein the plating layer contacts a side surface of the UBM pad.

[0007] According to another aspect of the inventive concept, a method for manufacturing a semiconductor package is provided, the method comprising: forming an intermediate member; forming a UBM pad on the intermediate member; mounting a semiconductor chip on the UBM pad; and molding the semiconductor chip, wherein mounting the semiconductor chip on the UBM pad comprises forming a plating layer on the UBM pad and attaching a connecting member to the UBM pad, the plating layer contacting a side surface of the UBM pad. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 is a cross-sectional view showing a semiconductor package according to an embodiment;

[0010] Figure 2 According to the embodiment Figure 1 an enlarged cross-sectional view of region A;

[0011] Figure 3 According to the embodiment Figure 1 an enlarged cross-sectional view of region A;

[0012] Figure 4 According to the embodiment Figure 1 an enlarged cross-sectional view of region A;

[0013] Figure 5 According to the embodiment Figure 1 an enlarged cross-sectional view of region A;

[0014] Figure 6 According to the embodiment Figure 1 an enlarged cross-sectional view of region A;

[0015] Figure 7 According to the embodiment Figure 1 an enlarged cross-sectional view of region A of FIG. Figures 8 to 15 is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to an embodiment. DETAILED DESCRIPTION

[0016] Hereinafter, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. The same reference numerals are used to refer to the same components in the drawings, and repeated descriptions thereof are omitted.

[0017] Figure 1 is a cross-sectional view showing a semiconductor package 10 according to an embodiment. Figure 2 According to the embodiment Figure 1 An enlarged cross-sectional view of area A.

[0018] Reference Figure 1 and Figure 2 , the semiconductor package 10 includes an intermediate member 100 , an under bump metal (UBM) structure 140 , a connection member 150 , an external connection terminal 160 , a semiconductor chip 200 , and a molding layer 300 .

[0019] When the semiconductor chip 200 is miniaturized and / or the number of input / output terminals increases, the semiconductor package 10 has a limitation in accommodating all the external connection terminals 160 that are input / output terminals within the main surface of the semiconductor chip 200. Therefore, a fan-out wafer level package (FO-WLP) or fan-out panel level package (FO-PLP) structure including the external connection terminals 160 is applied to the semiconductor package 10 by extending the intermediate member 100 to the molding layer 300 forming the outer peripheral surface of the semiconductor chip 200.

[0020] In addition, the semiconductor package 10 in the FO package may be implemented using a chip-last manufacturing method in which the intermediate member 100 is first formed on a carrier substrate and then the semiconductor chip 200 is mounted on the formed intermediate member 100 .

[0021] The middleware 100 may electrically connect different semiconductor chips 200 to each other. In this specification, the middleware 100 is shown as a redistribution layer (RDL) middleware, but the middleware 100 may include various types of middleware, such as a silicon middleware and / or an organic middleware. Hereinafter, the case where the middleware 100 is an RDL middleware (i.e., a redistribution structure 100) will be described as an example.

[0022] The redistribution structure 100 may be disposed on a lower portion of the semiconductor package 10. The redistribution structure 100 may transmit an electrical signal of the semiconductor chip 200 to the external connection terminal 160. Conversely, the redistribution structure 100 may transmit an electrical signal received through the external connection terminal 160 to the semiconductor chip 200. Alternatively, the redistribution structure 100 may transmit an electrical signal between the semiconductor chips 200. The middleware 100 may electrically connect different semiconductor chips 200 to each other.

[0023] The redistribution structure 100 may include a redistribution insulating layer 110, a redistribution line pattern 120, and a redistribution through-piece pattern 130. The redistribution structure 100 may be formed as a single metal wiring layer or a multi-metal wiring layer. For example, the redistribution structure 100 may include copper (Cu), nickel (Ni), gold (Au), chromium (Cr), titanium (Ti), or palladium (Pd) or an alloy thereof. In some embodiments, the redistribution structure 100 may be formed using an electroplating process.

[0024] The redistribution insulating layer 110 may be formed as a single layer or multiple layers. The redistribution insulating layer 110 may include an insulating material, for example, a photoimageable dielectric (PID) resin, and may further include a photosensitive polyimide and / or an inorganic filler. All layers of the redistribution insulating layer 110 may include the same material, or at least one layer thereof may include a different material.

[0025] Although Figure 1 and Figure 2Although not shown in the drawings, the semiconductor package 10 may further include a protection layer that protects pads on the upper and / or lower surfaces of the redistribution structure 100 .

[0026] The redistribution line pattern 120 and the redistribution through-piece pattern 130 may transmit electrical signals and / or heat in the redistribution structure 100. The redistribution line pattern 120 may be formed in the redistribution insulating layer 110 and may extend in the horizontal direction (X direction and / or Y direction). The redistribution through-piece pattern 130 may electrically connect the redistribution line patterns 120 spaced apart in the vertical direction (Z direction) and may extend in the vertical direction (Z direction). The redistribution line pattern 120 and the redistribution through-piece pattern 130 may each include a metal such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), ruthenium (Ru) or an alloy thereof, but is not limited thereto.

[0027] The redistribution line pattern 120 and the redistribution via pattern 130 may be formed using a plating method. For example, the redistribution line pattern 120 and the redistribution via pattern 130 may be formed using a plating method such as immersion plating, electroless plating, or electroplating.

[0028] In some embodiments, the plurality of redistribution via patterns 130 may each have a tapered shape with a decreasing horizontal width extending from top to bottom. That is, the plurality of redistribution via patterns 130 may each have a horizontal width decreasing away from the semiconductor chip 200 in a vertical direction (Z direction).

[0029] In this specification, a direction parallel to the main surface of the redistribution structure 100 may be referred to as a horizontal direction (X direction and / or Y direction), and a direction perpendicular to the horizontal direction (X direction and / or Y direction) may be referred to as a vertical direction (Z direction).

[0030] The UBM structure 140 may be formed on the redistribution structure 100. The UBM structure 140 may be located in the opening of the redistribution structure 100. The UBM structure 140 may be in contact with the uppermost redistribution line pattern 120 and / or the uppermost redistribution via pattern 130. Figure 1 and Figure 2 , the UBM structure 140 is shown as being in contact with the redistribution line pattern 120, but the UBM structure 140 may be in contact with the redistribution via pattern 130. As will be described below, the UBM structure 140 and the connection member 150 may electrically connect the redistribution line pattern 120 and the redistribution via pattern 130 to the semiconductor chip 200.

[0031] The UBM structure 140 may include an adhesive layer 142, a seed layer 143, a lower UBM pad 144, and an upper UBM pad 146. The lower UBM pad 144 and the upper UBM pad 146 may be collectively referred to as a UBM pad 147.

[0032] The adhesive layer 142 and the seed layer 143 may be disposed between the UBM pad 147 and the redistribution line pattern 120 and / or the redistribution through-piece pattern 130. The seed layer 143 may be disposed on the adhesive layer 142. The adhesive layer 142 and the seed layer 143 may be disposed on the lower portion of the UBM structure 140 and may be formed to extend conformally. Specifically, the adhesive layer 142 may be formed to conformally extend to a portion of the upper surface of the redistribution structure 100. In addition, the seed layer 143 may be formed to conformally extend to at least a portion of each of the lower surface of the lower UBM pad 144, the side surface of the lower UBM pad 144, and the lower surface of the upper UBM pad 146.

[0033] Adhesion layer 142 may enhance adhesion between redistribution structure 100 and UBM pad 147. For example, adhesion layer 142 may include a metal including at least one selected from titanium (Ti), titanium tungsten (TiW), nickel vanadium (NiV), and chromium (Cr), or an alloy thereof. Seed layer 143 may be used as a seed when forming UBM pad 147. Seed layer 143 may provide a path through which current may flow when UBM pad 147 is formed by an electroplating process, and allows UBM pad 147 to be formed on seed layer 143. Seed layer 143 may include a metal including at least one selected from copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), and titanium (Ti), or an alloy thereof.

[0034] In the present inventive concept, seed layer 143 and UBM pad 147 include different materials so that there is an interface therebetween, but in another embodiment, when seed layer 143 and UBM pad 147 include the same material, seed layer 143 and UBM pad 147 may be integrally formed since there is no interface therebetween.

[0035] The UBM pads 147 may include a lower UBM pad 144 disposed adjacent to a lower portion of the UBM structure 140 and an upper UBM pad 146 disposed adjacent to an upper portion of the UBM structure 140. An upper surface of the upper UBM pad 146 may have a flat shape.

[0036] Lower UBM pad 144 may contact seed layer 143 and upper UBM pad 146. In more detail, at least a portion of each of a lower surface and a side surface of lower UBM pad 144 may contact seed layer 143. In addition, at least a portion of an upper surface of lower UBM pad 144 may contact upper UBM pad 146.

[0037] Upper UBM pad 146 may contact lower UBM pad 144 and connection member 150. In more detail, at least a portion of a lower surface of upper UBM pad 146 may contact lower UBM pad 144, and at least a portion of each of an upper surface and a side surface of upper UBM pad 146 may contact connection member 150.

[0038] The UBM pad 147 may have a T-shape. That is, a first width W1 that is a horizontal width of the lower UBM pad 144 may be smaller than a second width W2 that is a horizontal width of the upper UBM pad 146 .

[0039] In this specification, lower UBM pad 144 and upper UBM pad 146 are just formal divisions for explanation purposes, and lower UBM pad 144 and upper UBM pad 146 may be integrally formed. In another embodiment, lower UBM pad 144 and upper UBM pad 146 may be separately formed.

[0040] In addition, the connection member 150 may be disposed on the UBM structure 140. The connection member 150 may be a solder bump. The UBM structure 140 and the connection member 150 may electrically connect the redistribution line pattern 120 and the redistribution via pattern 130 to the semiconductor chip 200.

[0041] The connection member 150 may contact each of the redistribution structure 100, the UBM structure 140, and the chip pad 240 of the semiconductor chip 200. In more detail, the connection member 150 may contact at least a portion of each of the upper surface of the uppermost redistribution insulation layer 110, the side surface of the adhesive layer 142, the side surface of the seed layer 143, and the side surface of the UBM pad 147. Figures 8 to 15 The reason why the connection member 150 has such a shape is explained in more detail.

[0042] The connection member 150 is formed to contact at least a portion of the side surface of the UBM structure 140, and thus, the electrical connection between the connection member 150 and the UBM structure 140 can be enhanced. Therefore, the contact area between the UBM structure 140 and the connection member 150 increases and wettability is enhanced, and thus, the semiconductor package 10 can achieve fine bumps and / or fine pad pitches.

[0043] A plurality of external connection terminals 160 may be provided on the lower surface of the redistribution structure 100. The external connection terminals 160 may transmit electrical signals of the semiconductor chip 200 to the outside of the semiconductor package 10. Conversely, the external connection terminals 160 may transmit electrical signals outside the semiconductor package 10 to the semiconductor chip 200. Through the external connection terminals 160, the semiconductor package 10 may be electrically connected to a main board (e.g., a printed circuit board (PCB)) of an electronic device on which the semiconductor package 10 is mounted. The external connection terminals 160 may include solder bumps and / or solder balls. The redistribution structure 100 may be electrically connected to the external connection terminals 160 through the lowermost redistribution line pattern 120.

[0044] Although Figure 1 Although not shown in the drawings, the pad directly contacting the external connection terminal 160 may also have a shape similar to that of the UBM structure 140 .

[0045] The semiconductor chip 200 may be disposed on the connection member 150. The semiconductor chip 200 may include a semiconductor substrate 220 and a chip pad 240. The semiconductor chip 200 may be a logic chip or a memory chip. The logic chip may be, for example, a microprocessor, an analog device, or a digital signal processor. In addition, the memory chip may be a volatile memory chip such as a dynamic random access memory (DRAM) or a static random access memory (SRAM), or may be a non-volatile memory chip such as a phase change random access memory (PRAM), a magnetoresistive random access memory (MRAM), a resistance random access memory (RRAM), or a ferroelectric random access memory (FeRAM). In some embodiments, the semiconductor chip 200 may be a high bandwidth memory chip. The semiconductor package 10 may include a plurality of semiconductor chips 200.

[0046] The semiconductor chip 200 may be understood as a concept including a semiconductor device having an integrated circuit. Specifically, the semiconductor chip 200 may include a semiconductor substrate 220 including an active surface and a passive surface facing each other. A circuit unit that implements the integrated circuit function of the semiconductor chip 200 may be formed on the active surface of the semiconductor substrate 220 by a semiconductor manufacturing process. That is, on the semiconductor substrate 220, a wiring layer such as a conductive wiring, an interlayer insulating layer disposed between the wiring layers, and a separate unit device may be formed.

[0047] In addition, the semiconductor chip 200 may include a chip pad 240 formed on the semiconductor substrate 220, and the chip pad 240 extends the function of the circuit to the outside. The chip pad 240 may have a peripheral portion covered by a protective layer formed on the active surface of the semiconductor substrate 220 and a central portion opened by the protective layer. The protective layer may physically and chemically protect the semiconductor device on the active side of the semiconductor substrate 220. The protective layer may include, for example, an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride, an organic insulating material such as an insulating polymer, or an insulating material including a combination thereof.

[0048] For example, the chip pad 240 may have a polygonal shape such as a square, a hexagon or an octagon, or a circular or elliptical shape. The chip pad 240 may have a certain size or more to withstand electrical and mechanical stress. The connection member 150 may be disposed on a lower portion of the chip pad 240 .

[0049] In the present specification, the lower surface of the components of the semiconductor package 10 except the external connection terminals 160 may be defined as a surface adjacent to the external connection terminals 160 of two surfaces of the components spaced apart in the vertical direction (Z direction), and a surface opposite to the lower surface of the components may be defined as an upper surface of the components. In addition, a surface in contact between the redistribution structure 100 and the external connection terminals 160 may be defined as an upper surface of the external connection terminals 160, and a surface opposite to the upper surface of the external connection terminals 160 may be defined as a lower surface of the external connection terminals 160.

[0050] A mold layer 300 covering at least a portion of each of the UBM structure 140, the connection member 150, and the semiconductor chip 200 may be formed on the redistribution structure 100. The mold layer 300 may protect the semiconductor chip 200 from external influences such as contamination and / or vibration. For example, the mold layer 300 may include an epoxy molding compound, a resin, and the like. In addition, the mold layer 300 may be formed by processes such as molding, lamination, and screen printing. In some embodiments, the mold layer 300 may cover only the side surface of the semiconductor chip 200, so that the upper surface of the semiconductor chip 200 is exposed to the outside. The mold layer 300 may configure the appearance of the semiconductor package 10, and the redistribution structure 100 may be expanded and arranged by utilizing the mold layer 300.

[0051] In a conventional semiconductor package, the connection member contacts only the upper surface of the UBM structure but not the side surface thereof. Therefore, the electrical connectivity between the UBM structure and the connection member is relatively low, resulting in a problem of relatively low electrical reliability of the semiconductor package.

[0052] On the other hand, in the semiconductor package 10 of the present inventive concept, the connection member 150 contacts at least a portion of each of the upper surface and the side surface of the UBM structure 140, and thus, the electrical connectivity between the UBM structure 140 and the connection member 150 may be relatively high. Therefore, the wettability of the connection member 150 is improved, and thus, the electrical reliability of the semiconductor package 10 may be relatively high.

[0053] Figure 3 and Figure 4 According to the embodiment Figure 1 An enlarged cross-sectional view of region A. Figure 1 and Figure 2 Described together Figure 3 and Figure 4 Embodiment of the invention.

[0054] Reference Figure 3 and Figure 4 , Figure 3 The UBM structure 140a may include an adhesive layer 142, a seed layer 143, a lower UBM pad 144, an upper UBM pad 146, and a first additional plating layer 148. Figure 4 The UBM structure 140 b may include an adhesive layer 142 , a seed layer 143 , a lower UBM pad 144 , an upper UBM pad 146 , a first additional plating layer 148 , and a second additional plating layer 149 . Figure 3 and Figure 4 The adhesive layer 142, the seed layer 143, the lower UBM pad 144 and the upper UBM pad 146 are respectively Figure 1 and Figure 2 The adhesive layer 142 , the seed layer 143 , the lower UBM pad 144 , and the upper UBM pad 146 of the UBM structure 140 are substantially the same, and therefore, the first additional plating layer 148 and the second additional plating layer 149 are mainly described herein.

[0055] The first additional plating layer 148 and / or the second additional plating layer 149 may be used as a barrier layer. The first additional plating layer 148 and / or the second additional plating layer 149 may be disposed between the UBM pad 147 and the connection member 150. The first additional plating layer 148 and / or the second additional plating layer 149 may be disposed between the upper UBM pad 146 and the connection member 150. The first additional plating layer 148 and the second additional plating layer 149 may be sequentially stacked on the upper UBM pad 146.

[0056] The first additional plating layer 148 and the second additional plating layer 149 may each include a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The first additional plating layer 148 and the second additional plating layer 149 may include different materials. In another embodiment, the first additional plating layer 148 and the second additional plating layer 149 may include the same material.

[0057] The first additional plating layer 148 and / or the second additional plating layer 149 are disposed between the UBM pad 147 and the connection member 150, and thus the connection member 150 may be in contact with the side surface of the UBM pad 147 and spaced apart from the upper surface of the UBM pad 147. That is, the UBM pad 147 may be in contact with the lower surface of the first additional plating layer 148 and / or the lower surface of the second additional plating layer 149.

[0058] exist Figure 3 and Figure 4 , one and two plating layers are shown as being respectively disposed between the UBM pad 147 and the connection member 150 , but the inventive concept is not limited thereto. For example, three or more plating layers may be disposed between the UBM pad 147 and the connection member 150 .

[0059] Figure 5 and Figure 6 According to the embodiment Figure 1 An enlarged cross-sectional view of region A. Figure 1 and Figure 2 Describe together Figure 5 and Figure 6 Embodiment of the invention.

[0060] Reference Figure 5 and Figure 6 , Figure 5 The UBM structure 140c may include an adhesive layer 142, a seed layer 143, a lower UBM pad 144 and an upper UBM pad 146a. Figure 6 The UBM structure 140d may include an adhesive layer 142, a seed layer 143, a lower UBM pad 144, and an upper UBM pad 146b. Figure 5 and Figure 6 The adhesive layer 142, the seed layer 143 and the lower UBM pad 144 are respectively Figure 1 and Figure 2 The adhesive layer 142 , the seed layer 143 , and the lower UBM pads 144 of the semiconductor package 10 are substantially the same, and therefore, the upper UBM pads 146 a and 146 b are mainly described herein.

[0061] Figure 5 The upper surface of the upper UBM pad 146a may have an upwardly convex shape, and Figure 6The upper surface of the upper UBM pad 146b may have a downwardly convex shape. That is, Figure 5 The upper surface of the upper UBM pad 146a may include a convex rounded surface 146aR, and Figure 6 The upper surface of upper UBM pad 146b may include a recessed rounded surface 146bR. This may be a feature resulting from the process of forming each of upper UBM pads 146a and 146b.

[0062] The shapes of upper UBM pads 146a and 146b are not limited thereto and may be modified in various ways. For example, the upper surfaces of upper UBM pads 146a and 146b may each have a concave-convex shape. That is, at least a portion of the upper surfaces of upper UBM pads 146a and 146b may not be flat.

[0063] Figure 7 According to the embodiment Figure 1 An enlarged cross-sectional view of region A. Figure 1 and Figure 2 Describe together Figure 7 Embodiment of the invention.

[0064] Reference Figure 7 , the UBM structure 140e may include an adhesive layer 142a, a seed layer 143a, a lower UBM pad 144, and an upper UBM pad 146c. A first width W1 as a horizontal width of the lower UBM pad 144 may be greater than a second width W2a as a horizontal width of the upper UBM pad 146c. In another embodiment, the first width W1 as a horizontal width of the lower UBM pad 144 may be equal to the second width W2a as a horizontal width of the upper UBM pad 146c.

[0065] When the first width W1 is equal to the second width W2a and / or the first width W1 is greater than the second width W2a, the adhesive layer 142a and the seed layer 143a may be spaced apart from the upper UBM pad 146c. That is, the adhesive layer 142a may not contact the upper UBM pad 146c. The adhesive layer 142a may contact at least a portion of each of the lower surface and the side surface of the lower UBM pad 144. In addition, the connecting member 150 may contact the redistribution structure 100, the UBM structure 140e, and the molding layer 300. In more detail, the connecting member 150 may contact the redistribution insulation layer 110, the adhesive layer 142a, the lower UBM pad 144, and / or the upper UBM pad 146c.

[0066] Figures 8 to 15 is a cross-sectional view showing a method of manufacturing a semiconductor package according to an embodiment. Figures 1 to 7 describe Figures 8 to 15 method.

[0067] Reference Figure 8 , a redistribution structure 100 including a redistribution insulation layer 110 , a redistribution line pattern 120 , and a redistribution via pattern 130 may be formed on the first carrier substrate CS1 .

[0068] The first carrier substrate CS1 may support the redistribution structure 100 and may include a material having stability with respect to semiconductor processes. For example, the first carrier substrate CS1 may include glass or alumina. In order for the first carrier substrate CS1 to stably support the redistribution structure 100, a first adhesive film (not shown) may be provided between the first carrier substrate CS1 and the redistribution structure 100.

[0069] The redistribution line pattern 120 and the redistribution through-piece pattern 130 may be formed by forming a redistribution insulating layer 110 including a photosensitive insulating material on the first carrier substrate CS1 and performing an exposure process and a development process on the photosensitive insulating material. After at least a portion of the redistribution insulating layer 110 may be removed by an etching process, the redistribution line pattern 120 and the redistribution through-piece pattern 130 may be formed by a plating process. The redistribution line pattern 120 may extend in a horizontal direction (X direction and / or Y direction) within the redistribution insulating layer 110, and the redistribution through-piece pattern 130 may extend in a vertical direction (Z direction) within the redistribution insulating layer 110. The redistribution line pattern 120 and the redistribution through-piece pattern 130 may be formed by stacking a metal and / or a metal alloy on a seed layer.

[0070] For example, the redistribution insulating layer 110 may include an insulating material such as a PID resin, and may further include a photosensitive polyimide and / or an inorganic filler, but is not limited thereto. The redistribution line pattern 120 and the redistribution through-piece pattern 130 may each include a metal such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), ruthenium (Ru) or an alloy thereof, but is not limited thereto.

[0071] By repeating this process multiple times, the redistribution structure 100 may be formed. Then, a plurality of first openings OP1 may be formed by removing at least a portion of an upper portion of the redistribution structure 100. Each of the plurality of first openings OP1 may expose at least a portion of an upper surface of the uppermost redistribution line pattern 120 and / or the uppermost redistribution through-piece pattern 130 to the outside. Figure 8 , a portion of an upper surface of the redistribution line pattern 120 is shown as being exposed through the first opening OP1 , but a portion of an upper surface of the redistribution via pattern 130 may be exposed through the first opening OP1 .

[0072] In addition, Figure 8 , the upper surface of the redistribution line pattern 120 is shown as being exposed by removing at least a portion of the upper portion of the redistribution insulation layer 110, but the upper surface of the redistribution line pattern 120 may be exposed by adding a protective layer (not shown) on the redistribution insulation layer 110 and then removing at least a portion of the protective layer. In this case, the protective layer may include an inorganic insulating material, an organic insulating material, or an insulating material including a combination thereof.

[0073] Reference Fig. 9 ,exist Figure 8 The initial adhesive layer 142p and the initial seed layer 143p are formed on the resultant. Figure 8 The initial bonding layer 142p and the initial seed layer 143p are conformally formed on the resultant. Figure 8 At least a portion of each of the initial adhesion layer 142p and the initial seed layer 143p is disposed in the first opening OP1 of the substrate. The initial adhesion layer 142p may include a metal including at least one selected from titanium (Ti), titanium tungsten (TiW), nickel vanadium (NiV), and chromium (Cr), or an alloy thereof. The initial seed layer 143p may include a metal including at least one selected from copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), and titanium (Ti), or an alloy thereof.

[0074] Initial adhesive layer 142p may increase the adhesive force between redistribution structure 100 and UBM pad 147. Initial seed layer 143p may be a seed for forming lower UBM pad 144 and upper UBM pad 146. For example, when lower UBM pad 144 and upper UBM pad 146 are formed by an electroplating process, initial seed layer 143p may provide a path through which current may flow, so that lower UBM pad 144 and upper UBM pad 146 may be formed on an upper portion of initial seed layer 143p.

[0075] Available in Figure 8 An initial adhesive layer 142p and an initial seed layer 143p are disposed in the first opening OP1 to form a second opening OP2. In a subsequent process, a lower UBM pad 144 may be formed in the second opening OP2.

[0076] Reference Fig.10 , a mask pattern MP is formed on the initial seed layer 143p. The mask pattern MP may expose at least a portion of the initial seed layer 143p. The portion of the initial seed layer 143p exposed by the mask pattern MP may correspond to a portion where a UBM pad 147 is formed in a subsequent process. With the formation of the mask pattern MP, a third opening OP3 may be formed. In a subsequent process, a UBM pad 147 may be formed in the second opening OP3.

[0077] Reference Fig.11 , available in Fig.10 The UBM pad 147 may be formed in the third opening OP3 of the substrate. The UBM pad 147 may be formed on the initial seed layer 143p. The UBM pad 147 may include a lower UBM pad 144 and an upper UBM pad 146. The UBM pad 147 may have a T-shape in which the horizontal width of the upper UBM pad 146 is greater than the horizontal width of the lower UBM pad 144.

[0078] To form the UBM pad 147, electroplating may be performed. For example, the UBM pad 147 may include a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The UBM pad 147 may be formed to partially fill the region defined by the mask pattern MP without completely filling the region. That is, the height of the UBM pad 147 may be formed to be lower than the height of the mask pattern MP.

[0079] Reference Fig.12 , can be removed by performing an ashing process and a stripping process Fig.11 In addition, the mask pattern MP may be removed by dry etching and / or wet etching. Fig.11 The initial bonding layer 142p and Fig.11 Adhesive layer 142 and seed layer 143 are formed by at least a portion of each of initial seed layers 143p. A side surface of upper UBM pad 146 may be aligned with a side surface of each of adhesive layer 142 and seed layer 143 in a vertical direction (Z direction).

[0080] An adhesive layer 142 and a seed layer 143 may be disposed between the redistribution structure 100 and the UBM pad 147. The adhesive layer 142 may contact at least a portion of each of the redistribution insulation layer 110 and the redistribution line pattern 120. The seed layer 143 may contact a lower surface of the lower UBM pad 144, a side surface of the lower UBM pad 144, and at least a portion of a lower surface of the upper UBM pad 146.

[0081] Reference Fig.13 , a plating layer PL is formed to cover at least a portion of each of the upper surface and the side surface of the upper UBM pad 146. In order for the plating layer PL to cover the side surface of the adhesive layer 142, the side surface of the seed layer 143, and the side surface of the upper UBM pad 146, the plating layer PL may be formed after removing the mask pattern MP.

[0082] The plating layer PL may include a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) or an alloy thereof. The plating layer PL may be formed using an electroless plating method. For example, the plating layer PL may be formed using an immersion plating method. When the plating layer PL is formed using an electroless plating method, the thickness of the plating layer PL may be reduced, and the manufacturing process may be simple, and therefore, the plating layer PL may be effectively formed. In addition, when the plating layer PL is formed using an electroless plating method, electrical noise may be reduced and process stability may be increased.

[0083] Although not shown in the drawings, a surface treatment may be performed on the upper UBM pad 146 before forming the plating layer PL.

[0084] Although Fig.13 14. However, when the first additional plating layer 148 and / or the second additional plating layer 149 are provided between the upper surface of the upper UBM pad 146 and the plating layer PL, a Figure 3 or Figure 4 UBM pad 147.

[0085] Reference Fig.14 ,exist Fig.13 A semiconductor chip 200 is mounted on the resultant, and a mold layer 300 is formed on the redistribution structure 100 .

[0086] First, the connection member 150 may be mounted on the UBM pad 147. The connection member 150 in contact with the semiconductor chip 200 may be attached to the plating layer PL through a reflow process. As described above, the plating layer PL is formed on the upper surface and the side surface of the upper UBM pad 146, and thus, the connection member 150 may also be in contact with the upper surface and the side surface of the upper UBM pad 146. In addition, the connection member 150 may be in contact with the upper surface of the redistribution structure 100, the adhesive layer 142, and the seed layer 143. Therefore, the contact surface between the connection member 150 and the UBM pad 147 is increased, and thus, the electrical characteristics of the semiconductor package 10 may be improved.

[0087] In the process of attaching the connection member 150 to the UBM pad 147, the plating layer PL may diffuse into the connection member 150. Therefore, the UBM pad 147 and the connection member 150 may contact each other, and the connection member 150 may include the material of the plating layer PL. For example, when the plating layer PL includes gold (Au), the connection member 150 may also include gold (Au).

[0088] Semiconductor chip 200 may be an independent semiconductor die or may be a sub-package in which a semiconductor die is molded. Semiconductor chip 200 is mounted so that the active surface on which chip pad 240 is formed faces downward so that chip pad 240 of semiconductor chip 200 may be aligned with the upper surface of UBM pad 147 .

[0089] A plurality of semiconductor chips 200 may be mounted. Some of the plurality of semiconductor chips 200 may be logic chips, and others may be memory chips.

[0090] In the process of electrically connecting the connection member 150 to the semiconductor chip 200, a gap may be formed between the connection member 150 and the semiconductor chip 200. Because the gap may cause a problem in connection reliability between the connection member 150 and the semiconductor chip 200, an underfill (not shown) may be injected and hardened to strengthen the connection.

[0091] Through the underfill, the semiconductor chip 200 is more stably fixed on the connection member 150, and the connection member 150 and the semiconductor chip 200 are not electrically separated despite the difference in thermal expansion coefficient between the connection member 150 and the semiconductor chip 200. In some cases, the mold layer 300 may be directly filled into the gap between the connection member 150 and the semiconductor chip 200, and in this case, the underfill may be unnecessary.

[0092] The mold layer 300 may cover the side surfaces and the upper surface of the semiconductor chip 200 on the redistribution structure 100. In some embodiments, the mold layer 300 may cover only the side surfaces of the semiconductor chip 200, so that the upper surface of the semiconductor chip 200 is exposed to the outside. The mold layer 300 may be used to protect the semiconductor chip 200 from external influences such as vibration. For example, the mold layer 300 may include an epoxy molding compound, a resin, etc.

[0093] Reference Fig.15 , the second carrier substrate CS2 may be attached to the mold layer 300 to face the first carrier substrate CS1, and the Fig.14 The first carrier substrate CS1.

[0094] The second carrier substrate CS2 may be Fig.14 In order to facilitate the attachment of the second carrier substrate CS2, a second adhesive film (not shown) may be formed between the second carrier substrate CS2 and the mold layer 300. The adhesive film may be in a liquid form or a gel form that is easily deformed under a certain pressure.

[0095] Then, after the resultant is turned over, the external connection terminal 160 may be formed on the lower surface of the redistribution structure 100. The external connection terminal 160 may be formed by a reflow process. The external connection terminal 160 may be formed on the lower surface of the redistribution structure 100 so that Figure 1 A semiconductor package 10 is provided.

[0096] In a general semiconductor package manufacturing method, a plating layer is provided on an upper surface of a UBM pad, and a side surface of the UBM pad does not contact a connection member.

[0097] On the other hand, in the method of manufacturing the semiconductor package of the present inventive concept, the plating layer PL may contact the side surface of the UBM pad 147, and the connection member 150 may contact the side surface of the UBM pad 147. Therefore, the contact area between the UBM pad 147 and the connection member 150 may be increased, and thus, the electrical characteristics of the semiconductor package 10 may be improved.

[0098] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor package, comprising: middleware; a semiconductor chip disposed on the middleware; an under-bump metal pad disposed between the intermediate member and the semiconductor chip and including an upper under-bump metal pad and a lower under-bump metal pad; and a connecting member disposed between the lower bump metal pad and the semiconductor chip, Wherein, the connection member contacts the under-bump metal pad and a side surface of the intermediate member.

2. The semiconductor package according to claim 1, further comprising: An additional plating layer is disposed between the upper under bump metal pad and the connection member.

3. The semiconductor package according to claim 1, further comprising: An adhesive layer and a seed layer are provided between the lower under-bump metal pad and the intermediate member, Wherein, the connecting member is in contact with the adhesive layer or the seed layer.

4. The semiconductor package according to claim 3, wherein: The adhesive layer and the seed layer are disposed along a lower surface and side surfaces of the lower under bump metal pad and along a lower surface of the upper under bump metal pad.

5. The semiconductor package according to claim 3, wherein: A side surface of the lower under bump metal pad, a side surface of the adhesive layer, and a side surface of the seed layer are aligned in a vertical direction.

6. The semiconductor package according to claim 1, wherein: The intermediate member includes a plurality of conductive line patterns and a plurality of conductive via patterns, and The plurality of conductive via patterns each have a tapered shape whose width decreases as it moves away from the semiconductor chip.

7. The semiconductor package according to claim 1, wherein: The upper under bump metal pad has a horizontal width wider than a horizontal width of the lower under bump metal pad.

8. The semiconductor package according to claim 1, wherein: An upper surface of the upper under-bump metal pad includes a rounded surface.

9. A method for manufacturing a semiconductor package, the method comprising: Forming middleware; forming an under-bump metal pad on the intermediate member; forming a plating layer on the lower bump metal pad; as well as attaching a connecting member to the lower bump metal pad, Wherein, the plating layer contacts the side surface of the lower bump metal pad.

10. The method according to claim 9, wherein: The connection member contacts a side surface of the under bump metal pad.

11. The method according to claim 9, wherein: The plating layer is in contact with the intermediate member.

12. The method according to claim 9, wherein: Forming the lower bump metal pad includes: forming an adhesive layer and a seed layer on the intermediate member; forming a mask pattern on the seed layer; and A pad is formed on the seed layer.

13. The method according to claim 12, wherein: The forming of the plating layer is performed after removing the mask pattern.

14. The method according to claim 9, further comprising: An additional plating layer is formed on the under bump metal pad in contact with the under bump metal pad.

15. The method according to claim 9, wherein: Forming the plated layer is performed by an electroless plating method.

16. A method for manufacturing a semiconductor package, the method comprising: Forming middleware; forming an under-bump metal pad on the intermediate member; Mounting a semiconductor chip on the lower bump metal pad; as well as molding the semiconductor chip, Wherein, mounting the semiconductor chip on the lower bump metal pad comprises: forming a plating layer on the under-bump metal pad; and attaching a connecting member to the lower bump metal pad, The plating layer contacts a side surface of the under-bump metal pad.

17. The method according to claim 16, wherein: Forming the under-bump metal pad includes: conformally forming an adhesive layer and a seed layer on the intermediate member, and The plating layer contacts the adhesive layer and the seed layer.

18. The method according to claim 16, further comprising: forming an additional plating layer on the under bump metal pad and in contact with the under bump metal pad, The additional plating layer includes a material different from that of the plating layer.

19. The method according to claim 16, wherein: The connecting member includes a material of the plating layer.

20. The method according to claim 16, wherein: Forming the plating layer is performed by an immersion plating method.

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