Packaged electronic device and manufacturing process thereof

Abstract

The invention relates to a packaged electronic device and a manufacturing process thereof. A packaged electronic device has a C-type lead frame including a base member and a lateral member extending laterally to the base member. A first die and a second die having a first contact region at the first major surface and a second contact region at the second major surface; first main surfaces of the first die and the second die are attached to a first face of the base portion of the lead frame. The first lead is coupled to the second contact region of the first die and has a first external contact portion. A second lead is coupled to a second contact region of the second die and has a second external contact portion. A package mass extends around the lead frame, the first lead and the second lead, embedded in the first die and the second die, and flush with the base member, a lateral member of the lead frame, and an external contact portion of the leads.

Description

Technical Field

[0001] The present disclosure relates to an electronic device with high heat dissipation including a plurality of power transistors and a process for manufacturing the same. Background Art

[0002] It is known that high voltage and / or high current power semiconductor devices are widely used in applications such as power conversion applications, where these devices are subject to high voltage or very high voltage biases (with values ​​even up to 1000-2000 V) and possibly rapidly switched currents.

[0003] In these devices, specific measures are required for forming the package in order to provide high electrical insulation, suitable separation distances between leads associated with the gate, source, and drain terminals, and high heat dissipation to the outside.

[0004] A vertical power semiconductor device (metal oxide semiconductor field effect transistor (MOSFET) and insulated gate bipolar transistor (IGBT) in the case of a silicon substrate) is formed in a die of a semiconductor material (typically silicon, silicon carbide, silicon and gallium nitride (GaN) or only gallium nitride), the die having a first main surface and a second main surface, the second main surface being opposite to the first main surface, a drain pad extending from the first main surface, and a source pad or a gate pad extending from the second main surface.

[0005] The die is attached to a conductive support (called a lead frame) having a drain, source and gate for external connections of the device. To this end, a drain pad is generally attached to a bearing portion of the lead frame, which also has a heat dissipation function; the gate lead and the source lead are coupled to the gate pad and the source pad, respectively, by bonding wires or terminals or clamps. The assembled die / lead frame is encapsulated in a resin mass or other encapsulating insulating material. The encapsulating insulating material can be molded or laminated.

[0006] Conventional packages for power semiconductor devices are generally arranged vertically and include pins protruding downward from a single bottom side of a package structure (generally parallelepiped shaped) to electrically couple to a printed circuit board (PCB). A suitable heat sink (usually a metal sheet) is coupled to the package structure, which is also arranged vertically relative to the printed circuit board.

[0007] To achieve more compact thickness dimensions, horizontal packages such as surface mounted devices (SDM) were developed, which also allow for double-sided cooling (DSC).

[0008] For example, Italian Patent 102018000004782 (corresponding to U.S. Patent No. 10,910,302) describes a double island package for a MOSFET transistor having a silicon carbide SiC or silicon Si substrate in a source-source configuration (e.g., with coupling of source regions) or for a gallium nitride GaN-based MOSFET transistor in a drain-drain configuration (e.g., with coupling of drain regions).

[0009] The object of the present disclosure is to provide a solution that allows obtaining a single dual-island package for MOSFET transistors with a silicon carbide SiC or silicon Si substrate in a drain-drain configuration or for gallium nitride GaN-based MOSFET transistors in a source-source configuration. Summary of the invention

[0010] According to the present disclosure, a packaged electronic device is provided. Specifically, the present disclosure relates to a high voltage and / or high power semiconductor device, including a vertical MOSFET transistor (e.g., with a silicon carbide (SiC) or silicon (Si) substrate in a drain-drain (i.e., with drain region coupling) configuration or a planar MOSFET transistor (e.g., based on gallium nitride (GaN)) in a source-source (i.e., with source region coupling) configuration, which is configured for surface mounting and has double-sided cooling.

[0011] A packaged electronic device comprises: a C-shaped lead frame, comprising a base member and a pair of lateral members, the base member having a first face and a second face and the lateral member extending laterally to the base member; a first die and a second die, the first die and the second die each having a first main surface and a second main surface, a first contact area at the first main surface of the first die and the first main surface of the second die, a second contact area at the second main surface of the first die and the second main surface of the second die, the first main surface at the first die and the second die attached to the first face of the base member; a first lead coupled to the second contact area of ​​the first die and having a first external contact portion; a second lead coupled to the second contact area of ​​the second die and having a second external contact portion; and a packaging mass, surrounding the lead frame, the first lead and the second lead and embedding the first die and the second die, wherein the packaging mass extends flush with the base member, with the lateral member of the lead frame, and with the first external contact portion of the first lead and the second external contact portion of the second lead, respectively. A method for manufacturing the same is also provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] For a better understanding of the present disclosure, some embodiments of the present disclosure will now be described, by way of non-limiting examples only, with reference to the accompanying drawings, in which:

[0013] Figure 1Ais a simplified circuit diagram of a MOSFET transistor connected using a common source topology;

[0014] Figure 1B is a simplified circuit diagram of a MOSFET transistor connected using a common drain topology;

[0015] Figure 2A is a simplified circuit diagram of n MOSFET transistors connected in parallel through external connections in a common drain topology;

[0016] Figure 2B It is a simplified circuit diagram of n MOSFET transistors connected in parallel via an internal connection (island in the package) in a common drain topology;

[0017] Figure 3A is a simplified circuit diagram of n MOSFET transistors connected in parallel via external connections in a common source topology;

[0018] Figure 3B It is a simplified circuit diagram of n MOSFET transistors connected in parallel via internal connections (islands in the package) in a common-source topology;

[0019] Figure 4 is a simplified cross-sectional view of an example of a MOS transistor that may be used in a common drain topology;

[0020] Figure 5 is a top view above the package of two MOSFET transistors coupled to each other using a common drain topology.

[0021] Figure 6 yes Figure 5 Bottom view of the package;

[0022] Figure 7 yes Figure 5 and Figure 6 A cross-sectional view of a package;

[0023] Figure 8 yes Figure 7 A cross-sectional view of the package after being connected to a support and a heat sink;

[0024] Fig. 9 is a simplified cross-sectional diagram of an example of a MOS transistor that may be used in a common-source topology.

[0025] Fig.10 is a top view above the package of two MOSFET transistors coupled to each other using a common source topology;

[0026] Fig.11 yes Fig.10 Bottom view of the package;

[0027] Fig.12 yes Fig.10 and Fig.11 a cross-sectional view of a package; and

[0028] Fig.13 yes Fig.12 Cross-sectional view of the package after being attached to the support and heat sink.

[0029] Tool block implementation

[0030] The following description refers to the arrangement shown; therefore, expressions such as "above", "below", "upper", "lower", "right", "left" refer to the accompanying drawings and are not to be interpreted in a limiting manner.

[0031] It is known that semiconductor switches need to meet two requirements:

[0032] Capable of blocking voltage in both directions (voltage blocking bidirectionality); and

[0033] Allows current to flow in both directions (current bidirectionality).

[0034] The MOSFET transistor meets the second requirement as it is able to pass current from the drain terminal to the source terminal and vice versa, but only partially meets the first requirement as it blocks the forward voltage (BV) from the drain terminal to the source terminal. DSS ), but the blocking ability in the opposite direction is very small.

[0035] In actual operation, there are usually two topologies used for MOSFET transistors: common source topology ( Figure 1A The "back-to-back") and common-drain topologies ( Figure 1B ).

[0036] The common-source topology is generally preferred due to the advantage of simpler gate drive, but the common-drain topology is preferred in some applications, such as in the case of solar micro-inverters using GaN-based transistors or silicon-based devices, where noise and electromagnetic emissions EMI need to be reduced.

[0037] For example, such a topology can be used for a full-bridge converter or a plate-bridge converter, where the MOSFET transistors have low conduction losses. In the full-bridge configuration, there are two series-connected drain-source resistors R with very low voltage drop in the on-state. DS(on) .

[0038] Specifically, for the common source topology, the main advantages are:

[0039] There is no lower limit on conduction losses, since it is sufficient to connect a suitable number of transistors in parallel;

[0040] The number of components is minimal; and

[0041] High frequency switching capability during charge / discharge phases.

[0042] For common drain topology, some limitations may be due to:

[0043] The number of dies connected in parallel to obtain the desired conduction power loss value;

[0044] Technology Type Effect on On-State Drain-Source Resistance R DS(on) The impact of the value of

[0045] Fewer favorable form factors; and

[0046] The charge Qrr linked to the intrinsic body-drain diode enables current to flow also in the anti-parallel connected diode at very high current levels and with the MOSFET transistor in reverse conduction.

[0047] When n MOSFETs are connected in parallel, as Figure 2A As shown in Figure 2, for a MOSFET transistor that can be connected in a common drain topology, the drain-source R DS(on) Linearly decreasing to ideally reduce conduction losses to zero, but a single package makes the arrangement and parallelization process more complicated.

[0048] When n MOSFETs are connected in parallel by dual islands in each package, as shown in Figure 2B As shown in the previous case, the drain-source resistance R DS(on) This decreases linearly to ideally reduce conduction losses to zero, but is very simple for the user to parallelize.

[0049] In actual operation, with this coupling, a single electronic device 10 comprises two MOSFET transistors 11A, 11B having a single common drain terminal D, two source terminals S1 , S2 and two gate terminals G1 , G2 .

[0050] exist Figure 3A and Figure 3B Similar assumptions apply in the case of the co-source topology shown in .

[0051] In actual operation, Figure 3B It shows the parallel coupling by the dual islands in each packaged device 20. Here, a single sub-device 20 comprises two MOSFETs 21A, 21B with a single common source terminal S, two drain terminals D1, D2 and two gate terminals G1, G2.

[0052] In order to better understand the scope of this disclosure, Figure 4 An example of a MOSFET transistor 24 having vertical conduction, such as an N-channel MOSFET transistor that may be used in a common-drain topology, herein a charge-balanced transistor (also referred to as a "superjunction" transistor), is shown.

[0053] In detail, Figure 4 The transistor 24 includes a substrate 25 having an upper or first surface 25A and a lower or second surface 25B.

[0054] The substrate 25 forms a drain region 26 and is electrically contacted by a drain metal layer 27 , which extends onto a bottom surface 25B of the substrate 25 and is coupled to a drain terminal D.

[0055] Source region 28 is formed in body region 23 and faces upper surface 25A of substrate 25. Source region 28 is contacted by a source metal layer 29, which extends onto upper surface 25A and is coupled to a source terminal S.

[0056] Insulated gate region 30 extends above upper surface 25A of substrate 25 and has a corresponding gate conducting portion 31 coupled to gate terminal G.

[0057] Other implementations are possible, such as in vertical silicon carbide technology, all of which have a drain metal layer 27 arranged on a surface (e.g., a lower surface 25B of a substrate 25), a source metal layer 29 arranged on another surface (e.g., an upper surface 25A of the substrate 25), and a gate pad (forming a gate terminal G).

[0058] Figures 5 to 7 Shows Figure 2B An implementation method of an electronic device 10, wherein for example Figure 4 The MOSFET transistor 24 forms the MOSFET transistor 11A and the MOSFET transistor 11B. In order to simplify the description in a non-limiting manner, the following uses Figure 4 The reference numeral of the MOSFET transistor 24 indicates a portion of the MOSFET transistor 11A and the MOSFET transistor 11B.

[0059] Specifically, Figures 5 to 7 A surface mount type package device 50 is shown, which includes two MOSFET transistors 11A, 11B, in Figure 7 Only the substrate 25, the drain metal layer 27 and the source metal layer 29 are shown.

[0060] The structure formed by each substrate 25 , the corresponding drain metal layer 27 , the corresponding source metal layer 29 , and the corresponding gate metallization (not shown) is a die 60 .

[0061] As will be described in detail below, packaging device 50 is embedded in packaging mass 51, which is made of resin or other insulating material and completely surrounds MOSFET transistors 11A, 11B except for external terminals of packaging device 50, and the external terminals extend flush with packaging mass 51.

[0062] Generally, the packaging device 50 has a parallelepiped shape, which is formed by two main surfaces 50A, 50B (first main surface 50A and second main surface 50B) opposite to each other and having a rectangular shape, and four lateral surfaces 50C to 50F (first lateral surface 50C, second lateral surface 50D, third lateral surface 50E and fourth lateral surface 50F).

[0063] The two lateral surfaces (the first lateral surface 50C and the third lateral surface 50E) correspond to the short sides of the rectangular shape of the main surfaces 50A and 50B and the two lateral surfaces (the second lateral surface 50D and the fourth lateral surface 50F) correspond to the long sides of the rectangular shape of the main surfaces 50A and 50B.

[0064] The packaging device 50 includes a metal support structure (hereinafter also referred to as a lead frame) 52, which is Figure 2B The drain terminal D; two metal source leads 53, which are Figure 2B The source terminal S1 and the source terminal S2; and two gate leads 54 of metal, which are Figure 2B The gate terminal G1 and the gate terminal G2.

[0065] The lead frame 52 has a C-shaped body with a base side 52A ( Figure 5 ) and two lateral sides or extensions 52B. The two extensions 52B are opposite to each other. The lead frame 52 has a groove between the two extensions 52B.

[0066] The base side 52A of the lead frame 52 has an inner face 58 and an outer face 59, wherein the inner face 58 faces the inner side of the packaging device 50, and the outer face 59 is flush with the first main surface 50A of the packaging device 50. The two extensions 52B each have an inner surface facing each other. The inner surfaces of the two extensions 52B are transverse to the inner face 58 of the lead frame 52.

[0067] like Figure 7 As shown in FIG. 5 , the base side 52A of the lead frame 52 is in direct contact with the drain metal layer 27 of the MOSFET transistors 11A and 11B on its inner face 58, so that they are electrically coupled. It thus forms a drain region ( Figure 4 26) dual, unique and shared island.

[0068] The lateral side 52B of the lead frame 52 extends from the base side 52A upwards to the second main surface 50B, flush with the first lateral surface 50C and the third lateral surface 50E, at a distance from the MOSFET transistors or the first and second dies 11A, 11B.

[0069] In the side view, the source leads 53 have an inverted L-shape and each include a source base plate 53A and a corresponding source metal layer 29 ( Figure 4 ) are electrically contacted, and the corresponding source pin 53B is monolithically integrated with the corresponding source base plate 53A. Each source pin 53B extends between the corresponding source base plate 53A and the second main surface 50B and is flush with the latter.

[0070] Furthermore, each source lead 53B has a lateral end portion ( Figure 6 ).

[0071] The gate leads 54 have a shape similar to that of the source leads 53, an inverted L-shape in the side view, and each includes a gate plate (not visible) and a gate pin 54B.

[0072] The gate plate (not visible) of the gate lead 54 is in electrical contact with a gate pad (not shown) which forms a Figure 2B The gate terminal G of the MOSFET transistor 24 is arranged on the same side as the source metal layer 29 .

[0073] like Figure 6 As shown in , a gate pin 54B having, for example, the same (or similar) shape as the source pin 53B protrudes flush with the second main surface 50B of the packaged device 50 , beside the source pin 53B, but spaced apart from the source pin 53B.

[0074] Furthermore, each gate pin 54B has a lateral end portion ( Figure 5 ).

[0075] In this manner, packaged device 50 implements a surface mount drain-drain configuration in a simple and efficient manner.

[0076] Package device 50 has a wide dissipation surface because dissipation can occur on both main surface 50A and main surface 50B, and thus can be used in high-power applications.

[0077] By arranging the C-shaped heat sink 55 in contact with the first main surface 50A of the package device 50 and with at least the first lateral surface 50C and the third lateral surface 50E, the dissipation capacity of the package device 50 can be increased by Figure 8 Increase in the manner shown in .

[0078] Furthermore, the packaged device 50 may also dissipate heat at its second main surface 50B.

[0079] Specifically, if Figure 8 As shown, high heat flow is achieved by forming heat dissipation holes 56 (eg, thermal vias) in a support 57 having the same packaging device 50 (eg, a printed circuit board) attached thereto.

[0080] Fig. 9 An example of a MOSFET transistor 70 that may be used in a common-source topology is shown, where the planar power MOSFET transistor is made using Gallium Nitride (GaN) based technology.

[0081] In detail, the MOSFET transistor 70 includes a semiconductor body 71 having an upper surface 71A and a lower surface 71B.

[0082] The semiconductor body 71 here includes a substrate 72 (e.g., silicon) defining a lower surface 71B; a buffer layer 73 of gallium nitride (GaN), superimposed on the substrate 72; a channel layer 74, such as gallium nitride (GaN), superimposed on the buffer layer 73; and a barrier layer 75, such as aluminum gallium nitride (AlGaN), superimposed on the channel layer 74 and defining an upper surface 71A of the semiconductor body 71.

[0083] A gate region 76 having a P-type conductive semiconductor material (e.g., gallium nitride) (p-GaN) extends over the barrier layer 75; a gate contact region 77 of metal (e.g., TiN / AlCu / TiN) extends over the gate region 76 and is in direct electrical contact with the gate region 76; a source contact region 80 of metal (e.g., Ti / AlCu / TiN) extends over the barrier layer 75 on a first side of the gate region 76 and is in direct electrical contact with the barrier layer 75; a drain contact region 81 of metal (e.g., TiN / AlCu / TiN) extends over the barrier layer 75 on a second side of the gate region 76 opposite to the first side and is in direct electrical contact with the barrier layer 75; and an insulating layer 83 of, e.g., silicon oxide, extends over the upper surface 71A of the semiconductor body 71 between the gate region 76, the gate contact region 77, the source contact region 80, and the drain contact region 81.

[0084] Figures 10 to 12 Shows Figure 3BThe implementation method of the packaging device 20, wherein the MOSFET transistor 21A and the MOSFET transistor 21B are composed of, for example, Fig. 9 In order to simplify the description in a non-limiting manner, the following uses the Fig. 9 The reference numeral of the MOSFET transistor 70 indicates a portion of the MOSFET transistor 21A, the MOSFET transistor 21B.

[0085] Specifically, Fig.12 A packaged device 90 of surface mount type is shown, comprising two MOSFET transistors 21A, 21B, of which only their semiconductor bodies 71 , source contact regions 80 , drain contact regions 81 and rear metallization 85 in contact with the lower surface 71B of the semiconductor bodies 71 are represented.

[0086] The structure formed by each semiconductor body 71 , the respective source contact region 80 , the respective drain contact region 81 and the respective post metallization 85 forms a die 86 .

[0087] As will be described in detail below, packaging device 90 is embedded in packaging mass 91 of resin or other insulating material that completely surrounds MOSFET transistors 21A, 21B except for external terminals of packaging device 90 that extend flush with packaging mass 91 .

[0088] In summary, the packaging device 90 has a parallelepiped shape formed by two main surfaces 90A and 90B opposite to each other, has a rectangular shape (a first main surface 90A and a second main surface 90B) and four lateral surfaces 90C to 90F (a first lateral surface 90C, a second lateral surface 90D, a third lateral surface 90E and a fourth lateral surface 90F).

[0089] Two lateral surfaces (first lateral surface 90C and third lateral surface 90E) correspond to the short sides of the rectangular shape of main surface 90A and main surface 90B, and two lateral surfaces (second lateral surface 90D and fourth lateral surface 90F) correspond to the long sides of the rectangular shape of main surface 90A and main surface 90B.

[0090] The package device 90 includes a metallic support structure (also referred to herein as a lead frame) 92, which is Figure 3B The source terminal S; two metal drain leads 93, which are Figure 3B The drain terminal D1 and the drain terminal D2 of the transistor; and two gate leads of metal, which are Figure 3B Gate terminal G1 and gate terminal G2.

[0091] Lead frame 92 has a C-shape with a base side 92A and two lateral sides 92B.

[0092] The base side 92A of the lead frame 92 has an inner face 88 and an outer face 89 , the inner face 88 facing towards the inside of the packaging device 90 and the outer face 89 being flush with the first main surface 90A of the packaging device 90 .

[0093] like Fig.12 As can be seen in FIG. 8 , base side 92A of lead frame 92 is in direct contact with rear metallization 85 of MOSFET transistor 21A and MOSFET transistor 21B on its inner face 88 , electrically coupling them.

[0094] The lateral side 92B of the lead frame 92 extends from the base side 92A flush with the first and third lateral surfaces 90C, 90E upwards to the second main surface 90B at a distance from the MOSFET transistors 21A, 21B.

[0095] The lateral sides 92B of the lead frame 92 extend upwards to the second main surface 90B of the packaging device 90 and have corresponding recesses 98 facing the inner side of the packaging device 90 .

[0096] In the side view, the drain leads 93 have an inverted L-shape and each include a drain base plate 93A ( Fig. 9 ), and a corresponding drain pin 93B monolithically integrated with the corresponding drain base plate 93A. Each drain pin 93B extends between the corresponding drain base plate 93A and the second main surface 90B flush with it.

[0097] In addition, each drain lead 93B has a lateral end portion ( Fig.11 ).

[0098] The gate leads 94 have a similar shape to the drain leads 93 and each include a gate plate (not visible) and a gate pin 94B ( Fig.11 ).

[0099] The gate plate (not visible) of the gate lead 94 is connected to the Fig. 9 The gate contact region 77 is electrically contacted and arranged on the same side of the MOSFET transistor 90, located Fig. 9 The side of the drain contact region 81.

[0100] like Fig.11 As can be seen in FIG. 1 , a gate pin 94B having, for example, the same shape (or a similar shape) as the source pin 93B protrudes flush with the second main surface 90B of the packaged device 90 , beside the drain pin 93B, but spaced apart from the drain pin 93B.

[0101] Furthermore, each gate pin 94B has a lateral end portion ( Fig.10 ).

[0102] The connection structure of the die 86 also includes a pair of source plates 99 .

[0103] Each source plate 99 is in electrical contact with the corresponding source contact region 80, protrudes laterally relative to the corresponding tube core 86 and extends with its protruding end into the corresponding groove 98 of the lateral side 92B of the lead structure 92. The source plate 99 is blocked (e.g., fitted or welded / soldered) in the corresponding groove 98.

[0104] In this manner, lead frame 92 and source plate 99 create direct electrical connections between MOSFET transistors 21A, 21B and substrate 72, and between substrates 72. Base side 92A of lead frame 92 is thus Figure 3B The source terminal S of the package device 20 and thus represents a source contact region 80 ( Fig. 9 )'s dual, unique and shared island.

[0105] In this manner, packaged device 90 forms a surface mount source-source configuration in a simple and efficient manner.

[0106] Figures 10 to 12 The package device 90 also has a high dissipation surface, and the dissipation capacity can be Fig.13 In the manner shown in , the C-shaped heat sink 95 is arranged to be in contact with the first main surface 90A of the package device 90 and in contact with at least the first lateral surface 90C and the third lateral surface 90E.

[0107] also, Figures 10 to 12 The packaged device can also dissipate heat at its second main surface 90B.

[0108] Specifically, if Fig.13 As shown in , high heat flow is achieved by forming heat dissipation holes 96 (eg, metal vias) in a support 97 having the same packaged device 90 (eg, a printed circuit board) attached thereto.

[0109] Finally, it is evident that modifications and variations may be made to the packaged electronic device described and illustrated herein, without thereby departing from the scope of the present disclosure.

[0110] A packaged electronic device (50; 70) comprises: a C-shaped lead frame (52; 92) comprising a base member (52A; 92A) and a pair of lateral members (52B; 92B), the base member (52A; 92A) having a first face and a second face (58, 59; 88, 89), and the lateral members (52B; 92B) extending laterally to the base member; a first tube die (11A, 60; 21A, 86) and a second tube die (11B, 60; 21A, 86) B, 86), the first die and the second die each having a first main surface and a second main surface, a first contact area (27; 85) at the first main surface of the first die and the second die (11A, 11B, 60; 21A, 21B, 86), a second contact area (29; 81) at the second main surface of the first die and the second die, the first main surfaces of the first die and the second die being attached to a first side (58; 88) of a base component (52A; 92A); a first A lead (53; 93) coupled to a second contact region (29; 81) of a first die (11A, 60; 21A, 86) and having a first external contact portion (53B; 93B); a second lead (53; 93) coupled to a second contact region (29; 81) of a second die and having a second external contact portion (53B; 93B); and a package quality block (52; 92) surrounding the lead frame (52; 92), the first lead and the second lead ( 53; 93) and embedding the first tube core and the second tube core (11A, 11B, 60; 21A, 21B, 86), wherein the packaging mass block (52; 92) extends flush with the base part (52A; 92A) and extends flush with the lateral part (52B; 92B) of the lead frame (52; 92), with the first external contact part (53B) of the corresponding first lead (53) and the second external contact part (93B) of the second lead (93).

[0111] The second lead (53; 93) is spaced apart from the first lead (53; 93).

[0112] The first die (11A, 60; 21A, 86) is separated from the second die.

[0113] The package mass (52; 92) forms a first main surface and a second main surface (50A, 50B; 90A, 90B) opposite to each other and a first lateral surface, a second lateral surface, a third lateral surface and a fourth lateral surface (50C-50F; 90C-90F) opposite to each other, the first lateral surface and the third lateral surface (50C, 50E; 90C; 90E) are opposite to each other, and the second lateral surface and the fourth lateral surface (50D, 50F; 90D, 90F) are opposite to each other, and the lead frame (52 The second surface (59; 89) of the package assembly (52; 92) is flush with the first main surface (50A; 90A) of the package mass block (52; 92), the lateral part (52B; 92B) is flush with the first lateral surface and the third lateral surface (50C, 50E; 90C, 90E) of the package mass block, respectively, and the first external contact portion (53B) of the corresponding first lead (53) and the second external contact portion (93B) of the second lead (93) are flush with the second main surface (50B; 90B) of the package mass block.

[0114] The first external contact portion (53B) of the corresponding first lead (53) and the second external contact portion (93B) of the second lead (93) are also flush with the second lateral surface and the fourth lateral surface (50D, 50F; 90D, 90F) of the packaging mass (52; 92), respectively.

[0115] The first die and the second die (11A, 11B, 60; 21A, 21B, 86) each include a respective third contact region (G; 77) arranged on a second main surface of the respective first die and the second die, the device further includes a third lead and a fourth lead (54; 84), the third lead (54) being coupled to the third contact region (G; 77) of the first die (11A, 60) and having a third external contact portion (54B; 84B) flush with the packaging mass (52; 92), and the fourth lead (54; 84) being coupled to the third contact region (G; 77) of the second die (11B, 60; 21B, 86) and having a fourth external contact portion (54B; 84B) flush with the packaging mass.

[0116] The first tube core and the second tube core (11A, 11B, 60; 21A, 21N, 86) are vertical MOSFET devices, the first contact area (27) of the first tube core and the second tube core is a drain contact area, the second contact area (29) of the first tube core and the second tube core is a source contact area, and the third contact area (G) of the first tube core and the second tube core is a gate contact area.

[0117] The first die and the second die (11A, 11B, 60) are silicon-based MOSFET devices or silicon carbide-based MOSFET devices.

[0118] The first die and the second die (21A, 21B, 84) are planar MOSFET devices having respective source contact regions (80) extending at the second side of the first die and the second die, the first contact regions (72) of the first die and the second die being substrate contact regions, the second contact regions (81) of the first die and the second die being drain contact regions, the third contact regions (77) of the first die and the third die being gate contact regions, the device further comprising a source contact plate (99) coupled to the source contact region (80) and in electrical contact with a lateral portion (52B; 2B) of a lead frame (52; 92).

[0119] The lateral part (52B; 92B) of the lead frame (52; 92) has a groove (98) facing the first die and the second die and coupled to the corresponding edges of the source contact plate (99).

[0120] The first die and the second die are gallium nitride based MOSFET devices.

[0121] The packaging mass (52; 92) includes a first main surface (50A; 90A) flush with the second surface (59; 89) of the lead frame (52; 92) and a second main surface (50B; 90B) flush with the first external contact portion and the second external contact portion (53B; 93B), and the device further includes a C-shaped heat sink (55; 95), and the heat sink (55; 95) contacts the second surface (59; 89) of the lead frame (52; 92).

[0122] The device further comprises a support (57; 97) provided with heat dissipation holes (56; 96), the support (57; 97) being in contact with the packaging mass.

[0123] The various embodiments described above can be combined to provide further embodiments. Aspects of the embodiments can be modified, if necessary to employ concepts of the various patents, applications and publications to provide further embodiments.

[0124] These and other changes may be made to the embodiments within the scope of the above detailed description. In general, in the following claims, the terms used should not be interpreted to limit the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments, and the full range of equivalents to which these claims are entitled. Therefore, the claims are not limited by the present disclosure.

Claims

1. A packaged electronic device, comprising: A C-shaped lead frame including a base member and a pair of cross members, the base member having a first face and a second face and the cross members extending laterally to the base member; a first die and a second die, each having a first main surface and a second main surface, a first contact area at the first main surface of the first die and the first main surface of the second die, and a second contact area at the second main surface of the first die and the second main surface of the second die, the first main surface of the first die and the first main surface of the second die being attached to the first side of the base member; a first lead coupled to the second contact region of the first die and having a first external contact portion; a second lead coupled to the second contact region of the second die and having a second external contact portion; as well as a packaging mass, surrounding the lead frame, the first lead and the second lead and embedding the first die and the second die, The packaging mass extends flush with the base part, with the lateral part of the lead frame, and with the first external contact portion of the first lead and the second external contact portion of the second lead, respectively. 2 . The device of claim 1 , wherein the second lead is spaced apart from the first lead. 3 . The apparatus of claim 1 , wherein the first die is spaced apart from the second die.

4. The apparatus according to claim 1, wherein: The packaging mass forms a first main surface and a second main surface opposite to each other, and a first lateral surface, a second lateral surface, a third lateral surface and a fourth lateral surface, the first lateral surface and the third lateral surface opposite to each other, and the second lateral surface and the fourth lateral surface opposite to each other, The second surface of the lead frame is flush with the first main surface of the packaging mass, The lateral member is flush with the first lateral surface and the third lateral surface of the packaging mass, respectively, and The first external contact portion of the first lead and the second external contact portion of the second lead are respectively flush with the second main surface of the packaging mass. 5 . The device of claim 4 , wherein the first external contact portion of the first lead and the second external contact portion of the second lead are flush with the second lateral surface and the fourth lateral surface of the packaging mass, respectively.

6. The device of claim 4 , wherein the first die and the second die each include a corresponding third contact area respectively arranged on the second main surface of the first die and the second main surface of the second die, the device further including a third lead and a fourth lead, the third lead coupled to the third contact area of ​​the first die and having a third external contact portion flush with the packaging mass block, and the fourth lead coupled to the third contact area of ​​the second die and having a fourth external contact portion flush with the packaging mass block.

7. The device of claim 6, wherein the first die and the second die are vertical MOSFET devices, the first contact regions of the first die and the second die are drain contact regions, the second contact regions of the first die and the second die are source contact regions, and the third contact regions of the first die and the second die are gate contact regions. 8 . The device of claim 7 , wherein the first die and the second die are silicon-based MOSFET devices or silicon carbide-based MOSFET devices.

9. The device of claim 6, wherein the first die and the second die are planar MOSFET devices having corresponding source contact regions, the source contact regions extending at the second surface of the first die and the second surface of the second die, the first contact region of the first die and the first contact region of the second die being substrate contact regions, the second contact region of the first die and the second contact region of the second die being drain contact regions, the third contact region of the first die and the third contact region of the second die being gate contact regions, the device further comprising a source contact plate coupled to the source contact region and electrically contacting the lateral portion of the lead frame. 10 . The device of claim 9 , wherein the lateral member of the lead frame has grooves facing the first die and the second die and coupled to respective edges of the source contact plate.

11. The device of claim 9, wherein the first die and the second die are gallium nitride based MOSFET devices.

12. The device of claim 1 , wherein the packaging mass comprises a first main surface and a second main surface, the first main surface being flush with the second side of the lead frame, the second main surface being flush with the first external contact portion and the second external contact portion, the device further comprising a C-shaped heat sink and the heat sink is in contact with the second side of the lead frame. 13 . The apparatus of claim 12 , further comprising a support member having heat dissipation holes, the support member being in contact with the packaging mass.

14. A device comprising: A C-shaped lead frame, comprising a first extension portion opposite to a second extension portion, a first surface of the lead frame extending between the first extension portion and the second extension portion, the first extension portion and the second extension portion each having a first surface transverse to the second surface of the lead frame, the second surface opposite to the first surface of the lead frame; a first die coupled to the first surface of the lead frame; a first lead coupled to the first die, the first lead comprising a first external contact region; a second die coupled to the first surface of the lead frame, the second die being spaced apart from the first die; a second lead coupled to the second die, the second lead comprising a second external contact region; as well as A packaging mass is provided, and the first external contact area and the second external contact area are exposed from the packaging mass on the lead frame.

15. The device of claim 14, wherein the lead frame is a drain terminal or a source terminal.

16. The apparatus of claim 14, wherein the lead frame comprises a plurality of grooves, the first extension comprises a second surface opposite the first surface, the second extension comprises a second surface opposite the first surface, and wherein the plurality of grooves are in the second surfaces of the first extension and the second extension.

17. The apparatus of claim 16, wherein the first die has a first source plate and the second die has a second source plate, the first source plate and the second source plate being in respective ones of the plurality of recesses of the lead frame.

18. A device comprising: C-type lead frame, including: A first groove having a first surface, wherein the lead frame has a second surface opposite to the first surface; a first extension, transverse to the second surface; and a second extension portion, opposite to the first extension portion and transverse to the second surface, the groove being between the first extension portion and the second extension portion; a plurality of dies in the first recess and coupled to the first surface of the first recess, each of the plurality of dies being spaced apart from one another; a plurality of leads in the first recess and having external contact areas, each die having a respective lead coupled to the respective die; and A packaging mass is provided, on the lead frame, and the external contact area is exposed from the packaging mass.

19. The apparatus of claim 18, wherein each die is a vertical MOSFET.

20. The apparatus of claim 18, wherein each die has an L-shaped gate terminal.

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