Semiconductor package including stiffener

Abstract

A semiconductor package includes a first redistribution structure, a second redistribution structure disposed on the first redistribution structure, a semiconductor chip disposed on an upper surface of the second redistribution structure, a bridge chip disposed on a lower surface of the second redistribution structure, a molding layer disposed between the first redistribution structure and the second redistribution structure, and a reinforcement disposed on an upper surface of the second redistribution structure, where the molding layer surrounds the bridge chip. The stiffener includes an opening. The semiconductor chip is disposed in the opening of the stiffener.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Singapore Patent Application No. 10202303246V filed with the Intellectual Property Office of Singapore (IPOS) on November 16, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present inventive concept relates to a semiconductor package. More particularly, the present inventive concept relates to a semiconductor package including a reinforcement member. Background Art

[0004] Semiconductor packages are implemented by semiconductor chips for electronic products. In semiconductor packages, the semiconductor chips are mounted on a printed circuit board and electrically connected to the printed circuit board using bonding wires or bonding bumps. As advances in semiconductor packages have led to higher performance, the size of semiconductor packages has increased. Therefore, semiconductor packages including reinforcements are used to control warpage that occurs due to differences in thermal expansion coefficients of one or more components in the semiconductor package. Summary of the invention

[0005] A semiconductor package includes: a first redistribution structure; a second redistribution structure disposed on the first redistribution structure; a semiconductor chip disposed on an upper surface of the second redistribution structure; a bridge chip disposed on a lower surface of the second redistribution structure; a molding layer disposed between the first redistribution structure and the second redistribution structure, wherein the molding layer surrounds the bridge chip; and a reinforcement member disposed on an upper surface of the second redistribution structure. In one aspect, the reinforcement member includes an opening. In one aspect, the semiconductor chip is disposed in the opening of the reinforcement member.

[0006] A semiconductor package includes: a first redistribution structure; a second redistribution structure disposed on the first redistribution structure; a semiconductor chip disposed on an upper surface of the second redistribution structure; a bridge chip disposed on a lower surface of the second redistribution structure; a passive device disposed on the lower surface of the second redistribution structure and spaced apart from the bridge chip in a horizontal direction. In one aspect, the horizontal direction is parallel to the upper surface of the second redistribution structure. The semiconductor package also includes: a molding layer disposed between the first redistribution structure and the second redistribution structure, wherein the molding layer surrounds the bridge chip and the passive device; a conductive column spaced apart from the bridge chip and the passive device in a horizontal direction within the molding layer; a heat sink disposed on an upper surface of the semiconductor chip; and a reinforcement member disposed on an upper surface of the second redistribution structure, wherein the reinforcement member includes an opening. In one aspect, the semiconductor chip is disposed in the opening of the reinforcement member.

[0007] A semiconductor package includes: a first redistribution structure including a passivation layer, an under-bump metallization (UBM) layer disposed on a portion of a lower surface of the passivation layer and covering the portion of the lower surface of the passivation layer, and a conductive layer in contact with the UBM layer and exposed at an upper surface of the passivation layer. The semiconductor package also includes: a second redistribution structure disposed on the first redistribution structure, wherein the second redistribution structure includes one or more redistribution insulating layers, one or more conductive line patterns disposed in the one or more redistribution insulating layers and extending in a horizontal direction, and one or more conductive through-pieces disposed in the one or more redistribution insulating layers and extending in a vertical direction perpendicular to the horizontal direction, wherein the horizontal direction is parallel to an upper surface of the second redistribution structure. The semiconductor package further includes: one or more semiconductor chips disposed on the upper surface of the second redistribution structure; a bridge chip disposed on the lower surface of the second redistribution structure, wherein the bridge chip provides an electrical connection path between the one or more semiconductor chips; a passive device disposed on the lower surface of the second redistribution structure and spaced apart from the bridge chip in a horizontal direction; a molding layer disposed between the first redistribution structure and the second redistribution structure, wherein the molding layer surrounds the lower surface and side surface of the bridge chip and the lower surface and side surface of the passive device; a conductive column spaced apart from the bridge chip and the passive device in a horizontal direction within the molding layer; and a stiffener disposed on the upper surface of the second redistribution structure, wherein the stiffener includes an opening. The one or more semiconductor chips are disposed in the opening of the stiffener. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1A is an example of a horizontal cross-sectional view of a shape of a reinforcement member according to an embodiment of the inventive concept.

[0009] Figure 1B and Figure 1C is along Figure 1A An example of a vertical cross-sectional view taken along line AA' in FIG.

[0010] Figure 2A is an example of a horizontal cross-sectional view of a shape of a reinforcement member according to an embodiment of the inventive concept.

[0011] Figure 2B is along Figure 2A An example of a vertical cross-sectional view taken along line BB' in FIG.

[0012] Figure 3A is an example of a plan view of a semiconductor package according to an embodiment of the inventive concept.

[0013] Figure 3B is along Figure 3A An example of a cross-sectional view taken along line CC' in FIG.

[0014] Figure 4 is an example of a cross-sectional view of a semiconductor package according to an embodiment of the inventive concept.

[0015] Figure 5 is an example of a cross-sectional view of a semiconductor package according to an embodiment of the inventive concept.

[0016] Figure 6 is an example of a cross-sectional view of a semiconductor package according to an embodiment of the inventive concept.

[0017] Figure 7 is an example of a cross-sectional view of a semiconductor package according to an embodiment of the inventive concept.

[0018] Figure 8 is an example of a plan view of a semiconductor package according to an embodiment of the inventive concept.

[0019] Fig. 9A , Fig. 9B , Fig. 9C , Fig.9D , Fig.9E , Fig.9F , Figure 9G and Figure 9H is an example of a cross-sectional view of a method for manufacturing a semiconductor package according to an embodiment of the inventive concept. DETAILED DESCRIPTION

[0020] Hereinafter, embodiments of the inventive concept are described in detail with reference to the accompanying drawings. In some cases, the same reference numerals are used for the same components in the drawings. In some cases, redundant descriptions thereof may be omitted.

[0021] In some cases, the embodiments of the present invention can be modified in various ways. In some cases, the present invention includes various embodiments. In some cases, specific embodiments are shown in the drawings, and specific embodiments are described in detail in the specific embodiments. However, this is not intended to limit the scope to specific embodiments, and should be understood to include all modifications, equivalents and substitutes included in the disclosed spirit and technical scope. When describing an embodiment, when it is determined that a detailed description of the relevant known technology may obscure the main points, its detailed description is omitted.

[0022] Figure 1A is an example of a horizontal cross-sectional view of a shape of a reinforcement member according to an embodiment of the inventive concept. Figure 1B and Figure 1C is along Figure 1A An example of a vertical cross-sectional view taken along line AA' in FIG. Figure 2A is an example of a horizontal cross-sectional view of a shape of a reinforcement member according to an embodiment of the inventive concept. Figure 2B is along Figure 2AAn example of a vertical cross-sectional view taken along line BB' in FIG.

[0023] Reference Figures 1A to 1C , the reinforcement 70 may have a disc shape including a plurality of openings, wherein each of the plurality of openings includes a quadrilateral shape in a horizontal cross-sectional view. In some cases, the reinforcement 70 has a grid shape. The reinforcement 70 may include a molding material. For example, the molding material may include a thermoset, a thermoplastic, a UV curable resin, or a combination thereof. For example, the molding material may include an epoxy resin, a silicone resin, or a combination thereof. For example, the molding material may include an epoxy molding compound (EMC). Figure 1B As shown, the reinforcement member 70 may be disposed on the first redistribution structure 100. Figure 1C As shown, the reinforcement member 70 may be disposed on the first redistribution structure 100 and the adhesive layer 72. For example, the adhesive layer 72 is disposed between the reinforcement member 70 and the first redistribution structure 100.

[0024] Reference Figure 2A and Figure 2B , the reinforcement 70' may include a metal material. The reinforcement 70' may be prefabricated based on a method such as die casting, injection, or forging. In some cases, the reinforcement 70' is attached to the first redistribution structure 100 using an adhesive layer 72. For example, the adhesive layer 72 is disposed between the reinforcement 70' and the first redistribution structure 100. As described below, one or more semiconductor chips may be disposed in the openings of the reinforcements 70 and 70'.

[0025] Figure 3A is an example of a plan view of a semiconductor package according to an embodiment. Figure 3B is along Figure 3A For the convenience of describing the embodiments shown in the accompanying drawings, Figure 3A A first semiconductor chip 10 , a second semiconductor chip 20 , a bridge chip 40 , a first redistribution structure 100 , and a stiffener 70 are shown.

[0026] Reference Figure 3A and Figure 3B , the semiconductor package 1 may include a first semiconductor chip 10 , a second semiconductor chip 20 , a first device 30 , a bridge chip 40 , a first redistribution structure 100 , a molding layer 200 , a second redistribution structure 300 , and a reinforcement 70 .

[0027] In some aspects, a direction parallel to the upper surface of the first redistribution structure 100 may be referred to as a horizontal direction (e.g., X direction and / or Y direction), and a direction perpendicular to the horizontal direction (e.g., X direction and / or Y direction) may be referred to as a vertical direction (e.g., Z direction). In some cases, the vertical direction (e.g., Z direction) is parallel to the side surface of the first redistribution structure 100.

[0028] In some aspects, of the two surfaces spaced apart in the vertical direction (eg, Z direction), the surface farther from the external connection terminal 170 may be referred to as an upper surface of the component, and the surface opposite to the upper surface may be referred to as a lower surface of the component.

[0029] In some embodiments, the first redistribution structure 100 may include a passivation layer 110, an under-bump metal (UBM) layer 150, and a conductive layer 160. For example, the passivation layer 110 may have a single-layer structure. In an embodiment, the passivation layer 110 may have a multi-layer structure. In some cases, the passivation layer 110 may completely cover the lower surface and side surface of the conductive layer 160 and expose the upper surface of the conductive layer 160. For example, the upper surface of the passivation layer 110 may be substantially coplanar with the upper surface of the conductive layer 160. In some cases, a portion of the lower surface of the passivation layer 110 may be covered by the UBM layer 150. For example, the lower portion of the UBM layer 150 (e.g., a UBM pad) may be disposed on the lower surface of the passivation layer 110. In some cases, for example, the passivation layer 110 may include silicon oxide, silicon nitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), or an insulating material including a combination thereof.

[0030] The UBM layer 150 may include a UBM pad disposed on the lower surface of the passivation layer 110. In some cases, the lower surface of the UBM pad may be at a level lower than the lower surface of the passivation layer 110. In some cases, the lower surface of the UBM pad may be substantially coplanar with the lower surface of the passivation layer 110. In some cases, the UBM layer 150 may include a UBM through-piece that vertically penetrates at least a portion of the passivation layer 110 and electrically connects the UBM pad and the conductive layer 160. The UBM through-piece may have a truncated cone cup shape with a partially empty central space. In an embodiment, the UBM through-piece may have a truncated cone shape with a filled central space. The UBM pad may have a ring shape with an empty central space. In an embodiment, the UBM pad may have a coin shape with a filled central space.

[0031] The UBM layer 150 may electrically connect different components of the semiconductor package 1, such as the conductive layer 160 and the external connection terminals 170. In some cases, the UBM layer 150 may prevent cracks from being formed in the external connection terminals 170 due to thermal shock between the external connection terminals 170 and the first redistribution structure 100, thereby improving the reliability of the semiconductor package 1. In some cases, for example, the UBM layer 150 may include copper (Cu), aluminum (Al), silver (Ag), gold (Au), tungsten (W), titanium (Ti), or a conductive material including a combination thereof.

[0032] The conductive layer 160 may be disposed in the passivation layer 110, and the upper surface of the conductive layer 160 may be exposed to the upper surface of the passivation layer 110. The conductive layer 160 may be disposed under the plurality of conductive pillars 210, respectively, and the upper surface of the conductive layer 160 may be connected to the lower surface of the plurality of conductive pillars 210. The conductive layer 160 may be a conductive pattern spaced apart in a first horizontal direction (e.g., X direction) or a second horizontal direction (e.g., Y direction). Figure 3B As shown, the conductive layer 160 is a conductive pattern disposed at one vertical level. In an embodiment, the conductive layer 160 may be a conductive pattern having a multilayer structure disposed at different vertical levels within the passivation layer 110. The conductive layer 160 may electrically connect different components, such as a plurality of conductive pillars 210 and the UBM layer 150. In some cases, for example, the conductive layer 160 may include a metal, such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), ruthenium (Ru) or a combination thereof.

[0033] In some embodiments, the semiconductor package 1 may include an external connection terminal 170 disposed on the lower surface of the passivation layer 110. For example, the external connection terminal 170 may be disposed below the UBM layer 150. The external connection terminal 170 may be configured to electrically and physically connect the first redistribution structure 100 to an external device. In some cases, for example, the external connection terminal 170 may have a structure of a solder ball or a conductive bump. The external connection terminal 170 may be electrically connected to the UBM layer 150 of the first redistribution structure 100 and electrically connected to an external device such as a module substrate or a system board. In some cases, the width of the external connection terminal 170 measured along the first horizontal direction (e.g., the X direction) may be less than the width of the UBM pad of the UBM layer 150.

[0034] like Figure 3BAs shown, the external connection terminal 170 may not directly contact and connect to the plurality of conductive pillars 210 surrounding the bridge chip 40. For example, the first redistribution structure 100 may be formed between the plurality of conductive pillars 210 and the external connection terminal 170. When the first redistribution structure 100 is formed between the plurality of conductive pillars 210 and the external connection terminal 170, the line width of the conductive layer 160 is smaller than the external connection terminal 170, resulting in a more sophisticated manufacturing process. In some cases, when the first redistribution structure 100 is formed between the plurality of conductive pillars 210 and the external connection terminal 170, more external connection terminals 170 may be provided compared to the case where the external connection terminal 170 is directly in contact and connected to the plurality of conductive pillars 210. For example, the number of conductive pillars 210 may be less than the number of conductive layers 160 of the first redistribution structure 100. In some cases, the number of conductive layers 160 is equal to the number of external connection terminals 170. When the semiconductor package 1 includes more external connection terminals 170 , the semiconductor package 1 may receive more stable power supply compared to a semiconductor package including fewer external connection terminals 170 .

[0035] The mold layer 200 and the plurality of conductive pillars 210 may be disposed on the first redistribution structure 100. The mold layer 200 may cover the first device 30, the bridge chip 40, and the plurality of conductive pillars 210 on the first redistribution structure 100. In some cases, the mold layer 200 may surround the side surfaces of the conductive pillars 210, the side surfaces and the lower surface of the first device 30, and the side surfaces and the lower surface of the bridge chip 40. In some cases, the mold layer 200 may cover the upper surface of the first redistribution structure 100. For example, the mold layer 200 may cover the upper surface of the passivation layer 110 and the upper surface of the conductive layer 160. The mold layer 200 may completely seal the first device 30 and the bridge chip 40 between the first redistribution structure 100 and the second redistribution structure 300. The mold layer 200 may cover the side surfaces of the plurality of conductive pillars 210 between the first redistribution structure 100 and the second redistribution structure 300. In some cases, an upper layer of mold layer 200 may be substantially coplanar with an upper surface of conductive pillars 210 .

[0036] In some cases, for example, the mold layer 200 may include a thermosetting resin, a thermoplastic resin, a UV curable resin, or a combination thereof. In some cases, for example, the mold layer 200 may include an epoxy resin, a silicone resin, or a combination thereof. For example, the mold layer 200 may include EMC.

[0037] A plurality of conductive pillars 210 may be disposed within the mold layer 200 between the first redistribution structure 100 and the second redistribution structure 300. The plurality of conductive pillars 210 may each provide an electrical connection path between the first redistribution structure 100 and the second redistribution structure 300. In some cases, for example, the plurality of conductive pillars 210 may include a conductive material including copper (Cu), aluminum (Al), silver (Ag), gold (Au), tungsten (W), titanium (Ti), or a combination thereof.

[0038] The plurality of conductive pillars 210 may have upper and lower surfaces spaced apart from each other in a vertical direction (e.g., Z direction). The upper surfaces of the plurality of conductive pillars 210 may be coplanar with the upper surface of the mold layer 200, and the lower surfaces of the plurality of conductive pillars 210 may be coplanar with the lower surface of the mold layer 200. The plurality of conductive pillars 210 may directly contact the conductive layer 160 exposed on the upper surface of the passivation layer 110. For example, the lower surfaces of the plurality of conductive pillars 210 may be connected to the upper surface of the conductive layer 160.

[0039] The plurality of conductive pillars 210 may each have a cylindrical shape. For example, the diameter of each of the plurality of conductive pillars 210 may be constant along the vertical direction (e.g., the Z direction). In an embodiment, the plurality of conductive pillars 210 may each have a tapered shape whose diameter varies along the vertical direction (e.g., the Z direction). For example, the diameter of the upper surface of the conductive pillar 210 may be smaller than the diameter of the lower surface of the conductive pillar 210, and vice versa.

[0040] In some embodiments, the second redistribution structure 300 may be disposed on the mold layer 200. For example, the second redistribution structure 300 may cover the upper surface of the mold layer 200, the upper surface of the conductive pillars 210, the first device 30, and the bridge chip 40. The second redistribution structure 300 may include one or more redistribution insulation layers 310, a plurality of conductive line patterns 320, and a plurality of conductive vias 330.

[0041] One or more redistribution insulating layers 310 may be stacked in a vertical direction (e.g., Z direction). In some cases, for example, redistribution insulating layer 310 may include an insulating material such as a photoimageable dielectric (PID) resin. In some cases, redistribution insulating layer 310 may include photosensitive polyimide and / or an inorganic filler.

[0042] A conductive pattern including a plurality of conductor patterns 320 and a plurality of conductive through-holes 330 may be disposed on at least one of the upper surface and the lower surface of the redistribution insulating layer 310. In some cases, the upper surface of the conductor pattern 320 may be coplanar with the upper surface of the redistribution insulating layer 310. In some cases, the lower surface of the conductive through-holes 330 may be coplanar with the lower surface of the redistribution insulating layer 310. The plurality of conductor patterns 320 may be disposed to extend in a horizontal direction (e.g., X direction and / or Y direction) within the redistribution insulating layer 310. The plurality of conductive through-holes 330 may penetrate at least one redistribution insulating layer 310 in a vertical direction (e.g., Z direction). The plurality of conductive through-holes 330 may contact and electrically connect some of the plurality of conductor patterns 320 at different redistribution insulating layers 310, respectively.

[0043] In some embodiments, at least some of the plurality of conductor patterns 320 may be integrally formed with some of the plurality of conductive vias 330. For example, the plurality of conductor patterns 320 may be integrally formed with the plurality of conductive vias 330 that contact the upper surfaces of the plurality of conductor patterns 320 in the lower insulating layer from the one or more redistribution insulating layers 310. In some cases, the one or more conductive vias 330 may contact and be electrically connected with the conductor patterns 320.

[0044] In some embodiments, the plurality of conductive vias 330 may each have a tapered shape extending from top to bottom, the tapered shape having a decreasing width measured in a horizontal direction (e.g., X direction). For example, the plurality of conductive vias 330 may each have a width that becomes narrower as it is farther from the first semiconductor chip 10. For example, the width of the upper surface of each of the plurality of conductive vias 330 may be greater than the width of the lower surface of each of the plurality of conductive vias 330.

[0045] In some cases, for example, the plurality of redistribution patterns including the plurality of conductor patterns 320 and the plurality of conductive through-holes 330 may each include a metal such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium Ga, ruthenium (Ru) or an alloy thereof, but is not necessarily limited thereto.

[0046] The first semiconductor chip 10, the second semiconductor chip 20, and the reinforcement 70 may be disposed on the upper surface of the second redistribution structure 300. In some cases, the first device 30, the bridge chip 40, the molding layer 200, and the conductive pillars 210 may be disposed on the lower surface of the second redistribution structure 300. The first semiconductor chip 10 and the second semiconductor chip 20 may be spaced apart in a horizontal direction (e.g., X direction) on the second redistribution structure 300. In some cases, the first device 30 and the bridge chip 40 may be spaced apart in a horizontal direction (X direction) below the second redistribution structure 300.

[0047] The first semiconductor chip 10 may include a first substrate 12 and a first chip pad 14. The second semiconductor chip 20 may include a second substrate 22 and a second chip pad 24. Each of the first substrate 12 and the second substrate 22 may include an active surface and an inactive surface opposite to the active surface. The active surface may be disposed adjacent to a lower surface of each of the first substrate 12 and the second substrate 22.

[0048] In some embodiments, one or more of the first semiconductor chip 10 and the second semiconductor chip 20 may be a memory chip or a logic chip. For example, the memory chip may be a volatile memory chip, such as a dynamic random access memory (DRAM) or a static random access memory (SRAM). In some cases, for example, the memory chip may be a non-volatile memory chip, such as a phase change random access memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FeRAM), or a resistive random access memory (RRAM). In some cases, for example, the logic chip may be a microprocessor, an analog component, or a digital signal processor.

[0049] The first substrate 12 and the second substrate 22 may each include an integrated circuit. The integrated circuit may be a memory circuit, a logic circuit, or any type of integrated circuit including a combination thereof. For example, the memory circuit may include a dynamic random access memory (DRAM) circuit, a static random access memory (SRAM) circuit, a flash memory circuit, an electrically erasable programmable read-only memory (EEPROM) circuit, a phase change random access memory (PRAM) circuit, a magnetic random access memory (MRAM) circuit, a resistive random access memory (RRAM) circuit, or a combination thereof. In some cases, for example, the logic circuit may include a central processing unit (CPU) circuit, a graphics processing unit (GPU) circuit, a controller circuit, an application specific integrated circuit (ASIC) circuit, an application processor (AP) circuit, or a combination thereof.

[0050] In some cases, the first substrate 12 and the second substrate 22 may each include a semiconductor material, such as a Group IV semiconductor material, a Group III-V semiconductor material, a Group II-VI semiconductor material, or a combination thereof. For example, the Group IV semiconductor material may include silicon (Si), germanium (Ge), or a combination thereof. For example, the Group III-V semiconductor material may include gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), indium arsenide (InAs), indium antimonide (InSb), indium gallium arsenide (InGaAs), or a combination thereof. For example, the Group II-VI semiconductor material may include zinc telluride (ZnTe), cadmium sulfide (CdS), or a combination thereof.

[0051] The first chip pad 14 and the second chip pad 24 may be disposed on the lower surfaces of the first substrate 12 and the second substrate 22, respectively, and may extend along the lower surface of each of the first substrate 12 and the second substrate 22 as an active surface. In some cases, the first connection member 16 may be disposed between the first semiconductor chip 10 and the second redistribution structure 300. For example, the first connection member 16 may be disposed between the lower surface of the first chip pad 14 and the upper surface of the second redistribution structure 300. In some cases, the second connection member 26 may be disposed between the second semiconductor chip 20 and the second redistribution structure 300. For example, the second connection member 26 may be disposed between the lower surface of the second chip pad 24 and the upper surface of the second redistribution structure 300.

[0052] The first chip pad 14 may contact the first connection member 16, and the second chip pad 24 may contact the second connection member 26. Each of the first connection member 16 and the second connection member 26 may contact the wire pattern 320 and / or the conductive via 330 of the second redistribution structure 300. Therefore, the first connection member 16 may provide an electrical connection path between the first semiconductor chip 10 and the second redistribution structure 300, and the second connection member 26 may provide an electrical connection path between the second semiconductor chip 20 and the second redistribution structure 300.

[0053] In some cases, for example, the first chip pad 14 and the second chip pad 24 may include a conductive material including copper (Cu), aluminum (Al), silver (Ag), gold (Au), tungsten (W), titanium (Ti), or a combination thereof. In some cases, for example, the first connection member 16 and the second connection member 26 may each include a solder ball or a solder bump.

[0054] When viewed from the upper surface of the semiconductor package 1, the reinforcement member 70 may have a quadrangular ring shape surrounding the first semiconductor chip 10 and the second semiconductor chip 20. For example, the first semiconductor chip 10 and the second semiconductor chip 20 may be disposed on the reinforcement member 70 (eg, refer to Figure 1AThe first semiconductor chip 10 and the second semiconductor chip 20 may be spaced apart from the side surface (or sidewall) of the opening of the reinforcement member 70 by a constant interval in some cases, wherein the constant interval may be in a range from about 2 mm to about 3 mm. The upper surface of the reinforcement member 70 may be disposed at a lower vertical level than the upper surfaces of the first semiconductor chip 10 and the second semiconductor chip 20. For example, relative to the upper surface of the second redistribution structure 300, the height H1 of the reinforcement member 70 measured in the vertical direction may be less than the height H2 of each of the first semiconductor chip 10 and the second semiconductor chip 20 measured in the vertical direction. As a result, heat can be effectively dissipated from the first semiconductor chip 10 and the second semiconductor chip 20.

[0055] The first device 30 may be disposed on the lower surface of the second redistribution structure 300. The first device 30 may include various types of passive components or various forms of surface mountable components. For example, the first device 30 may be referred to as a passive device. For example, the passive component may include one or more of a resistor, a capacitor, an inductor, a thermistor, an oscillator, a ferrite bead, an antenna, a varistor, and / or a crystal. For example, the passive component may include a multilayer ceramic capacitor (MLCC), a low inductance chip capacitor (LICC), a pad side capacitor (LSC), an integrated passive device (IPD), etc.

[0056] The third connection member 32 may be disposed between the first device 30 and the second redistribution structure 300. The first device 30 may be electrically connected to the second redistribution structure 300 through the third connection member 32. For example, the third connection member 32 may be a solder ball or a solder bump.

[0057] The bridge chip 40 may be disposed on the lower surface of the second redistribution structure 300. In some cases, the bridge chip 40 may be spaced apart from the first device 30 in a horizontal direction (e.g., an X direction). The bridge chip 40 may provide an electrical connection path between the first semiconductor chip 10 and the second semiconductor chip 20 disposed on the second redistribution structure 300. For example, the first semiconductor chip 10 and the second semiconductor chip 20 may be electrically connected to each other through a bridge circuit within the bridge chip 40. Figure 3A As shown, each of the first semiconductor chip 10 and the second semiconductor chip 20 may overlap at least a portion of the bridge chip 40 in a vertical direction (eg, Z direction).

[0058] The bridge chip 40 may include a bridge substrate 42 and a bridge circuit. The bridge chip 40 may not be directly electrically connected to the first redistribution structure 100 but may be electrically connected to the first redistribution structure 100 through the conductive pillars 210 and the second redistribution structure 300.

[0059] The active surface of the bridging substrate 42 can be arranged adjacent to the upper surface of the bridging substrate 42, and the passive surface of the bridging substrate 42 can be arranged adjacent to the lower surface of the bridging substrate 42. The bridging substrate 42 may include a semiconductor material, such as a Group IV semiconductor material, a Group III-V semiconductor material, a Group II-VI semiconductor material, or a combination thereof. For example, the Group IV semiconductor material may include silicon (Si), germanium (Ge), or a combination thereof. For example, the Group III-V semiconductor material may include gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), indium arsenide (InAs), indium antimonide (InSb), indium gallium arsenide (InGaAs), or a combination thereof. For example, the Group II-VI semiconductor material may include zinc telluride (ZnTe), cadmium sulfide (CdS), or a combination thereof. In some cases, the bridging substrate 42 may include glass or ceramic.

[0060] The bridge circuit may be formed in the bridge substrate 42. The bridge circuit may have a pitch corresponding to the fine pitch of the chip pad of each of the first semiconductor chip 10 and the second semiconductor chip 20. The bridge circuit may have a finer pitch than the conductive layer 160. For example, the line width of the bridge circuit may be smaller than the line width of the conductive layer 160.

[0061] The fourth connection member 44 may be disposed between the bridge chip 40 and the second redistribution structure 300. The fourth connection member 44 may electrically connect the second redistribution structure 300 to the bridge chip 40. The fourth connection member 44 may contact the conductor pattern 320 and / or the conductive through-piece 330 of the second redistribution structure 300. For example, the fourth connection member 44 may include a conductive column. For example, the fourth connection member 44 may have a single cylindrical shape. For example, the diameter of the fourth connection member 44 may be constant along the vertical direction (e.g., Z direction). In an embodiment, the fourth connection member 44 may have a conical shape whose diameter changes along the vertical direction (e.g., Z direction). For example, the fourth connection member 44 may include copper (Cu), aluminum (Al), silver (Ag), gold (Au), tungsten (W), titanium (Ti), or a conductive material including a combination thereof.

[0062] In an embodiment, each of the first device 30 and the bridge chip 40 may include a chip pad. When the first device 30 includes a chip pad, the first device chip pad may contact the third connection member 32. In some cases, the first device chip pad may be disposed between the first device 30 and the third connection member 32. In some cases, when the bridge chip 40 includes a chip pad, the bridge chip pad may contact the fourth connection member 44. In some cases, the bridge chip pad may be disposed between the bridge chip 40 and the fourth connection member 44.

[0063] In some embodiments, the semiconductor package 1 may include an underfill layer 50, which surrounds the third connection member 32 and the fourth connection member 44. For example, the underfill layer 50 may be disposed between the first device 30 and the second redistribution structure 300. For example, the underfill layer 50 may be disposed between the bridge chip 40 and the second redistribution structure 300. The underfill layer 50 may fill the space between the first device 30 and the second redistribution structure 300 and the space between the bridge chip 40 and the second redistribution structure 300. The underfill layer 50 may include an outer surface having an inclination. The underfill layer 50 may include epoxy resin or two or more silicone hybrid materials. Therefore, the third connection member 32 and the fourth connection member 44 may contact the underfill layer 50. However, the inventive concept is not necessarily limited thereto, and the underfill layer 50 may be omitted.

[0064] The first device 30 and the bridge chip 40 may be disposed at a vertical level higher than the upper surface of the first redistribution structure 100. In some cases, the first device 30 and the bridge chip 40 may be arranged to be spaced apart from the upper surface of the first redistribution structure 100 in the vertical direction (Z direction). For example, the first device 30 and the bridge chip 40 may be spaced apart from the first redistribution structure 100. For example, the mold layer 200 may be disposed between the first device 30 and the first redistribution structure 100 and between the bridge chip 40 and the first redistribution structure 100.

[0065] In some cases, inside the molding layer 200, the first device 30 may have a third height H3 measured in the vertical direction (e.g., Z direction), and the bridge chip 40 may have a fourth height H4 measured in the vertical direction (e.g., Z direction). The third height H3 and the fourth height H4 may be different from each other. In an embodiment, the third height H3 may be greater than the fourth height H4, and vice versa. In an embodiment, the third height H3 and the fourth height H4 may be equal to each other.

[0066] The semiconductor package 1 according to the inventive concept may first form the stiffener 70 including a plurality of openings each having a quadrangular cross-section, thereby ensuring mechanical stability without a wafer support system (WSS) process.

[0067] Figure 4 2 is an example of a cross section of a semiconductor package 2 according to an embodiment of the inventive concept. Figure 3A and Figure 3B describe Figure 4 A semiconductor package 2. In some cases, the description Figure 3B The semiconductor package 1 and Figure 4 The difference between the semiconductor packages 2.

[0068] Reference Figure 4 The semiconductor package 2 may include a first semiconductor chip 10 , a second semiconductor chip 20 , a first device 30 , a bridge chip 40 , a second device 60 , a first redistribution structure 100 , a molding layer 200 , a second redistribution structure 300 , and a reinforcement 70 . Figure 4 The first semiconductor chip 10, the second semiconductor chip 20, the first device 30, the bridge chip 40, the first redistribution structure 100, the molding layer 200, the second redistribution structure 300 and the reinforcement 70 of the semiconductor package 2 are respectively Figure 3B The first semiconductor chip 10, the second semiconductor chip 20, the first device 30, the bridge chip 40, the first redistribution structure 100, the molding layer 200, the second redistribution structure 300, and the stiffener 70 of the semiconductor package 1 are substantially the same. Therefore, the second device 60 is described below.

[0069] The second device 60 may be disposed on a lower surface of the second redistribution structure 300. For example, the second device 60 may be spaced apart from the first redistribution structure 100 in a vertical direction (e.g., Z direction). The second device 60 may be spaced apart from each of the first device 30 and the bridge chip 40 in a horizontal direction (e.g., X direction and / or Y direction). Each of the first device 30, the bridge chip 40, and the second device 60 may be surrounded by the molding layer 200.

[0070] For example, the second device 60 may include a chiplet. The chiplet may include multiple IP blocks, and the multiple IP blocks may perform different functions. Each of the multiple IP blocks may include multiple integrated circuits. In an embodiment, the second device 60 may be an active device. In an embodiment, the second device 60 may be a semiconductor chip. For example, the second device 60 may be an input / output chip (I / O chip) or a power management chip. The power management chip may include a power management integrated circuit (PMIC). In some cases, the second device 60 may include a second device substrate 62, wherein the second device substrate 62 includes multiple IP blocks.

[0071] The second device 60 may be spaced apart from the first redistribution structure 100 in the vertical direction (Z direction). For example, the mold layer 200 may be disposed between the second device 60 and the first redistribution structure 100. For example, the mold layer 200 may cover the lower surface and side surfaces of the second device 60.

[0072] In some cases, the second device 60 may have a fifth height H5 measured from the upper surface to the lower surface of the second device 60. The third height H3, the fourth height H4, and the fifth height H5 may be different from each other. In an embodiment, at least two of the third height H3, the fourth height H4, and the fifth height H5 may be the same. For example, the third height H3 and the fifth height H5 may be the same.

[0073] The fifth connection member 64 may be disposed between the second device 60 and the second redistribution structure 300. The second device 60 may be electrically connected to the second redistribution structure 300 through the fifth connection member 64. The fifth connection member 64 may contact the conductive line pattern 320 and / or the conductive via 330 of the second redistribution structure 300. A plurality of fifth connection members 64 may also be surrounded by the underfill layer 50.

[0074] In an embodiment, the second device 60 may include a chip pad. When the second device 60 includes a second device chip pad, the second device chip pad may contact the fifth connection member 64. For example, the second device chip pad may be disposed between the upper surface of the second device and the lower surface of the fifth connection member 64 and contact the upper surface of the second device and the lower surface of the fifth connection member 64. In some cases, the fifth connection member 64 may be a reference Figure 3B The example of the fourth connecting member 44 described, or including reference Figure 3B Aspects of the fourth connecting member 44 are described.

[0075] In some cases, in each of the semiconductor package 1 and the semiconductor package 2, the fourth connection member 44 may include a solder ball, and the third connection member 32 may include a conductive column. The conductive column may have a single cylindrical shape. For example, the diameter of the conductive column may be constant along the vertical direction (e.g., Z direction). In an embodiment, the conductive column may have a tapered shape in which the diameter changes along the vertical direction (e.g., Z direction). For example, the third connection member 32 and the fourth connection member 44 may each include copper (Cu), aluminum (Al), silver (Ag), gold (Au), tungsten (W), titanium (Ti), or a conductive material including a combination thereof. In some cases, the third connection member 32 and the fourth connection member 44 may be modified in various ways.

[0076] Figure 5 is an example of a cross-sectional view of a semiconductor package 3 according to an embodiment of the inventive concept. Figure 4 describe Figure 5 3. In some cases, the semiconductor package described Figure 4 The semiconductor package 2 and Figure 5 The differences between the semiconductor packages 3.

[0077] Reference Figure 5 The semiconductor package 3 may include a first semiconductor chip 10 , a second semiconductor chip 20 , a first device 30 , a bridge chip 40 , a second device 60 , a first redistribution structure 100 , a molding layer 200 , a second redistribution structure 300 , and a reinforcement 70 . Figure 5The first semiconductor chip 10, the second semiconductor chip 20, the first device 30, the bridge chip 40, the second device 60, the first redistribution structure 100, the molding layer 200, the second redistribution structure 300 and the reinforcement member 70 of the semiconductor package 3 are respectively Figure 4 The first semiconductor chip 10, the second semiconductor chip 20, the first device 30, the bridge chip 40, the second device 60, the first redistribution structure 100, the mold layer 200, the second redistribution structure 300, and the stiffener 70 are substantially the same. Therefore, the difference of the conductive pillar 210 is described below.

[0078] In some embodiments, the conductive pillar 210 may include a columnar portion 210a including copper (Cu) and a connection layer 210b allowing the columnar portion 210a to be connected to the first redistribution structure 100. In some cases, the columnar portion 210a of the conductive pillar 210 is disposed on the connection layer 210b of the conductive pillar 210. In some cases, for example, the upper surface of the columnar portion 210a of the conductive pillar 210 may be disposed on the lower surface of the conductive via 330 and / or the conductive wire pattern 320 of the second redistribution structure 300 and contact the lower surface of the conductive via 330 and / or the conductive wire pattern 320 of the second redistribution structure 300. In some cases, the lower surface of the connection layer 210b of the conductive pillar 210 may be disposed on the upper surface of the conductive layer 160 of the first redistribution structure 100 and contact the upper surface of the conductive layer 160 of the first redistribution structure 100. The connection layer 210b may include lead (Pb), but the material of the connection layer 210b is not necessarily limited thereto.

[0079] Figure 6 is an example of a cross-sectional view of a semiconductor package 4 according to an embodiment of the inventive concept. Figure 7 is an example of a cross-sectional view of a semiconductor package 5 according to an embodiment of the inventive concept. Figure 6 and Figure 7 , Figure 6 The semiconductor package 4 and Figure 7 The semiconductor packages 5 may include Figure 6 The heat sink 80 and Figure 7 Radiator 80b in.

[0080] Reference Figure 6, the first semiconductor chip 10 and the second semiconductor chip 20 may be connected to the heat sink 80 through an interface material layer 82. For example, the interface material layer 82 is disposed between the heat sink 80 and the upper surface of each of the first semiconductor chip 10 and the second semiconductor chip 20. In an embodiment, the heat sink 80 may include a first heat sink and a second heat sink, wherein the first heat sink and the second heat sink are connected to the first semiconductor chip 10 and the second semiconductor chip 20, respectively. The interface material layer 82 may include a thermally conductive and electrically insulating material. For example, the interface material layer 82 may include a polymer including a metal powder such as silver or copper, thermal grease, white grease, or a combination thereof. The heat sink 80 may directly contact the first semiconductor chip 10 and the second semiconductor chip 20 through the interface material layer 82, thereby improving the heat dissipation characteristics. Figure 6 As shown, the upper surface of the reinforcement member 70 is spaced apart from the bottom surface of the heat sink 80, but the arrangement of the reinforcement member 70 is not necessarily limited thereto. For example, the upper surface of the reinforcement member 70 may be formed to be in direct contact with the bottom surface of the heat sink 80. In some cases, an interface material layer may be provided on the upper surface of the reinforcement member 70, and the reinforcement member 70 may contact the heat sink 80 through the interface material layer. In a plan view, the heat sink 80 may have a shape protruding into the opening of the reinforcement member 70.

[0081] Reference Figure 7 , Figure 7 The interface material layer 82 and Figure 6 The interface material layer 82 is the same as that in FIG. 1 , so the description thereof is omitted. Figure 7 The heat sink 80b and Figure 6 The difference between the radiator 80 in.

[0082] The heat sink 80b may include a protruding portion protruding downward from a portion in contact with the first semiconductor chip 10 and the second semiconductor chip 20 through the interface material layer 82. Figure 7 As shown, the upper surface of the reinforcement member 70 is spaced apart from the bottom surface of the heat sink 80b, but the arrangement of the reinforcement member 70 is not necessarily limited thereto. For example, the upper surface of the reinforcement member 70 may be formed to be in direct contact with the bottom surface of the heat sink 80b. In some cases, an interface material layer may be provided on the upper surface of the reinforcement member 70, and the reinforcement member 70 may contact the heat sink 80b through the interface material layer. In a plan view, the heat sink 80b may have a shape protruding into the opening of the reinforcement member 70.

[0083] Figure 8 1 is an example of a plan view of a semiconductor package 6 according to an embodiment of the inventive concept. For the convenience of describing the embodiment, the first semiconductor chip 10, the second semiconductor chip 20, the bridge chip 40, the first redistribution structure 100 and the reinforcement 70 are shown in FIG. Figure 8 See Figure 3A and Figure 3B To describe Figure 8 For example, the semiconductor package 6 is described Figure 3A and Figure 3B The semiconductor package 1 and Figure 8 The differences between the semiconductor packages 6 in FIG.

[0084] Reference Figure 8 , the bridge chip 40 may be disposed on the lower surface of the second redistribution structure 300. The bridge chip 40 may provide an electrical connection path between the first semiconductor chip 10 and the second semiconductor chip 20 disposed on the second redistribution structure 300. For example, the first semiconductor chip 10 and the second semiconductor chip 20 may be electrically connected to each other through a bridge circuit inside the bridge chip 40. Figure 8 As shown, two first semiconductor chips 10 spaced apart in the horizontal direction (e.g., Y direction) and two second semiconductor chips 20 spaced apart in the horizontal direction (e.g., Y direction) may each overlap at least a portion of the bridge chip 40 in the vertical direction (e.g., Z direction). For example, the bridge chip 40 is disposed near the central region of the opening in the stiffener 70. In a plan view, each of the four corners of the bridge chip 40 may overlap with a corner region of each of the two first semiconductor chips 10 and each of the two second semiconductor chips 20.

[0085] However, the present inventive concept is not necessarily limited thereto, and the first semiconductor chip 10, the second semiconductor chip 20, and the bridge chip 40 may be arranged in various ways. The bridge chip 40 may electrically connect the plurality of semiconductor chips to each other. Figure 3A Contrary to the illustrated embodiment, the bridge chip 40 may be disposed on the lower surface of the second redistribution structure to electrically connect the plurality of semiconductor chips to each other.

[0086] 9A to 9H is an example of a cross-sectional view of a method for manufacturing a semiconductor package according to an embodiment of the inventive concept. Figures 1A to 8 describe 9A to 9H method.

[0087] Reference Fig. 9A , a second redistribution structure 300 may be formed. The second redistribution structure 300 may include one or more redistribution insulation layers 310, a wire pattern 320, and a conductive through-piece 330. For example, each of the one or more redistribution insulation layers 310 may include a plurality of wire patterns 320 and a plurality of conductive through-pieces 330 disposed on the wire patterns 320.

[0088] One or more redistribution insulation layers 310 may be stacked in a vertical direction (e.g., Z direction). The conductor pattern 320 may extend in a horizontal direction (e.g., X direction and / or Y direction) inside the redistribution insulation layer 310. The conductive through-piece 330 may extend in a vertical direction (e.g., Z direction) inside the redistribution insulation layer 310 and may be electrically connected to at least one conductor pattern 320.

[0089] First, a lowermost bottom conductor pattern 320 is formed, and a preliminary lowermost redistribution insulating layer is formed to cover the lowermost bottom conductor pattern 320. Then, at least a portion of the preliminary lowermost redistribution insulating layer may be removed by performing an exposure process, and a lowermost redistribution insulating layer 310 including a via hole may be formed. The via hole may be formed to have a narrow horizontal width from the upper surface of the lowermost redistribution insulating layer 310 to the lower surface of the lowermost redistribution insulating layer 310. A base redistribution conductive layer may be formed on the lowermost redistribution insulating layer 310 and patterned, and a base conductive pattern including a conductor pattern 320 and a conductive through-piece 330 may be formed. Then, a second redistribution structure 300 may be formed by repeatedly forming a redistribution insulating layer 310 and a base conductive pattern.

[0090] Reference Fig. 9B , a reinforcement member 70 may be formed. The reinforcement member 70 may include an opening extending from the upper surface to the lower surface. As described below, a semiconductor chip may be disposed in the opening of the reinforcement member 70. Figures 1A to 1C , Figure 2A and Figure 2B In some embodiments, the reinforcement member 70 may be disposed on the second redistribution structure 300 through an adhesive layer. In some cases, the reinforcement member 70 is disposed on the bottom surface of the lowermost redistribution insulation layer 310. For example, an adhesive layer may be disposed between the reinforcement member 70 and the second redistribution structure 300.

[0091] Reference Fig. 9C , a conductive pillar 210 may be formed. For example, the conductive pillar 210 may be disposed on the uppermost redistribution insulating layer 310 of the second redistribution structure 300. For example, the conductive pillar 210 may include copper (Cu), aluminum (Al), silver (Ag), gold (Au), tungsten (W), titanium (Ti), or a conductive material including a combination thereof. In some embodiments, as shown in FIG. Figure 6 As described above, the conductive pillar 210 may include a columnar portion 210a including copper (Cu) and a connection layer 210b allowing the columnar portion 210a to be connected to the first redistribution structure 100. For example, the connection layer 210b may include lead (Pb), but the material of the connection layer 210b is not necessarily limited thereto.

[0092] Reference Fig.9D, the first device 30 and the bridge chip 40 may be attached to the second redistribution structure 300. Each of the first device 30, the bridge chip 40, and the conductive pillar 210 may be spaced apart from each other in a horizontal direction (e.g., an X direction). In some cases, each of the first device 30, the bridge chip 40, and the conductive pillar 210 may be disposed on the conductive via 330 of the second redistribution structure 300.

[0093] The first device 30 may be disposed on and connected to the third connection member 32, and the bridge chip 40 may be disposed on and connected to the fourth connection member 44. In some cases, an underfill layer 50 is disposed on the second redistribution structure 300. The underfill layer 50 may surround and cover the third connection member 32 and the fourth connection member 44, but the present inventive concept is not necessarily limited thereto.

[0094] For example, the first device 30 may be connected to the second redistribution structure 300 using a solder bonding method, and the bridge chip 40 may be connected to the second redistribution structure 300 using an oxide bonding method. Therefore, the third connection member 32 may include a solder ball, and the fourth connection member 44 may include a conductive column. However, the bonding method of the first device 30 and / or the bridge chip 40 may be modified in various ways.

[0095] Reference Fig.9E , the molding layer 200 may be formed on the second redistribution structure 300 by forming a molding material around the first device 30, the bridge chip 40, and the conductive pillars 210. In some cases, the molding material may cover the upper surface of the conductive pillars 210. In some cases, a portion of the molding material is removed to form the molding layer 200.

[0096] The material of the molding material can be compared with the reference Figure 3B The material of the mold layer 200 described above is the same. After the mold material is formed, the upper portion of the mold material and the upper portion of the conductive pillar 210 may be removed by grinding. The mold layer 200 may be formed by grinding the mold material. When the removal process of the mold layer 200 is completed, the upper surface of the mold layer 200 may be coplanar with the upper surface of the conductive pillar 210. For example, the upper surface of the conductive pillar 210 is exposed.

[0097] Reference Fig.9F , the semiconductor package can be rotated or flipped 180 degrees around its central axis. Fig.9F It can be shown Fig.9EThe result of the above steps is an inverted form (or an inverted version) of the result. Then, the first semiconductor chip 10 and the second semiconductor chip 20 may be disposed on the second redistribution structure 300. The first semiconductor chip 10 and the second semiconductor chip 20 may be disposed in the opening of the reinforcement member 70. In some cases, the reinforcement member 70 surrounds the first semiconductor chip 10 and the second semiconductor chip 20. In some cases, the reinforcement member 70, the first semiconductor chip 10 and the second semiconductor chip 20 may be spaced apart from each other in a horizontal direction (e.g., an X direction). The first semiconductor chip 10 may include a first substrate 12 and a first chip pad 14, and the second semiconductor chip 20 may include a second substrate 22 and a second chip pad 24.

[0098] The first connection member 16 may be disposed between the first semiconductor chip 10 and the second redistribution structure 300, and the second connection member 26 may be disposed between the second semiconductor chip 20 and the second redistribution structure 300. For example, the first connection member 16 may be disposed between the first chip pad 14 and the second redistribution structure 300, and the second connection member 26 may be disposed between the second chip pad 24 and the second redistribution structure 300. The first connection member 16 and the second connection member 26 may be electrically connected to the wire pattern 320 and / or the conductive via 330 of the second redistribution structure 300.

[0099] Reference Figure 9G , the first redistribution structure 100 may be formed on the mold layer 200. For example, the first redistribution structure 100 may be disposed below the mold layer 200. The first redistribution structure 100 may include a passivation layer 110, a UBM layer 150, and a conductive layer 160. The passivation layer 110 may completely cover the lower surface and the side surface of the conductive layer 160 and expose the upper surface of the conductive layer 160. In some cases, a portion of the lower surface of the passivation layer 110 may be covered by the UBM layer 150.

[0100] In order to form the first redistribution structure 100, a conductive layer 160 may be first formed on the lower surface of the mold layer 200. The conductive layer 160 may be formed by an electroplating process. Then, a seed layer may be formed on the edge of the conductive layer 160 to prevent the metal material of the conductive layer 160 from diffusing into the passivation layer 110. After forming the conductive layer 160, a first operation of forming a passivation layer 110 covering the conductive layer 160 and including a via, a second operation of forming a UBM through-hole to fill the via, and a third operation of forming a UBM pad integrally formed with the UBM through-hole and covering a portion of the lower surface of the passivation layer 110 may be performed. The second operation and the third operation of forming the UBM through-hole and the UBM pad, respectively, may include an electroplating process. In the first operation, the passivation layer 110 may be formed, for example, by lamination, application, chemical vapor deposition (CVD), physical vapor deposition (PVD), or a combination thereof.

[0101] Reference Figure 9H , the semiconductor package 1 may be completed by connecting the external connection terminal 170 to the UBM layer 150. For example, the external connection terminal 170 may include a solder ball structure or a conductive bump structure.

[0102] Although the embodiments of the present disclosure have been described with reference to the accompanying drawings, the present disclosure is not necessarily limited to the above embodiments, but can be implemented in various different forms. It will be appreciated by those skilled in the art that the present disclosure can be implemented in other specific forms without changing the technical spirit or basic features of the present disclosure. Therefore, it should be understood that the above embodiments are not restrictive but illustrative in all aspects.

Claims

1. A semiconductor package, comprising: First redistribution structure; a second redistribution structure, which is disposed on the first redistribution structure; A semiconductor chip disposed on an upper surface of the second redistribution structure; a bridge chip disposed on a lower surface of the second redistribution structure; a molding layer disposed between the first redistribution structure and the second redistribution structure, wherein the molding layer surrounds the bridge chip; as well as a reinforcement member disposed on an upper surface of the second redistribution structure, wherein the reinforcement member includes an opening, Wherein, the semiconductor chip is arranged in the opening of the reinforcement.

2. The semiconductor package according to claim 1, wherein: A horizontal cross-section of the opening of the reinforcement member is in a quadrilateral shape.

3. The semiconductor package according to claim 1, wherein: An upper surface of the reinforcement is disposed at a lower vertical level than an upper surface of the semiconductor chip.

4. The semiconductor package according to claim 1, further comprising: An adhesive layer is disposed between the lower surface of the reinforcement and the upper surface of the second redistribution structure.

5. The semiconductor package according to claim 1, wherein: The semiconductor chip disposed in the opening of the stiffener is spaced apart from a sidewall of the opening of the stiffener by a constant interval.

6. The semiconductor package according to claim 5, wherein: The constant interval ranges from 2 mm to 3 mm.

7. The semiconductor package according to claim 1, wherein: The bridge chip is electrically connected to the first redistribution structure through the second redistribution structure, The bridge chip overlaps a portion of the semiconductor chip in a vertical direction, and Wherein, the vertical direction is perpendicular to an upper surface of the second redistribution structure.

8. The semiconductor package according to claim 1, further comprising: A conductive pillar is disposed in the molding layer and is spaced apart from the bridge chip in a horizontal direction, wherein the horizontal direction is parallel to an upper surface of the second redistribution structure.

9. The semiconductor package according to claim 8, wherein: The conductive column includes a columnar portion and a connection layer disposed between the columnar portion and an upper surface of the first redistribution structure, and Wherein, the columnar portion includes copper (Cu), and the connection layer includes lead (Pb).

10. The semiconductor package according to claim 1, further comprising: A connecting member is disposed between the bridge chip and the second redistribution structure and is in direct contact with the bridge chip and the second redistribution structure.

11. A semiconductor package, comprising: First redistribution structure; a second redistribution structure, which is disposed on the first redistribution structure; A semiconductor chip disposed on an upper surface of the second redistribution structure; a bridge chip disposed on a lower surface of the second redistribution structure; a passive device disposed on a lower surface of the second redistribution structure and spaced apart from the bridge chip in a horizontal direction, wherein the horizontal direction is parallel to an upper surface of the second redistribution structure; a molding layer disposed between the first redistribution structure and the second redistribution structure, wherein the molding layer surrounds the bridge chip and the passive device; a conductive pillar spaced apart from the bridge chip and the passive device in the horizontal direction within the molding layer; a heat sink disposed on the upper surface of the semiconductor chip; as well as a reinforcement member disposed on an upper surface of the second redistribution structure, wherein the reinforcement member includes an opening, Wherein, the semiconductor chip is arranged in the opening of the reinforcement.

12. The semiconductor package according to claim 11, wherein The heat sink is spaced apart from the uppermost surface of the reinforcement in a vertical direction, and Wherein, the vertical direction is perpendicular to the horizontal direction.

13. The semiconductor package according to claim 11, wherein: The heat sink is in contact with the uppermost surface of the reinforcement member.

14. The semiconductor package according to claim 11, wherein The heat sink includes a protruding portion, and the protruding portion protrudes toward the semiconductor chip.

15. The semiconductor package according to claim 11, wherein A height of the passive device and a height of the bridge chip are different from each other.

16. A semiconductor package, comprising: a first redistribution structure including a passivation layer, an under bump metallurgy layer disposed on and covering a portion of a lower surface of the passivation layer, and a conductive layer contacting the under bump metallurgy layer and exposed at an upper surface of the passivation layer; a second redistribution structure disposed on the first redistribution structure, wherein the second redistribution structure comprises one or more redistribution insulation layers, one or more conductive line patterns disposed in the one or more redistribution insulation layers and extending in a horizontal direction, and one or more conductive vias disposed in the one or more redistribution insulation layers and extending in a vertical direction perpendicular to the horizontal direction, wherein the horizontal direction is parallel to an upper surface of the second redistribution structure; One or more semiconductor chips disposed on an upper surface of the second redistribution structure; a bridge chip disposed on a lower surface of the second redistribution structure, wherein the bridge chip provides an electrical connection path between the one or more semiconductor chips; a passive device disposed on a lower surface of the second redistribution structure and spaced apart from the bridge chip in the horizontal direction; a molding layer disposed between the first redistribution structure and the second redistribution structure, wherein the molding layer surrounds a lower surface and a side surface of the bridge chip and a lower surface and a side surface of the passive device; a conductive pillar spaced apart from the bridge chip and the passive device in the horizontal direction within the molding layer; as well as a reinforcement member disposed on an upper surface of the second redistribution structure, wherein the reinforcement member includes an opening, The one or more semiconductor chips are disposed in the opening of the reinforcement.

17. The semiconductor package according to claim 16, wherein: A horizontal cross-section of the opening of the reinforcement member is in a quadrilateral shape.

18. The semiconductor package according to claim 16, wherein: An upper surface of the stiffener is at a lower vertical level than an upper surface of each of the one or more semiconductor chips.

19. The semiconductor package according to claim 16, wherein: The one or more semiconductor chips disposed in the opening of the stiffener are spaced apart from a sidewall of the opening of the stiffener by a gap ranging from 2 mm to 3 mm.

20. The semiconductor package according to claim 16, further comprising: a passive device connecting member disposed between the passive device and the second redistribution structure; as well as a bridge chip connecting member, which is arranged between the bridge chip and the second redistribution structure, Wherein, each of the passive device connection member and the bridge chip connection member includes one or more of a solder ball and a conductive column.

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