Semiconductor package structure and method for forming the same

Abstract

A semiconductor package structure and a method for forming a semiconductor package structure are disclosed. In certain aspects, a semiconductor package structure includes an interposer structure including an interconnect bridge, device circuitry, a set of conductive elements, and a molding layer. The interconnect bridge includes a stack of conductive layers and dielectric layers alternately disposed, and an interconnect structure formed in the stack and penetrating at least a portion of the stack to connect to the conductive layers in the stack. Device circuitry is disposed on and coupled to the interconnect bridge. The set of conductive elements is disposed on and coupled to the interconnect bridge. The set of conductive elements is disposed on the periphery of the device circuitry. An interconnect structure of the interconnect bridge is connected to at least one conductive element from the set of conductive elements. A molding layer encapsulates the device circuitry and the set of conductive elements.

Description

Background Art

[0001] The present disclosure relates to a semiconductor package structure and a method for manufacturing the same.

[0002] Package on package (POP) is a semiconductor packaging scheme that involves stacking two or more packages on top of each other. Signals can be routed between packages through standard package interfaces. POP provides a packaging solution for applications that require more features in a smaller space, such as mobile terminals (e.g., smart phones, digital cameras, MP3 players, mobile gaming devices, etc.). Summary of the invention

[0003] In one aspect, a semiconductor package structure includes a device package and a first memory package. The device package includes a substrate, a device circuit disposed on and coupled to the substrate, a group of vertical conductive elements disposed on and coupled to the substrate, and a mold layer encapsulating the device circuit and the group of vertical conductive elements. The group of vertical conductive elements is disposed at the periphery of the device circuit. The first memory package is stacked on the mold layer and coupled to the substrate through the group of vertical conductive elements.

[0004] In some embodiments, the semiconductor package structure further includes a second memory package disposed on the substrate side by side with the device package and coupled to the substrate.

[0005] In some embodiments, the device circuit is disposed on the first side of the substrate. The semiconductor package structure further includes a printed circuit board (PCB) disposed on a second side of the substrate opposite to the first side and coupled to the substrate on the second side of the substrate.

[0006] In some embodiments, the semiconductor package structure further includes a second memory package disposed on the PCB side by side with the device package and coupled to the PCB.

[0007] In some embodiments, the device circuit comprises a system on chip (SoC), and the device package comprises an SoC package. The first memory package comprises a volatile memory device. The second memory package comprises a non-volatile memory device and a memory controller.

[0008] In some implementations, the device circuitry includes a SoC, and the device package includes a SoC package. The first memory package is an integrated memory package including a volatile memory device, a nonvolatile memory device, and a memory controller.

[0009] In some embodiments, the set of vertical conductive elements includes one or more conductive elements that are respectively vertically bonded to one or more contacts located on the substrate.

[0010] In some embodiments, the material of the set of vertical conductive elements includes gold.

[0011] In some embodiments, a size of a top surface of a vertical conductive element from the set of vertical conductive elements is equal to a size of a bottom surface of the vertical conductive element.

[0012] In another aspect, a semiconductor package structure includes an interposer structure. The interposer structure includes a first interconnection bridge, a device circuit, a group of conductive elements, and a molding layer. The first interconnection bridge includes: a stack of conductive layers and dielectric layers alternately arranged, and an interconnection structure formed in the stack and penetrating at least a portion of the stack to connect to the conductive layers in the stack. The device circuit is arranged on the first interconnection bridge and coupled to the first interconnection bridge. The group of conductive elements is arranged on the first interconnection bridge and coupled to the first interconnection bridge. The group of conductive elements is arranged at the periphery of the device circuit, and the interconnection structure of the first interconnection bridge is connected to at least one conductive element from the group of conductive elements. The molding layer encapsulates the device circuit and the group of conductive elements.

[0013] In some embodiments, the device circuit is coupled to the interconnect structure through a set of solder balls formed on the first interconnect bridge. Alternatively, the device circuit is coupled to the interconnect structure using hybrid bonding.

[0014] In some embodiments, the set of conductive elements are respectively vertically bonded to a first set of contacts located on the first interconnect bridge.

[0015] In some embodiments, the device circuit and the set of conductive elements are formed on a first side of the first interconnect bridge. The semiconductor package structure also includes a PCB formed on a second side of the first interconnect bridge opposite the first side and coupled to the first interconnect structure of the first interconnect bridge.

[0016] In some embodiments, the interposer structure further includes a second interconnect bridge disposed on the molding layer and coupled to the group of conductive elements. The semiconductor package structure further includes an integrated memory package stacked on the second interconnect bridge of the interposer structure and coupled to the second interconnect bridge of the interposer structure.

[0017] In some implementations, the integrated memory package is coupled to the second interconnect bridge using hybrid bonding.

[0018] In some embodiments, the set of conductive elements are respectively vertically bonded to a second set of contacts located on the second interconnect bridge.

[0019] In some implementations, the device circuit includes a SoC.The integrated memory package includes a volatile memory device, a non-volatile memory device stacked on the volatile memory device, and a memory controller.

[0020] In another aspect, an interposer structure includes a first interconnect bridge, a device circuit, a group of conductive elements, a molding layer, and a second interconnect bridge. The device circuit is disposed on the first interconnect bridge and coupled to the first interconnect bridge. The group of conductive elements is disposed on the first interconnect bridge and coupled to the first interconnect bridge. The group of conductive elements is disposed at the periphery of the device circuit. The molding layer encapsulates the device circuit and the group of conductive elements. The second interconnect bridge is disposed on the molding layer and coupled to the group of conductive elements.

[0021] In some embodiments, the first interconnection bridge includes: a first stack of conductive layers and dielectric layers arranged alternately, and a first interconnection structure, the first interconnection structure is formed in the first stack and penetrates at least a portion of the first stack to connect to the first conductive layer in the first stack. The second interconnection bridge includes: a second stack of conductive layers and dielectric layers arranged alternately, and a second interconnection structure, the second interconnection structure is formed in the second stack and penetrates at least a portion of the second stack to connect to the second conductive layer in the second stack.

[0022] In some embodiments, at least one conductive element from the set of conductive elements is connected to a first interconnect structure of a first interconnect bridge and to a second interconnect structure of a second interconnect bridge. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate aspects of the disclosure and, together with the description, further serve to explain the principles of the disclosure and to enable one skilled in the relevant art to make and use the disclosure.

[0024] Figure 1A Schematic diagrams showing cross-sections of semiconductor package structures according to some examples.

[0025] Figure 1B A schematic diagram illustrating a cross-section of another semiconductor package structure according to some examples.

[0026] Figure 2A A schematic diagram showing a cross-section of a semiconductor package structure according to some aspects of the present disclosure is shown.

[0027] Figure 2B A schematic diagram showing a cross-section of another semiconductor package structure according to some aspects of the present disclosure.

[0028] Figure 2C A schematic diagram showing a cross section of yet another semiconductor package structure according to some aspects of the present disclosure.

[0029] Figure 3 A schematic diagram showing a cross section of yet another semiconductor package structure according to some aspects of the present disclosure.

[0030] Figure 4A A schematic top view of an interconnect bridge according to some aspects of the present disclosure is shown.

[0031] Figure 4B According to some aspects of the present disclosure Figure 4A Schematic diagram of a first cross section of an interconnect bridge in FIG.

[0032] Figure 4C According to some aspects of the present disclosure Figure 4A Schematic diagram of a second cross section of the interconnect bridge.

[0033] Figure 5 is a flow chart of a first method for forming a semiconductor package structure according to some aspects of the present disclosure.

[0034] Figure 6 is a flow chart of a second method for forming a semiconductor package structure according to some aspects of the present disclosure.

[0035] Figure 7 is a flow chart of a third method for forming a semiconductor package structure according to some aspects of the present disclosure.

[0036] Fig. 8A is a flow chart of a first method for forming a device package according to some aspects of the present disclosure.

[0037] Figure 8B-Figure 8E A first manufacturing process for forming a device package according to some aspects of the present disclosure is shown.

[0038] Fig.9A is a flow chart of a second method for forming a device package according to some aspects of the present disclosure.

[0039] Figure 9B-9F A second manufacturing process for forming a device package according to some aspects of the present disclosure is shown.

[0040] Fig.10 is a flow chart of a fourth method for forming a semiconductor package structure according to some aspects of the present disclosure.

[0041] Fig.11A is a flow chart of a method for forming an interposer structure according to some aspects of the present disclosure.

[0042] Figure 11B-Figure 11F A fabrication process for forming an interposer structure according to some aspects of the present disclosure is shown.

[0043] The present disclosure will be described with reference to the accompanying drawings. DETAILED DESCRIPTION

[0044] Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. Therefore, other configurations and arrangements may be used without departing from the scope of the present disclosure. Moreover, the present disclosure may also be used in various other applications. The functions and structural features described in the present disclosure may be combined, adjusted, and modified with each other and in a manner not explicitly depicted in the accompanying drawings, so that these combinations, adjustments, and modifications are within the scope of the present disclosure.

[0045] In general, terms can be understood at least in part from usage in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least in part on the context, terms such as "one" or "the" can also be understood to convey singular usage or to convey plural usage. In addition, also depending at least in part on the context, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, but can allow for the presence of additional factors that are not necessarily explicitly described.

[0046] It should be readily understood that the meanings of “on,” “over,” and “over” in the present disclosure should be interpreted in the broadest manner, so that “on” not only means “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween, and “over” or “over” not only means “over something” or “on something,” but also can include the meaning of “over something” or “on something” with no intervening features or layers therebetween (i.e., directly on something).

[0047] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature to another (or multiple) element or feature as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0048] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself can be patterned. The material added on top of the substrate can be patterned or can remain unpatterned. In addition, the substrate can include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of non-conductive materials, such as glass, plastic, or sapphire wafers.

[0049] As used herein, the term "layer" refers to a material portion including an area with a thickness. A layer may extend over the entire underlying layer or overlying structure, or may have a range less than the range of the underlying layer or overlying structure. In addition, a layer may be an area of ​​a uniform or non-uniform continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top surface and the bottom surface of the continuous structure or between any pair of horizontal planes at the top surface and the bottom surface. A layer may extend horizontally, vertically and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, and / or may have one or more layers thereon, above it and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductors and a contact layer (wherein interconnect lines and / or vertical contacts are formed) and one or more dielectric layers.

[0050] As used herein, the term "nominal / nominally" refers to an expected or target value for a characteristic or parameter set for a component or process operation during the design phase of a product or process, as well as a range of values ​​above and / or below the expected value. The range of values ​​may be due to slight variations in manufacturing processes or tolerances.

[0051] As used herein, the term "vertical / vertically" means nominally perpendicular to a lateral surface of a substrate. As used herein, the x-axis and y-axis may both represent a horizontal direction and may be located in a horizontal plane. The z-axis may represent a vertical direction and may be perpendicular to the horizontal plane. The y-axis is perpendicular to the xz plane.

[0052] Due to the limited motherboard area, the mobile terminal may impose high requirements on its memory device, such as having high performance but with a small area. Heterogeneously integrated memory chips can provide a solution that can well meet the high requirements of mobile terminals, wherein the heterogeneously integrated memory chips can be formed by memory devices with different structures. Currently, there are some heterogeneous integration solutions that can form memory chips with satisfactory high performance and small area. In addition, the cost for forming heterogeneously integrated memory chips is also high.

[0053] In order to solve one or more of the aforementioned problems, the present disclosure introduces a heterogeneous integration solution, which can form a semiconductor package structure with high transmission bandwidth, low transmission delay and small packaging area. For example, the semiconductor package structure disclosed herein includes a device package, a first memory package and a second memory package. The device package and the second memory package can be arranged side by side on the same PCB or the same substrate. The first memory package can be stacked on the device package and connected to the device package. The device package may include a substrate, a device circuit arranged on the substrate and electrically coupled to the substrate, a group of conductive elements arranged on the substrate and electrically bonded to the substrate, and a mold layer encapsulating the device circuit and the group of conductive elements. Because the group of conductive elements can be directly bonded to the substrate, the use of the group of conductive elements can avoid etching holes in the mold layer, and its manufacturing cost can be reduced.

[0054] In another example, the semiconductor package structure disclosed herein may include an interposer structure and an integrated memory package stacked on the interposer structure. The interposer structure may include a first interconnection bridge, a device circuit such as a SoC, and a second interconnection bridge. The device circuit may be disposed on the first interconnection bridge and electrically coupled to the first interconnection bridge, so that the first interconnection bridge may function as a fan-out of the device circuit. By using the first interconnection bridge, the density of the fan-out may be increased. The first interconnection bridge and the second interconnection bridge may be connected to each other by a set of conductive elements to achieve a vertical connection with an increased interconnection density between the first interconnection bridge and the second interconnection bridge. The use of this set of conductive elements may avoid etching holes in the mold layer of the interposer structure, and may reduce its manufacturing cost. The first interconnection bridge and the second interconnection bridge may have a narrower wiring distance, so that the bandwidth of the signal transmission may be increased.

[0055] In some embodiments, the integrated memory package can be a universal flash storage (UFS)-based multi-chip package (e.g., a UFS-based multimedia card) or an embedded multi-chip package (e.g., an embedded multimedia card (eMMC)). The integrated memory package may include a non-volatile (NV) memory device (e.g., a NAND flash memory device) and a volatile memory device (e.g., a DRAM). The volatile memory device can be placed closer to the interposer structure than the non-volatile memory device to ensure that the volatile memory device has a high communication speed with the device circuit. In addition, the second interconnect bridge of the interposer structure can replace the integrated memory package to achieve high-bandwidth signal transmission between the integrated memory package and the device circuit. In addition, the second interconnect bridge of the interposer structure can be bonded to the integrated memory package using hybrid bonding to achieve fast signal transmission.

[0056] Figure 1AA schematic diagram of a cross section of a semiconductor package structure 100 according to some examples is shown. The semiconductor package structure 100 may include a device package 102 and a first memory package 114 stacked on the device package 102 and electrically connected to the device package 102. In some embodiments, the device package 102 may include a substrate 104, a device circuit 106 disposed on the substrate 104, a mold layer 110 encapsulating the device circuit 106, and a plurality of contact structures 108 extending through the mold layer 110 and connected to the substrate 104.

[0057] In some embodiments, substrate 104 can be an organic substrate. Substrate 104 can be a laterally oriented substrate in which two lateral surfaces (e.g., a top surface and a bottom surface) extend laterally in an xy plane. Substrate 104 can include a plurality of contacts 105 (e.g., 105a, 105b) on the top surface and a plurality of contacts 106 on the bottom surface. In some embodiments, substrate 104 includes polysilicon.

[0058] The device circuit 106 may be disposed on the top surface of the substrate 104 and connected to the substrate 104. For example, the device circuit 106 may be electrically coupled to a first set of contacts 105a located on the substrate 104 through a set of solder balls, respectively. In some embodiments, the device circuit 106 may include a SoC or any other suitable circuit structure. For example, the device package 102 may be a SoC package.

[0059] The molding layer 110 may be formed on the substrate 104 to encapsulate and cover the device circuit 106 to protect the device circuit 106 and reduce physical and / or chemical damage (eg, oxidation, damage caused by moisture) to the device circuit 106. The molding layer 110 may include epoxy or any other suitable molding compound.

[0060] The contact structure 108 may extend through the mold layer 110 to connect with the substrate 104. For example, the contact structure 108 may extend through the mold layer 110 so that the bottom surface of the contact structure 108 may be electrically connected to the second set of contacts 105b located on the substrate 104. The second set of contacts 105b may be electrically connected to the first set of contacts 105a so that the contact structure 108 may be electrically connected to the device circuit 106. In some embodiments, an opening may be formed in the mold layer 110 (e.g., by etching the mold layer 110 to form a hole in the mold layer 110). Then, a conductive material (e.g., a metal such as Cu, Tin, etc., or any other suitable conductive material) may be used to fill the opening to form the contact structure 108. In some embodiments, the contact structure 108 may be formed at the periphery of the device circuit 106. In some embodiments, a solder ball may be formed on the top surface of the contact structure 108. Each of the solder balls may serve as a signal input / output terminal. Through the solder balls, signals from the first memory package 114 may be input into the device package 102 , and signals from the device package 102 may be output to the first memory package 114 .

[0061] The first memory package 114 may be stacked on the molding layer 110 and may be electrically coupled to the contact structure 108 of the device package 102 (e.g., by solder balls). The first memory package 114 may then be electrically coupled to the substrate 104 (and the device circuit 106) of the device package 102 through the contact structure 108. The first memory device 114 may include a substrate 116 and a volatile memory device 118 formed on the substrate 116. The volatile memory device 118 may be a DRAM and is electrically connected to the substrate 116. A molding layer 117 may be formed on the substrate 116 to encapsulate and cover the volatile memory device 118.

[0062] In some embodiments, the semiconductor package structure 100 may further include a printed circuit board (PCB) 130 disposed on a side of the substrate 104 opposite to the device package 102. For example, the device package 102 may be disposed on a first side of the substrate 104, and the PCB 130 may be disposed on a second side of the substrate 104 opposite to the first side. The PCB 130 may be coupled to the substrate 104. For example, Figure 1A As shown, the PCB 130 may be electrically coupled to the contacts 106 located on the second side of the substrate 104 through solder balls. The PCB 130 may be connected to an external device (not shown).

[0063] In some embodiments, the semiconductor package structure 100 may further include a second memory package 120 disposed on the PCB 130 side by side with the device package 102. The second memory package 120 may be coupled to the PCB 130. For example, Figure 1A As shown, the second memory package 120 can be electrically coupled to the PCB 130 through solder balls. The second memory package 120 may include a substrate 122, a nonvolatile memory device 124, a memory controller 126, and a mold layer 123 disposed on the substrate 122 and encapsulating the nonvolatile memory device 124 and the memory controller 126. The nonvolatile memory device 124 may be a NAND flash memory device or any other suitable nonvolatile memory device. The memory controller 126 may control the operation of the nonvolatile memory device 124. The nonvolatile memory device 124 and the memory controller 126 may be electrically coupled to the substrate 122.

[0064] Figure 1B FIG. 1 is a schematic diagram showing a cross-section of another semiconductor package structure 150 according to some examples. The semiconductor package structure 150 may include a semiconductor package structure similar to Figure 1A The components of the semiconductor package structure 100 are similar to those of the components of the semiconductor package structure 100 , and similar descriptions will not be repeated herein.

[0065] In some embodiments, the semiconductor package structure 150 may include a device package 152 and an integrated memory package 154 stacked on the device package 152. In some embodiments, the semiconductor package structure 150 may also include a PCB 130 disposed on a first side of the device package 152, and the integrated memory package 154 disposed on a second side of the device package 152 opposite to the first side.

[0066] In some embodiments, the device package 152 may include a substrate 104, a redistribution layer (RDL) 153 disposed on the substrate 104, a device circuit 106 disposed on and connected to the RDL 153, a mold layer 110 disposed on the RDL 153 and encapsulating the device circuit 106, and a contact structure 108 extending through the mold layer 110 and connected to the RDL 153. Figure 1A Compared with the device package 102, Figure 1B The device package 152 in EM further includes an RDL 153 located between the device circuitry 106 and the substrate 104 .

[0067] The RDL 153 may include at least one conductive layer and at least one dielectric layer. The at least one conductive layer may be coupled to one or more of the substrate 104, the device circuit 106, and the contact structure 108 to achieve electrical connection between the substrate 104, the device circuit 106, and the contact structure 108. The at least one conductive layer may include a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium nitride (TiN), polycrystalline silicon (polysilicon), doped silicon, silicide, or any combination thereof. The at least one dielectric layer may include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0068] The contact structure 108 may penetrate the mold layer 110 to connect with the RDL 153. In some embodiments, an opening may be formed in the mold layer 110 by etching. A conductive material may be used to fill the opening to form the contact structure 108 within the mold layer 110.

[0069] Integrated memory package 154 may be stacked on mold layer 110 and may be electrically coupled to contact structure 108 of device package 152 (e.g., via solder balls). Integrated memory package 154 may then be electrically coupled to substrate 104 (and device circuitry 106) of device package 152 via contact structure 108 and RDL 153. Integrated memory device 154 may be Figure 1A 1 and 120. For example, the integrated memory device 154 may include a substrate 156, a volatile memory device 118 disposed on the substrate 156, a nonvolatile memory device 124 disposed on the volatile memory device 118, and a memory controller 126 disposed on the substrate 156. The volatile memory device 118, the nonvolatile memory device 124, and the memory controller 126 may be electrically coupled to the substrate 156. For example, the volatile memory device 118 may have a shorter distance to the substrate 156 than a distance of the nonvolatile memory device 124 to the substrate 156, so that the volatile memory device 118 may have a shorter distance to the device circuit 106 than a distance of the nonvolatile memory device 124 to the device circuit 106, to ensure a high communication speed between the volatile memory device 118 and the device circuit 106. A molding layer 157 may be formed on the substrate 156 to encapsulate and cover the volatile memory device 118, the nonvolatile memory device 124, and the memory controller 126. In some embodiments, the integrated memory package 154 may be a UFS-based multi-chip package or an eMMC.

[0070] like Figure 1A and Figure 1BAs shown, the contact structure 108 can be formed in the mold layer 110 by first etching the mold layer 110 to form a hole and then filling the hole with a conductive material. The manufacturing cost for forming the contact structure 108 is high, but the density of interconnections achieved using the contact structure 108 is low. Consistent with some aspects of the present disclosure, as described below in Figure 2A-2C and Figure 3 The set of vertical conductive elements 202 shown in FIG. 1 can be used to replace the contact structure 108 to achieve a higher density interconnection. As described in more detail below, the formation of the vertical conductive elements 202 is different from the formation of the contact structure 108. For example, in Figure 2A-2B In the embodiment, a set of vertical conductive elements 202 may be formed by vertically depositing one or more conductive structures (eg, conductive wires, conductive pillars, conductive cylinders, etc.) and electrically bonding them to one or more contacts located on the substrate 104. Figure 2C In the embodiment, a set of vertical conductive elements 202 may be formed by vertically arranging one or more conductive structures and electrically bonding them to one or more contacts located on the RDL 153. Figure 3 In the embodiment, a group of vertical conductive elements 202 can be formed by vertically arranging one or more conductive structures and electrically bonding them to one or more contacts located on the first interconnection bridge 302. The group of vertical conductive elements 202 can also be electrically bonded to one or more contacts located on the second interconnection bridge 304. That is, when forming the vertical conductive elements 202, it is not necessary to perform etching on the mold layer 110 to form holes in the mold layer 110, so that the manufacturing cost can be reduced.

[0071] Figure 2A A schematic diagram showing a cross-section of a semiconductor package structure 200 according to some aspects of the present disclosure is shown. The semiconductor package structure 200 may include a semiconductor package structure similar to Figure 1A The components of the semiconductor package structure 100 are similar to those of the components of the semiconductor package structure 100 , and similar descriptions will not be repeated herein.

[0072] In some embodiments, the semiconductor package structure 200 may include a device package 201 and a first memory package 114 stacked on the device package 201 and electrically connected to the device package 201. In some embodiments, the semiconductor package structure 200 may further include a PCB 130 disposed on a side of the device package 201 opposite to the first memory package 114. In some embodiments, the semiconductor package structure 200 may further include a second memory package 120 disposed on the PCB 130 side by side with the device package 201.

[0073] In some embodiments, the device package 201 may include a substrate 104, a device circuit 106 disposed on the substrate 104, a mold layer 110 encapsulating the device circuit 106, and a set of vertical conductive elements 202 extending through the mold layer 110 and connected to the substrate 104. Figure 1A and Figure 2A For comparison, Figure 1A The contact structure 108 is Figure 2A A set of vertical conductive elements 202 in are replaced.

[0074] A group of vertical conductive elements 202 can penetrate the mold layer 110 and can be connected to the substrate 104. For example, a group of vertical conductive elements 202 may include one or more conductive elements that are respectively vertically bonded to a group of contacts 105b (e.g., contact pads) located on the substrate 104. In some embodiments, a group of vertical conductive elements 202 can be formed on the periphery of the device circuit 106. In some embodiments, solder balls can be formed on the top surface of the vertical conductive elements 202. In some embodiments, the material of the group of vertical conductive elements 202 can include gold or any other suitable conductive material. The size of the top surface of each vertical conductive element 202 can be equal to the size of the bottom surface of the vertical conductive element 202. Reference is made to Figure 8B-Figure 8E The formation of a set of vertical conductive elements 202 is described in greater detail.

[0075] Figure 2B FIG. 2 is a schematic diagram showing a cross-section of another semiconductor package structure 210 according to some aspects of the present disclosure. The semiconductor package structure 210 may include a semiconductor package structure similar to Figure 1A The semiconductor package structure 100 or Figure 2A The components of the semiconductor package structure 200 are similar to those of the components of the semiconductor package structure 200, and similar descriptions will not be repeated herein. Figure 2A Compared with the semiconductor package structure 200, Figure 2B The semiconductor package structure 210 in the embodiment may not include the PCB 130. Figure 2B In the embodiment, the device package 201 and the second memory package 212 may be formed on the same substrate 104. The second memory package 212 may be electrically coupled to the device package 201 through the substrate 104.

[0076] Figure 2C A schematic diagram showing a cross-section of another semiconductor package structure 250 according to some aspects of the present disclosure is shown. The semiconductor package structure 250 may include a semiconductor package structure similar to Figure 1B The semiconductor package structure 150 or Figure 1A The components of the semiconductor package structure 200 are described above, and similar descriptions will not be repeated herein.

[0077] In some embodiments, semiconductor package structure 250 may include device package 252 and integrated memory package 154 stacked on and electrically connected to device package 252. Semiconductor package structure 250 may also include PCB 130 disposed on a side of device package 252 opposite to integrated memory package 154.

[0078] In some embodiments, the device package 252 may include a substrate 104, an RDL 153 disposed on the substrate 104, a device circuit 106 disposed on the RDL 153, a molding layer 110 disposed on the RDL 153, and a set of vertical conductive elements 202 extending through the molding layer 110 and connected to the RDL 153. Figure 1B Compared with the device package 152, Figure 1B The contact structure 108 in FIG. 1 is replaced by a set of vertical conductive elements 202 .

[0079] A set of vertical conductive elements 202 may extend through the molding layer 110 and may be connected to a set of contacts located on the RDL 153. For example, the set of vertical conductive elements 202 may include one or more conductive elements vertically bonded to one or more contacts located at the periphery of the RDL 153. The set of vertical conductive elements 202 may be electrically connected to the device circuit 106 through the RDL 153. Figure 9B-9F Forming a set of vertical conductive elements 202 in a semiconductor package structure 250 is described in greater detail.

[0080] Figure 3 A schematic diagram showing a cross-section of another semiconductor package structure 300 according to some aspects of the present disclosure is shown. The semiconductor package structure 300 may include a semiconductor package structure similar to Figure 1B The semiconductor package structure 150 or Figure 2C The components of the semiconductor package structure 250 are described above, and similar descriptions will not be repeated herein.

[0081] In some embodiments, the semiconductor package structure 300 may include an interposer structure 310 and an integrated memory package 320 stacked on and electrically connected to the interposer structure 310. The semiconductor package structure 300 may also include a PCB 130 disposed on a side of the interposer structure 310 opposite to the integrated memory package 320.

[0082] In some embodiments, the interposer structure 310 may include a first interconnection bridge 302, a device circuit 106 disposed on and coupled to the first interconnection bridge 302, a group of conductive elements 301 disposed on and coupled to the first interconnection bridge 302, a mold layer 110 encapsulating the device circuit 106 and the group of conductive elements 301, and a second interconnection bridge 304 disposed on the mold layer 110. The group of conductive elements 301 may include, for example Figure 2A-2C A set of vertical conductive elements 202 is shown in FIG. A set of conductive elements 301 can be disposed on the periphery of the device circuit 106. Figure 2C Compared with the device package 252, Figure 3 The interposer structure 310 in FIG. 1 replaces the substrate 104 and the RDL 153 of the device package 252 with the first interconnect bridge 302 .

[0083] The first interconnect bridge 302 may include a first stack of alternating conductive layers and dielectric layers. The first interconnect bridge 302 may also include at least one first interconnect structure formed in the first stack and passing through at least a portion of the first stack to connect to the first conductive layer in the first stack. Similarly, the second interconnect bridge 304 may include a second stack of alternating conductive layers and dielectric layers. The second interconnect bridge 304 may also include at least one second interconnect structure formed in the second stack and passing through at least a portion of the second stack to connect to the second conductive layer in the second stack. Figure 4A-4C An example of the first interconnection bridge 302 or the second interconnection bridge 304 is illustrated.

[0084] In some embodiments, a group of conductive elements 301 can be respectively vertically bonded to a first group of contacts 303 located on the first interconnection bridge 302. A group of conductive elements 301 can also be respectively vertically bonded to a second group of contacts 305 located on the second interconnection bridge 304. For example, the bottom surface of the conductive element 301 can be bonded to the contact 303 of the first interconnection structure located in the first interconnection bridge 302. The top surface of the conductive element 301 can be bonded to the contact 305 of the second interconnection structure located in the second interconnection bridge 304. The first interconnection bridge 302 and the second interconnection bridge 304 can be coupled to each other through the group of conductive elements 301.

[0085] In some embodiments, the device circuit 106 can be coupled to at least one first interconnect structure of the first interconnect bridge 302 by a set of solder balls formed on the first interconnect bridge 302. Alternatively, the device circuit 106 can be coupled to at least one first interconnect structure of the first interconnect bridge 302 using hybrid bonding. Hybrid bonding is described in more detail below. The device circuit 106 and the set of conductive elements 301 can be formed on a first side of the first interconnect bridge 302, and the PCB 130 can be formed on a second side of the first interconnect bridge 302 opposite to the first side. The PCB 130 can be coupled to one or more first interconnect structures of the first interconnect bridge 302 by solder balls.

[0086] and Figure 2C Unlike the integrated memory device 154 including the substrate 156, Figure 3 The integrated memory device 320 in the embodiment may not include a substrate. For example, after forming the integrated memory device 154, the substrate 156 may be removed from the integrated memory device 154 to form Figure 3 The integrated memory package 320 may include a volatile memory device 118 , a nonvolatile memory device 124 stacked on the volatile memory device 118 , and a memory controller 126 , each of which is connected to the second interconnect bridge 304 .

[0087] and using solder balls to connect the device package 252 to the integrated memory device 154. Figure 2C different, Figure 3 The second interconnect bridge 304 in the interposer structure 310 can be used to connect the interposer structure 310 with the integrated memory device 320. In some embodiments, the integrated memory package 320 can be coupled to the second interconnect bridge 304 using hybrid bonding. Therefore, a hybrid bonding interface 330 can be formed between the integrated memory device 320 and the interposer structure 310.

[0088] In some embodiments, hybrid bonding (also referred to as "metal / dielectric hybrid bonding") is a direct bonding technology (e.g., forming a bond between surfaces without using an intermediate layer such as solder or adhesive) and can simultaneously achieve metal-metal bonding and dielectric-dielectric bonding. Face-to-face hybrid bonding can achieve millions of parallel short interconnections between bonded semiconductor structures to increase the throughput and input / output (I / O) speed of semiconductor packaging structures.

[0089] Specifically, the integrated memory package 320 can be bonded on the top of the interposer structure 310 in a face-to-face manner at the bonding interface 330. For example, the second interconnect bridge 304 may include a first bonding layer located on its top surface. The integrated memory package 320 may also include a second bonding layer at the bonding interface 330. Each of the first bonding layer and the second bonding layer may include a plurality of bonding contacts and a dielectric that electrically isolates the bonding contacts. The bonding contacts may include a conductive material, such as Cu. A dielectric material (e.g., silicon oxide) may be used to form the remaining area of ​​each of the first bonding layer and the second bonding layer. The bonding contacts and the surrounding dielectric in each of the first bonding layer and the second bonding layer may be used for hybrid bonding. In some embodiments, the bonding interface 330 is where the first bonding layer and the second bonding layer meet and bond. In fact, the bonding interface 330 may include a layer with a certain thickness of the top surface of the first bonding layer of the second interconnect bridge 304 and the bottom surface of the second bonding layer of the integrated memory package 320.

[0090] Will Figure 2C and Figure 3 For comparison, Figure 2C The substrate 104 and the RDL 153 may be Figure 3 The first interconnect bridge 302 in is replaced. Figure 2C The substrate 156 and interconnect layers (eg, solder balls) between the integrated memory package 154 and the device package 252 are Figure 3 Therefore, in Figure 3 A high transmission bandwidth can be achieved in the semiconductor package structure 300. Figure 3 In the embodiment of the present invention, the use of the vertical conductive element 202 can avoid etching holes in the mold layer 110 of the interposer structure 310, and can reduce its manufacturing cost. The combined application of (a) the first interconnection bridge 302 and the second interconnection bridge 304, (b) a set of vertical conductive elements 202, and (c) hybrid bonding between the interposer structure 310 and the integrated memory package 320 can achieve signal transmission with ultra-high density and ultra-high bandwidth, so that complex chip stacking and signal routing can be implemented. By stacking the integrated memory device 320 on the interposer structure 310, when the interposer structure 310 is connected to the integrated memory package 320, the integrated memory device 320 can be connected to the interposer structure 310. Figure 2A The semiconductor package structure 200 or Figure 2B Compared with the semiconductor package structure 210 in FIG. 1 , the package area of ​​the semiconductor package structure 300 can be saved.

[0091] Figure 4A A schematic top view of an interconnect bridge 400 is shown, in accordance with some aspects of the present disclosure. Figure 4B According to some aspects of the present disclosure Figure 4A FIG. 4 is a schematic diagram of a first cross section of the interconnect bridge 400 at line AA′. Figure 4C According to some aspects of the present disclosure Figure 4A Schematic diagram of a second cross section of the interconnection bridge 400 located at line BB'. Figure 4A-4C .

[0092] refer to Figure 4B , the interconnection bridge 400 may include a stack of alternating conductive layers 420 (e.g., 420a, 420b, etc.) and dielectric layers 422. The conductive layer 420 may include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium nitride (TiN), polycrystalline silicon (polysilicon), doped silicon, silicide, or any combination thereof. The dielectric layer 422 may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0093] The interconnect bridge 400 may also include a plurality of interconnect structures 426 (e.g., 426a, 426b, 426c, etc.) formed in the stack. The plurality of interconnect structures 426 may extend at different depths or at the same depth in the stack, which is not limited herein. Each interconnect structure 426 may penetrate at least a portion of the stack to connect to the conductive layer 420 in the stack. For example, Figure 4B The interconnect structure 426c in the stack may include a spacer 428, a conductive filler 430, and a contact 402 coupled to the conductive filler 430. A first end of the conductive filler 430 may be coupled to the conductive layer 420a in the stack, and a second end of the conductive filler 430 may be coupled to the contact 402.

[0094] In some embodiments, each interconnect structure 426 may be divided into a top interconnect structure or a bottom interconnect structure. The top interconnect structure may be an interconnect structure whose contacts are formed on the top surface of the interconnect bridge 400. The bottom interconnect structure may be an interconnect structure whose contacts are formed on the bottom surface of the interconnect bridge 400. In some embodiments, the top interconnect structure and the bottom interconnect structure may be formed in different regions of the interconnect bridge 400. For example, the interconnect bridge 400 may be divided into two regions 401 and 403. The top interconnect structure 426 of the interconnect bridge 400 may be formed in the region 403, and the bottom interconnect structure 426 of the interconnect bridge 400 may be formed in the region 401. Figure 4AAs shown, the contacts (e.g., 408, 410, 412, 414, 416) of the top interconnect structure 426 are located on the top surface of the interconnect bridge 400 and are visible in the top view of the interconnect bridge 400 (shown as a solid oval in area 403). The contacts (e.g., 402, 404, 406, 408) of the bottom interconnect structure 426 are located on the bottom surface of the interconnect bridge 400 and are not visible in the top view of the interconnect bridge 400 (shown as a dashed oval in area 401).

[0095] Figure 4A The contacts in the interconnect bridge 400 may be labeled with the numbers 1, 2, and 3. If a first contact located on the top surface of the interconnect bridge 400 is labeled with the same number as a second contact located on the bottom surface of the interconnect bridge 400, this indicates that they are interconnected with each other. For example, the contact 408 of the top interconnect structure 426b and the contact 404 of the bottom interconnect structure 426a are labeled with the same number "2". The top interconnect structure 426b and the bottom interconnect structure 426a may be connected to the same conductive layer 420b. Then, the contact 408 located on the top surface may be interconnected with the contact 404 located on the bottom surface through the top interconnect structure 426b, the conductive layer 420b, and the bottom interconnect structure 426a.

[0096] The interconnect bridge 400 may also include a plurality of isolation trenches 424. The plurality of isolation trenches 424 may extend in the stack at different depths or at the same depth, which is not limited herein. Each isolation trench 424 may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, the isolation trench 424 may have the same dielectric material as the dielectric layer 422. In some other embodiments, the isolation trench 424 may have a dielectric material different from the dielectric material of the dielectric layer 422.

[0097] Figure 5 is a flow chart of a first method 500 for forming a semiconductor package structure according to some aspects of the present disclosure. An example of a semiconductor package structure formed by the method 500 may be Figure 2A The semiconductor package structure 200 in the method 500 is shown. It should be understood that the operations shown in the method 500 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. In addition, some of these operations may be performed simultaneously or in parallel. Figure 5 The different orders shown in .

[0098] refer to Figure 5 , method 500 begins at operation 502, in which a device package may be formed on a first substrate. For example, referring to Figure 2A, the device package 201 may be formed on the substrate 104. Figure 8A-8E An exemplary method of forming a device package at operation 502 is illustrated.

[0099] like Figure 5 As shown, method 500 proceeds to operation 504, in which a first memory package may be formed on a second substrate. Figure 2A , a first memory package 114 may be formed on a substrate 116 .

[0100] like Figure 5 As shown, method 500 proceeds to operation 506, in which the first memory package can be stacked on the device package to form a stacked package structure. Figure 2A , the first memory package 114 may be stacked on and coupled to the device package 201 to form a stacked package structure.

[0101] like Figure 5 As shown, method 500 proceeds to operation 508, in which a second memory package can be formed on a third substrate. Figure 2A , the second memory package 120 may be formed on the substrate 122 .

[0102] like Figure 5 As shown, method 500 proceeds to operation 510, in which the stacked package structure and the second memory package can be arranged side by side on the PCB. Figure 2A , the second memory device 120 and the stacked package structure formed by the device package 201 and the first memory device 114 may be disposed side by side on the PCB 130 .

[0103] Figure 6 is a flow chart of a second method 600 for forming a semiconductor package structure according to some aspects of the present disclosure. An example of a semiconductor package structure formed by the method 600 may be Figure 2B The semiconductor package structure 210 in the method 600 is shown. It should be understood that the operations shown in the method 600 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. In addition, some of these operations may be performed simultaneously or in parallel. Figure 6 The different orders shown in .

[0104] refer to Figure 6 , method 600 begins at operation 602, in which a device package may be formed on a first substrate. For example, referring to Figure 2B , the device package 201 may be formed on the substrate 104. Figure 8A-8EAn exemplary method of forming a device package at operation 602 is illustrated.

[0105] like Figure 6 As shown, method 600 proceeds to operation 604, in which a first memory package can be formed on a second substrate. Figure 2B , a first memory package 114 may be formed on a substrate 116 .

[0106] like Figure 6 As shown, method 600 proceeds to operation 606, in which the first memory package can be stacked on the device package to form a stacked package structure. Figure 2B , the first memory package 114 may be stacked on and coupled to the device package 201 to form a stacked package structure.

[0107] like Figure 6 As shown, method 600 proceeds to operation 608, in which a second memory package can be formed on the first substrate side by side with the stacked package structure. Figure 2B , the second memory package 120 may be formed on the substrate 104 side by side with the stacked package structure formed by the device package 201 and the first memory device 114 .

[0108] Figure 7 is a flowchart of a third method 700 for forming a semiconductor package structure according to some aspects of the present disclosure. An example of a semiconductor package structure formed by the method 700 may be Figure 2C The semiconductor package structure 250 in the method 700 is shown. It should be understood that the operations shown in the method 700 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. In addition, some of these operations may be performed simultaneously or in parallel. Figure 7 The different orders shown in .

[0109] refer to Figure 7 , method 700 begins at operation 702, in which a device package may be formed on a first substrate. For example, referring to Figure 2C , device package 252 may be formed on substrate 104. Figure 9A-9F An exemplary method of forming a device package at operation 702 is illustrated.

[0110] like Figure 7 As shown, method 700 proceeds to operation 704, in which an integrated memory package can be formed on a second substrate. Figure 2C , an integrated memory package 154 may be formed on a substrate 156 .

[0111] like Figure 7 As shown, method 700 proceeds to operation 706, in which the integrated memory package can be stacked on the device package to form a stacked package structure. Figure 2C , the integrated memory package 154 may be stacked on and coupled to the device package 252 to form a stacked package structure.

[0112] like Figure 7 As shown, method 700 proceeds to operation 708, and in operation 718, the stacked package structure can be disposed on a PCB. Figure 2C , a stacked package structure formed by the device package 252 and the integrated memory device 154 may be disposed on the PCB 130 .

[0113] Fig. 8A is a flow chart of a first method 800 for forming a device package according to some aspects of the present disclosure. Figure 8B-Figure 8E A first manufacturing process for forming a device package according to some aspects of the present disclosure is shown. Figure 8A-8E An example of a device package described in may be Figure 2A-2B The device package 201 in will be described together Figure 8A-8E It should be understood that the operations shown in method 800 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. In addition, some of these operations may be performed simultaneously or in parallel. Fig. 8A The different orders shown in .

[0114] refer to Fig. 8A , method 800 begins at operation 802, in which a device circuit may be formed. Fig. 8A As shown, method 800 may proceed to operation 804, in which device circuitry may be disposed on a substrate. Figure 8B , a device circuit 106 (eg, SoC) may be formed. Then, the device circuit 106 may be disposed on the substrate 104. The device circuit 106 may be connected to a first set of contacts 105a located on the substrate 104.

[0115] like Fig. 8A As shown, method 800 may proceed to operation 806, in which a set of vertical conductive elements surrounding the device circuit may be formed on the substrate. Figure 8C A group of conductive structures (eg, conductive wires, conductive pillars, conductive cylinders, etc.) can be vertically disposed on the substrate 104 and bonded to a second group of contacts 105 b located on the substrate 104 to form a group of vertical conductive elements 202 .

[0116] like Fig. 8A As shown, method 800 may proceed to operation 808, where the device circuit and a set of vertical conductive elements may be encapsulated using a molding layer. Fig.8D As shown, a mold layer 110 may be formed to encapsulate the device circuitry 106 and a set of vertical conductive elements 202 .

[0117] like Fig. 8A As shown, method 800 may proceed to operation 810, in which an interconnect layer may be formed on the mold layer. Fig. 8E As shown, a group of solder balls may be formed above the molding layer 110. The group of solder balls may be connected to a group of vertical conductive elements 202, respectively.

[0118] Fig.9A is a flow chart of a second method 900 for forming a device package according to some aspects of the present disclosure. Figure 9B-9F A second manufacturing process for forming a device package according to some aspects of the present disclosure is shown. Figure 9A-9F An example of a device package described in may be Figure 2C The device package 252 in will be described together Figure 9A-9F It should be understood that the operations shown in method 900 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. In addition, some of these operations may be performed simultaneously or in parallel. Fig.9A The different orders shown in .

[0119] refer to Fig.9A , method 900 begins at operation 902, in which a device circuit may be formed. Fig.9A As shown, method 900 may proceed to operation 903, in which a redistribution layer may be formed on the substrate. Fig.9A As shown, method 900 may proceed to operation 904 where device circuitry may be disposed on the redistribution layer.

[0120] For example, a device circuit 106 (eg, a SoC) may be formed. Fig. 9B , RDL 153 may be formed on substrate 104. Fig. 9C , the device circuit 106 may be disposed on the RDL 153 . The device circuit 106 may be electrically connected to the RDL 153 .

[0121] like Fig.9A As shown, method 900 may proceed to operation 906, where a set of vertical conductive elements surrounding the device circuit may be formed on the redistribution layer. Fig.9DA set of conductive structures may be respectively disposed vertically on the RDL 153 and bonded to a set of contacts located on the RDL 153 to form a set of vertical conductive elements 202 .

[0122] like Fig.9A As shown, method 900 may proceed to operation 908, where the device circuit and a set of vertical conductive elements may be encapsulated using a molding layer. Fig.9E As shown, a mold layer 110 may be formed to encapsulate the device circuitry 106 and a set of vertical conductive elements 202 .

[0123] like Fig.9A As shown, method 900 may proceed to operation 910, in which an interconnect layer may be formed on the mold layer. Fig.9F As shown, a group of solder balls may be formed above the molding layer 110. The group of solder balls may be connected to a group of vertical conductive elements 202, respectively.

[0124] Fig.10 is a flowchart of a fourth method 1000 for forming a semiconductor package structure according to some aspects of the present disclosure. An example of a semiconductor package structure formed by the method 1000 may be Figure 3 The semiconductor package structure 300 in the method 1000 is shown. It should be understood that the operations shown in the method 1000 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. In addition, some of these operations may be performed simultaneously or in parallel. Fig.10 The different orders shown in .

[0125] refer to Fig.10 , method 1000 begins at operation 1002, in which an interposer structure may be formed. For example, referring to Figure 3 , an interposer structure 310 may be formed. Figures 11A-11F An exemplary method of forming the interposer structure 310 is described.

[0126] like Fig.10 As shown, method 1000 proceeds to operation 1004, in which an integrated memory package can be formed. Figure 3 , an integrated memory package 320 may be formed.

[0127] like Fig.10 As shown, method 1000 proceeds to operation 1006, in which the integrated memory package can be stacked on the interposer structure using hybrid bonding to form a stacked package structure. Figure 3, the integrated memory package 320 may be stacked on and coupled to the interposer structure 310 using hybrid bonding to form a stacked package structure.

[0128] like Fig.10 As shown, method 1000 proceeds to operation 1008, in which the stacked package structure can be disposed on a PCB. Figure 3 , a stacked package structure formed of the interposer structure 310 and the integrated memory device 320 may be disposed on the PCB 130 and connected to the PCB 130 through solder balls.

[0129] Fig.11A is a flow chart of a method 1100 of forming an interposer structure according to some aspects of the present disclosure. Figure 11B-Figure 11F A fabrication process for forming an interposer structure according to some aspects of the present disclosure is shown. Figures 11A-11F An example of the interposer structure described in the example may be Figure 3 The intermediate layer structure 310 in FIG. Figures 11A-11F It should be understood that the operations shown in method 1100 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. In addition, some of these operations may be performed simultaneously or in parallel. Fig.11A The different orders shown in .

[0130] refer to Fig.11A , method 1100 begins at operation 1102, in which a device circuit may be formed. Fig.11A As shown, method 1100 may proceed to operation 1104, in which a first interconnect bridge may be formed. Fig.11A As shown, the method 1100 may proceed to operation 1106, in which a device circuit may be disposed on the first interconnect bridge. For example, the device circuit 106 (eg, a SoC) may be formed. Fig. 11B , a first interconnection bridge 302 may be formed. Fig. 11C , the device circuit 106 may be disposed on the first interconnection bridge 302. The device circuit 106 may be electrically connected to the first interconnection bridge 302.

[0131] like Fig.11A As shown, method 1100 may proceed to operation 1108, in which a set of vertical conductive elements surrounding the device circuit may be formed on the first interconnect bridge. Fig.11D A group of conductive structures may be respectively vertically disposed on the first interconnection bridge 302 and electrically bonded to a group of contacts located on the first interconnection bridge 302 to form a group of vertical conductive elements 202 .

[0132] like Fig.11A As shown, method 1100 may proceed to operation 1110, where the device circuit and a set of vertical conductive elements may be encapsulated using a molding layer. Fig.11E As shown, a mold layer 110 may be formed to encapsulate the device circuitry 106 and a set of vertical conductive elements 202 .

[0133] like Fig.11A As shown, method 1100 may proceed to operation 1112, in which a second interconnect bridge may be formed on the molding layer. Fig.11F As shown, the second interconnection bridge 304 may be formed on the molding layer 110. A set of vertical conductive elements 202 may be electrically bonded to a set of contacts located on the second interconnection bridge 304, respectively.

[0134] The above description of specific embodiments can be easily modified and / or adjusted for various applications. Therefore, based on the teaching and guidance given herein, such adjustments and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments.

[0135] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A semiconductor packaging structure, comprising: A device package, the device package comprising: substrate; device circuitry disposed on and coupled to the substrate; a set of vertical conductive elements disposed on and coupled to the substrate, wherein the set of vertical conductive elements are disposed at a periphery of the device circuit; and a molding layer encapsulating the device circuitry and the set of vertical conductive elements; and A first memory package is stacked on the molding layer and coupled to the substrate through the set of vertical conductive elements.

2. The semiconductor package structure according to claim 1, further comprising: A second memory package is disposed on the substrate side-by-side with the device package and coupled to the substrate.

3. The semiconductor package structure according to claim 1, wherein: The device circuit is disposed on a first side of the substrate; and The semiconductor packaging structure further includes: A printed circuit board (PCB) is disposed on a second side of the substrate opposite the first side and coupled to the substrate on the second side of the substrate.

4. The semiconductor package structure according to claim 3, further comprising: A second memory package is disposed on the PCB side-by-side with the device package and coupled to the PCB.

5. The semiconductor package structure according to claim 4, wherein: The device circuitry comprises a system on a chip (SoC), and the device package comprises a SoC package; The first memory package includes a volatile memory device; and The second memory package includes a non-volatile memory device and a memory controller.

6. The semiconductor package structure according to claim 3, wherein: The device circuitry comprises a system on a chip (SoC), and the device package comprises a SoC package; and The first memory package is an integrated memory package that includes a volatile memory device, a non-volatile memory device, and a memory controller.

7. The semiconductor package structure according to claim 1, wherein: The set of vertical conductive elements includes one or more conductive elements, each of which is vertically bonded to one or more contacts located on the substrate.

8. The semiconductor package structure according to claim 1, wherein: The material of the set of vertical conductive elements includes gold.

9. The semiconductor package structure according to claim 1, wherein: A size of a top surface of a vertical conductive element from the set of vertical conductive elements is equal to a size of a bottom surface of the vertical conductive element.

10. A semiconductor packaging structure, comprising: An interposer structure, the interposer structure comprising: A first interconnection bridge, the first interconnection bridge comprising: A stack of alternating conductive and dielectric layers; and an interconnect structure formed in the stack and penetrating at least a portion of the stack to connect to a conductive layer in the stack; a device circuit disposed on the first interconnection bridge and coupled to the first interconnection bridge; a set of conductive elements disposed on and coupled to the first interconnect bridge, wherein the group of conductive elements is disposed at the periphery of the device circuit, and the interconnect structure of the first interconnect bridge is connected to at least one conductive element from the group of conductive elements; and A molding layer encapsulates the device circuit and the set of conductive elements.

11. The semiconductor package structure according to claim 10, wherein: The device circuit is coupled to the interconnect structure via a set of solder balls formed on the first interconnect bridge; or The device circuitry is coupled to the interconnect structure using hybrid bonding.

12. The semiconductor package structure according to claim 10, wherein: The set of conductive elements are respectively vertically bonded to a first set of contacts located on the first interconnect bridge.

13. The semiconductor package structure according to claim 10, wherein: The device circuitry and the set of conductive elements are formed on a first side of the first interconnect bridge; and The semiconductor package structure further includes a printed circuit board formed on a second side of the first interconnection bridge opposite to the first side and coupled to the first interconnection structure of the first interconnection bridge.

14. The semiconductor package structure according to claim 10, wherein: The interposer structure further includes a second interconnect bridge disposed on the molding layer and coupled to the set of conductive elements; and The semiconductor package structure also includes an integrated memory package stacked on the second interconnect bridge of the interposer structure and coupled to the second interconnect bridge of the interposer structure.

15. The semiconductor package structure according to claim 14, wherein: The integrated memory package is coupled to the second interconnect bridge using hybrid bonding.

16. The semiconductor package structure according to claim 14, wherein: The set of conductive elements are respectively vertically bonded to a second set of contacts located on the second interconnect bridge.

17. The semiconductor package structure according to claim 14, wherein: The device circuitry comprises a system on a chip (SoC); and The integrated memory package includes a volatile memory device, a nonvolatile memory device stacked on the volatile memory device, and a memory controller.

18. An interposer structure, comprising: First Interconnection Bridge; a device circuit disposed on the first interconnection bridge and coupled to the first interconnection bridge; a set of conductive elements disposed on and coupled to the first interconnect bridge, wherein the set of conductive elements is disposed at a periphery of the device circuit; a molding layer encapsulating the device circuitry and the set of conductive elements; and A second interconnect bridge is disposed on the molding layer and coupled to the set of conductive elements.

19. The interposer structure of claim 18, wherein: The first interconnection bridge comprises: a first stack of alternating conductive layers and dielectric layers; and a first interconnect structure formed in the first stack and penetrating at least a portion of the first stack to be connected to a first conductive layer in the first stack; and The second interconnection bridge comprises: a second stack of alternating conductive and dielectric layers; and A second interconnect structure is formed in the second stack and penetrates at least a portion of the second stack to be connected to a second conductive layer in the second stack.

20. The interposer structure according to claim 19, wherein: At least one conductive element from the set of conductive elements is connected to the first interconnect structure of the first interconnect bridge and to the second interconnect structure of the second interconnect bridge.

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