Packaging substrate and preparation method thereof, chip packaging structure and electronic equipment

Abstract

The invention provides a packaging substrate and a preparation method thereof, a chip packaging structure and electronic equipment, relates to the technical field of semiconductor packaging, and aims to solve the problem that the preparation process of the packaging substrate is complicated. The packaging substrate comprises a stacking structure, a plurality of conductive parts and a plurality of separation grooves. The stacked structure comprises a plurality of first material layers and a plurality of second material layers which are alternately stacked, the first material layers are made of insulating materials, and the second material layers are made of conductive materials. The conductive part extends from the upper surface of the stacked structure to a second material layer, and an insulating part is arranged between the side wall of the conductive part and the stacked structure. The isolation groove is located between two adjacent conductive parts extending to the same second material layer, and the isolation groove extends from the upper surface of the stacked structure to the lower surface of one second material layer.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor packaging technology, and in particular to a packaging substrate and a preparation method thereof, a chip packaging structure, and an electronic device. Background Art

[0002] In traditional packaging technology, interconnection and communication between chips are generally achieved through packaging substrate wiring. However, the traditional packaging substrate preparation process is complicated. Summary of the invention

[0003] The embodiments of the present disclosure provide a packaging substrate and a preparation method thereof, a chip packaging structure, and an electronic device, aiming to solve the problem of complex packaging substrate preparation process.

[0004] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0005] On the one hand, a packaging substrate is provided. The packaging substrate includes a stacking structure, a plurality of conductive parts and a plurality of partition grooves. The stacking structure includes a plurality of first material layers and a plurality of second material layers alternately stacked, wherein the first material layers are insulating materials and the second material layers are conductive materials. The conductive part extends from the upper surface of the stacking structure to a second material layer, and an insulating part is provided between the side wall of the conductive part and the stacking structure. The partition groove is located between two adjacent conductive parts extending to the same second material layer, and the partition groove extends from the upper surface of the stacking structure to the lower surface of a second material layer.

[0006] In the package substrate provided by the above embodiment of the present disclosure, the partition grooves separate the second material layer into a plurality of parts, each of which can be used as a part of the patterned wiring, and the patterned wiring in the package substrate is realized through the partition grooves, so that the separated second material layers form a patterned wiring layer. The partition grooves can be formed at the same time, and then multiple layers of patterned wiring layers can be formed at the same time, thereby simplifying the preparation process of the package substrate 100.

[0007] In some embodiments, the packaging substrate further includes a plurality of spacers, and the spacers are located in the partition grooves.

[0008] In some embodiments, the first material layer, the spacer, and the insulating portion are made of the same material.

[0009] In some embodiments, a dimension of the conductive portion in the first direction is greater than a dimension of the partition groove in the first direction, and the first direction is parallel to a plane where the stacking structure is located.

[0010] In some embodiments, an upper surface of the conductive portion is flush with an upper surface of the stacked structure.

[0011] In some embodiments, the thickness of the first material layer is greater than the thickness of the second material layer.

[0012] In another aspect, a chip packaging structure is provided, which comprises a packaging substrate as described in any of the above embodiments and a plurality of chips, wherein the chip is connected to a conductive portion of the packaging substrate.

[0013] In some embodiments, the chip packaging structure further includes an adhesive layer. The adhesive layer is disposed between at least one chip and the packaging substrate. At least one chip is connected to the conductive portion of the packaging substrate via a lead.

[0014] In some embodiments, at least one chip is soldered to a conductive portion of the package substrate.

[0015] In some embodiments, at least one chip is bonded to a conductive portion of the package substrate.

[0016] In another aspect, an electronic device is provided, wherein the electronic device comprises the chip packaging structure as described in any one of the above embodiments.

[0017] On the other hand, a method for preparing a package substrate is provided. The method for preparing a package substrate includes providing a carrier; forming a stacking structure on the carrier, the stacking structure including a plurality of first material layers and a plurality of second material layers alternately stacked. The first material layer is an insulating material, and the second material layer is a conductive material; forming a plurality of partitions in the stacking structure, the partitions extending from the upper surface of the stacking structure to the lower surface of a second material layer; forming a plurality of conductive parts, the conductive parts extending from the upper surface of the stacking structure to a second material layer, two adjacent conductive parts extending to the same second material layer are separated by the partitions, and an insulating part is provided between the sidewall of the conductive part and the stacking structure; removing the carrier.

[0018] In some embodiments, the method for preparing a packaging substrate further includes: forming a spacer in the plurality of grooves.

[0019] In some embodiments, forming multiple conductive parts includes: forming multiple first holes, the first holes extending from the upper surface of the stacked structure to the second material layer and exposing the second material layer or a portion of the first material layer adjacent to the lower surface of the second material layer; depositing a third material on the sidewalls of the first holes to form an insulating part; and depositing a conductive material in the first holes to form a conductive part.

[0020] In some embodiments, a plurality of first holes are formed while a plurality of partitions are formed. The partitions penetrate from the upper surface of the stacked structure to the lower surface of a second material layer, and the partitions are located between two adjacent first holes extending to the same second material layer.

[0021] In some embodiments, the method for preparing the packaging substrate further includes: when forming a spacer in a plurality of grooves, depositing a third material on sidewalls of a plurality of first holes while depositing a third material in the plurality of grooves to form the spacer.

[0022] In some embodiments, the third material is the same as the material of the first material layer.

[0023] It can be understood that the beneficial effects that can be achieved by the chip packaging structure, electronic device and packaging substrate preparation method provided by the above embodiments of the present disclosure can refer to the beneficial effects of the packaging substrate mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0025] Figure 1 A flow chart of a method for preparing a packaging substrate provided for related technology;

[0026] Figure 2 A structural diagram of a packaging substrate provided for some embodiments of the present disclosure;

[0027] Figure 3 for Figure 2 a sectional view taken along section line A1-A2;

[0028] Figure 4 is a structural diagram of another packaging substrate provided according to some embodiments;

[0029] Figure 5 is a structural diagram of another packaging substrate provided according to some embodiments;

[0030] Figure 6 A flow chart of a method for preparing a packaging substrate provided in an embodiment of the present disclosure;

[0031] Figure 7 to Figure 14 is a structural diagram corresponding to each step in a method for preparing a packaging substrate according to some embodiments;

[0032] Fig.15 A structural diagram of forming a plurality of partition grooves and a plurality of first holes in another method for preparing a packaging substrate according to some embodiments;

[0033] Fig.16 is another structural diagram of forming a spacer in a method for preparing a package substrate according to some embodiments;

[0034] Fig.17 A structural diagram of a chip packaging structure provided according to some embodiments;

[0035] Fig.18 A structural diagram of another chip packaging structure provided according to some embodiments;

[0036] Fig.19 A structural diagram of another chip packaging structure provided according to some embodiments;

[0037] Fig. 20 A block diagram of a storage system according to some embodiments is provided. DETAILED DESCRIPTION

[0038] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0039] In the description of the present disclosure, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0040] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0041] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0042] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0043] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0044] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0045] The use of "adapted to" or "configured to" herein is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0046] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0047] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of variation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0048] In the context of the present disclosure, the meanings of “on,” “over,” and “over” should be interpreted in the broadest manner, so that “on” means not only “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween, and “over” or “above” means not only “above” or “over” something, but also includes the meaning of “above” or “over” something without intervening features or layers therebetween (i.e., directly on something).

[0049] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0050] As used herein, the term "substrate" refers to a material on which subsequent material layers may be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0051] Figure 1 A flow chart of a method for preparing a packaging substrate provided for related technology.

[0052] In the related art, see Figure 1 In the preparation method of the packaging substrate, a first dielectric layer is first formed, a first through hole connected to the chip is formed in the first dielectric layer, the first through hole is metallized and conductively filled, a first rewiring layer is formed on the upper surface of the first dielectric layer, the first dielectric layer and the first rewiring layer are laminated to form a first connection layer; then a second dielectric layer is formed, a second through hole connected to the chip is formed in the second dielectric layer, the second through hole is metallized and conductively filled, a second rewiring layer is formed on the upper surface of the second dielectric layer, the second dielectric layer and the second rewiring layer are laminated to form a second connection layer; the above steps are repeated to form a stacked multi-layer connection layer, solder resist material is deposited on the upper surface of the stacked multi-layer connection layer to form a pad connected to the chip, and then a packaging substrate is formed. In this process, each connection layer is formed separately, and multiple etching processes, multiple thin film depositions and metal filling processes are required in the process of forming a connection layer, and the preparation process is complicated.

[0053] In order to solve the above technical problems, some embodiments of the present disclosure provide a packaging substrate.

[0054] Figure 2 A structural diagram of a packaging substrate provided for some embodiments of the present disclosure. Figure 3 for Figure 2 A sectional view taken along the section line A1-A2. For the convenience of the following description, see Figure 3, the first direction X represents a direction parallel to the plane where the packaging substrate is located, and the second direction Y represents a direction perpendicular to the plane where the packaging substrate is located.

[0055] See also Figure 2 and Figure 3 The package substrate 100 includes a stacked structure 10 , a plurality of conductive portions 20 and a plurality of partition grooves 30 .

[0056] The stacking structure 10 includes a first material layer 11 and a second material layer 12 that are alternately stacked. Alternating stacking means that in the thickness direction of the packaging substrate 100, a plurality of first material layers 11 and a plurality of second material layers 12 are stacked, and the arrangement is arranged in an alternating manner; for example, in the direction from the bottom layer to the top layer of the stacking structure 10, a first material layer 11 is first arranged, and then a second material layer 12 is arranged on the first material layer 11, and then another first material layer 11 is arranged on the second material layer 12, and so on, and the stacking structure 10 is formed in an alternating cycle.

[0057] The bottom and top layers of the stacked structure 10 are the first material layer 11, which separates the second material layer 12 from moisture and oxygen in the outside world (e.g., outside the packaging substrate 100), thereby preventing the second material layer 12 from being exposed over a large area and being corroded and damaged by moisture and oxygen.

[0058] It should be noted that Figure 3 The number of the first material layer 11 and the second material layer 12 is only for illustration, and the embodiments of the present disclosure do not limit the number of the first material layer 11 and the second material layer 12 .

[0059] The first material layer 11 is an insulating material, and the insulating material includes, for example, one or more combinations of silicon oxide, silicon nitride, silicon oxynitride, and high dielectric constant insulating materials, or other suitable materials. The second material layer 12 is a conductive material, and the conductive material may include at least one of gold (Au), silver (Ag), aluminum (Al), copper (Cu), zinc (Zn), tin (Sn), lead (Pb), antimony (Sb), bismuth (Bi), lithium (Li), gallium (Ga), and cadmium (Cd), or an alloy containing two or more metal elements.

[0060] The conductive part 20 is used to connect with the chip. The conductive part 20 is connected to a second material layer 12. Specifically, the conductive part 20 extends from the upper surface of the stacked structure 10 to a second material layer 12. The bottom of the conductive part 20 extends to the upper surface of the corresponding second material layer 12, or extends into the corresponding second material layer 12, and the conductive part 20 penetrates all material layers of the corresponding second material layer 12 close to the upper surface of the stacked structure 10.

[0061] Each of the multiple second material layers 12 can be electrically connected to the chip through at least one conductive part 20. For example, the i-th conductive part 20 extends and stops at the layer where the i-th second material layer 12 is located, and is connected to the i-th second material layer 12; i∈[1,2,…,N], N represents the total number of layers of the second material layer 12. It can be understood that the heights of the multiple conductive parts 20 are different. In this way, the conductive parts 20 of different heights can be electrically connected to the second material layers 12 of different layers. The conductive part 20 is a conductive material, and the conductive material can refer to the description above, which will not be repeated here.

[0062] In order to prevent the conductive part 20 from contacting the second material layer 12 of other non-corresponding layers, an insulating part 40 is provided on the side wall of the conductive part 20, and the insulating part 40 is located between the stacked structure 10 and the conductive part 20. Specifically, the insulating part 40 extends from the upper surface of the stacked structure 10 to the second material layer 12 connected to the conductive part 20. The insulating part 40 penetrates all material layers of the second material layer 12 close to the upper surface of the stacked structure 10. Specifically, the insulating part 40 can extend to the upper surface of the second material layer 12, or extend into the second material layer 12, without penetrating the second material layer 12. The material of the insulating part 40 is a third material, and the third material includes, for example, one or more combinations of silicon oxide, silicon nitride, and high dielectric constant insulating materials, or other suitable materials. In some implementations, the third material can be the same as the material of the first material layer 11.

[0063] The packaging substrate 100 further includes a plurality of partitions 30. The partitions 30 extend from the upper surface of the stacked structure 10 to the lower surface of a second material layer 12, exposing a portion of the first material layer 11 located below the second material layer 12. The partitions 30 penetrate the second material layer 12 and all material layers of the second material layer 12 close to the upper surface of the stacked structure 10. The plurality of partitions 30 separate a whole layer of the second material layer 12 into a plurality of wiring patterns, that is, the wiring patterns are separated by the partitions 30, and the wiring patterns are not connected to each other. At this time, the second material layer 12 serves as a rewiring layer.

[0064] The partition groove 30 is located between two adjacent conductive parts 20 extending to the same second material layer 12, that is, the two adjacent conductive parts 20 extending to the same second material layer 12 are separated, and the number of the partition grooves 30 between the two adjacent conductive parts 20 is at least one, for example, one, or more, to prevent the two adjacent conductive parts 20 from being short-circuited after being connected to the chip.

[0065] The extension depth of the partition 30 is related to the shape of the wiring pattern of each second material layer 12. The extension depth refers to the distance from the plane where the opening of the partition 30 is located to the bottom of the partition 30. For a second material layer 12, in order to form a wiring pattern, the partition 30 at least extends to the interval of the wiring pattern to be formed in the second material layer 12. The extension depth of the partition 30 is controlled by the etching time. The longer the etching time, the deeper the extension depth of the partition 30.

[0066] When preparing the packaging substrate of this embodiment, partition grooves and conductive parts 20 are formed in the stacking structure in which the first material layer and the second material layer are alternately stacked, and each second material layer 12 is formed into a redistribution layer by using the partition grooves 30. The second material layer 12 is connected to the chip through the conductive part 20, thereby reducing the number of etching processes, thin film deposition processes and metal filling processes, simplifying the preparation process, and improving the efficiency of packaging substrate preparation.

[0067] Figure 4 The present invention is a structural diagram of another packaging substrate provided according to some embodiments.

[0068] In some embodiments, see Figure 4 , the packaging substrate 100 also includes a plurality of spacers 50. The spacers 50 are located in the partitions 30, that is, the spacers 50 extend from the upper surface of the stacking structure 10 to the lower surface of a second material layer 12. Specifically, the spacers 50 penetrate the second material layer 12 and all material layers of the second material layer 12 close to the upper surface of the stacking structure 10. The spacers 50 are located between two adjacent conductive parts 20 extending to the same second material layer 12. The number of spacers 50 between the two adjacent conductive parts 20 is at least one, for example, one, or more than one. The number of spacers 50 may be the same as the number of partitions 30, or may be less than the number of partitions 30. The material of the spacers 50 may be an insulating material, and the insulating material may refer to the description above, which will not be repeated here. The spacer 50 is filled in the partition groove 30 to prevent foreign matter (such as water vapor or metal) from falling into the partition groove 30, causing the different layers of the second material layer 12 exposed from the side wall of the partition groove 30 and the wiring patterns of the same second material layer 12 to be connected to each other, resulting in a short circuit and causing signal transmission disorder.

[0069] In some embodiments, see Figure 4 , a dimension D1 of the conductive portion 20 in the first direction X is greater than a dimension D2 of the partition groove 30 in the first direction.

[0070] If the dimension D2 of the partition 30 in the first direction is too large, the size of the package substrate 100 will be increased, which is not conducive to the miniaturization of the chip package structure. When the partition 50 is formed in the partition 30, the dimension D2 of the partition 30 in the first direction is smaller than the dimension D1 of the conductive part 20 in the first direction X, and the width required to be filled is smaller, which improves the reliability of filling the partition 50. The dimension D1 of the conductive part 20 in the first direction X is larger, which can increase the area of ​​the conductive part 20 on the upper surface of the stacked structure 10, that is, increase the connection area between the chip and the conductive part 20, improve the connection strength between the chip and the package substrate 100, and improve the product yield.

[0071] In some embodiments, see Figure 4 , the thickness D3 of the first material layer 11 is greater than the thickness D4 of the second material layer 12. The material of the first material layer 11 is an insulating material, which can prevent signal crosstalk. The thicker the first material layer 11 is, the farther the spacing between different layers of second material layers 12 in the second direction Y is. The signal can only be transmitted to a specific second material layer 12 through the conductive part 20, and will not be transmitted to other second material layers 12 through the first material layer 11, thereby reducing the influence of signal crosstalk.

[0072] In some embodiments, see Figure 4 The upper surface of the conductive part 20 is flush with the upper surface of the stacking structure 10, that is, the distance from the upper surface of the conductive part 20 to the lower surface of the stacking structure 10 is roughly equal to the distance from the upper surface to the lower surface of the stacking structure 10. In this way, the upper surface of the packaging substrate 100 is roughly a plane, which facilitates the connection between the chip and the packaging substrate 100 and improves the stability of the chip connection.

[0073] Figure 5 The present invention is a structural diagram of another packaging substrate provided according to some embodiments.

[0074] In some embodiments, see Figure 5 , the spacer 50 and the insulating portion 40 are made of the same material. Exemplarily, the spacer 50 and the insulating portion 40 are made of a third material, such as silicon oxide. Since the spacer 50 and the insulating portion 40 are made of the same material, the spacer 50 and the insulating portion 40 can be formed at the same time, reducing the number of manufacturing steps and improving the manufacturing efficiency of the package substrate 100.

[0075] In some embodiments, see Figure 5 The first material layer 11 , the spacer 50 and the insulating portion 40 are made of the same material, for example, silicon nitride.

[0076] In the embodiment of the present disclosure, the materials of the first material layer 11, the spacer portion 50 and the insulating portion 40 are the same. At this time, the packaging substrate 100 includes two materials, the material of the first material layer 11 and the material of the second material layer 12. The formed packaging substrate 100 has a simple structure, and the number of times the deposited material is replaced during the production process is small, which further improves the production efficiency of the packaging substrate 100.

[0077] The disclosed embodiment also provides a method for preparing a packaging substrate.

[0078] Figure 6 A flow chart of a method for preparing a packaging substrate provided in an embodiment of the present disclosure. Figure 7 to Figure 14 1 is a structural diagram corresponding to each step in a method for preparing a packaging substrate according to some embodiments.

[0079] The following is a schematic illustration of a method for manufacturing a packaging substrate provided by an embodiment of the present disclosure with reference to the accompanying drawings.

[0080] See also Figure 6 , and combined with Figure 7 to Figure 14 The manufacturing method of the above-mentioned packaging substrate includes: S1~S5.

[0081] S1. Provide slide 1.

[0082] Figure 7 A structural diagram of a carrier is provided in a method for preparing a packaging substrate according to some embodiments.

[0083] See also Figure 7 The carrier 1 plays a supporting role in the formation process of the package substrate 100. The carrier 1 may include, for example, a composite structure, and its material may include a combination of silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), and any other suitable materials. Of course, in some embodiments, the carrier 1 may also include a single-layer structure, which is not limited in the embodiments of the present disclosure.

[0084] S2. Forming a stacking structure 10.

[0085] Figure 8 FIG. 1 is a structural diagram of forming a stacked structure 10 in a method for preparing a package substrate according to some embodiments.

[0086] See also Figure 8 , a stacking structure 10 is formed on the carrier. The stacking structure 10 includes a plurality of first material layers 11 and a plurality of second material layers 12 alternately stacked. The structures and materials of the first material layers 11 and the second material layers 12 are described above and will not be repeated here.

[0087] In some examples, an etch stop layer may be provided on one side of the carrier 1 where the stack structure 10 is provided. In other examples, an adhesive layer may be provided on one side of the carrier 1 where the stack structure 10 is provided, and the etch stop layer or adhesive layer is used to protect the stack structure 10 from being damaged when the carrier 1 is subsequently removed.

[0088] S3. Form a plurality of partition grooves 30.

[0089] Fig. 9 FIG. 1 is a structural diagram of forming a plurality of partition grooves 30 in a method for preparing a package substrate according to some embodiments.

[0090] See also Fig. 9 , an etching process (such as a dry etching process or a wet etching process) can be used to form a plurality of partitions 30 in the stacked structure 10. By controlling the etching time, the partitions 30 with the same extension depth are formed. The structure of the partitions 30 is described above and will not be repeated here.

[0091] S4. Form a plurality of conductive parts 20.

[0092] Figure 10 to Figure 12 FIG. 1 is a diagram showing steps of forming a plurality of conductive portions in a method for preparing a package substrate according to some embodiments.

[0093] See also Figure 10 to Figure 12 , a first hole H1 is formed in the stacked structure 10, and the first hole H1 extends from the upper surface of the stacked structure 10 to a second material layer 12. A thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD) or atomic layer deposition (ALD) can be used to deposit a conductive material in the first hole H1 to form a conductive portion 20. The structure and material of the conductive portion 20 are described above and will not be repeated here.

[0094] In this embodiment, a plurality of first holes (eg, all first holes) H1 may be formed first, and then corresponding conductive portions 20 may be formed in the first holes H1 simultaneously, which can simplify the manufacturing process.

[0095] In the above process, the sidewall of the first hole H1 can be surrounded by the third material, so that the third material can protect the second material layers 12 at a higher level than the second material layer 12 at the bottom of the first hole H1 to prevent these second material layers 12 from being connected to each other and causing a short circuit.

[0096] In some embodiments, forming the plurality of conductive parts 20 may include the following steps:

[0097] S41 , forming a plurality of first holes H1 .

[0098] See also Fig.10 , an etching process is used to form a first hole H1 on the side of the stacked structure 10 away from the carrier 1. Specifically, a mask layer can be formed on the plurality of partitions 30 to expose the position where the first hole H1 is formed, and then the mask layer is used as a mask (i.e., a shield) to remove a portion of the stacked structure 10 to form the first hole H1.

[0099] The first hole H1 extends from the upper surface of the stacked structure 10 to the second material layer 12 to expose the second material layer 12 . The first hole H1 penetrates all material layers of the second material layer 12 close to the upper surface of the stacked structure 10 , but does not penetrate the second material layer 12 .

[0100] The first hole H1 extends from the upper surface of the stacking structure 10 to the second material layer 12, and may also expose a portion of the first material layer 11 adjacent to the lower surface of the second material layer 12. The first hole H1 passes through the second material layer 12 and all material layers of the second material layer 12 close to the upper surface of the stacking structure 10.

[0101] S42 . Form the insulating portion 40 .

[0102] Through a thin film deposition process, a third material is deposited on the sidewall and bottom of the first hole H1. At this time, the sidewall and bottom of the first hole H1 may be surrounded by the third material. Fig.11 , the bottom of the first hole H1 is etched to form an insulating portion 40. For example, an etching process can be used to remove the third material at the bottom of the first hole H1, and the third material formed on the sidewall of the first hole H1 constitutes the insulating portion 40. The structure of the insulating portion 40 is described above and will not be repeated here.

[0103] S43 , depositing a conductive material in the first hole H1 to form a conductive portion 20 .

[0104] See also Fig.12 After the insulating portion 40 is formed on the sidewall of the first hole H1, a conductive material is deposited in the middle gap of the first hole H1 to form a conductive portion 20. The material and structure of the conductive portion 20 can refer to the above description and will not be repeated here.

[0105] S5. Remove slide 1.

[0106] Fig.13 A structural diagram of a packaging substrate formed in a method for preparing a packaging substrate according to some embodiments.

[0107] The carrier 1 can be removed from the lower surface of the stacking structure 10 by etching or direct stripping, or a solvent can be used to dissolve the adhesive layer between the carrier 1 and the stacking structure 10 to separate the carrier 1 and the stacking structure to form a packaging substrate.

[0108] Fig.14 FIG. 1 is a structural diagram of forming a spacer in a method for preparing a package substrate according to some embodiments.

[0109] In some embodiments, see Fig.14 In the method for preparing the package substrate, step S3 is performed to form the partition groove 30, and then the partition part 50 is formed in the partition groove 30. The partition part 50 can be formed by depositing a material in the partition groove 30 by using a thin film deposition process such as CVD, PVD or ALD. The structure and material of the partition part 50 refer to the above description and will not be repeated here.

[0110] Exemplarily, the forming of the spacer 50 in the partition 30 may be performed after step S3 and before step S4. Also exemplarily, the forming of the spacer 50 in the partition 30 may be performed after step S4 and before step S5. Also exemplarily, the forming of the spacer 50 in the partition 30 may be performed during the process of forming the conductive part 20 in step S4.

[0111] The embodiment of the present disclosure further provides a method for preparing a semiconductor structure, which may include steps S1A to S5A.

[0112] Among them, S1A~S2A and S4A~S5A refer specifically to S1~S2 and S4~S5 above.

[0113] S3A, forming a plurality of partition grooves 30 and a plurality of first holes H1 at the same time.

[0114] Fig.15 A structural diagram of forming a plurality of partition grooves and a plurality of first holes in another method for preparing a packaging substrate according to some embodiments.

[0115] See also Fig.15 , an etching process is used to form a plurality of partitions 30 and a plurality of first holes H1 in the stacked structure 10. By controlling the etching time, the partitions 30 and the first holes H1 with the same extension depth are formed, and the partitions 30 extend from the upper surface of the stacked structure 10 to the lower surface of a second material layer 12. The partitions 30 are located between two adjacent first holes H1 extending to the same second material layer 12. The number of the partitions 30 between the two adjacent first holes H1 is at least one, for example, one, or more. The structures of the partitions 30 and the first holes H1 refer to the above description and will not be repeated here. The partitions 30 and the first holes H1 are formed at the same time, which can simplify the preparation process.

[0116] Fig.16FIG. 4 is another structural diagram of forming a spacer in a method for preparing a package substrate according to some embodiments.

[0117] In some embodiments, see Fig.16 While the third material 2 is deposited on the sidewalls of the plurality of first holes H1 , the third material 2 is deposited in the plurality of partitions 30 to form the spacers 50 , which can simplify the manufacturing process.

[0118] See also Figure 3 and Fig.16 Since the size D1 of the conductive portion 20 in the first direction X is larger than the size D2 of the partition groove 30 in the first direction, it can be understood that the size of the first hole H1 in the first direction X is larger than the size of the partition groove 30 in the first direction. Therefore, under the same deposition conditions, when the third material 2 is filled in the first hole H1 to form the spacer 50, there is still space in the first hole H1 for depositing the conductive material, and there is no need to etch again to form the first hole H1, thereby simplifying the process.

[0119] The embodiment of the present disclosure also provides a chip packaging structure. The chip packaging structure includes a packaging substrate 100 as described in any of the above embodiments and a plurality of chips 200. The chip 200 is connected to the conductive portion 20 of the packaging substrate 100. Specifically, the chip 200 is connected to the conductive portion 20 on the upper surface of the stacked structure 10.

[0120] Fig.17 The structure diagram of a chip packaging structure provided according to some embodiments.

[0121] In some embodiments, see Fig.17 , the chip packaging structure also includes an adhesive layer 203. At least one (for example, one, or more than one) chip is connected to the conductive part of the packaging substrate through a lead. The adhesive layer 203 is provided between at least one chip and the packaging substrate to prevent the chip from being connected to the packaging substrate through the lead while being connected to the conductive part, causing signal transmission disorder. Exemplarily, the chip includes a first chip 201 and a second chip 202. The bottoms of the first chip 201 and the second chip 202 are provided on the packaging substrate 100, and an adhesive layer 203 is provided between the first chip 201 and the second chip 202 and the packaging substrate 100. The first chip 201 and the second chip 202 are provided with a lead on the side away from the packaging substrate 100, and the lead is connected to the conductive part 20 of the packaging substrate. The lead and the conductive part 20 can be connected through a pad or directly.

[0122] Fig.18 It is a structural diagram of yet another chip packaging structure provided according to some embodiments.

[0123] In some embodiments, see Fig.18, at least one chip is soldered to the conductive part of the package substrate. Specifically, bumps are provided at the bottom of the first chip 201 and the second chip 202, and pads are provided on the conductive part of the package substrate. The bumps are reflowed so that the first chip 201 and the second chip 202 are connected to the package substrate.

[0124] Fig.19 It is a structural diagram of yet another chip packaging structure provided according to some embodiments.

[0125] In some embodiments, see Fig.19 , at least one chip is bonded to the conductive portion of the package substrate. Specifically, the bottom of the first chip 201 and the second chip 202 are bonded to the upper surface of the conductive portion.

[0126] Fig. 20 A block diagram of a storage system according to some embodiments is provided.

[0127] The embodiment of the present disclosure also provides a storage system. Fig. 20 Some embodiments of the present disclosure provide a storage system 1000. The storage system includes a controller and a chip packaging structure, wherein the controller is coupled to the chip packaging structure to control the chip packaging structure to store data.

[0128] The storage system 1000 can be integrated into various types of storage devices, for example, included in the same package (for example, a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). That is, the storage system 1000 can be applied to and packaged in different types of electronic devices.

[0129] In some embodiments, the storage system 1000 may be integrated into a memory card, which may include a PC (i.e., PCMCIA, Personal Computer Memory Card International Association) card, a Compact Flash (CF) card, a Smart Media (SM) card, a memory stick, a Multimedia Card (MMC), a Secure Digital Memory Card (SD), or a Universal Flash Storage (UFS) card.

[0130] In other embodiments, the storage system is integrated into solid state drives (SSD).

[0131] The storage system 1000 includes a chip packaging structure and a controller, and may also include a circuit board. The circuit board is connected to the chip packaging structure, and the circuit board may be a flexible printed circuit (FPC) or a rigid printed circuit board (PCB).

[0132] The controller is coupled to the chip package structure. In some embodiments, the controller is configured to operate in a low duty cycle environment, such as an SD card, a CF card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, and mobile phones.

[0133] In other embodiments, the controller is configured to operate in a high duty cycle environment SSD or eMMC used for data storage in mobile devices such as smartphones, tablets, laptops, and enterprise storage arrays.

[0134] In some embodiments, the controller may be configured to control operations of the chip package structure, such as read, erase, and program operations. In some embodiments, the controller may also be configured to manage various functions regarding data stored or to be stored in the chip package structure, including at least one of bad block management, garbage collection, logical to physical address conversion, and wear leveling. In some embodiments, the controller is also configured to process error correction codes regarding data read from or written to the chip package structure. Of course, the controller may also perform any other suitable functions, such as formatting the chip package structure.

[0135] In some embodiments, the controller may also be configured to communicate with an external device (e.g., a host), for example, the controller may communicate with the external device via at least one of various interface protocols. It should be noted that the interface protocol includes at least one of a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a minicomputer mini interface (SCSI) protocol, an enhanced minidisk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, and a Firewire protocol.

[0136] Some embodiments of the present disclosure also provide an electronic device. The electronic device may be any one of a mobile phone (e.g., a mobile phone), a desktop computer, a tablet computer, a laptop computer, a server, a vehicle-mounted device, a wearable device (e.g., a smart watch, a smart bracelet, smart glasses, etc.), a mobile power supply, a game console, a digital multimedia player, a printer, a positioning device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, etc.

[0137] The electronic device may include the storage system 1000, and may also include at least one of a central processing unit (CPU) and a cache.

[0138] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A packaging substrate, characterized in that: include: A stacked structure, comprising a plurality of first material layers and a plurality of second material layers alternately stacked; The first material layer is an insulating material, and the second material layer is a conductive material; A plurality of conductive portions, each conductive portion extending from an upper surface of the stacked structure to a second material layer; An insulating portion is provided between the side wall of the conductive portion and the stacking structure; A plurality of partitions are provided, wherein the partitions are located between two adjacent conductive portions extending to the same second material layer; and the partitions extend from the upper surface of the stacked structure to the lower surface of a second material layer.

2. The packaging substrate according to claim 1, characterized in that: Also includes: A plurality of spacers are provided, wherein the spacers are located in the spacers.

3. The packaging substrate according to claim 2, characterized in that: The first material layer, the spacer, and the insulating portion are made of the same material.

4. The packaging substrate according to claim 1, characterized in that: The size of the conductive portion in a first direction is greater than the size of the partition groove in the first direction, and the first direction is parallel to the plane where the stacking structure is located.

5. The packaging substrate according to claim 1, characterized in that: An upper surface of the conductive portion is flush with an upper surface of the stacked structure.

6. The packaging substrate according to claim 1, characterized in that: The thickness of the first material layer is greater than the thickness of the second material layer.

7. A chip packaging structure, characterized in that: include: The packaging substrate according to any one of claims 1 to 6, A plurality of chips are connected to the conductive portion of the package substrate.

8. The chip packaging structure according to claim 7, characterized in that: Also includes: an adhesive layer, provided between at least one chip and the packaging substrate; The at least one chip is connected to the conductive portion of the packaging substrate through wires.

9. The chip packaging structure according to claim 7, characterized in that: At least one chip is soldered to the conductive portion of the packaging substrate.

10. The chip packaging structure according to claim 7, characterized in that: At least one chip is bonded to the conductive portion of the packaging substrate.

11. An electronic device, characterized in that: Comprising the chip packaging structure as described in any one of claims 7-10.

12. A method for preparing a packaging substrate, characterized in that: include: Provide slides; forming a stacking structure on the carrier; the stacking structure comprises a plurality of first material layers and a plurality of second material layers alternately stacked; The first material layer is an insulating material, and the second material layer is a conductive material; forming a plurality of partitions in the stacked structure, wherein the partitions extend from the upper surface of the stacked structure to the lower surface of one of the second material layers; forming a plurality of conductive parts, wherein the conductive parts extend from the upper surface of the stacked structure to a second material layer, and two adjacent conductive parts extending to the same second material layer are separated by the partition groove; an insulating part is provided between the side wall of the conductive part and the stacked structure; Remove the slide.

13. The method for preparing a packaging substrate according to claim 12, characterized in that: Also includes: In the plurality of partition grooves, partitions are formed.

14. The method for preparing a packaging substrate according to claim 12 or 13, characterized in that: The forming of a plurality of conductive parts comprises: forming a plurality of first holes; wherein the first holes extend from the upper surface of the stacked structure to the second material layer and expose the second material layer or a portion of the first material layer adjacent to the lower surface of the second material layer; Depositing a third material on the sidewall of the first hole to form an insulating portion; A conductive material is deposited in the first hole to form a conductive portion.

15. The method for preparing a packaging substrate according to claim 14, characterized in that: A plurality of first holes are formed while forming the plurality of partition grooves; the partition grooves penetrate from the upper surface of the stacked structure to the lower surface of a second material layer, and the partition grooves are located between two adjacent first holes extending to the same second material layer.

16. The method for preparing a packaging substrate according to claim 14, characterized in that: The method for preparing the package substrate further includes: in the case where a spacer is formed in the plurality of partitions; While the third material is deposited on the sidewalls of the plurality of first holes, the third material is deposited in the plurality of isolation grooves to form spacers.

17. The method for preparing a packaging substrate according to claim 16, characterized in that: The third material is the same as that of the first material layer.

Images