Semiconductor device and forming method thereof

Abstract

In an embodiment, a semiconductor device may include an interposer. The semiconductor device may also include a plurality of chiplets directly bonded to the interposer. The device may further include a plurality of interposer dies directly bonded to the interposer adjacent to the plurality of chiplets, the plurality of interposer dies having through substrate vias. The device may additionally include a memory package over and bonded to at least one of the plurality of interposer dies. The embodiment of the invention relates to a semiconductor device and a forming method thereof.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor devices and methods of forming the same. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the continuous improvement in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, the improvement in integration density comes from the iterative reduction of the minimum component size, which allows more components to be integrated into a given area. As the demand for shrinking electronic devices grows, there is a demand for smaller and more creative packaging technologies for semiconductor die. An example of such a packaging system is package-on-package (PoP) technology. In a PoP device, a top semiconductor package is stacked on top of a bottom semiconductor package to provide a high level of integration and component density. PoP technology is generally capable of producing semiconductor devices with enhanced functionality and a small footprint on a printed circuit board (PCB). Summary of the invention

[0003] Some embodiments of the present application provide a semiconductor device comprising: an interposer; a plurality of chiplets directly bonded to the interposer; a plurality of interposer dies directly bonded to the interposer adjacent to the plurality of chiplets, the plurality of interposer dies comprising substrate through holes; and a memory package located above and bonded to at least one of the plurality of interposer dies.

[0004] Other embodiments of the present application provide a method for forming a semiconductor device, comprising: directly bonding a plurality of chiplets to an interposer; directly bonding a plurality of interposer dies to the interposer adjacent to the plurality of chiplets, wherein the plurality of interposer dies include substrate through-holes; and bonding a memory package over and to at least one of the plurality of interposer dies using a solder connection.

[0005] Still other embodiments of the present application provide a method for forming a semiconductor device, comprising: bonding a plurality of integrated circuit dies to an interposer using a direct bonding process, the interposer comprising a substrate through hole and an interconnect structure above the substrate through hole, the interconnect structure comprising a dielectric layer and a metallization layer; bonding a memory package above the plurality of integrated circuit dies; and forming an electrical connection between the interconnect structure of the interposer and the memory package, the electrical connection being adjacent to the plurality of integrated circuit dies. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the disclosed embodiments can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figures 1 to 10 are cross-sectional and top view diagrams of intermediate steps in a process for forming a semiconductor package in accordance with some embodiments.

[0008] Figure 11 to Figure 12 is a cross-sectional view of an intermediate step in a process for forming a semiconductor package according to some embodiments.

[0009] Fig.13 is a cross-sectional view of an intermediate step in a process for forming a semiconductor package according to some embodiments.

[0010] Fig.14 is a cross-sectional view of an intermediate step in a process for forming a semiconductor package according to some embodiments.

[0011] Fig.15 is a cross-sectional view of an intermediate step in a process for forming a semiconductor package according to some embodiments.

[0012] Figure 16 to Figure 17 is a cross-sectional view of an intermediate step in a process for forming a semiconductor package according to some embodiments.

[0013] Fig.18 is a cross-sectional view of an intermediate step in a process for forming a semiconductor package according to some embodiments. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments or examples for realizing different features of the disclosed embodiments. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0015] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0016] The disclosed embodiments relate to the field of semiconductor devices, and more specifically, to the integration of one or more raised memory dies in an integrated system-on-chip (SoIC) chiplet, a modular application processor. In semiconductor technology, the integration of various components such as SoIC chiplets (also referred to as IC dies), memory dies, and power management integrated circuits (PMICs) for application processors (APs) presents technical challenges. This challenge is mainly due to the lack of solutions that can effectively integrate these components while maintaining low latency and high bandwidth.

[0017] In response to this technical problem, the disclosed embodiment introduces a method involving the use of an adapter interposer die or dielectric through-holes. This method enables the use of direct bonding and bumps in the structure. This solution is not only suitable for AP, but also cost-effective because it enables the SoIC chiplet to have no through-silicon vias (TSVs) in the active die. In addition, it provides better efficiency, allows the selection of appropriate nodes for the SoIC chiplet, and the interconnection length between the SoIC chiplets is shorter due to the surrounding adapter interposer die.

[0018] In some embodiments, features of the disclosed embodiments include: the adapter interposer die is a power interface die / active interposer die (PID / AID) surrounding the CPU / xPU die; using TSVs in the PID / AID to replace traditional InFO through-hole vias (TIVs) in an integrated fan-out (InFO) package; and using SoIC bonding technology (e.g., direct bonding technology) to bond the PID / AID and the CPU / xPU die to the interposer below. In addition, some embodiments may include adding an additional supporting substrate above the CPU / xPU die to improve heat dissipation. In addition, additional power management ICs may be added to coordinate the power requirements of the CPU, xPU, and memory dies, as these dies may have different power domains. The SoIC bonding includes dielectric-to-dielectric bonding, and in some embodiments, a vertical stacking interface for two silicon photonic dies may be provided.

[0019] The disclosed embodiments provide solutions to the technical problem of integrating various components in a modular application processor. By introducing an interposer die or dielectric vias, the disclosed embodiments provide a way to achieve lower latency and higher bandwidth, thereby enhancing the performance of the application processor. The inventive components and benefits of the disclosed embodiments are further described in the following paragraphs.

[0020] Figures 1 to 10 1 is a cross-sectional view and a top view of intermediate steps of a process for forming a semiconductor package 100 according to some embodiments. The semiconductor package 100 includes an interposer with a chiplet (or die) and an adapter die bonded to the interposer. The chiplet and adapter die may be encapsulated.

[0021] refer to Figure 1 , depicting a cross-sectional view of an intermediate stage of processing a package structure 100. The package structure 100 includes a substrate 102, which can be used as a base layer of the package structure 100. The substrate 102 can be formed of various materials, including but not limited to silicon, glass, ceramic, or any other suitable material. In some embodiments, the substrate 102 can be an interposer 110, which can be made of a silicon material. The interposer 110 can be used as a base layer for integrating various components, such as SoIC chiplets, dies, adapter dies, and memory packages.

[0022] The substrate 102 includes a series of trenches 104 formed therein. In some embodiments, the trenches 104 are evenly distributed across the substrate 102. The trenches 104 can be formed using various patterning techniques, such as etching or laser ablation. The trenches 104 can be filled with a dielectric material, a conductive material, or left empty, depending on the specific requirements of the package structure 100. In some embodiments, the trenches 104 will have deep trench capacitors formed therein.

[0023] exist Figure 2 , the package structure 100 is shown as having a series of deep trench capacitors 106 formed in trenches 104 in a substrate 102. The deep trench capacitors 106 can be formed using various techniques known in the art, such as deposition and etching processes. The deep trench capacitors 106 can be used as energy storage devices, provide power source decoupling, noise filtering, or other functions within the package structure 100.

[0024] In some embodiments, the deep trench capacitor 106 can be formed of multiple layers of dielectric material and conductive material. In some embodiments, the dielectric material and the conductive material are alternated, wherein the dielectric layer is sandwiched between two conductive layers. The dielectric material can be an oxide, a nitride, a high-k dielectric material, or any other suitable dielectric material. The conductive layer can be formed of a metal (e.g., copper, etc.), a semiconductor, a conductive polymer, or any other suitable conductive material.

[0025] In some embodiments, deep trench capacitor 106 may be replaced with other types of passive components, such as resistors or inductors, depending on the specific requirements of package structure 100. Alternatively, trench 104 and deep trench capacitor 106 may be omitted, with the trench left empty or filled with a dielectric material for isolation purposes.

[0026] Forming deep trench capacitor 106 within trench 104 represents an efficient use of available space within substrate 102, allowing for integration of additional components within package structure 100. This may result in a more compact and efficient design, potentially leading to improved performance and reduced cost.

[0027] like Figure 2 The configuration of the package structure 100 depicted in FIG. 1 is one example of how the deep trench capacitor 106 may be integrated within the substrate 102 . Other configurations and arrangements of the deep trench capacitor 106 within the substrate 102 are also possible, depending on the specific requirements of the package structure 100 .

[0028] Figure 3 The formation of a through substrate via 108 in the substrate 102 is shown. The through substrate via 108 may be formed using various patterning techniques, such as laser drilling, etching, or other suitable methods. Initially, the through substrate via 108 may only extend partially through the substrate 102, and may not extend to the back side of the substrate 102 until after the thinning process.

[0029] In some embodiments, substrate through-holes 108 are filled with conductive materials to provide electrical connections between different layers or components of package structure 100. The conductive material can be a metal, a doped semiconductor, a conductive polymer, or any other suitable conductive material. In some embodiments, substrate through-holes 108 can be lined with a barrier layer or a seed layer before being filled with a conductive material. The barrier layer can be formed of a material such as titanium, titanium nitride, tantalum, tantalum nitride, or any other suitable barrier material. The seed layer can be formed of a material such as copper, gold, silver, or any other suitable seed material.

[0030] Various configurations and arrangements of through-substrate vias 108 within substrate 102 are possible, depending on the specific requirements of package structure 100. For example, through-substrate vias 108 may be arranged in a regular grid pattern, a staggered pattern, a random pattern, or any other suitable pattern. The size, shape, and spacing of through-substrate vias 108 may also vary, depending on the specific requirements of package structure 100.

[0031] Figure 4The thinning of the backside surface 102B of the substrate 102 is shown. In some embodiments, the thinning process may include a planarization process, such as chemical mechanical polishing (CMP), grinding, etching, or other suitable methods. The thinning process may be controlled to achieve a desired thickness of the substrate 102, which may depend on the specific requirements of the package structure 100. In some embodiments, the thinning process may be performed until the substrate through via 108 is exposed at the backside surface 102B of the substrate 102. After thinning, the substrate through via 108 extends through the substrate 102 from the frontside surface 102A to the backside surface 102B.

[0032] The exposure of the through substrate vias 108 at the backside surface 102B may facilitate the formation of electrical connections from the backside of the substrate 102 to the through substrate vias 108. These electrical connections may be used to connect the through substrate vias 108 to other components or layers of the package structure 100, such as an integrated circuit die, an interposer die, a memory package, or other components.

[0033] In some embodiments, the thinning process may also expose the deep trench capacitors 106 at the backside surface 102B of the substrate 102. This may facilitate the formation of electrical connections from the backside of the substrate 102 to the deep trench capacitors 106. These electrical connections may be used to connect the deep trench capacitors 106 to other components or layers of the package structure 100, such as an integrated circuit die, an interposer die, a memory package, or other components.

[0034] The thinning of backside surface 102B and the exposure of through substrate vias 108 and deep trench capacitors 106 represent an efficient way to provide electrical connections within package structure 100. This can result in improved signal transmission, reduced signal delays, and increased bandwidth, potentially leading to improved performance of package structure 100.

[0035] Figure 5 The formation of an interconnect structure 120 on the front side surface 102A of the substrate 102 of the interposer 110 is shown. The interconnect structure 120 may include a plurality of dielectric layers 122 and metallization layers 124. The dielectric layers 122 may be formed of various dielectric materials, such as silicon dioxide, silicon nitride, low-k dielectric materials, high-k dielectric materials, or any other suitable dielectric materials. The metallization layers 124 may be formed of various conductive materials, such as copper, aluminum, gold, silver, or any other suitable conductive materials.

[0036] In some embodiments, the interconnect structure 120 can be formed using various techniques, such as deposition and patterning processes including damascene processes. The interconnect structure 120 can include a bonding surface 126 at the top where components will subsequently bond. The bonding surface 126 can include metallization structures, such as bonding pads, dielectric materials, or combinations thereof.

[0037] Interconnect structure 120 may facilitate electrical connections between various components of package structure 100 , such as an integrated circuit die, an interposer die, a memory package, or other components. Electrical connections may be formed through metallization layers 124 and through substrate vias 108 , providing horizontal and vertical electrical connections within package structure 100 .

[0038] Figure 6 The bonding of the integrated circuit dies 130A and 130B to the interconnect structure 120 is shown. The integrated circuit dies 130 may also be referred to as chiplets 130. The interconnect structure 120, including the dielectric layer 122 and the metallization layer 124, facilitates electrical connections between the integrated circuit dies 130A, 130B and other components within the package structure 100. These electrical connections may be formed through the metallization layer 124 and the substrate through vias 108, providing horizontal and vertical electrical connections within the package structure 100.

[0039] In some embodiments, the integrated circuit die 130A, 130B can be bonded to the interconnect structure 120 using a direct bonding process. Such a direct bonding process may include metal-to-metal bonding, dielectric-to-dielectric bonding, or any other suitable bonding technology. For example, the dielectric layer of the integrated circuit die 130A, 130B can be directly bonded to the topmost dielectric layer of the interconnect structure 120, and the bonding pads of the integrated circuit die 130A, 130B can be directly bonded to the bonding pads of the interconnect structure 120. In an embodiment, the bonding between the dielectric layers can be oxide-to-oxide bonding, etc. The direct bonding process also directly bonds the bonding pads of the integrated circuit die 130A, 130B to the bonding pads of the interconnect structure 120 through direct metal-to-metal bonding. The direct bonding process can provide a strong and reliable bond between the integrated circuit die 130A, 130B and the interconnect structure 120, potentially resulting in improved performance and reliability of the package structure 100.

[0040] Each of the integrated circuit dies 130A, 130B may be a bare chip semiconductor die (e.g., an unpackaged semiconductor die) formed as part of a larger wafer. For example, each of the integrated circuit dies 130A, 130B may be a logic die (e.g., an application processor (AP), a central processing unit, a microcontroller, etc.), a memory die (e.g., a dynamic random access memory (DRAM) die, a hybrid memory cube (HBC), a static random access memory (SRAM) die, a wide input / output (wide IO) memory die, a magnetoresistive random access memory (mRAM) die, a resistive random access memory (rRAM) die, etc.), a power management die (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a microelectromechanical system (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die), a front-end die (e.g., an analog front-end (AFE) die), a biomedical die, etc.

[0041] Each of the integrated circuit dies 130A, 130B can be processed according to an applicable manufacturing process to form an integrated circuit in the integrated circuit die 130A, 130B. For example, each of the integrated circuit dies 130A, 130B can include a semiconductor substrate, such as doped or undoped silicon, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate can include: other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer or gradient substrates, can also be used.

[0042] Active and / or passive devices, such as transistors, diodes, capacitors, resistors, etc., may be formed in and / or on a semiconductor substrate. The devices may be interconnected by an interconnect structure including, for example, metallization patterns in one or more dielectric layers on the semiconductor substrate. The interconnect structure electrically connects the devices on the substrate to form one or more integrated circuits.

[0043] The integrated circuit die 130A, 130B also includes contact pads or bonding pads that allow connections to be made to the interconnect structures of the integrated circuit die 130A, 130B and devices on the substrate of the integrated circuit die 130A, 130B. The contact pads may include copper, aluminum (e.g., 28K aluminum), gold, silver, or another conductive material.

[0044] The integrated circuit dies 130A, 130B can be formed as part of a larger wafer (e.g., connected to other integrated circuit dies 130). In some embodiments, the integrated circuit dies 130A, 130B can be separated from each other after packaging. For example, the integrated circuit dies 130A, 130B can be packaged while still connected as part of the wafer. In other embodiments, the integrated circuit dies 130A, 130B can be packaged after they have been separated from other components of the wafer. In some embodiments, a chip probe (CP) test can be applied to each of the integrated circuit dies 130A, 130B (e.g., through a contact pad or a bonding pad). The CP test checks the electrical functions of the integrated circuit dies 130A, 130B, and the dies that pass the CP test are called known good dies (KGD). Discard or repair the integrated circuit dies 130A, 130B that have not passed the CP test. In this way, a KGD for packaging is provided, which reduces the waste and expense of packaging defective dies.

[0045] Contact pads or bonding pads of the integrated circuit dies 130A, 130B are bonded to bonding pads of the bonding surface 126 on the interconnect structure 120. The bonding pads may provide locations for electrical connections between the integrated circuit dies 130A, 130B and the interconnect structure 120.

[0046] In some embodiments, the plurality of chiplets (which may include integrated circuit die 130A and integrated circuit die 130B) may include at least one processor chiplet and at least one memory chiplet. In some embodiments, the plurality of chiplets also include a neural system engine chiplet. This configuration may provide a flexible and efficient way to integrate various types of chiplets within package structure 100, resulting in improved performance and functionality of package structure 100.

[0047] Figure 7 An interposer die 140 is shown bonded to the interposer 110 adjacent to the integrated circuit die 130A and 130B. The interposer die 140 may also be referred to as an adapter interposer die 140. Each interposer die 140 includes an interposer substrate 142 and a bonding pad 144. The interposer substrate 142 may be formed of a variety of materials, such as silicon, glass, ceramic, or any other suitable material. The bonding pad 144 may be formed of a conductive material, such as copper, gold, silver, or any other suitable conductive material. The bonding pad 144 may provide a location for electrical connection between the interposer die 140 and other components of the package structure 100.

[0048] In some embodiments, the interposer die 140 may include a substrate through-via 146 that facilitates vertical electrical connections. The substrate through-via 146 may be similar to the substrate through-via 108 and will not be described again herein. The substrate through-via 146 may extend vertically through the interposer substrate 142 to provide electrical connections between different layers or components of the package structure 100. In some embodiments, the substrate through-via 146 has a width in the range of from 2 um to 10 um.

[0049] The interposer die 140 may be formed by a process similar to that of the integrated circuit die 130 and will not be described again herein. For example, the interposer die 140 may be formed as part of a larger wafer and separated into separate interposer die 140. In some embodiments, the interposer die 140 includes passive devices such as capacitors, inductors, resistors, etc. or combinations thereof, but does not include active devices. In some embodiments, the interposer die 140 includes active devices such as transistors that are interconnected to form a circuit.

[0050] In some embodiments, the interposer die 140 can be bonded to the interconnect structure 120 by a direct bonding process. Such a direct bonding process may include metal-to-metal bonding, dielectric-to-dielectric bonding, or any other suitable bonding technology. The direct bonding process can provide a strong and reliable bond between the interposer die 140 and the interconnect structure 120, potentially resulting in improved performance and reliability of the package structure 100. In addition, the interposer die 140 can be bonded to the interconnect structure 120 using a similar direct bonding process described above, and the description is not repeated here.

[0051] In some embodiments, the method may include bonding a plurality of interposer dies (such as interposer die 140) to an interposer (such as interposer 110) using a direct bonding process. The electrical connections between the interconnect structure (such as interconnect structure 120) of the interposer and the memory package (such as memory package 202) may include through-substrate vias in the plurality of interposer dies, such as through-substrate via 146. This configuration may provide an efficient way to integrate various components within the package structure 100, potentially resulting in improved performance and functionality of the package structure 100.

[0052] refer to Figure 8 , the integrated circuit die 130A, 130B and the interposer die 140 are encapsulated with an encapsulant 150. The encapsulant 150 may be a molding compound, an oxide, or any other suitable material. The encapsulant 150 may provide structural support and environmental protection for the integrated circuit die 130A, 130B and the interposer die 140. In some embodiments, the encapsulant 150 may also provide electrical insulation between the integrated circuit die 130A, 130B and the interposer die 140.

[0053] Bump pads 148 are formed on the top surface of interposer die 140 to be electrically connected to substrate through vias 146. Bump pads 148 may be referred to as under bump metallurgy (UBM) 148. UBM 148 is formed for external connection to interposer die 140. UBM 148 has a dielectric layer located on interposer die 140 (or an upper dielectric layer, if present, see e.g. Fig. 9A and Fig. 9B ) and extending along the top surface of the interposer die 140, and having a via portion extending into the interposer die 140 (or an upper dielectric layer, if present) to physically and electrically couple the substrate via 146. Thus, the UBM 148 is electrically connected to the interconnect 120 (e.g., through the substrate via 146). The UBM 148 may be formed of a conductive material, such as copper, aluminum, tungsten, titanium, gold, silver, etc., or combinations thereof. The UBM 148 may provide a location for electrical connection between the interposer die 140 and a subsequently attached component, such as a memory package or other integrated circuit die.

[0054] Fig. 9A and Fig. 9B A cross-sectional view of an interposer die 140 is shown according to various embodiments. Fig. 9B including an interconnect structure 160 on an upper surface of the interposer substrate 142, and Fig. 9A Interconnect structures are not included. Both embodiments show that the bonding pads 144 on the lower surface of the interposer substrate 142 are embedded in the dielectric layer 168. In addition, both embodiments show that the UBM 148 is embedded in the dielectric layer on the upper surface of the interposer die 140. Fig. 9A In the embodiment, dielectric layer 147 laterally surrounds UBM 148 and Fig. 9B In FIG. 1 , one of the dielectric layers 162 of the interconnect structure 160 laterally surrounds the UBM 148 .

[0055] The interconnect structure includes a dielectric layer 162 and a metallization layer 164. The interconnect structure 160 may be similar to the interconnect structure 120 described above and will not be described again herein. The through substrate via 146 extends vertically through the interposer substrate 142 and may be electrically coupled to the interconnect structure 160 and / or the UBM 148.

[0056] Reference now Fig.10 , depicting a top view of the interposer 110, wherein Figure 8 The structure along Fig.101. In some embodiments, the integrated circuit dies 130A, 130B, 130C, and 130D are located in the center of the interposer 110. These integrated circuit dies may include at least one processor chiplet and at least one memory chiplet. The specific type and configuration of the integrated circuit dies may vary, depending on the specific requirements of the package structure 100. For example, the integrated circuit die may include a central processing unit (CPU), a graphics processing unit (GPU), a memory controller, a neural processing unit (NPU), or any other suitable type of processing or memory unit.

[0057] Adjacent to each of the integrated circuit dies is an interposer die 140. The interposer die 140 can be directly bonded to the interposer 110. The metallization layer 124 of the interconnect structure 120 electrically couples the integrated circuit die 130 and the interposer die 140. The metallization layer 124 can facilitate electrical connections between various components of the package structure 100, such as the integrated circuit die, memory package, or other components. These electrical connections can be formed through the metallization layer 124 and the substrate through vias 108, providing horizontal and vertical electrical connections within the package structure 100.

[0058] Although in Fig.10 100 . Although four integrated circuit dies or chiplets 130 are shown, there may be more or fewer integrated circuit dies or chiplets 130, depending on the specific requirements of the package structure 100. Similarly, although six interposer dies 140 are shown, there may be more or fewer interposer dies 140, depending on the specific requirements of the package structure 100. The specific arrangement and configuration of the integrated circuit dies 130 and the interposer dies 140 on the interposer 110 may also vary, depending on the specific requirements of the package structure 100. For example, the integrated circuit dies 130 and the interposer dies 140 may be arranged in a grid pattern, a staggered pattern, a random pattern, or any other suitable pattern. The size, shape, and spacing of the integrated circuit dies 130 and the interposer dies 140 may also vary, depending on the specific requirements of the package structure 100.

[0059] Fig.11The package structure 200 is shown joined to the package structure 100 using a conductive connector 204. The package structure 200 may include a memory package 202. In some embodiments, the memory package 202 may be a memory device, such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a hybrid memory cube (HMC) module, a high bandwidth memory (HBM) module, a flash memory device, or any other suitable type of memory device. The conductive connector 204 provides an electrical and physical connection between the package structure 100 and the memory package 202. The conductive connector 204 may be a bump, such as a controlled collapse chip connection (C4) bump, a solder ball, a ball grid array, or any other suitable type of conductive connector.

[0060] Although the package structure 200 is shown with a single memory device 202, other embodiments may have more structures in the package 200. For example, the package 200 may include multiple memory devices 202, integrated circuit dies, supporting substrates, etc., or combinations thereof.

[0061] Fig.12 A sealant 210 is shown formed between the packages 100 and 200 around the conductive connector 204. The sealant 210 may be a molding compound, an oxide, or any other suitable material. Such a process may involve various techniques known in the art, such as deposition, molding, or other suitable methods. The sealant 210 may be applied in different thicknesses or patterns, depending on the specific requirements of the package structure 100. The sealant 210 may provide structural support and environmental protection for the assembly. In some embodiments, the sealant 210 may also provide electrical insulation between the packages 100 and 200, resulting in improved performance and reliability of the package structure 100.

[0062] The lower surface of the memory package 202, the upper portions of the integrated circuit dies 130A and 130B, and the conductive connectors 204 are sealed by the encapsulant 210. This sealing process can protect the integrated circuit dies 130A, 130B, the memory package 202, and the conductive connectors 204 from environmental factors, such as moisture, dust, or other contaminants, potentially resulting in improved reliability and life of the package structure 100.

[0063] Fig.13 1 shows a cross-sectional view of an intermediate stage in the formation of a package structure according to some embodiments. Fig.13 In the same reference numerals as above, the same reference numerals denote Figures 1 to 12 The same components are formed by the same processes described in the examples, unless otherwise stated. Fig.13 In FIG. 1 , packages 100 and 200 are connected via conductive connector 224 and UBMs 220 and 222 .

[0064] Conductive connector 224 can be formed on UBM 148. Conductive connector 224 can be a ball grid array (BGA) connector, a solder ball, a metal column, a controlled collapse chip connection (C4) bump, a microbump, a bump formed by chemical nickel plating-chemical palladium plating-immersion gold technology (ENEPIG), etc. Conductive connector 224 can include conductive materials, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc. or a combination thereof. In some embodiments, conductive connector 224 is formed by initially forming a solder layer by evaporation, electroplating, printing, solder transfer, ball placement, etc. Once the solder layer has been formed on the structure, reflow can be implemented to shape the material into a desired bump shape. In another embodiment, conductive connector 224 includes a metal column (such as a copper column) formed by sputtering, printing, electroplating, chemical plating, CVD, etc. The metal column can be solder-free and have a substantially vertical sidewall. In some embodiments, a metal capping layer is formed on the top of the metal column. The metal capping layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, etc. or a combination thereof and may be formed by a plating process. In a specific embodiment, the conductive connector 224 and the UBMs 220 and 222 are micro-bump structures.

[0065] like Fig.13 The configuration of the package structure depicted in FIG. 1 is one example of how the memory package 202 may be bonded to the interposer die 140 using a microbump bonding structure. Other configurations and arrangements of the memory package 202, the interposer die 140, and the microbump bonding structure are possible, depending on the specific requirements of the package structure 100. For example, the number, type, and arrangement of microbumps may vary, and the memory package 202 may include additional features or components, depending on the specific requirements of the package structure.

[0066] Fig.14 1 shows a cross-sectional view of an intermediate stage in the formation of a package structure according to some embodiments. Fig.14 In the same reference numerals as above, the same reference numerals denote Figures 1 to 13 The same components are formed by the same processes described in the examples, unless otherwise stated. Fig.14 In the embodiment, the package structure 100 is similar to Fig.13 The package structure 100 is a package structure in which a redistribution structure 180 is added. The redistribution structure 180 includes a dielectric layer 182 and a metallization layer 184, which facilitates the routing of electrical signals within the package structure 100.

[0067] A redistribution structure 180 is formed on the encapsulant 150 and the dies 130 and 140. The redistribution structure 180 may include a redistribution line (RDL) 184, such as a metal trace (or metal line), and a via located under and connected to the metal trace. The redistribution line of the redistribution structure 180 is physically and electrically connected to the substrate through-via 146 of the interposer die 140.

[0068] In some embodiments, RDL 184 is formed by a plating process, wherein each of RDL 184 includes a seed layer (not shown) and a metallized material above the seed layer. The seed layer can be formed using, for example, PVD, etc. Then a photoresist is formed and patterned on the seed layer. The photoresist can be formed by spin coating, etc., and can be exposed to light for patterning. The pattern of the photoresist corresponds to RDL 184. Patterning forms an opening through the photoresist to expose the seed layer. Conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material can be formed by plating, such as electroplating or chemical plating, etc. The seed layer and the metallized material can be formed by the same material or different materials. The conductive material can be a metal, such as copper, titanium, tungsten, aluminum, etc. Then, the photoresist and the seed layer are removed on which the conductive material is not formed. Once the photoresist is removed, the exposed portion of the seed layer is removed, such as by using an acceptable etching process, such as by wet etching and / or dry etching. The seed layer and remaining portions of the conductive material form RDL 184 .

[0069] A dielectric layer or passivation layer 182 may be formed over each layer of metal traces 184. In some embodiments, the dielectric layer or passivation layer 182 is formed of a polymer, which may be a photosensitive material that can be patterned using a photolithography mask, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), etc. In other embodiments, the dielectric layer or passivation layer 182 is formed of: a nitride, such as silicon nitride; an oxide, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG); etc. The dielectric layer or passivation layer may be formed by spin coating, lamination, chemical vapor deposition (CVD), etc., or a combination thereof.

[0070] A patterning process may be used to form openings in the top dielectric or passivation layer 182, exposing some or all of the top metal layer 184 of the redistribution structure 180. The patterning process may be an acceptable process, such as by exposing the dielectric or passivation layer 182 to light when the dielectric layer is a photosensitive material, or by etching using, for example, anisotropic etching.

[0071] The redistribution structure 180 can provide a flexible and efficient way to route electrical signals between various components (such as integrated circuit dies, memory packages, or other components) of the package structure 100. This can result in improved signal transmission, reduced signal delays, and increased bandwidth, potentially leading to improved performance of the package structure 100.

[0072] The redistribution structure 180 is shown as an example. More or fewer dielectric layers 182 and metallization layers 184 than shown may be formed in the redistribution structure 180 by repeating or omitting previously described steps.

[0073] Fig.15 1 shows a cross-sectional view of an intermediate stage in the formation of a package structure according to some embodiments. Fig.15 In the same reference numerals as above, the same reference numerals denote Figures 1 to 14 The same components are formed by the same processes described in the examples, unless otherwise stated. Fig.15 In the embodiment, the package structure 100 is similar to Fig.13 The package structure of FIG. 100 is shown in FIG. 100 , except that, in an embodiment, the interposer die 140 is not included in the package structure 100 . In this configuration, the encapsulant 150 surrounds the integrated circuit dies 130A and 130B and the dielectric vias 242 .

[0074] The dielectric vias 242 extend through the encapsulant 150 to enable vertical electrical connections between the interposer 110, the integrated circuit die 130A, 130B, and the memory package 202. The dielectric vias 242 can be formed using various techniques known in the art, such as laser drilling, etching, or other suitable methods. The dielectric vias 242 can be formed by patterning openings through the encapsulant 150 and forming a conductive material in the openings. The dielectric vias 242 can be similar to the substrate through-holes 108 and 146, and are not repeated here. In some embodiments, the dielectric vias 242 have a width in the range of from 2um to 10um.

[0075] This configuration may provide an efficient way to integrate various components within package structure 100, potentially resulting in improved performance and functionality of package structure 100. Fig.15 100 is one example of how the integrated circuit dies 130A, 130B may be encapsulated with the encapsulant 150 and how the dielectric vias 242 may be formed through the encapsulant 150. Other configurations and arrangements of the encapsulant 150 and the dielectric vias 242 within the package structure are possible, depending on the specific requirements of the package structure 100. For example, the encapsulant 150 may be applied in different thicknesses or patterns, and the dielectric vias 242 may be formed in different sizes, shapes, or arrangements, depending on the specific requirements of the package structure 100.

[0076] Fig.16 and Fig.17 1 shows a cross-sectional view of an intermediate stage in the formation of a package structure according to some embodiments. Fig.16 and Fig.17 In the same reference numerals as above, the same reference numerals denote Figures 1 to 15 The same components are formed by the same processes described in the examples, unless otherwise stated. Fig.16 and Fig.17 In the embodiment, the package structure 300 is attached to the package structure 100 , and the package structure 300 includes a support substrate 304 and a plurality of memory packages 306 surrounding the support substrate 304 .

[0077] Reference now Fig.16 , the package structure 100 is depicted as being in a Figure 8 A similar processing stage occurs, where a support substrate 304 is added. In some embodiments, the support substrate 304 is attached to the package structure 100 with a thermal interface material 302 .

[0078] The support substrate 304 may be formed of a variety of materials, such as silicon, glass, ceramic, or any other suitable material. In some embodiments, the support substrate 304 may be attached over a plurality of chiplets, such as the integrated circuit die 130, with a thermal interface material 302. The thermal interface material 302 may be a thermally conductive material, such as a metal, a thermally conductive polymer, or any other suitable thermally conductive material. The thermal interface material 302 may provide a path for heat transfer from the integrated circuit die 130 to the support substrate 304, resulting in improved thermal management and performance of the package structure 100.

[0079] Fig.17 Memory package 306 is shown bonded to package structure 100 using UBM 222 and conductive connector 224. In some embodiments, memory package 306 is bonded adjacent to support substrate 304. Memory package 306 may be similar to memory package 202 and will not be described again herein.

[0080] Support substrate 304 may provide structural support for memory package 306, potentially resulting in improved reliability and lifetime of package structure 100. In some embodiments, support substrate 304 may also provide a path for heat transfer from memory package 306 to the surrounding environment, potentially resulting in improved thermal management and performance of package structure 300.

[0081] Encapsulant 210 seals memory package 306 and support substrate 304. Encapsulant 210 may be similar to encapsulant 150 and will not be described again herein. Encapsulant 210 may provide structural support and environmental protection for memory package 306 and support substrate 304. In some embodiments, encapsulant 210 may also provide electrical insulation between memory package 306, support substrate 304, and other components of package structure 100, potentially resulting in improved performance and reliability of package structure 100.

[0082] like Fig.17 The configuration of the package structure 100 depicted in FIG. 1 is one example of how the memory package 306 may be bonded to the package structure 100 using the UBM 222 and the conductive connector 224. Other configurations and arrangements of the memory package 306, the UBM 222, the conductive connector 224, the support substrate 304, and the encapsulant 210 within the package structure 100 are also possible, depending on the specific requirements of the package structure 100. For example, the number, type, and arrangement of the memory package 306, the UBM 222, and the conductive connector 224 may vary, and the support substrate 304 and the encapsulant 210 may include additional features or components, depending on the specific requirements of the package structure.

[0083] Fig.18 1 shows a cross-sectional view of an intermediate stage in the formation of a package structure according to some embodiments. Fig.18 In the same reference numerals as above, the same reference numerals denote Figures 1 to 17 The same components are formed by the same processes described in the examples, unless otherwise stated. Fig.18 In the configuration, it is similar to Fig.17 A configuration in which a redistribution structure 180 is added over the dies 130 and 140 and the integrated circuit die 310 in the package structure 300 .

[0084] In some embodiments, the package structure 300 includes an integrated circuit die 310 between the memory packages 306. The integrated circuit die 310 can be any type of integrated circuit die, such as a processor die, a memory die, a sensor die, or any other suitable type of integrated circuit die. In a specific embodiment, the die 310 is a power management IC (PMIC) die. The integrated circuit die 310 can be bonded to the package structure 100 using various techniques known in the art, such as solder bumps, wire bonding, flip chip bonding, or any other suitable bonding technique.

[0085] like Fig.18The configuration of the package structure depicted in is an example of how the redistribution structure 180 can be integrated within the package structure and how the integrated circuit die 310 can be included between the memory packages 306. Other configurations and arrangements of the redistribution structure 180, the integrated circuit die 310, and the memory packages 306 within the package structure are also possible, depending on the specific requirements of the package structure. For example, the redistribution structure 180 can include additional components or assemblies, such as through-vias, contacts, or other interconnect elements, depending on the specific requirements of the package structure 100. Similarly, the integrated circuit die 310 and the memory package 306 can include additional components or assemblies, depending on the specific requirements of the package structure.

[0086] Figures 12 to 18 The embodiments in are exemplary configurations, but the embodiments of the present disclosure are not limited to the specific configurations shown. For example, Fig.15 An embodiment may include a redistribution structure 180, Fig.17 and Fig.18 Embodiments of the present invention may include dielectric vias 242. Furthermore, each of the embodiments may undergo further processing to bond the interposer 110 to another structure, such as a package substrate having conductive connections coupled to substrate through vias 108 between the backside 102B of the interposer 110 and the package substrate. Furthermore, any embodiment including the interposer die 140 may include active devices, passive devices, or a combination thereof in the interposer die 140.

[0087] Other components and processes may also be included. For example, a test structure may be included to help perform verification testing on a 3D package or 3DIC device. The test structure may include, for example, a test pad formed in a redistribution layer or on a substrate, which allows testing of the 3D package or 3DIC, using probes and / or probe cards, etc. Verification testing may be performed on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein may be used in conjunction with a test method that incorporates intermediate verification of known good dies to increase yield and reduce costs.

[0088] In an embodiment, a semiconductor device may include an interposer. The semiconductor device may also include a plurality of chiplets directly bonded to the interposer. The device may further include a plurality of interposer dies directly bonded to the interposer adjacent to the plurality of chiplets, the plurality of interposer dies having substrate through vias. The device may additionally include a memory package located above at least one of the plurality of interposer dies and bonded to at least one of the plurality of interposer dies.

[0089] The described embodiments may also include one or more of the following features: a semiconductor device, wherein the interposer may include: a silicon material; a semiconductor device, wherein the plurality of chiplets include at least one processor chiplet and at least one memory chiplet; a semiconductor device, wherein the plurality of interposer dies include passive components selected from a group consisting of capacitors, resistors, and inductors; a semiconductor device, wherein the memory package may include a dynamic random access memory (DRAM) package; the semiconductor device may include a redistribution structure located above the interposer, the redistribution structure including a dielectric layer and a metallization layer; the semiconductor device, wherein the interposer may also include an interconnect structure having a plurality of dielectric layers and a metallization layer, the metallization layer being electrically coupled to the plurality of chiplets and the plurality of interposer dies; a semiconductor device, wherein the memory package is bonded to at least one of the plurality of interposer dies using a microbump bonding structure.

[0090] In an embodiment, the method may include directly bonding the plurality of chiplets to the interposer. The method may also include directly bonding the plurality of interposer dies to the interposer adjacent to the plurality of chiplets, wherein the plurality of interposer dies may include through substrate vias. The method may further include bonding the memory package over and to at least one of the plurality of interposer dies using a solder connection.

[0091] The described embodiments may also include one or more of the following features: a method wherein directly bonding a plurality of chiplets to an interposer may include metal-to-metal bonding and dielectric-to-dielectric bonding; a method wherein directly bonding a plurality of chiplets to an interposer includes bonding at least one processor chiplet and at least one memory chiplet; a method wherein directly bonding a plurality of interposer dies to an interposer includes integrating passive components into the plurality of interposer dies, the passive components being selected from a group consisting of capacitors, resistors, and inductors; a method wherein the plurality of interposer dies may include transistors; the method may include attaching a supporting substrate over the plurality of chiplets with a thermal interface material, the memory package being adjacent to the supporting substrate; the method may include forming an interconnect structure over the interposer, the interconnect structure having a dielectric layer and a metallization layer, the metallization layer of the interconnect structure being electrically coupled to the plurality of chiplets and the plurality of interposer dies; a method wherein bonding the memory package to at least one of the plurality of interposer dies includes using a microbump bonding structure.

[0092] In an embodiment, a method may include bonding a plurality of integrated circuit dies to an interposer using a direct bonding process, the interposer having a through substrate via and an interconnect structure above the through substrate via, the interconnect structure having a dielectric layer and a metallization layer. The method may also include bonding a memory package above the plurality of integrated circuit dies. The method may further include forming an electrical connection between the interconnect structure of the interposer and the memory package, the electrical connection being adjacent to the plurality of integrated circuit dies.

[0093] The described embodiments may also include one or more of the following features: the method may include bonding a plurality of interposer dies to an interposer using a direct bonding process, the electrical connection between the interconnect structure of the interposer and a memory package having substrate through-holes in the plurality of interposer dies; the method may include sealing a plurality of integrated circuit dies with a sealant and forming dielectric through-holes through the sealant, the electrical connection between the interconnect structure of the interposer and the memory package having dielectric through-holes; the method may attach a supporting substrate over the plurality of integrated circuit dies using a thermal interface material, the memory package being adjacent to the supporting substrate.

[0094] Some embodiments of the present application provide a semiconductor device comprising: an interposer; a plurality of chiplets directly bonded to the interposer; a plurality of interposer dies directly bonded to the interposer adjacent to the plurality of chiplets, the plurality of interposer dies comprising substrate through holes; and a memory package located above and bonded to at least one of the plurality of interposer dies.

[0095] In some embodiments, the interposer comprises a silicon material. In some embodiments, the plurality of chiplets comprises at least one processor chiplet and at least one memory chiplet. In some embodiments, the plurality of interposer dies comprises a passive component selected from the group consisting of a capacitor, a resistor, and an inductor. In some embodiments, the memory package comprises a dynamic random access memory package. In some embodiments, the semiconductor device further comprises a redistribution structure located above the interposer, the redistribution structure comprising a dielectric layer and a metallization layer. In some embodiments, the interposer further comprises an interconnect structure having a plurality of dielectric layers and a metallization layer, the metallization layer being electrically coupled to the plurality of chiplets and the plurality of interposer dies. In some embodiments, the memory package is bonded to at least one of the plurality of interposer dies using a microbump bonding structure.

[0096] Other embodiments of the present application provide a method for forming a semiconductor device, comprising: directly bonding a plurality of chiplets to an interposer; directly bonding a plurality of interposer dies to the interposer adjacent to the plurality of chiplets, wherein the plurality of interposer dies include substrate through-holes; and bonding a memory package over and to at least one of the plurality of interposer dies using a solder connection.

[0097] In some embodiments, directly bonding the plurality of chiplets to the interposer comprises metal-to-metal bonding and dielectric-to-dielectric bonding. In some embodiments, directly bonding the plurality of chiplets to the interposer comprises bonding at least one processor chiplet and at least one memory chiplet. In some embodiments, directly bonding the plurality of interposer dies to the interposer comprises integrating passive components into the plurality of interposer dies, the passive components being selected from the group consisting of capacitors, resistors, and inductors. In some embodiments, the plurality of interposer dies may comprise transistors. In some embodiments, the method further comprises attaching a support substrate over the plurality of chiplets with a thermal interface material, the memory package being adjacent to the support substrate. In some embodiments, the method further comprises forming an interconnect structure over the interposer, the interconnect structure comprising a dielectric layer and a metallization layer, the metallization layer of the interconnect structure being electrically coupled to the plurality of chiplets and the plurality of interposer dies. In some embodiments, bonding the memory package to at least one of the plurality of interposer dies comprises using a microbump bonding structure.

[0098] Still other embodiments of the present application provide a method for forming a semiconductor device, comprising: bonding a plurality of integrated circuit dies to an interposer using a direct bonding process, the interposer comprising a substrate through hole and an interconnect structure above the substrate through hole, the interconnect structure comprising a dielectric layer and a metallization layer; bonding a memory package above the plurality of integrated circuit dies; and forming an electrical connection between the interconnect structure of the interposer and the memory package, the electrical connection being adjacent to the plurality of integrated circuit dies.

[0099] In some embodiments, the method further comprises: bonding a plurality of interposer dies to the interposer using a direct bonding process, the electrical connection between the interconnect structure of the interposer and the memory package comprising substrate through-holes in the plurality of interposer dies. In some embodiments, the method further comprises: sealing the plurality of integrated circuit dies with an encapsulant; and forming dielectric through-holes through the encapsulant, the electrical connection between the interconnect structure of the interposer and the memory package comprising the dielectric through-holes. In some embodiments, a support substrate is attached over the plurality of integrated circuit dies using a thermal interface material, the memory package being adjacent to the support substrate.

[0100] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A semiconductor device, comprising: Intermediary layer; a plurality of chiplets directly bonded to the interposer; a plurality of interposer dies bonded directly to the interposer adjacent the plurality of chiplets, the plurality of interposer dies comprising through substrate vias; as well as A memory package is positioned over and bonded to at least one of the plurality of interposer dies.

2. The semiconductor device according to claim 1, wherein The interposer includes silicon material.

3. The semiconductor device according to claim 1, wherein The plurality of chiplets include at least one processor chiplet and at least one memory chiplet.

4. The semiconductor device according to claim 1, wherein: The plurality of interposer dies include passive components selected from the group consisting of capacitors, resistors, and inductors.

5. The semiconductor device according to claim 1, wherein The memory package includes a dynamic random access memory package. 6 . The semiconductor device of claim 1 , further comprising a redistribution structure located above the interposer, the redistribution structure comprising a dielectric layer and a metallization layer.

7. The semiconductor device according to claim 1, wherein The interposer also includes an interconnect structure having a plurality of dielectric layers and a metallization layer electrically coupled to the plurality of chiplets and the plurality of interposer dies.

8. The semiconductor device according to claim 1, wherein The memory package is bonded to the at least one of the plurality of interposer dies using a micro-bump bonding structure.

9. A method of forming a semiconductor device, comprising: Bonding multiple chiplets directly to an interposer; directly bonding a plurality of interposer dies to the interposer adjacent the plurality of chiplets, wherein the plurality of interposer dies include through substrate vias; as well as A memory package is bonded over and to at least one of the plurality of interposer dies using solder connections.

10. A method of forming a semiconductor device, comprising: bonding a plurality of integrated circuit dies to an interposer using a direct bonding process, the interposer comprising a through substrate via and an interconnect structure over the through substrate via, the interconnect structure comprising a dielectric layer and a metallization layer; bonding a memory package over the plurality of integrated circuit dies; as well as An electrical connection is formed between the interconnect structure of the interposer and the memory package, the electrical connection being adjacent to the plurality of integrated circuit dies.

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