High-voltage protection circuit applied to data transmission chip

Abstract

The invention discloses a high-voltage protection circuit applied to a data transmission chip. Multistage protection and dynamic bias are realized through collaborative design of an output driver protection circuit and a maximum value taking protection circuit. The output driver protection circuit adopts a differential input tube and two stages of CMOS high-voltage protection geminate transistors which are connected in series, and the drain end voltage stress of a short-channel transistor is reduced through graded voltage division, so that the output driver protection circuit can work safely under a 3.3 V power supply. The maximum value protection circuit dynamically selects the highest potential to provide bias for a low-threshold transistor substrate by comparing the analog power supply voltage with the output common-mode voltage, and performance degradation caused by abnormal substrate voltage is avoided. A specially designed tail current tube is linked with a control signal, a working mode is automatically switched when a chip starts / disables an analog power supply, and through a voltage distribution mechanism of two-stage protection pair tubes and a dynamic substrate bias technology, 6GSPS high-speed transmission under 3V common-mode voltage required by an HDMI2.0 protocol is ensured, and transistor breakdown is effectively prevented.

Description

Technical Field

[0001] The invention relates to a protection circuit, and in particular to a high-voltage protection circuit applied to a data transmission chip. Background Art

[0002] As the demand for data transmission rate increases, high-speed serial interface (HSS) technology gradually replaces parallel interface and becomes mainstream. SerDes (serializer / deserializer) as a core module needs to realize the conversion between high-speed differential signal and low-speed parallel signal. CN107346971A (A design method for full-swing output VCO delay unit for SerDes) discloses a full-swing VCO design under low-voltage power supply environment, which improves phase noise performance by optimizing MOS tube size and load structure, but it does not involve the breakdown protection problem of short channel transistors under high power supply voltage.

[0003] At the same time, low-speed serial interface technology was widely used in the early days of data transmission. As the data transmission rate requirements continued to increase, traditional low-speed serial interface technology gradually failed to meet the demand. In order to increase the total bandwidth of data, the first thing that comes to mind is to increase the data transmission bit width, that is, the parallel interface method. However, with the development of parallel interfaces, people have found that the shortage of chip IO numbers, crosstalk between parallel port data, and difficulties in data synchronization will limit the improvement of parallel interface data transmission rates.

[0004] At the same time, the SerDes technology used in high-speed serial links converts low-speed parallel signals into high-speed differential signals and sends them through serial links. At the same time, it can receive high-speed differential signals input in serial and correctly convert them into low-speed parallel signals, that is, complete the data parallel-to-serial and serial-to-parallel conversion. In order to meet the GSPS-level rate requirements, short-channel low-threshold voltage transistors are often used. However, in scenarios where the interface protocol requires a 3.3V common-mode voltage (such as PCIe, USB4, etc.), additional consideration must be given to how to effectively protect transistors with shorter channel lengths under high power supply voltage conditions of 3.3V to prevent short-channel transistors from being broken down.

[0005] At present, the industry needs to achieve a physical layer protection solution for short channel transistors under 3.3V power supply while meeting GSPS-level transmission rates. The existing technology focuses on signal integrity optimization. The existing technology CN119232142B clock data recovery circuit and CN118631409B SerDes data clock recovery method provide methods and structures for protection. However, it lacks a systematic design method for high-voltage working conditions and compatibility with short channel devices.

[0006] In view of the above-mentioned defects, the designer has actively carried out research and innovation in order to create a high-voltage protection circuit for data transmission chips to make it more valuable for industrial use. Summary of the invention

[0007] In order to solve the above technical problems, an object of the present invention is to provide a high voltage protection circuit applied to a data transmission chip.

[0008] The high-voltage protection circuit for a data transmission chip of the present invention includes an output driver protection circuit and a maximum value protection circuit. The output driver protection circuit includes a differential signal input tube composed of transistors MP1 and MP2, a first-level high-voltage protection pair of transistors MP3 and MP4, a second-level high-voltage protection pair of transistors MP5 and MP6, and a tail current tube composed of transistor MP7; The output terminal VNW of the maximum value protection circuit is connected to the input terminal VB of the output drive protection circuit, and is used to protect and bias the substrates of the transistors MP1, MP2, and MP7 in the output drive protection circuit; The gate terminal of the transistor MP1 is connected to the differential input signal VIN, and the gate terminal of the transistor MP2 is connected to the differential input signal VIP; the gate terminals of the transistor MP3 and the transistor MP4 are connected to the protection bias voltage PBHV1; The maximum value protection circuit comprises a transistor MN1, a transistor MN2, a transistor MP8, a transistor MP9, a transistor MP10, a transistor MP11, a transistor MP12, a transistor MP13, and a transistor MP14, wherein: The gate terminal and the source terminal of the transistor MN1 are both connected to the ground GND, and the drain terminal is connected to the source terminal of the transistor MN2. The gate terminal of the transistor MN2 is connected to the protection bias voltage VN, the source terminal thereof is connected to the drain terminal of the transistor MN1, the drain terminal thereof is respectively connected to the drain terminals of the transistor MP8 and the transistor MP11, and is also connected to the output control signal V3SW. The source terminal of the transistor MP8 is connected to the protection bias voltage VP, the gate terminal is connected to its own drain terminal and the drain terminals of the transistor MP10 and the transistor MN2, and the drain terminal is also connected to the output control signal V3SW. The gate terminal of the transistor MP9 is connected to the protection bias voltage VP, the source terminal is connected to the output common mode voltage VOUTCM, and the drain terminal is connected to the source terminal of the transistor MP10. The gate terminal of the transistor MP10 is connected to the analog power supply voltage AVDD, the source terminal thereof is connected to the drain terminal of the transistor MP9, the drain terminal thereof is connected to the drain terminals of the transistors MP8 and MN2, and the drain terminal is also connected to the output control signal V3SW. The gate terminal of the transistor MP11 is connected to the protection bias voltage VP, the source terminal is connected to the output common mode voltage VOUTCM, and the drain terminal is connected to the source terminal of the transistor MP12. The gate terminal of the transistor MP12 is connected to the analog power supply voltage AVDD, the source terminal thereof is connected to the drain terminal of the transistor MP11, the drain terminal thereof is connected to the drain terminals of the transistors MP13 and MP14, and the source terminal thereof is also connected to the output voltage VNW; The gate terminal of the transistor MP13 is connected to the output control signal V3SW, the source terminal is connected to the analog power supply voltage AVDD and the source terminal of the transistor MP14, the drain terminal is connected to the drain terminals of the transistors MP12 and MP14, and the drain terminal is also connected to the output voltage VNW; The gate terminal of the transistor MP14 is connected to its own drain terminal and the drain terminals of the transistors MP12 and MP13 , and the source terminal of the transistor MP14 is connected to the analog power supply voltage AVDD and the source terminal of the transistor MP13 .

[0009] Furthermore, in the above-mentioned high-voltage protection circuit applied to the data transmission chip, the transistors MP1, MP2 and MP7 are short-channel low threshold voltage transistors, and the transistors MP3, MP4, MP5 and MP6 are CMOS 0.18μm standard threshold voltage transistors.

[0010] Furthermore, in the above-mentioned high-voltage protection circuit applied to the data transmission chip, the source end of the transistor MP3 is connected to the drain end of the transistor MP1, and the drain end of the transistor MP3 is connected to the source end of the transistor MP5. The source terminal of the transistor MP4 is connected to the drain terminal of the transistor MP2, and the drain terminal of the transistor MP4 is connected to the source terminal of the transistor MP6. The gate terminal of the transistor MP5 is connected to the protection bias voltage PBHV2, and the drain terminal thereof is connected to the differential output signal VOUTP. The gate terminal of the transistor MP6 is connected to the protection bias voltage PBHV2, and the drain terminal thereof is connected to the differential output signal VOUTN. The gate terminal of the transistor MP7 is connected to the bias voltage VBP, the source terminal is connected to the analog power supply AVDD, and the drain terminal is connected to the source terminals of the transistor MP1 and the transistor MP2.

[0011] Furthermore, in the above-mentioned high-voltage protection circuit applied to the data transmission chip, during the operation of the first-level high-voltage protection pair, the drain voltage of the transistor MP1 and the transistor MP2 is: VD(MP1 / MP2)=VG(MP3 / MP4)+|VGS(MP3 / MP4)|=VPBHV1+|VGS(MP3 / MP4)|.

[0012] By setting the value of the bias voltage PBHV1, the drain voltage of the transistor MP1 and the transistor MP2 is in a suitable range, so that they are not broken down and work normally in the saturation region; During the operation of the second-level high-voltage protection pair, the drain voltage of transistor MP3 and transistor MP4 is: VD(MP3 / MP4)=VG(MP5 / MP6)+|VGS(MP5 / MP5)|=VPBHV2+|VGS(MP5 / MP6)|.

[0013] By setting the value of the bias voltage PBHV2, the drain voltages of the transistors MP3 and MP4 are in a suitable range, so that they are not broken down and work normally in the saturation region. The transistors MP5 and MP6 are also not broken down after being connected to the corresponding differential output signals VOUTP and VOUTN.

[0014] Furthermore, the above-mentioned high-voltage protection circuit is applied to the data transmission chip, wherein the maximum value protection circuit reasonably biases the substrate of the low threshold voltage PMOS tube in the SerDes circuit when the data transmission chip is not powered by an analog power supply, thereby preventing the PMOS tube from malfunctioning in this working mode due to the substrate voltage being lower than the source voltage.

[0015] By means of the above scheme, the present invention has at least the following advantages: 1. It can realize effective hierarchical voltage protection, realize voltage division by connecting two-stage PMOS tubes in series, and reduce the drain voltage stress of key transistors.

[0016] 2. Dynamic substrate bias can be realized, and the highest potential can be automatically selected through the maximum value circuit to provide a stable bias for the low threshold PMOS substrate.

[0017] 3. It can achieve dual-mode compatibility. Relying on the output control signal V3SW, it can realize seamless switching of power supply modes to ensure reliability in different scenarios.

[0018] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention and implement it according to the contents of the specification, the following is a detailed description of the preferred embodiments of the present invention in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 Schematic diagram of the output driver protection circuit.

[0020] Figure 2 It is a structural diagram of the maximum value protection circuit.

[0021] Figure 3 It is a schematic diagram of combining the high-voltage protection circuit of the present application with the data transmission chip. DETAILED DESCRIPTION

[0022] The specific implementation of the present invention is further described in detail below in conjunction with the accompanying drawings and examples. The following examples are used to illustrate the present invention, but are not intended to limit the scope of the present invention.

[0023] like Figures 1 to 3 The high-voltage protection circuit applied to the data transmission chip is different in that the circuit includes an output driver protection circuit and a maximum value protection circuit. The output driver protection circuit includes a differential signal input tube composed of transistors MP1 and MP2, and also includes a first-level high-voltage protection pair of transistors MP3 and MP4, and also includes a second-level high-voltage protection pair of transistors MP5 and MP6. In this way, multi-level protection can be achieved. In addition, the tail current tube composed of transistor MP7 is included to avoid accidental breakdown. During the implementation, the output terminal VNW of the maximum value protection circuit is connected to the input terminal VB of the output drive protection circuit, which is used to protect and reasonably bias the substrates of transistors MP1, MP2, and MP7 in the output drive protection circuit. At the same time, the gate terminal of transistor MP1 is connected to the differential input signal VIN, and the gate terminal of transistor MP2 is connected to the differential input signal VIP; the gate terminals of transistors MP3 and MP4 are connected to the protection bias voltage PBHV1.

[0024] The maximum value protection circuit adopted by the present invention includes transistor MN1, transistor MN2, transistor MP8, transistor MP9, transistor MP10, transistor MP11, transistor MP12, transistor MP13, and transistor MP14. Specifically, the gate terminal and source terminal of transistor MN1 are both connected to the ground GND, and its drain terminal is connected to the source terminal of transistor MN2. The gate terminal of transistor MN2 is connected to the protection bias voltage VN, its source terminal is connected to the drain terminal of transistor MN1, and its drain terminal is respectively connected to the drain terminals of transistor MP8 and transistor MP11, and is also connected to the output control signal V3SW, so as to receive the corresponding control signal.

[0025] At the same time, the source terminal of transistor MP8 is connected to the protection bias voltage VP, the gate terminal is connected to its own drain terminal and the drain terminals of transistor MP10 and transistor MN2, and the drain terminal is also connected to the output control signal V3SW. The gate terminal of transistor MP9 is connected to the protection bias voltage VP, the source terminal is connected to the output common mode voltage VOUTCM, and the drain terminal is connected to the source terminal of transistor MP10.

[0026] The gate terminal of transistor MP10 is connected to the analog power supply voltage AVDD, the source terminal is connected to the drain terminal of transistor MP9, the drain terminal is connected to the drain terminals of transistor MP8 and transistor MN2, and the drain terminal is also connected to the output control signal V3SW. Similarly, it is convenient to control by the output control signal V3SW later.

[0027] During the implementation, the gate terminal of transistor MP11 is connected to the protection bias voltage VP, the source terminal is connected to the output common mode voltage VOUTCM, and the drain terminal is connected to the source terminal of transistor MP12. The gate terminal of transistor MP12 is connected to the analog power supply voltage AVDD, the source terminal is connected to the drain terminal of transistor MP11, the drain terminal is connected to the drain terminals of transistors MP13 and MP14, and the source terminal is also connected to the output voltage VNW, which is convenient for the introduction of the output voltage VNW. At the same time, the gate terminal of transistor MP13 is connected to the output control signal V3SW, the source terminal is connected to the analog power supply voltage AVDD and the source terminal of transistor MP14, the drain terminal is connected to the drain terminals of transistors MP12 and MP14, and the drain terminal is also connected to the output voltage VNW. Furthermore, the gate terminal of transistor MP14 is connected to its own drain terminal and the drain terminals of transistors MP12 and MP13, and the source terminal is connected to the analog power supply voltage AVDD and the source terminal of transistor MP13.

[0028] In combination with a preferred embodiment of the present invention, transistor MP1, transistor MP2, and transistor MP7 are short channel low threshold voltage transistors. Transistor MP1 and transistor MP2 are key transistors in the entire signal transmission link, and their operating speed directly affects the data transmission rate of the entire SerDes circuit. Therefore, faster short channel devices are preferred. During use, the substrate terminals of transistors MP1 and MP2 are connected to the input terminal VB of the output drive protection circuit and then biased. In addition, transistors MP3, MP4, MP5, and MP6 are CMOS 0.18μm standard threshold voltage transistors. It should be noted that since the substrates of transistors MP3 to MP6 are all normally biased and can be directly connected to the analog power supply AVDD, Figure 1 The connection at the substrate end is not marked.

[0029] Further, the source terminal of transistor MP3 is connected to the drain terminal of transistor MP1, and the drain terminal is connected to the source terminal of transistor MP5. The source terminal of transistor MP4 is connected to the drain terminal of transistor MP2, and the drain terminal is connected to the source terminal of transistor MP6. At the same time, considering the control needs of the corresponding differential signal, the gate terminal of transistor MP5 is connected to the protection bias voltage PBHV2, and the drain terminal is connected to the differential output signal VOUTP. The gate terminal of transistor MP6 is connected to the protection bias voltage PBHV2, and the drain terminal is connected to the differential output signal VOUTN. Considering the convenience of introducing the analog power supply AVDD, the gate terminal of transistor MP7 is connected to the bias voltage VBP, the source terminal is connected to the analog power supply AVDD, and the drain terminal is connected to the source terminals of transistors MP1 and MP2.

[0030] In order to achieve effective high-voltage protection, during the operation of the first-level high-voltage protection pair adopted by the present invention, the drain voltage of the transistor MP1 and the transistor MP2 is: VD(MP1 / MP2)=VG(MP3 / MP4)+|VGS(MP3 / MP4)|=VPBHV1+|VGS(MP3 / MP4)|.

[0031] In this way, by setting the value of the bias voltage PBHV1, the drain voltage of transistors MP1 and MP2 can be in a suitable range, so that they are not broken down and work normally in the saturation region. At this time, since transistors MP3 and MP4 are CMOS 0.18μm standard threshold voltage transistors, if they are directly connected to VOUTP / VOUTN, the first-level high-voltage protection tube itself still has the risk of being broken down, making the protection function invalid.

[0032] Furthermore, during the operation of the second-level high-voltage protection pair, the drain voltage of transistor MP3 and transistor MP4 is: VD(MP3 / MP4)=VG(MP5 / MP6)+|VGS(MP5 / MP5)|=VPBHV2+|VGS(MP5 / MP6)|.

[0033] In this way, by setting the value of the bias voltage PBHV2, the drain voltage of the transistor MP3 and the transistor MP4 can be in a suitable range, so that they are not broken down and work normally in the saturation region. At the same time, the transistor MP5 and the transistor MP6 can be connected to the corresponding differential output signal VOUTP and the differential output signal VOUTN without being broken down.

[0034] To this end, by adopting the solution of the present invention, after being protected by a two-stage high-voltage protection circuit, the short-channel-length low-threshold voltage transistors MP1, MP2, and MP7 and the CMOS 0.18μm standard threshold voltage transistors MP3, MP4, MP5, and MP6 used for protection can all operate normally under a power supply voltage of 3.3V without the risk of breakdown.

[0035] In the present invention, transistors MP1 and MP2 constituting the differential input pair are key transistors in the entire signal transmission link, and their operating speed is directly related to the data transmission rate that the overall SerDes circuit can achieve. Taking the HDMI2.0 data transmission protocol as an example, the protocol stipulates that the common mode voltage of data transmission is 3V, that is, the common mode level of VOUTP / VOUTN is assumed to be 3V during circuit design. If the transistors MP1 and MP2 are not protected at this time, but the drain ends of the transistors MP1 and MP2 are directly connected to VOUTP / VOUTN, the 3V common mode voltage after connecting to the external port impedance will directly break down the short channel transistors MP1 and MP2, and the circuit will fail to work.

[0036] Looking further, by adopting the maximum value protection circuit, when the data transmission chip does not use analog power supply, the diode of the ESD protection circuit in the chip pin provides the analog circuit with a power supply voltage that does not generate current. To this end, the substrate of the low threshold voltage PMOS tube in the SerDes circuit can be reasonably biased to prevent the PMOS tube from abnormal in this working mode due to the substrate voltage being lower than the source voltage. In this way, problems such as reduced on-current, reduced driving capability, and increased leakage current can be effectively avoided.

[0037] In other words, the main function of the maximum protection circuit is to properly bias the substrate of the low threshold voltage PMOS tube in the SerDes circuit when the data transmission chip is not powered by analog power. In different working modes, the substrate of the low threshold voltage PMOS tube is automatically connected to the actual highest potential in the circuit. The specific working principle is as follows: When the data transmission chip is powered by a 3.3V analog power supply, the highest potential of the circuit is the analog power supply voltage 3.3V. In this working mode, with the level shift of the control signal, the substrate of the low threshold voltage PMOS tube can be directly connected to 3.3V without the risk of breakdown. In this working mode, the transistor MP10 is turned off, and the protection bias voltage VP is connected to the output control signal V3SW through the transistor MP8. At this time, the transistor MN1 and the transistor MN2 are in a reasonable voltage bias range and there is no risk of breakdown. During this period, the output control signal V3SW controls the transistor MP13 to turn on, so that the transistor MP12 is turned off, and the output voltage VNW is connected to the analog power supply voltage AVDD and connected to the substrate of the low threshold voltage PMOS tube.

[0038] When the data transmission chip is not powered by a 3.3V analog power supply, the AVDD pin voltage is less than the output common-mode voltage VOUTCM, that is, the highest potential of the circuit is the output common-mode voltage VOUTCM. In this working mode, if the substrate of the low threshold voltage PMOS tube is directly connected to the analog power supply voltage AVDD, problems such as reduced on-current, reduced driving capability, and increased leakage current will occur due to the substrate voltage being lower than the source voltage. In this working mode, transistor MP10 is turned on, and the output common-mode voltage VOUTCM is connected to the output control signal V3SW through transistors MP9 and MP10, and transistor MP8 is turned off. At the same time, the MN2 transistor will not be at risk of breakdown because the gate terminal is connected to the protection bias voltage VN. During this period, the output control signal V3SW controls the MP13 transistor to be turned off, which is lower than the analog power supply voltage AVDD in the output common-mode voltage VOUTCM, and can control the transistor MP12 to be turned on. As a result, the output common-mode voltage VOUTCM is connected to the output voltage VNW through transistors MP11 and MP12, and transistor MP14 is turned off.

[0039] The working principle of the present invention is as follows: like Figure 3 As shown, the circuit of the present invention is combined with a data transmission chip (TX, Transmitter) supporting the HDMI2.0 protocol. The data transmission chip requires a data output common mode of 2.8 to 3.2V and a data transmission rate of 6GSPS. The main circuit of the data transmission chip is composed of modules such as an input register, a protocol layer, a parallel-to-serial conversion circuit, a differential signal transmitter, and a PLL clock. During implementation, the input clock is connected to the PLL clock. Thus, the PLL clock can be constructed to provide a low-speed parallel data clock and a high-speed serial data clock to the circuit.

[0040] The workflow in actual application is as follows: First, the input register buffers and stores the input data. After that, the protocol layer encodes the input low-speed parallel data in different formats according to the HDMI2.0 interface protocol. This ensures that the data will not stop jumping for a long time, preventing possible erroneous sampling in the clock recovery circuit (CDR) in the data receiving chip (RX).

[0041] Next, the parallel-to-serial conversion circuit converts the low-speed parallel data encoded by the protocol layer into a high-speed low-voltage signal, that is, high-speed serial data, to realize the most critical parallel-to-serial conversion function in TX. At the same time, the differential signal transmitter drives the high-speed differential signal, which is sent to the input IO port of the data receiving chip as the output of the data transmission chip. In this module, the speed of the transistor plays a key role in the data transmission rate of the data transmission chip as a whole. For this reason, the present invention uses transistors with short channel lengths in circuit design. The high-voltage protection circuit proposed in this application protects the short channel length transistors used in this module.

[0042] The maximum value protection circuit during implementation first selects the larger voltage of the analog power supply voltage AVDD or the common mode voltage VOUTCM according to the actual working state of the chip. Then, the substrate of the low threshold voltage transistor in the output drive protection circuit is biased. In this way, after being properly biased, the output drive protection circuit can further protect the gate, source, and drain of the short channel length transistor in the differential signal transmitter to ensure that there will be no defect of excessive voltage causing the transistor to be broken down.

[0043] It can be seen from the simulation verification that the data transmission chip with the high-voltage protection circuit constructed by the present application method can support the data output common mode voltage of 2.8 to 3.2V required by the HDMI2.0 protocol. At the same time, it can meet the data transmission rate of 6GSPS. In addition, it can support two different working modes at the same time, and choose whether to use an external 3.3V analog power supply voltage to power the data transmission chip. During use, all short-channel transistors in the data transmission chip will not be broken down within the PVT fluctuation range and will be effectively protected.

[0044] It can be seen from the above textual description and the accompanying drawings that the present invention has the following advantages: 1. It can realize effective hierarchical voltage protection, realize voltage division by connecting two-stage PMOS tubes in series, and reduce the drain voltage stress of key transistors.

[0045] 2. Dynamic substrate bias can be realized, and the highest potential can be automatically selected through the maximum value circuit to provide a stable bias for the low threshold PMOS substrate.

[0046] 3. It can achieve dual-mode compatibility. Relying on the output control signal V3SW, it can realize seamless switching of power supply modes to ensure reliability in different scenarios.

[0047] In addition, the indicated orientations or positional relationships described in the present invention are all based on the orientations or positional relationships shown in the accompanying drawings and are only for the convenience of describing the present invention and simplifying the description. They do not indicate or imply that the device or structure referred to must have a specific orientation or be operated with a specific orientation structure. Therefore, they cannot be understood as limitations on the present invention.

[0048] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. It should be pointed out that a person skilled in the art can make several improvements and modifications without departing from the technical principles of the present invention, and these improvements and modifications should also be regarded as within the scope of protection of the present invention.

Claims

1. A high voltage protection circuit for a data transmission chip, characterized in that: Including output driver protection circuit and maximum value protection circuit, The output driver protection circuit includes a differential signal input tube composed of transistors MP1 and MP2, a first-level high-voltage protection pair of transistors MP3 and MP4, a second-level high-voltage protection pair of transistors MP5 and MP6, and a tail current tube composed of transistor MP7; The output terminal VNW of the maximum value protection circuit is connected to the input terminal VB of the output drive protection circuit, and is used to protect and bias the substrates of the transistors MP1, MP2, and MP7 in the output drive protection circuit; The gate terminal of the transistor MP1 is connected to the differential input signal VIN, the gate terminal of the transistor MP2 is connected to the differential input signal VIP; the gate terminals of the transistor MP3 and the transistor MP4 are connected to the protection bias voltage PBHV1.

2. The high voltage protection circuit for data transmission chip according to claim 1, characterized in that: The maximum value protection circuit comprises a transistor MN1, a transistor MN2, a transistor MP8, a transistor MP9, a transistor MP10, a transistor MP11, a transistor MP12, a transistor MP13, and a transistor MP14, wherein: The gate terminal and the source terminal of the transistor MN1 are both connected to the ground GND, and the drain terminal is connected to the source terminal of the transistor MN2. The gate terminal of the transistor MN2 is connected to the protection bias voltage VN, the source terminal thereof is connected to the drain terminal of the transistor MN1, the drain terminal thereof is respectively connected to the drain terminals of the transistor MP8 and the transistor MP11, and is also connected to the output control signal V3SW. The source terminal of the transistor MP8 is connected to the protection bias voltage VP, the gate terminal is connected to its own drain terminal and the drain terminals of the transistor MP10 and the transistor MN2, and the drain terminal is also connected to the output control signal V3SW. The gate terminal of the transistor MP9 is connected to the protection bias voltage VP, the source terminal is connected to the output common mode voltage VOUTCM, and the drain terminal is connected to the source terminal of the transistor MP10. The gate terminal of the transistor MP10 is connected to the analog power supply voltage AVDD, the source terminal thereof is connected to the drain terminal of the transistor MP9, the drain terminal thereof is connected to the drain terminals of the transistors MP8 and MN2, and the drain terminal is also connected to the output control signal V3SW. The gate terminal of the transistor MP11 is connected to the protection bias voltage VP, the source terminal is connected to the output common mode voltage VOUTCM, and the drain terminal is connected to the source terminal of the transistor MP12. The gate terminal of the transistor MP12 is connected to the analog power supply voltage AVDD, the source terminal thereof is connected to the drain terminal of the transistor MP11, the drain terminal thereof is connected to the drain terminals of the transistors MP13 and MP14, and the source terminal thereof is also connected to the output voltage VNW; The gate terminal of the transistor MP13 is connected to the output control signal V3SW, the source terminal is connected to the analog power supply voltage AVDD and the source terminal of the transistor MP14, the drain terminal is connected to the drain terminals of the transistors MP12 and MP14, and the drain terminal is also connected to the output voltage VNW; The gate terminal of the transistor MP14 is connected to its own drain terminal and the drain terminals of the transistors MP12 and MP13, and the source terminal is connected to the analog power supply voltage AVDD and the source terminal of the transistor MP13; The transistors MP1, MP2 and MP7 are short channel low threshold voltage transistors, and the transistors MP3, MP4, MP5 and MP6 are CMOS 0.18 μm standard threshold voltage transistors.

3. The high voltage protection circuit for data transmission chip according to claim 1, characterized in that: The source terminal of the transistor MP3 is connected to the drain terminal of the transistor MP1, and the drain terminal of the transistor MP3 is connected to the source terminal of the transistor MP5. The source terminal of the transistor MP4 is connected to the drain terminal of the transistor MP2, and the drain terminal of the transistor MP4 is connected to the source terminal of the transistor MP6. The gate terminal of the transistor MP5 is connected to the protection bias voltage PBHV2, and the drain terminal thereof is connected to the differential output signal VOUTP. The gate terminal of the transistor MP6 is connected to the protection bias voltage PBHV2, and the drain terminal thereof is connected to the differential output signal VOUTN. The gate terminal of the transistor MP7 is connected to the bias voltage VBP, the source terminal is connected to the analog power supply AVDD, and the drain terminal is connected to the source terminals of the transistor MP1 and the transistor MP2.

4. The high voltage protection circuit for data transmission chip according to claim 1, characterized in that: During the operation of the first-level high-voltage protection pair, the drain voltage of transistor MP1 and transistor MP2 is: VD(MP1 / MP2)=VG(MP3 / MP4)+|VGS(MP3 / MP4)|=VPBHV1+|VGS(MP3 / MP4)|, By setting the value of the bias voltage PBHV1, the drain voltage of the transistor MP1 and the transistor MP2 is in a suitable range, so that they are not broken down and work normally in the saturation region; During the operation of the second-level high-voltage protection pair, the drain voltage of transistor MP3 and transistor MP4 is: VD(MP3 / MP4)=VG(MP5 / MP6)+|VGS(MP5 / MP5)|=VPBHV2+|VGS(MP5 / MP6) |, By setting the value of the bias voltage PBHV2, the drain voltages of the transistors MP3 and MP4 are in a suitable range, so that they are not broken down and work normally in the saturation region. The transistors MP5 and MP6 are also not broken down after being connected to the corresponding differential output signals VOUTP and VOUTN.

5. The high voltage protection circuit for data transmission chip according to claim 1, characterized in that: The maximum value protection circuit reasonably biases the substrate of the low threshold voltage PMOS tube in the SerDes circuit when the data transmission chip is not powered by an analog power supply, thereby preventing the PMOS tube from being abnormal in this working mode due to the substrate voltage being lower than the source voltage.

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