Switching circuit and control method thereof

Abstract

The embodiment of the invention provides a switching circuit and a control method thereof. The switch circuit comprises a switch bridge arm which comprises a first switch transistor, a second switch transistor, a first capacitor, a second capacitor and an auxiliary switch assembly. The auxiliary switch assembly comprises a third switch transistor, a resonant capacitor and a resonant inductor. Wherein the resonant capacitor is connected in parallel with the third switch transistor, and the resonant inductor is connected in series with the third switch transistor; the first switch transistor is connected in series with the second switch transistor, the first switch transistor is connected in parallel with the first capacitor, and the second switch transistor is connected in parallel with the second capacitor; the auxiliary switch assembly is connected in parallel with the second switch transistor through a first end of the auxiliary switch assembly and a second end of the auxiliary switch assembly.

Description

Technical Field

[0001] The present invention relates to the field of electronic technology, and in particular to a switch circuit and a control method thereof. Background Art

[0002] Pulse Width Modulation (PWM) is a very typical voltage signal modulation strategy, which is widely used in digital power supply, Class D amplifier and other fields.

[0003] Digital power supplies or Class D amplifiers based on PWM modulation schemes usually have higher transfer efficiency, which is one of their significant advantages. However, the disadvantage of PWM is that compared with traditional linear power supplies or amplifiers, the ripple noise of PWM topology is greater. Although increasing the switching frequency can make the ripple base frequency higher and easier to filter out, it also increases the switching loss accordingly, which is particularly serious in high-voltage scenarios. Summary of the invention

[0004] Embodiments of the present disclosure provide a switch circuit and a control method thereof.

[0005] According to a first aspect of an embodiment of the present disclosure, a switching circuit is provided, wherein the switching circuit comprises at least one switching bridge arm, wherein the switching bridge arm comprises: a first switching transistor, a second switching transistor, a first capacitor, a second capacitor, and an auxiliary switching component; the auxiliary switching component comprises: a third switching transistor, a resonant capacitor, and a resonant inductor; wherein,

[0006] The resonant capacitor is connected in parallel with the third switch transistor, the resonant inductor is connected in series with the third switch transistor, the end of the resonant inductor that is not connected to the third switch transistor is the first end of the auxiliary switch component, and the end of the third switch transistor that is connected to the resonant capacitor and not connected to the resonant inductor is the second end of the auxiliary switch component;

[0007] The first switch transistor is connected in series with the second switch transistor, the first switch transistor is connected in parallel with the first capacitor, and the second switch transistor is connected in parallel with the second capacitor; the auxiliary switch component is connected in parallel with the second switch transistor through the first end of the auxiliary switch component and the second end of the auxiliary switch component; the series connection point between the first switch transistor and the second switch transistor is the output node of the switch bridge arm.

[0008] In some embodiments, the first switch transistor and the second switch transistor are turned on alternately, and a turn-on period of the first switch transistor and a turn-on period of the second switch transistor are separated from each other by a first predetermined time interval;

[0009] The third switching transistor is turned on at a first moment in a conduction period of the first switching transistor, and is turned off at a second moment in a conduction period of the second switching transistor, wherein the first moment includes a moment when the resonant capacitor and the resonant inductor resonate and a voltage difference across the resonant capacitor is within a predetermined voltage difference range, and the second moment includes a moment in the conduction period of the second switching transistor that is a second predetermined interval away from the conduction moment of the second switching transistor.

[0010] In some embodiments, the first terminal of the first switch transistor is connected to a first power supply voltage signal; the second terminal of the first switch transistor is connected to a first terminal of the second switch transistor; the second terminal of the second switch transistor is connected to a second power supply voltage signal;

[0011] Two ends of the first capacitor are connected to the first end of the first switch transistor and the second end of the first switch transistor respectively, and two ends of the second capacitor are connected to the first end of the second switch transistor and the second end of the second switch transistor respectively;

[0012] The first end of the resonant inductor is connected to the first end of the second switch transistor; the second end of the resonant inductor is connected to the first end of the third switch transistor; the second end of the third switch transistor is connected to the second power supply voltage signal; the two ends of the resonant capacitor are respectively connected to the first end of the third switch transistor and the second end of the third switch transistor;

[0013] The control end of the first switch transistor is connected to a first switch signal to turn on or off the first switch transistor, the control end of the second switch transistor is connected to a second switch signal to turn on or off the second switch transistor, and the control end of the third switch transistor is connected to a third switch signal to turn on or off the third switch transistor.

[0014] In some embodiments, the switch bridge arm further includes a switch limit component for turning on the third switch transistor when the third switch signal indicates turning on the third switch transistor and the voltage difference across the resonant capacitor is within a predetermined voltage difference range.

[0015] In some embodiments, the switch limit assembly includes: a comparator and an AND gate, wherein:

[0016] The inverting input terminal of the comparator is connected to the first terminal of the third switch transistor, and the positive input terminal of the comparator is connected to a reference voltage signal, wherein the voltage value of the reference voltage signal is within the predetermined voltage difference range;

[0017] The output end of the comparator is connected to the first input end of the AND gate, the second input end of the AND gate is connected to the third switch signal, and the output end of the AND gate is connected to the control end of the third switch transistor.

[0018] In some embodiments, the first terminal of the second switch transistor is connected to the first power supply voltage signal; the second terminal of the second switch transistor is connected to the first terminal of the first switch transistor; the second terminal of the first switch transistor is connected to the second power supply voltage signal;

[0019] Two ends of the first capacitor are connected to the first end of the first switch transistor and the second end of the first switch transistor respectively, and two ends of the second capacitor are connected to the first end of the second switch transistor and the second end of the second switch transistor respectively;

[0020] The first end of the resonant inductor is connected to the first end of the second switch transistor; the second end of the resonant inductor is connected to the first end of the third switch transistor; the second end of the third switch transistor is connected to the second end of the second switch transistor; the two ends of the resonant capacitor are respectively connected to the first end of the third switch transistor and the second end of the third switch transistor;

[0021] The control end of the first switch transistor is connected to a first switch signal to turn on or off the first switch transistor, the control end of the second switch transistor is connected to a second switch signal to turn on or off the second switch transistor, and the control end of the third switch transistor is connected to a third switch signal to turn on or off the third switch transistor.

[0022] In some embodiments, the first terminal of the second switch transistor is connected to the first power supply voltage signal; the second terminal of the second switch transistor is connected to the first terminal of the first switch transistor; the second terminal of the first switch transistor is connected to the second power supply voltage signal;

[0023] Two ends of the first capacitor are connected to the first end of the first switch transistor and the second end of the first switch transistor respectively, and two ends of the second capacitor are connected to the first end of the second switch transistor and the second end of the second switch transistor respectively;

[0024] The first end of the third switch transistor is connected to the first power supply voltage signal; the second end of the third switch transistor is connected to the first end of the resonant inductor; the second end of the resonant inductor is connected to the second end of the second switch transistor; the two ends of the resonant capacitor are respectively connected to the first end of the third switch transistor and the second end of the third switch transistor;

[0025] The control end of the first switch transistor is connected to a first switch signal to turn on or off the first switch transistor, the control end of the second switch transistor is connected to a second switch signal to turn on or off the second switch transistor, and the control end of the third switch transistor is connected to a third switch signal to turn on or off the third switch transistor.

[0026] In some embodiments, the first switch transistor, the second switch transistor and the second switch transistor are all N-type MOS transistors;

[0027] The first end of the first switch transistor is a drain, the second end of the first switch transistor is a source, and the control end of the first switch transistor is a gate;

[0028] The first end of the second switch transistor is a drain, the second end of the second switch transistor is a source, and the control end of the second switch transistor is a gate;

[0029] The first end of the third switch transistor is a drain, the second end of the third switch transistor is a source, and the control end of the third switch transistor is a gate.

[0030] In some embodiments, the switch circuit comprises a full-bridge switch circuit, and the full-bridge switch circuit comprises two switch bridge arms;

[0031] or

[0032] The switch circuit includes a three-phase switch circuit, and the full-bridge switch circuit includes three switch bridge arms.

[0033] According to a second aspect of an embodiment of the present disclosure, a switch circuit control method is provided, which is applied to the switch circuit described in the first aspect. The method includes:

[0034] Controlling the first switch transistor and the second switch transistor to be turned on alternately, wherein a conduction period of the first switch transistor and a conduction period of the second switch transistor are separated by a first predetermined interval;

[0035] The third switch transistor is controlled to be turned on at a first moment in a conduction period of the first switch transistor, and to be turned off at a second moment in a conduction period of the second switch transistor, wherein the first moment includes a moment when the resonant capacitor and the resonant inductor resonate so that the voltage difference across the resonant capacitor is within a predetermined voltage difference range, and the second moment includes a moment in the conduction period of the second switch transistor that is a second predetermined interval away from the conduction moment of the second switch transistor.

[0036] According to a third aspect of an embodiment of the present disclosure, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the processor implements the switch circuit control method as described in the second aspect.

[0037] According to a fourth aspect of the embodiments of the present disclosure, an electronic circuit is provided, characterized in that the electronic circuit comprises: a control device;

[0038] The control device is used to execute the switch circuit control method as described in the second aspect.

[0039] According to an embodiment of the present disclosure, a switch circuit is disclosed, the switch circuit includes at least one switch bridge arm, wherein the switch bridge arm includes: a first switch transistor, a second switch transistor, a first capacitor, a second capacitor, and an auxiliary switch component; the auxiliary switch component includes: a third switch transistor, a resonant capacitor, and a resonant inductor; wherein the resonant capacitor is connected in parallel with the third switch transistor, the resonant inductor is connected in series with the third switch transistor, the end of the resonant inductor not connected with the third switch transistor is the first end of the auxiliary switch component, and the end of the third switch transistor connected with the resonant capacitor and the resonant inductor is the second end of the auxiliary switch component; the first switch transistor is connected in series with the second switch transistor, the first switch transistor is connected in parallel with the first capacitor, and the second switch transistor is connected in parallel with the second capacitor; the auxiliary switch component is connected in parallel with the second switch transistor through the first end of the auxiliary switch component and the second end of the auxiliary switch component; the first switch transistor and the second switch transistor are connected in series at the output node of the switch bridge arm. The resonant capacitor and the resonant inductor resonate, so that the resonant capacitor generates a "zero voltage" opportunity. When the voltage at both ends of the capacitor is "zero voltage", the voltage at both ends of the capacitor is within a predetermined voltage difference range (such as 0V), that is, the voltage difference between the first end and the second end of the third switch transistor is within a predetermined voltage difference range. The smaller the maximum voltage value within the predetermined voltage difference range, the smaller the switching loss of the switch transistor. The third switch transistor can be turned on when the resonant capacitor is "zero voltage", thereby reducing the switching loss of the third switch transistor during the turn-on stage. Combined with the turn-on of the third switch transistor, the turn-off of the third switch transistor and / or the charging and discharging of the second capacitor by the resonant inductor, the adjustment of the voltage difference between the first end and the second end of the first switch transistor and the adjustment of the voltage difference between the first end and the second end of the third open-tube transistor are achieved, and then it is possible to achieve that the first switch transistor and the second switch transistor can achieve "zero voltage" switching. That is, the first switch transistor can be turned on when the voltage difference between the first end and the second end of the first switch transistor is within a predetermined voltage difference range, and the second switch transistor can be turned on when the voltage difference between the first end and the second end of the second switch transistor is within a predetermined voltage difference range. Thereby reducing the switching loss of the first switch transistor during the turn-on stage and the switching loss of the second switch transistor during the turn-on stage. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 is a schematic diagram of a switch circuit structure according to an exemplary embodiment;

[0041] Figure 2 is a schematic diagram of a switch circuit structure according to an exemplary embodiment;

[0042] Figure 3 is a schematic diagram of a switching circuit operation timing according to an exemplary embodiment;

[0043] Figure 4 is a schematic diagram of a switch circuit structure according to an exemplary embodiment;

[0044] Figure 5 is a schematic diagram of a switch circuit structure according to an exemplary embodiment;

[0045] Figure 6 is a schematic diagram of a switch circuit structure according to an exemplary embodiment;

[0046] Figure 7 is a schematic diagram of a switch circuit structure according to an exemplary embodiment;

[0047] Figure 8 is a schematic diagram of a switch circuit structure according to an exemplary embodiment;

[0048] Fig. 9 is a schematic diagram of a switch circuit structure according to an exemplary embodiment;

[0049] Fig.10 is a schematic diagram of a switch circuit structure according to an exemplary embodiment;

[0050] Fig.11 is a schematic diagram of a switch circuit structure according to an exemplary embodiment;

[0051] Fig.12 is a schematic diagram of a switch circuit structure according to an exemplary embodiment;

[0052] Fig.13 is a schematic diagram of a switch circuit structure according to an exemplary embodiment;

[0053] Fig.14 is a schematic diagram of a switch circuit structure according to an exemplary embodiment;

[0054] Fig.15 is a schematic diagram of a switch circuit structure according to an exemplary embodiment;

[0055] Fig.16 is a schematic diagram of a switch circuit structure according to an exemplary embodiment;

[0056] Fig.17 is a schematic diagram of a switch circuit structure according to an exemplary embodiment;

[0057] Fig.18 is a schematic diagram of a switching circuit operation timing according to an exemplary embodiment;

[0058] Fig.19is a schematic diagram of a switch circuit structure according to an exemplary embodiment;

[0059] Fig. 20 is a schematic diagram of a switch circuit structure according to an exemplary embodiment;

[0060] Fig.21 is a schematic diagram of a switch circuit structure according to an exemplary embodiment;

[0061] Fig. 22 The figure is a schematic diagram of implementation steps of a switch circuit control method according to an exemplary embodiment. DETAILED DESCRIPTION

[0062] In order to make the technical solutions and beneficial effects of the present invention more clearly understandable, the following is a detailed description by listing specific embodiments. The drawings are not necessarily drawn to scale, and local features may be enlarged or reduced to more clearly show the details of the local features; unless otherwise defined, the technical and scientific terms used herein have the same meanings as those in the technical field to which this application belongs.

[0063] The embodiments of the present disclosure are not exhaustive, but are only illustrative of some embodiments, and are not intended to be a specific limitation on the scope of protection of the present disclosure. In the absence of contradiction, each step in a certain embodiment can be implemented as an independent embodiment, and the steps can be arbitrarily combined. For example, a solution after removing some steps in a certain embodiment can also be implemented as an independent embodiment, and the order of the steps in a certain embodiment can be arbitrarily exchanged. In addition, the optional implementation methods in a certain embodiment can be arbitrarily combined; in addition, the embodiments can be arbitrarily combined, for example, some or all of the steps of different embodiments can be arbitrarily combined, and a certain embodiment can be arbitrarily combined with the optional implementation methods of other embodiments.

[0064] In each embodiment of the present disclosure, unless otherwise specified or there is a logical conflict, the terms and / or descriptions between the embodiments are consistent and can be referenced to each other, and the technical features in different embodiments can be combined to form a new embodiment based on their internal logical relationships.

[0065] The terms used in the embodiments of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0066] In the embodiments of the present disclosure, unless otherwise specified, elements expressed in the singular form, such as "a", "an", "the", "above", "said", "aforementioned", "this", etc., may mean "one and only one", or "one or more", "at least one", etc. For example, when using articles such as "a", "an", "the" in English in translation, the noun after the article may be understood as a singular expression or a plural expression.

[0067] In the embodiments of the present disclosure, “plurality” refers to two or more.

[0068] In some embodiments, the terms "at least one", "one or more", "aplurality of", "multiple", etc. can be used interchangeably.

[0069] In some embodiments, "at least one of A and B", "A and / or B", "A in one case, B in another case", "A in one case, B in another case", etc., may include the following technical solutions according to the situation: in some embodiments, A (A is executed independently of B); in some embodiments, B (B is executed independently of A); in some embodiments, execution is selected from A and B (A and B are selectively executed); in some embodiments, A and B (both A and B are executed). When there are more branches such as A, B, C, etc., the above is also similar.

[0070] In some embodiments, the recording method of "A or B" may include the following technical solutions according to the situation: in some embodiments, A (A is executed independently of B); in some embodiments, B (B is executed independently of A); in some embodiments, execution is selected from A and B (A and B are selectively executed). When there are more branches such as A, B, C, etc., the above is also similar.

[0071] The prefixes such as "first" and "second" in the embodiments of the present disclosure are only used to distinguish different description objects, and do not constitute restrictions on the position, order, priority, value or content of the description objects. The statement of the description object refers to the description in the context of the claims or embodiments, and should not constitute redundant restrictions due to the use of prefixes. For example, if the description object is a "field", the ordinal number before the "field" in the "first field" and the "second field" does not limit the position or order between the "fields", and the "first" and "second" do not limit whether the "fields" they modify are in the same message, nor do they limit the order of the "first field" and the "second field". For another example, if the description object is a "level", the ordinal number before the "level" in the "first level" and the "second level" does not limit the priority between the "levels". For another example, the numerical value of the description object is not limited by the ordinal number, and can be one or more. Taking the "first device" as an example, the numerical value of the "device" can be one or more. In addition, the objects modified by different prefixes may be the same or different. For example, if the description object is "device", then the "first device" and the "second device" may be the same device or different devices, and their types may be the same or different. For another example, if the description object is "information", then the "first information" and the "second information" may be the same information or different information, and their contents may be the same or different.

[0072] In some embodiments, “including A”, “comprising A”, “used to indicate A”, and “carrying A” can be interpreted as directly carrying A or indirectly indicating A.

[0073] In some embodiments, terms such as “…”, “determine…”, “in the case of…”, “at the time of…”, “when…”, “if…”, “if…”, etc. can be used interchangeably.

[0074] In some embodiments, terms such as "greater than", "greater than or equal to", "not less than", "more than", "more than or equal to", "not less than", "higher than", "higher than or equal to", "not lower than", and "above" can be replaced with each other, and terms such as "less than", "less than or equal to", "not greater than", "less than", "less than or equal to", "no more than", "lower than", "lower than or equal to", "not higher than", and "below" can be replaced with each other.

[0075] In addition, each element, each row, or each column in the table of the embodiments of the present disclosure may be implemented as an independent embodiment, and the combination of any elements, any rows, and any columns may also be implemented as an independent embodiment.

[0076] It should be noted that the switch transistor in the embodiment of the present application can be an N-type transistor or a P-type transistor. For the N-type transistor, the on-level is a high level and the off-level is a low level. That is, when the gate of the N-type transistor is at a high level, the first end and the second end thereof are connected, and when the gate of the N-type transistor is at a low level, the first end and the second end thereof are disconnected. For the P-type transistor, the on-level is a low level and the off-level is a high level. That is, when the control end of the P-type transistor is at a low level, the first end and the second end thereof are connected, and when the control end of the P-type transistor is at a high level, the first end and the second end thereof are disconnected. In a specific implementation, the gate of each of the above-mentioned switch transistors serves as its control end. In the embodiment of the present application, the drain and the source are determined according to the transistor type: for the N-type transistor, the first end thereof can be used as the drain and the second end as the source; for the P-type transistor, the first end thereof can be used as the source and the second end as the drain. In addition, the on-level and off-level in the embodiment of the present invention are both general terms. The on-level refers to any level that can turn on the transistor, and the off-level refers to any level that can turn off / off the transistor.

[0077] In the embodiment of the present application, the term "turning on the switching transistor" may refer to conduction between the first terminal and the second terminal of the switching transistor; the term "turning off the switching transistor" may refer to disconnection between the first terminal and the second terminal of the switching transistor.

[0078] In the embodiments of the present application, the term “connection” may refer to a direct electrical connection between two components, or may refer to an electrical connection between two components via one or more other components.

[0079] In the embodiments of the present application, unless otherwise specified, the switch transistor is described as an N-type transistor.

[0080] Here, the switching loss mechanism under high voltage and high frequency scenarios is analyzed, and the parasitic parameter model of the GaN switch tube is as follows: Figure 1 As shown. Figure 2 Taking the bridge arm shown in the figure as an example, the reasons why parasitic parameters cause switching losses are analyzed. Figure 3 This is a schematic diagram of the bridge arm timing. Figure 2 and Figure 3 As shown, during the time t1-t2, the lower tube S2 remains closed, and the upper tube S1 changes from the off state to the on state. During this stage, the drain-source voltage difference Vds1 of the switching transistor drops from Vbus (power supply voltage) to 0, and the gate-drain voltage difference Vgd1 of the switching transistor drops from Vbus to -Vpwm1 (negative S1 gate voltage). Since the switching speed of the switch tube is relatively fast, a pulse current with a large amplitude will be generated on the capacitors Cgd1 and Cds (as shown by the curve indicated by arrow A). This pulse current occurs during the shutdown period of the upper tube, and there is an intersection with Vds1, resulting in a relatively large shutdown loss.

[0081] The same applies to the lower tube during the turn-on process. At the same time, since Vpwm2 is very small compared to Vbus, the loss caused by the parasitic capacitor Cgs2 can be ignored.

[0082] When the upper and lower tubes are turned from on to off, the only energy discharge path is the load path. Due to the effect of the output filter inductor, the energy transfer to the load end is limited. Therefore, the Vo voltage remains unchanged in the short term. The switch tube can be regarded as zero voltage shutdown, and the shutdown loss is extremely small.

[0083] Therefore, in high-voltage and high-frequency PWM scenarios, the main switching loss is concentrated in the turn-on phase of the switching transistor, and is caused by the instantaneous change of voltage. Therefore, how to reduce the switching loss in the turn-on phase of the switching transistor and improve the voltage conversion efficiency is an urgent problem to be solved.

[0084] like Figure 4 As shown, a switch circuit shown in an embodiment of the present disclosure includes at least one switch bridge arm, wherein the switch bridge arm includes: a first switch transistor S1, a second switch transistor S2, a first capacitor C1, a second capacitor C2, and an auxiliary switch component; the auxiliary switch component includes: a third switch transistor S3, a resonant capacitor C3 and a resonant inductor Lr; wherein,

[0085] The resonant capacitor C3 is connected in parallel with the third switch transistor S3, the resonant inductor Lr is connected in series with the third switch transistor S3, the end of the resonant inductor Lr not connected to the third switch transistor S3 is the first end of the auxiliary switch component, and the end of the third switch transistor S3 connected to the resonant capacitor C3 and the resonant inductor Lr is the second end of the auxiliary switch component;

[0086] The first switch transistor S1 is connected in series with the second switch transistor S2, the first switch transistor S1 is connected in parallel with the first capacitor C1, and the second switch transistor S2 is connected in parallel with the second capacitor C2; the auxiliary switch component is connected in parallel with the second switch transistor S2 through the first end of the auxiliary switch component and the second end of the auxiliary switch component; the series connection point of the first switch transistor S1 and the second switch transistor S2 is the output node of the switch bridge arm.

[0087] In one possible implementation, Figure 5 As shown, the switch circuit may include a half-bridge circuit, and the half-bridge circuit may include a switch bridge arm. In some embodiments, the switch circuit includes a full-bridge switch circuit, and the full-bridge switch circuit includes two switch bridge arms;

[0088] like Figure 6 As shown, the switching circuit may include a full-bridge circuit, and the full-bridge circuit may include two switching bridge arms.

[0089] In some embodiments, the switching circuit includes a three-phase switching circuit, and the full-bridge switching circuit includes three switching bridge arms.

[0090] like Figure 7 As shown, the switching circuit may include a three-phase driving circuit, and the three-phase driving circuit may include three switching bridge arms.

[0091] In a possible implementation, the switch transistor may include a control terminal, a first terminal, and a second terminal. The switch transistor is turned on or off between the first terminal and the second terminal based on control of the control terminal.

[0092] In the above embodiment, connecting in series with the switch transistor may include connecting with the first end or the second end of the switch transistor. Exemplarily, connecting in series with the first switch transistor S1 and the second switch transistor S2 may include connecting the second end of the first switch transistor S1 and the first end of the second switch transistor S2.

[0093] In the above embodiment, being connected in series with the switch transistor may include being connected with the first end and the second end of the switch transistor. Exemplarily, being connected in parallel with the third switch transistor S3 may include: the two ends of the resonant capacitor C3 are respectively connected with the first end and the second end of the third switch transistor S3.

[0094] In one possible implementation, the switch transistor may include an N-type transistor. Figure 4 As shown, the first switch transistor S1 , the second switch transistor S2 and the third switch transistor S3 further include body diodes respectively.

[0095] like Figures 5 and 6 As shown, the output end of the bridge arm may be connected to an output circuit: a freewheeling inductor, an output energy storage capacitor, a load, etc. The first switch transistor S1 and the second switch transistor S2 are turned on and off based on the control of the PWM signal to adjust the output voltage.

[0096] In a possible implementation, the resonance of the resonant capacitor C3 and the resonant inductor Lr is decoupled from the resonance of the freewheeling inductor and the output energy storage capacitor. The resonant frequency of the resonant capacitor C3 and the resonant inductor Lr is greater than the resonant frequency of the freewheeling inductor and the output energy storage capacitor. The capacitance value of the resonant capacitor C3 is greater than the capacitance value of the parasitic capacitance of the third switch transistor S3.

[0097] Here, the resonant capacitor C3 and the resonant inductor Lr resonate, so that the resonant capacitor C3 generates a "zero voltage" timing. At the "zero voltage" timing, the voltage across the capacitor is within a predetermined voltage difference range (such as 0V), that is, the voltage difference between the first end and the second end of the third switching transistor S3 is within a predetermined voltage difference range. The smaller the maximum voltage value within the predetermined voltage difference range, the smaller the switching loss of the switching transistor. The third switching transistor S3 can be turned on at the "zero voltage" timing of the resonant capacitor C3, thereby reducing the switching loss of the third switching transistor S3 during the turn-on phase. The "zero voltage" switching of the switch bridge arm is achieved through the auxiliary switch component, reducing the switching loss of the switching circuit. Here, "zero voltage" can represent a voltage value that is smaller than the power supply voltage, such as any voltage value between 0V and 0.1V. Combined with the conduction of the third switch transistor S3, the turn-off of the third switch transistor S3 and / or the charging and discharging of the second capacitor C2 by the resonant inductor Lr, the voltage difference between the first end and the second end of the first switch transistor S1 and the voltage difference between the first end and the second end of the second switch transistor S2 are adjusted, and thus the first switch transistor S1 and the second switch transistor S2 can achieve "zero voltage" switching. That is, the first switch transistor S1 can be turned on when the voltage difference between the first end and the second end of the first switch transistor S1 is within a predetermined voltage difference range, and the second switch transistor S2 can be turned on when the voltage difference between the first end and the second end of the second switch transistor S2 is within a predetermined voltage difference range. Thereby reducing the switching loss in the turn-on stage of the first switch transistor S1 and the switching loss in the turn-on stage of the second switch transistor S2.

[0098] In some embodiments, the first switch transistor S1 and the second switch transistor S2 are turned on alternately, and the turn-on period of the first switch transistor S1 and the turn-on period of the second switch transistor S2 are separated from each other by a first predetermined interval;

[0099] The third switch transistor S3 is turned on at a first moment in a turn-on period of the first switch transistor S1, and is turned off at a second moment in a turn-on period of the second switch transistor S2, wherein the first moment includes a moment when the resonant capacitor C3 and the resonant inductor Lr resonate and the voltage difference across the resonant capacitor C3 is within a predetermined voltage difference range, and the second moment includes a moment in the turn-on period of the second switch transistor S2 that is a second predetermined interval away from the turn-on moment of the second switch transistor S2.

[0100] Here, the switch circuit may include a controller for controlling the on and off of the first switch transistor S1 , the second switch transistor S2 , and the third switch transistor S3 .

[0101] The first predetermined interval duration may include a dead time duration of the alternating switching of the first switch transistor S1 and the second switch transistor S2.

[0102] After the second switch transistor S2 is turned on, the third switch transistor S3 may be turned off. The second predetermined interval may be less than or equal to 10 ms, such as 5 ms, to reduce interference with the output current.

[0103] The smaller the predetermined voltage difference range is, that is, the smaller the voltage difference between the first end and the second end of the third switch transistor S3 during the conduction phase is, the smaller the loss of the third switch transistor S3 during the conduction phase is.

[0104] In combination with the conduction of the third switch transistor S3, the turn-off of the third switch transistor S3 and / or the charging and discharging of the second capacitor C2 by the resonant inductor Lr, the voltage difference between the first end and the second end of the first switch transistor S1 and the voltage difference between the first end and the second end of the second switch transistor S2 are adjusted, and thus the first switch transistor S1 and the second switch transistor S2 may be able to achieve "zero voltage" switching. That is, the first switch transistor S1 can be turned on when the voltage difference between the first end and the second end of the first switch transistor S1 is within a predetermined voltage difference range, and the second switch transistor S2 can be turned on when the voltage difference between the first end and the second end of the second switch transistor S2 is within a predetermined voltage difference range. Thereby reducing the switching loss in the turn-on stage of the first switch transistor S1 and the switching loss in the turn-on stage of the second switch transistor S2.

[0105] By limiting the first moment to the on-time period of the first switch transistor S1 and the second moment to the on-time period of the second switch transistor S2, different on- and off-duty ratios of the first switch transistor S1 and the second switch transistor S2 can be met, thereby improving the applicable scenarios of "zero voltage" switching.

[0106] Here, taking the two switch arms in the full bridge as an example, the conduction timing of each switch transistor is explained. Figure 6 As shown, PWM1 (the on-time of the first switch transistor S1) and PWM5 have the same phase and a duty cycle of D, PWM4 and PWM5 (the on-time of the second switch transistor S2) have the same phase and a duty cycle of 1-D-Tdead, and are complementary to PWM1 and PWM5 (Tdead is the dead time, during which the four PWMs are all in the 0 state). The output voltage is controlled by controlling the PWM duty cycle, and the output voltage Vo satisfies Vo=(1-2D)Vbus, where Vbus is the bus voltage.

[0107] In some embodiments, Figure 8 As shown, the first end of the first switch transistor S1 is connected to the first power supply voltage signal; the second end of the first switch transistor S1 is connected to the first end of the second switch transistor S2; the second end of the second switch transistor S2 is connected to the second power supply voltage signal;

[0108] Two ends of the first capacitor C1 are respectively connected to the first end of the first switch transistor S1 and the second end of the first switch transistor S1, and two ends of the second capacitor C2 are respectively connected to the first end of the second switch transistor S2 and the second end of the second switch transistor S2;

[0109] The first end of the resonant inductor Lr is connected to the first end of the second switch transistor S2; the second end of the resonant inductor Lr is connected to the first end of the third switch transistor S3; the second end of the third switch transistor S3 is connected to the second power supply voltage signal; the two ends of the resonant capacitor C3 are respectively connected to the first end of the third switch transistor S3 and the second end of the third switch transistor S3;

[0110] The control end of the first switch transistor S1 is connected to the first switch signal (represented by Vpwm1 in the drawings) to turn on or off the first switch transistor S1, the control end of the second switch transistor S2 is connected to the second switch signal (represented by Vpwm2 in the drawings) to turn on or off the second switch transistor S2, and the control end of the third switch transistor S3 is connected to the third switch signal (represented by Vpwm3 in the drawings) to turn on or off the third switch transistor S3.

[0111] like Figure 8 As shown, the output circuit of the switch circuit (including the freewheeling inductor, the output energy storage capacitor and the load) can be equivalent to a constant current source with a current of Iload. The output filter inductor is much larger than the resonant inductor Lr, and the load current variation frequency (base frequency) is much lower than the resonant current frequency. Therefore, the influence of the load end on the resonant process of the resonant inductor Lr and the resonant circuit can be ignored, so the output circuit can be equivalent to a constant current source.

[0112] The first power supply voltage signal may include an input power supply voltage signal. The second power supply voltage signal may include a ground signal.

[0113] like Figure 8 As shown, the third switch transistor S3 is connected in parallel with the lower tube of the switch bridge arm (the second switch transistor S2). In this way, the third switch signal only needs a lower voltage value to drive the control terminal of the third switch transistor S3, thereby reducing the cost of the fifth switch crystal driving circuit.

[0114] The following combination Figures 9 to 19 right Figure 8 The timing of the different working stages of the switching circuit shown is explained:

[0115] Working stage 1 (t1~t2): Fig. 9As shown, in this stage, S1 is turned on, S2 and S3 are turned off, and at time t1, Vo = Vbus, Vd3 = 0, at this time there is a voltage difference on both sides of the resonant inductor Lr, due to the formula Ilr = ∫U / Lr, so Ilr starts to increase, because Ilr is negative in this mode, so the current direction is D3->Lr->S1;

[0116] Working stage 2 (t2~t3): Fig.10 As shown, at time t2, Ilr rises to 0. In this stage, Ilr is positive, and the current direction is S1->Lr->C3. At the same time, C3 is charged. At this time, Lr and C3 together form a series resonant circuit. Ilr changes sinusoidally with zero as the base point, and Vds3 changes sinusoidally with Vbus as the base point.

[0117] Working stage 3 (t3~t4): Fig.11 As shown, at time t3, Vds3 just resonates to the 0 level, and S3 is turned on. Since Vds3 is 0, S3 is turned on at zero voltage. In this stage, the current direction is S1->Lr->S3. Due to the voltage difference on both sides of the inductor Lr, the inductor is charged and Ilr rises;

[0118] Working stage 4 (t4-t5): At time t4, S1 is turned off. The turn-off process of S1 is short. Due to the effect of the resonant capacitor C1, Vds1 cannot change rapidly. Therefore, S1 can be regarded as zero voltage turn-off.

[0119] Working stage 5 (t5~t6): Fig.12 As shown, in this stage, since S1 and S2 are both in the off state, the current direction is C2->Lr->S3. At this time, the charge on C2 is consumed to charge Lr, so Vo drops to zero;

[0120] Working stage 6 (t6-t7): Fig.13 As shown, at time t6, S2 is turned on. Since Vo has dropped to zero before, S2 is turned on with zero voltage. In this stage, the current direction is S2(D2)-Lr-S5;

[0121] Working stage 7 (t7-t8): Fig.14 As shown, at time t7, S3 is turned off. Due to the effect of the resonant capacitor C3, Vds3 cannot change rapidly, so S3 can be regarded as zero voltage turn-off. After that, the current direction is S2->Lr->C3, and Lr and C3 form a series resonance again until Vds3 drops to 0 again and Ilr reverses;

[0122] Working stage 8 (t8-t9): Fig.15As shown in the figure, since Ilr has reversed at time t8 and the voltage difference on both sides of Lr is zero, the current flows through diode D2 in the direction of D3->Lr->S2. At this stage, the current and voltage no longer change and are in a stable state.

[0123] Working stage 9 (t9-t10): At time t4, S2 is turned off. The turn-off process of S2 is short, but due to the effect of the resonant capacitor C2, Vds2 cannot change rapidly. Therefore, S2 can be regarded as zero voltage turn-off.

[0124] Working phase 10 (t10-t11): Fig.16 As shown, in this stage, since S1 and S2 are both in the off state, the current direction is D3->Lr->C2. At this time, the energy on Lr is consumed to charge C2, so Vo rises to Vbus.

[0125] Working phase 11 (t11-t12): Fig.17 As shown, at time t11, S1 is turned on. Since Vo has risen to Vbus before, S1 is turned on with zero voltage. At this stage, the current direction is C3-Lr-S1 (D1).

[0126] Combining the working conditions of the above-mentioned switch circuit at different working stages, it can be known that in a complete working cycle of the switch circuit, the first switch transistor S1, the second switch transistor S2 and the third switch transistor S3 all achieve zero voltage switching, thereby reducing the loss in the turn-on stage and the turn-off stage of the switch transistor and improving the voltage conversion efficiency.

[0127] In some embodiments, the switch bridge arm further includes a switch limit component for turning on the third switch transistor S3 when the third switch signal indicates turning on the third switch transistor S3 and the voltage difference across the resonant capacitor C3 is within a predetermined voltage difference range.

[0128] The third switch transistor S3 is turned on when the voltage across the resonant capacitor C3 is within a predetermined voltage difference range (e.g., the voltage across the resonant capacitor C3 is 0V), and the switching loss of the third switch transistor S3 is minimal. That is, the first moment when the third switch transistor S3 is turned on includes the moment when the voltage across the resonant capacitor C3 resonates to within the predetermined voltage difference range. Therefore, determining the moment when the voltage across the resonant capacitor C3 resonates to within the predetermined voltage difference range requires determining the resonance period.

[0129] The resonant period is usually related to the resonant inductor Lr, the resonant capacitor C3 and the input voltage of the circuit (such as Vbus). The resonant period will be affected by the inductance error of the resonant inductor Lr, the capacitance error of the resonant capacitor C3, parasitic parameters, and bus voltage fluctuations. Therefore, the moment when the voltage across the resonant capacitor C3 resonates to within the predetermined voltage difference range will drift.

[0130] Here, a switch limit component may be provided on the switch bridge arm so that the third switch transistor S3 is turned off when the third switch signal indicates that the third switch transistor S3 is turned on, and the voltage difference across the resonant capacitor C3 is within a predetermined voltage difference range.

[0131] Specifically, the third switch signal can be enabled within an enabling time period, indicating that the third switch transistor S3 is turned on. The switch limit component can detect the voltage difference across the resonant capacitor C3, and when the voltage difference across the resonant capacitor C3 is within a predetermined voltage difference range, the third switch transistor S3 is turned on. The enabling time period can be determined based on the drift range of the resonance period.

[0132] By setting the switch limit component, the probability of the third switch transistor S3 being turned on when the voltage difference across the resonant capacitor C3 is within a predetermined voltage difference range can be increased, the influence of circuit element errors on the conduction loss of the third switch transistor S3 can be reduced, and the robustness of the circuit can be improved.

[0133] In some embodiments, the switch limit assembly includes: a comparator and an AND gate, wherein:

[0134] The inverting input terminal of the comparator is connected to the first terminal of the third switch transistor S3, and the positive input terminal of the comparator is connected to a reference voltage signal, wherein the voltage value of the reference voltage signal is within the predetermined voltage difference range;

[0135] The output end of the comparator is connected to the first input end of the AND gate, the second input end of the AND gate is connected to the third switch signal, and the output end of the AND gate is connected to the control end of the third switch transistor S3.

[0136] The reference voltage signal can be set based on a predetermined voltage difference range. The voltage value of the reference voltage signal is less than or equal to the highest voltage value of the predetermined voltage difference range.

[0137] by Fig.19Take a switch arm in a full-bridge circuit as an example. The third switch signal can be enabled (high level enabled) within an enable time period. During the enabling period of the third switch signal, if the voltage at the first terminal of the third switch transistor S3 is greater than the voltage value of the reference voltage signal, the output terminal of the comparator outputs a low level, and the output terminal of the AND gate also outputs a low level, keeping the third switch transistor S3 turned off; during the enabling period of the third switch signal, if the voltage at the first terminal of the third switch transistor S3 is less than the voltage value of the reference voltage signal, the output terminal of the comparator outputs a high level, and the output terminal of the AND gate also outputs a high level, turning on the third switch transistor S3. In this way, on the one hand, by implementing the control logic through the comparator and the AND gate, the response speed of the switch limit component can be improved. On the other hand, the probability of the third switch transistor S3 being turned on when the voltage difference across the resonant capacitor C3 is within a predetermined voltage difference range can be increased, reducing the influence of the circuit element error on the conduction loss of the third switch transistor S3, and improving the robustness of the circuit.

[0138] In some embodiments, Fig. 20 As shown, the first end of the second switch transistor S2 is connected to the first power supply voltage signal; the second end of the second switch transistor S2 is connected to the first end of the first switch transistor S1; the second end of the first switch transistor S1 is connected to the second power supply voltage signal;

[0139] Two ends of the first capacitor C1 are respectively connected to the first end of the first switch transistor S1 and the second end of the first switch transistor S1, and two ends of the second capacitor C2 are respectively connected to the first end of the second switch transistor S2 and the second end of the second switch transistor S2;

[0140] The first end of the resonant inductor Lr is connected to the first end of the second switch transistor S2; the second end of the resonant inductor Lr is connected to the first end of the third switch transistor S3; the second end of the third switch transistor S3 is connected to the second end of the second switch transistor S2; the two ends of the resonant capacitor C3 are respectively connected to the first end of the third switch transistor S3 and the second end of the third switch transistor S3;

[0141] The control end of the first switch transistor S1 is connected to the first switch signal to turn on or off the first switch transistor S1, the control end of the second switch transistor S2 is connected to the second switch signal to turn on or off the second switch transistor S2, and the control end of the third switch transistor S3 is connected to the third switch signal to turn on or off the third switch transistor S3.

[0142] Here, the first power supply voltage signal may include an input power supply voltage signal. The second power supply voltage signal may include a ground signal.

[0143] like Fig. 20 As shown, the second switch transistor S2 is the upper transistor of the switch bridge arm. Figures 8 to 19 Similar to the embodiment, the third switch transistor S3 is turned on at a first moment in the conduction period of the first switch transistor S1, and is turned off at a second moment in the conduction period of the second switch transistor S2. To achieve the "zero voltage switch" of the third switch transistor S3. In combination with the conduction of the third switch transistor S3, the turn-off of the third switch transistor S3 and / or the charging and discharging of the second capacitor C2 by the resonant inductor Lr, the adjustment of the voltage difference between the first end and the second end of the first switch transistor S1 and the adjustment of the voltage difference between the first end and the second end of the second switch transistor S2 are achieved, and it is possible to achieve the "zero voltage" switch of the first switch transistor S1 and the second switch transistor S2. Thereby reducing the switching loss in the turn-on stage of the first switch transistor S1 and the switching loss in the turn-on stage of the second switch transistor S2. No further details are given here.

[0144] In some embodiments, the first end of the second switch transistor S2 is connected to the first power supply voltage signal; the second end of the second switch transistor S2 is connected to the first end of the first switch transistor S1; the second end of the first switch transistor S1 is connected to the second power supply voltage signal;

[0145] Two ends of the first capacitor C1 are respectively connected to the first end of the first switch transistor S1 and the second end of the first switch transistor S1, and two ends of the second capacitor C2 are respectively connected to the first end of the second switch transistor S2 and the second end of the second switch transistor S2;

[0146] The first end of the third switch transistor S3 is connected to the first power supply voltage signal; the second end of the third switch transistor S3 is connected to the first end of the resonant inductor Lr; the second end of the resonant inductor Lr is connected to the second end of the second switch transistor S2; the two ends of the resonant capacitor C3 are respectively connected to the first end of the third switch transistor S3 and the second end of the third switch transistor S3;

[0147] The control end of the first switch transistor S1 is connected to the first switch signal to turn on or off the first switch transistor S1, the control end of the second switch transistor S2 is connected to the second switch signal to turn on or off the second switch transistor S2, and the control end of the third switch transistor S3 is connected to the third switch signal to turn on or off the third switch transistor S3.

[0148] Here, the first power supply voltage signal may include an input power supply voltage signal. The second power supply voltage signal may include a ground signal.

[0149] like Fig.21 As shown, the second switch transistor S2 is the upper transistor of the switch bridge arm. Figures 8 to 18 Similar to the embodiment, the third switch transistor S3 is turned on at a first moment in the conduction period of the first switch transistor S1, and is turned off at a second moment in the conduction period of the second switch transistor S2. To achieve the "zero voltage switch" of the third switch transistor S3. In combination with the conduction of the third switch transistor S3, the turn-off of the third switch transistor S3 and / or the charging and discharging of the second capacitor C2 by the resonant inductor Lr, the adjustment of the voltage difference between the first end and the second end of the first switch transistor S1 and the adjustment of the voltage difference between the first end and the second end of the second switch transistor S2 are achieved, and it is possible to achieve the "zero voltage" switch of the first switch transistor S1 and the second switch transistor S2. Thereby reducing the switching loss in the turn-on stage of the first switch transistor S1 and the switching loss in the turn-on stage of the second switch transistor S2. No further details are given here.

[0150] like Fig. 22 As shown, a switch circuit control method shown in an embodiment of the present disclosure is applied to the switch circuit described in the first aspect, and the method includes:

[0151] Step 2201: Control the first switch transistor S1 and the second switch transistor S2 to be turned on alternately, wherein the first switch transistor S1 turn-on period and the second switch transistor S2 turn-on period are separated by a first predetermined time interval;

[0152] Step 2202: Control the third switch transistor S3 to be turned on at a first moment in the conduction period of the first switch transistor S1, and to be turned off at a second moment in the conduction period of the second switch transistor S2, wherein the first moment includes the moment when the resonant capacitor C3 and the resonant inductor Lr resonate so that the voltage difference across the resonant capacitor C3 is within a predetermined voltage difference range, and the second moment includes the moment in the conduction period of the second switch transistor S2 that is a second predetermined interval away from the conduction moment of the second switch transistor S2.

[0153] Here, the switch circuit control method may be executed by a controller in the switch circuit, such as a controller that generates a PWM signal in the circuit.

[0154] The switch circuit control method can be applied to any of the above embodiments. The control method is as described in the above embodiments and will not be described in detail here.

[0155] The embodiment of the present application also provides an electronic circuit, including a control device.

[0156] The control device is used to execute the switch circuit control method as described above.

[0157] The present application also provides a computer-readable storage medium, in which computer-executable instructions are stored. When a processor executes the computer-executable instructions, the above-mentioned switch circuit control method is implemented.

[0158] The computer-readable storage medium provided in this embodiment can execute the control method of the cleaning device in the above-mentioned embodiment, and its implementation principle and technical effect are similar, so this embodiment will not be repeated here.

[0159] The computer-readable storage medium mentioned above can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk. The readable storage medium can be any available medium that can be accessed by a general or special-purpose computer.

[0160] An exemplary readable storage medium is coupled to a processor so that the processor can read information from the readable storage medium and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can be located in an application specific integrated circuit (Application Specific Integrated Circuits, referred to as: ASIC). Of course, the processor and the readable storage medium can also exist as discrete components in an electronic device or a main control device.

[0161] Those skilled in the art can understand that all or part of the steps of implementing the above-mentioned method embodiments can be completed by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, the steps of the above-mentioned method embodiments are executed; and the aforementioned storage medium includes: ROM, RAM, disk or optical disk and other media that can store program codes.

[0162] The various embodiments or implementation methods in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referenced to each other.

[0163] In the description of this specification, reference to "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0164] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A switching circuit, characterized in that: The switch circuit includes at least one switch bridge arm, wherein the switch bridge arm includes: a first switch transistor, a second switch transistor, a first capacitor, a second capacitor, and an auxiliary switch component; the auxiliary switch component includes: a third switch transistor, a resonant capacitor, and a resonant inductor; wherein, The resonant capacitor is connected in parallel with the third switch transistor, the resonant inductor is connected in series with the third switch transistor, the end of the resonant inductor that is not connected to the third switch transistor is the first end of the auxiliary switch component, and the end of the third switch transistor that is connected to the resonant capacitor and not connected to the resonant inductor is the second end of the auxiliary switch component; The first switch transistor is connected in series with the second switch transistor, the first switch transistor is connected in parallel with the first capacitor, and the second switch transistor is connected in parallel with the second capacitor; the auxiliary switch component is connected in parallel with the second switch transistor through the first end of the auxiliary switch component and the second end of the auxiliary switch component; the series connection point between the first switch transistor and the second switch transistor is the output node of the switch bridge arm.

2. The switch circuit according to claim 1, characterized in that: The first switch transistor and the second switch transistor are alternately turned on, and a turn-on period of the first switch transistor and a turn-on period of the second switch transistor are separated from each other by a first predetermined time interval; The third switching transistor is turned on at a first moment in a conduction period of the first switching transistor, and is turned off at a second moment in a conduction period of the second switching transistor, wherein the first moment includes a moment when the resonant capacitor and the resonant inductor resonate and a voltage difference across the resonant capacitor is within a predetermined voltage difference range, and the second moment includes a moment in the conduction period of the second switching transistor that is a second predetermined interval away from the conduction moment of the second switching transistor.

3. The switch circuit according to claim 1 or 2, characterized in that: The first end of the first switch transistor is connected to a first power supply voltage signal; the second end of the first switch transistor is connected to a first end of the second switch transistor; the second end of the second switch transistor is connected to a second power supply voltage signal; Two ends of the first capacitor are connected to the first end of the first switch transistor and the second end of the first switch transistor respectively, and two ends of the second capacitor are connected to the first end of the second switch transistor and the second end of the second switch transistor respectively; The first end of the resonant inductor is connected to the first end of the second switch transistor; the second end of the resonant inductor is connected to the first end of the third switch transistor; the second end of the third switch transistor is connected to the second power supply voltage signal; the two ends of the resonant capacitor are respectively connected to the first end of the third switch transistor and the second end of the third switch transistor; The control end of the first switch transistor is connected to a first switch signal to turn on or off the first switch transistor, the control end of the second switch transistor is connected to a second switch signal to turn on or off the second switch transistor, and the control end of the third switch transistor is connected to a third switch signal to turn on or off the third switch transistor.

4. The switch circuit according to claim 3, characterized in that: The switch bridge arm further includes a switch limit component, which is used to turn on the third switch transistor when the third switch signal indicates turning on the third switch transistor and the voltage difference across the resonant capacitor is within a predetermined voltage difference range.

5. The switch circuit according to claim 4, characterized in that: The switch limit assembly includes: a comparator and an AND gate, wherein: The inverting input terminal of the comparator is connected to the first terminal of the third switch transistor, and the positive input terminal of the comparator is connected to a reference voltage signal, wherein the voltage value of the reference voltage signal is within the predetermined voltage difference range; The output end of the comparator is connected to the first input end of the AND gate, the second input end of the AND gate is connected to the third switch signal, and the output end of the AND gate is connected to the control end of the third switch transistor.

6. The switch circuit according to claim 1 or 2, characterized in that: The first end of the second switch transistor is connected to the first power supply voltage signal; the second end of the second switch transistor is connected to the first end of the first switch transistor; the second end of the first switch transistor is connected to the second power supply voltage signal; Two ends of the first capacitor are connected to the first end of the first switch transistor and the second end of the first switch transistor respectively, and two ends of the second capacitor are connected to the first end of the second switch transistor and the second end of the second switch transistor respectively; The first end of the resonant inductor is connected to the first end of the second switch transistor; the second end of the resonant inductor is connected to the first end of the third switch transistor; the second end of the third switch transistor is connected to the second end of the second switch transistor; the two ends of the resonant capacitor are respectively connected to the first end of the third switch transistor and the second end of the third switch transistor; The control end of the first switch transistor is connected to a first switch signal to turn on or off the first switch transistor, the control end of the second switch transistor is connected to a second switch signal to turn on or off the second switch transistor, and the control end of the third switch transistor is connected to a third switch signal to turn on or off the third switch transistor.

7. The switch circuit according to claim 1 or 2, characterized in that: The first end of the second switch transistor is connected to the first power supply voltage signal; the second end of the second switch transistor is connected to the first end of the first switch transistor; the second end of the first switch transistor is connected to the second power supply voltage signal; Two ends of the first capacitor are connected to the first end of the first switch transistor and the second end of the first switch transistor respectively, and two ends of the second capacitor are connected to the first end of the second switch transistor and the second end of the second switch transistor respectively; The first end of the third switch transistor is connected to the first power supply voltage signal; the second end of the third switch transistor is connected to the first end of the resonant inductor; the second end of the resonant inductor is connected to the second end of the second switch transistor; the two ends of the resonant capacitor are respectively connected to the first end of the third switch transistor and the second end of the third switch transistor; The control end of the first switch transistor is connected to a first switch signal to turn on or off the first switch transistor, the control end of the second switch transistor is connected to a second switch signal to turn on or off the second switch transistor, and the control end of the third switch transistor is connected to a third switch signal to turn on or off the third switch transistor.

8. The switch circuit according to claim 1 or 2, characterized in that: The first switch transistor, the second switch transistor and the third switch transistor are all N-type MOS transistors; The first end of the first switch transistor is a drain, the second end of the first switch transistor is a source, and the control end of the first switch transistor is a gate; The first end of the second switch transistor is a drain, the second end of the second switch transistor is a source, and the control end of the second switch transistor is a gate; The first end of the third switch transistor is a drain, the second end of the third switch transistor is a source, and the control end of the third switch transistor is a gate.

9. The switch circuit according to claim 1 or 2, characterized in that: The switch circuit comprises a full-bridge switch circuit, and the full-bridge switch circuit comprises two switch bridge arms; or The switch circuit includes a three-phase switch circuit, and the full-bridge switch circuit includes three switch bridge arms.

10. A switch circuit control method, characterized in that: Applied to the switch circuit according to any one of claims 1 to 9, the method comprising: Controlling the first switch transistor and the second switch transistor to be turned on alternately, wherein a conduction period of the first switch transistor and a conduction period of the second switch transistor are separated by a first predetermined interval; The third switch transistor is controlled to be turned on at a first moment in a conduction period of the first switch transistor, and to be turned off at a second moment in a conduction period of the second switch transistor, wherein the first moment includes a moment when the resonant capacitor and the resonant inductor resonate so that the voltage difference across the resonant capacitor is within a predetermined voltage difference range, and the second moment includes a moment in the conduction period of the second switch transistor that is a second predetermined interval away from the conduction moment of the second switch transistor.

11. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the processor implements the switch circuit control method according to claim 10 .

12. An electronic circuit, characterized in that: The electronic circuit comprises: a control device; The control device is used to execute the switch circuit control method as claimed in claim 10.

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