Driving signal generating circuit, half-bridge driving circuit and laser radar

Abstract

The embodiment of the invention discloses a driving signal generation circuit, a half-bridge driving circuit and a laser radar. The driving signal generation circuit comprises a first time delay module, a second time delay module and an edge acquisition module, the input end of the first delay module is used for accessing an input voltage and delaying the input voltage to obtain a first driving signal, and the first delay module is used for controlling the delay response time of the first driving signal to be dead time; the input end of the second delay module is connected with the output end of the first delay module, and the second delay module is used for delaying the first driving signal and inverting the first driving signal into an inverted control signal; and the first input end of the edge acquisition module is connected with the output end of the second delay module, and the second input end is used for accessing the input voltage and determining a second driving signal according to the input voltage and the anti-phase control signal. The driving signal generation circuit can ensure the charging stability of the load, thereby ensuring the use reliability of the laser radar.

Description

Technical Field

[0001] The present application relates to the field of laser radar technology, and in particular to a drive signal generating circuit, a half-bridge drive circuit and a laser radar. Background Art

[0002] At present, laser radar usually uses a half-bridge circuit to charge and discharge the load to complete the light emission and reset. Among them, the half-bridge circuit usually includes a high-side switch and a low-side switch. When the high-side switch is turned on, the load is charged; when the low-side switch is turned on, the load is discharged. However, in actual use, the high-side switch and the low-side switch may be turned on at the same time, resulting in a short circuit in the circuit and a large current loss. In severe cases, it may cause thermal failure of the high-side switch and the low-side switch, affecting the use of the laser radar.

[0003] In the related art, a non-overlapping signal generating circuit is usually set at the input end of the half-bridge circuit, and a dead time (Dead Time, DT) is inserted between the control signal received by the high-side switch and the control signal received by the low-side switch through the non-overlapping signal generating circuit, so that the high-side switch and the low-side switch will not be turned on at the same time. However, when inserting the dead time in the related art, there may be a loss of the pulse width of the control signal received by the high-side switch, which reduces the charging time and leads to poor reliability of the laser emitted by the laser radar. Summary of the invention

[0004] The embodiments of the present application provide a drive signal generating circuit, a half-bridge drive circuit and a laser radar. The drive signal generating circuit can ensure the charging stability of the load, thereby ensuring the reliability of the use of the laser radar.

[0005] In the first aspect, an embodiment of the present application provides a drive signal generating circuit, including a first delay module, a second delay module and an edge acquisition module; the input end of the first delay module is used to access the input voltage, and is used to delay the input voltage to obtain a first drive signal, and the first delay module is used to control the time of the delayed response of the first drive signal as a dead time; the input end of the second delay module is connected to the output end of the first delay module, and is used to delay the first drive signal and invert it into an inverted control signal; the first input end of the edge acquisition module is connected to the output end of the second delay module, and the second input end is used to access the input voltage, and is used to determine the second drive signal based on the input voltage and the inverted control signal.

[0006] In the above technical solution, the drive signal generating circuit provided in the embodiment of the present application can delay the input voltage to obtain the first drive signal and the second drive signal, and the first drive signal and the second drive signal are not high at the same time, which avoids the first drive signal and the second drive signal being high at the same time, causing the half-bridge drive circuit using the drive signal generating circuit to short-circuit, thereby causing a large current loss problem. Furthermore, on the one hand, the present application can delay the input voltage through the first delay module to obtain the first drive signal, and the first delay module can accurately control the dead time of the first drive signal, so that the upper edge and the falling edge of the first drive signal are delayed by the same time, and the width of the first drive signal after the delay is consistent with the pulse width of the input voltage, avoiding the problem of signal width loss in the first drive signal after the delay, thereby ensuring the reliability of charging the load. On the other hand, the present application delays and inverts the first drive signal through the second delay module to obtain an inverted control signal, and then determines the edge signal of the second drive signal according to the input voltage and the inverted control signal through the edge acquisition module, and then obtains the width of the second drive signal. That is, the width of the second drive signal can be determined according to the distance between the input voltage and the edge signal of the inverted control signal, rather than being determined solely by the level signal of the first drive signal, thereby avoiding the problem that the pulse width of the input voltage is limited by the dead time of the delay of the drive signal generating circuit.

[0007] In combination with the first aspect, in some possible implementations, the edge acquisition module includes an edge acquisition unit and a latch unit; the first input end of the edge acquisition unit is connected to the output end of the second delay module, for acquiring the rising edge pulse signal of the inverted control signal, and deriving the first edge signal according to the rising edge pulse signal of the inverted control signal; the second input end of the edge acquisition unit is connected to the input voltage, for acquiring the rising edge pulse signal of the input voltage, and deriving the second edge signal according to the rising edge pulse signal of the input voltage; the first input end of the latch unit is connected to the first output end of the edge acquisition unit, and the second input end is connected to the second output end of the edge acquisition unit, for determining and deriving the second drive signal according to the first edge signal and the second edge signal; the first edge signal and the second edge signal are narrow pulse signals, and the second drive signal is a short pulse signal.

[0008] In the above technical solution, the rising edge pulse signal of the input voltage and the inverted control signal can be collected by the edge acquisition unit, and the first edge signal and the second edge signal can be obtained, so as to obtain the width of the second drive signal, that is, at this time, the width of the second drive signal is determined by the distance between the edge signal of the input voltage and the inverted control signal, rather than just determined by the level signal of the first drive signal, thereby avoiding the problem that the pulse width of the input voltage is limited by the dead time of the delay of the drive signal generating circuit. Moreover, the latch unit can determine the second drive signal as a short pulse signal according to the narrow pulse signal of the first edge signal and the second edge signal, so that the second drive signal is a short pulse signal corresponding to the first drive signal.

[0009] In combination with the first aspect, in some possible implementations, the edge acquisition unit includes a first edge acquisition subunit and a second edge acquisition subunit; the input end of the first edge acquisition subunit is connected to the output end of the second delay module, and the output end is connected to the first input end of the latch unit, for acquiring the rising edge pulse signal of the inverting control signal and generating a first edge signal, which is output to the latch unit; the input end of the second edge acquisition subunit is connected to the input voltage, and the output end is connected to the second input end of the latch unit, for acquiring the rising edge pulse signal of the input voltage and generating a second edge signal, which is output to the latch unit.

[0010] In combination with the first aspect, in some possible implementations, the first edge acquisition subunit includes multiple first inverters and a first NAND gate, the multiple first inverters are connected in series in sequence and then connected in series with the first NAND gate, the first first inverter among the multiple first inverters is connected to the output end of the second delay module, the last first inverter among the multiple first inverters is connected to the first input end of the first NAND gate, the second input end of the first NAND gate is connected to the output end of the second delay module, and the output end of the first NAND gate is connected to the first input end of the latch unit; the number of the multiple first inverters connected in series is an odd number.

[0011] In combination with the first aspect, in some possible implementations, the second edge acquisition subunit includes a plurality of second inverters and a second NAND gate, the plurality of second inverters are sequentially connected in series and then connected in series with the second NAND gate, the first second inverter among the plurality of second inverters is connected to an input voltage, the last second inverter among the plurality of second inverters is connected to a first input terminal of the second NAND gate, the second input terminal of the second NAND gate is connected to an input voltage, and the output terminal of the second NAND gate is connected to a second input terminal of the latch unit; and the number of the plurality of second inverters connected in series is an odd number.

[0012] In combination with the first aspect, in some possible implementations, the latch unit includes a first AND gate and a second AND gate; the first input end of the first AND gate is connected to the output end of the first edge collection subunit, the second input end of the first AND gate is connected to the output end of the second AND gate, the first input end of the second AND gate is connected to the output end of the second edge collection subunit, and the second input end of the second AND gate is connected to the output end of the first AND gate.

[0013] In combination with the first aspect, in some possible implementations, the first delay module includes a plurality of third inverters connected in series and a first capacitor; the first third inverter among the plurality of third inverters is connected to the input voltage, and the output end of the last third inverter among the plurality of third inverters outputs the first drive signal; one end of the first capacitor is connected to the output end of the last third inverter, and the other end is grounded, for limiting the delay time of the first delay module; the number of the plurality of third inverters connected in series is an even number.

[0014] In the above technical solution, the dead time of the first delay module can be set by changing the capacitance of the first capacitor.

[0015] In combination with the first aspect, in some possible implementations, the second delay module includes a plurality of fourth inverters connected in series and a second capacitor; the first fourth inverter among the plurality of fourth inverters is connected to the output end of the first delay module, and the output end of the last fourth inverter among the plurality of fourth inverters outputs an inversion control signal; one end of the second capacitor is connected to the output end of the last fourth inverter, and the other end is grounded, for limiting the delay time of the second delay module; the number of the plurality of fourth inverters connected in series is an odd number.

[0016] In the above technical solution, the dead time of the second delay module can be set by changing the capacitance of the second capacitor.

[0017] In a second aspect, an embodiment of the present application provides a half-bridge drive circuit, comprising a load, the half-bridge drive circuit described in any optional manner in the first aspect, a high-side drive module, and a low-side drive module; the input end of the high-side drive module is connected to the first output end of the drive signal generating circuit for receiving a first drive signal, and the output end is connected to the load for charging the load according to the first drive signal; the input end of the low-side drive module is connected to the second output end of the drive signal generating circuit for receiving a second drive signal, and the output end is connected to the load for controlling the discharge of the load according to the second drive signal.

[0018] In a third aspect, an embodiment of the present application provides a laser radar, comprising the half-bridge drive circuit described in the second aspect.

[0019] In a fourth aspect, an embodiment of the present application provides a movable device, comprising a movable main body and the laser radar described in the third aspect, wherein the laser radar is mounted on the main body.

[0020] Based on the constant current transmitting circuit and laser radar provided in this application. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0022] Figure 1 It is a schematic diagram of a framework structure of a laser radar provided in the related art;

[0023] Figure 2 It is a schematic diagram of the framework structure of another laser radar provided in the related art;

[0024] Figure 3 It is a timing diagram of a first control signal and a second control signal provided in the related art;

[0025] Figure 4 It is a circuit structure diagram of a signal generating module provided in the related art;

[0026] Figure 5 is a timing diagram of another first control signal and a second control signal provided in the related art;

[0027] Figure 6 It is a schematic diagram of the framework structure of a half-bridge drive circuit provided in an embodiment of the present application;

[0028] Figure 7 It is a schematic diagram of the framework structure of a driving signal generating circuit provided in an embodiment of the present application;

[0029] Figure 8 is a circuit structure diagram of a driving signal generating circuit provided in an embodiment of the present application;

[0030] Fig. 9 is a circuit structure diagram of another driving signal generating circuit provided in an embodiment of the present application;

[0031] Fig.10 is a circuit structure diagram of another driving signal generating circuit provided in an embodiment of the present application;

[0032] Fig.11is a circuit structure diagram of another driving signal generating circuit provided in an embodiment of the present application;

[0033] Fig.12 is a circuit structure diagram of another driving signal generating circuit provided in an embodiment of the present application;

[0034] Fig.13 is a circuit structure diagram of another driving signal generating circuit provided in an embodiment of the present application;

[0035] Fig.14 is a circuit structure diagram of another driving signal generating circuit provided in an embodiment of the present application;

[0036] Fig.15 It is a timing diagram provided by an embodiment of the present application;

[0037] Fig.16 Schematic diagram of the circuit structure of another driving signal generating circuit provided in an embodiment of the present application.

[0038] Reference numerals:

[0039] 1. Half-bridge circuit; 11. High-side control module; 12. High-side switch; 13. Low-side control module; 14. Low-side switch; 15. Signal generating module; 151. First inverting module; 152. Second inverting module; 2. Laser; 3. Half-bridge driving circuit; 31. Load; 32. Driving signal generating circuit; 321. First delay module; 322. Second delay module; 323. Edge acquisition module; 3231. Edge acquisition unit; 32311. First edge acquisition subunit; 32312. Second edge acquisition subunit; 33. High-side driving module; 34. Low-side driving module; 3232. Latch unit;

[0040] VIN, input voltage; VDC, DC voltage; VDD, operating voltage; GND, ground terminal; PW, pulse width; DT, dead time; HS, first control signal; LS, second control signal; HO, third control signal; LO, fourth control signal; 32A, first drive signal; 32B, second drive signal; 321A, inverting control signal; 3231A, first edge signal; 3231B, second edge signal; NAND1, first NAND gate; NAND2, second NAND gate; NAND3, third NAND gate; INV1, first inverter; INV2, second inverter; INV3, third inverter; INV4, fourth inverter; INV5, fifth inverter; INV6, sixth inverter; INV7, seventh inverter; C1, first capacitor; C2, second capacitor; NAD1, first AND gate; NAD2, second AND gate. DETAILED DESCRIPTION

[0041] In order to make the objectives, technical solutions and advantages of the present application more clear, the embodiments of the present application will be further described in detail below with reference to the accompanying drawings.

[0042] When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Instead, they are only examples of devices and methods consistent with some aspects of the present application as detailed in the attached embodiments.

[0043] In the description of the present application, it should be understood that the terms "first", "second", etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to the specific circumstances. In addition, in the description of the present application, unless otherwise specified, "multiple" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated before and after are in an "or" relationship.

[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used in this specification are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0045] Before introducing the embodiments of the present application, the professional terms that may be involved in the embodiments of the present application are explained below.

[0046] Lidar: A radar system that uses laser beams to detect the position, speed and other characteristic quantities of a target. Its working principle is to emit a detection signal (laser beam) to the target object, and then compare the received echo signal reflected from the target object with the detection signal (or local oscillator signal). After appropriate processing, relevant information about the target object relative to the Lidar can be obtained, such as distance, direction, height, speed, attitude, and even shape parameters.

[0047] Half-bridge circuit: The working principle is based on field effect transistors with switching control functions such as Metal Oxide Semiconductor Field Effect Transistor (MOSFET). The on-time of MOSFET is controlled by pulse width modulation (PWM) signal, so that MOSFET works in high level or low level mode in each cycle.

[0048] At present, laser radar usually uses a half-bridge circuit to charge and discharge the laser, thereby completing the light emission and reset of the laser. Figure 1 As shown, the first end of the half-bridge circuit 1 is used to connect to the input voltage VIN, the second end of the half-bridge circuit 1 is used to connect to the working voltage VDD, and the third end of the half-bridge circuit 1 is connected to the ground terminal GND. Figure 1 As shown, the half-bridge circuit 1 may generally include a high-side control module 11, a high-side switch 12, a low-side control module 13 and a low-side switch 14, the input voltage VIN is used to generate a first control signal HS and a second control signal LS, the first end of the high-side control module 11 is used to access the first control signal HS, the first end of the low-side control module 13 is used to access the second control signal LS, the second end of the high-side control module 11 is connected to the controlled end of the high-side switch 12, the second end of the low-side control module 13 is connected to the controlled end of the low-side switch 13, the first end of the high-side switch 12 is connected to the DC voltage VDC, the first end of the low-side switch 14 is connected to the ground end GND, the second end of the high-side switch 12 is connected to the second end of the low-side switch 14 and connected to the laser 2.

[0049] Among them, the first control signal HS and the second control signal LS generated by the input voltage VIN are used to drive the high-side control module 11 and the low-side control module 13 respectively, so that the high-side control module 11 and the low-side control module 13 respectively generate the third control signal HO and the fourth control signal LO to correspondingly control the on and off of the high-side switch 12 and the low-side switch 14. Exemplarily, when it is necessary to charge the laser 2, the third control signal HO is at a high level, the high-side switch 12 is turned on, the fourth control signal LO is at a low level, the low-side switch 14 is turned off, and the DC voltage VDC charges (charges) the laser 2; when it is necessary to discharge the laser 2, the third control signal HO is at a low level, the high-side switch 12 is turned off, the fourth control signal LO is at a high level, the low-side switch 14 is turned on, and the laser 2 discharges through the low-side switch 14.

[0050] Here, it is worth noting that at the same time, the first control signal HS and the second control signal LS generated by the signal generating module 11 are usually a high signal and a low signal, and the first control signal HS and the second control signal LS are not at high level at the same time, so that the high side switch 12 and the low side switch 14 are not turned on at the same time, so as to ensure the reliability of the half-bridge circuit 1. However, in the actual use of the half-bridge circuit 1, the high side switch 12 and the low side switch 14 may be turned on at the same time, resulting in a short circuit of the half-bridge circuit 1, thereby generating a large current loss problem. In severe cases, it may even cause thermal failure of the high side switch 12 and the low side switch 14, affecting the reliability of the half-bridge circuit 1, and further affecting the reliability of the laser radar using the half-bridge circuit 1.

[0051] At present, in the related technologies, such as Figure 2 As shown, a signal generating module 15 is usually provided at the input end of the half-bridge circuit 1, that is, a signal generating module 15 is provided at the input voltage VIN, and the signal generating module 15 is used to adjust the width of the second control signal LS according to the input voltage VIN and the first control signal HS. Here, it is worth noting that Figure 3 As shown, at this time, the width of the first control signal HS generated by the signal generating module 15 is the same as the pulse width PW of the input voltage VIN and does not change. The signal generating module 15 can adjust the width of the second control signal LS according to the high level signal of the first control signal HS. At this time, compared with the first control signal HS, the rising edge and falling edge signals of the second control signal LS are delayed by 1 times the dead time DT, so that the high-side switch 12 and the low-side switch 14 will not be turned on at the same time, avoiding the high-side switch 12 and the low-side switch 14 from being turned on at the same time, causing the half-bridge circuit 1 to short-circuit, thereby generating a large current loss problem, thereby ensuring the reliability of the use of the half-bridge circuit 1. However, as Figure 3 As shown, the rising edge and falling edge signals of the second control signal LS are both delayed by 1 times the dead time DT, so the pulse width PW of the input voltage VIN needs to be at least greater than 2 times the dead time DT to avoid generating erroneous information. As a result, the pulse width PW of the input voltage VIN is limited by the dead time DT delayed by the signal generating module 15.

[0052] like Figure 4As shown, the signal generating module 15 in the related art may include a second NAND gate NAND2 , a third NAND gate NAND3 , a fifth inverter INV5 , a sixth inverter INV6 , a seventh inverter INV7 , a first inversion module 151 and a second inversion module 152 . The first input end of the second NAND gate NAND2 and one end of the fifth inverter INV5 are used to access the input voltage VIN, the other end of the fifth inverter INV5 is connected to the first input end of the third NAND gate NAND3, the second input end of the second NAND gate NAND2 is connected to the output end of the second inversion module 152 and one end of the seventh inverter INV7, the second input end of the third NAND gate NAND3 is connected to the output end of the first inversion module 151 and one end of the sixth inverter INV6, the output end of the second NAND gate NAND2 is connected to the input end of the first inversion module 151, the output end of the third NAND gate NAND3 is connected to the input end of the second inversion module 152, the other end of the sixth inverter INV6 is used to output the first control signal HS, and the other end of the seventh inverter INV7 is used to output the second control signal LS.

[0053] The first inverting module 151 and the second inverting module 152 respectively include a plurality of inverters connected in series, and the number of the plurality of inverters is an even number, so as to delay the signals output by the second NAND gate NAND2 and the third NAND gate NAND3. Figure 5 As shown, the input voltage VIN outputs the first control signal HS through the second NAND gate NAND2, the first inverting module 151 and the sixth inverter INV6. At this time, compared with the pulse width PW of the input voltage VIN, the rising edge of the first control signal HS is delayed by 2 times the dead time DT, and the falling edge of the first control signal HS is delayed by 1 times the dead time DT. The input voltage VIN outputs the second control signal LS through the third NAND gate NAND3, the second inverting module 152 and the seventh inverter INV7. At this time, compared with the pulse width PW of the input voltage VIN, the falling edge and the rising edge of the second control signal LS are both delayed by 1 times the dead time DT. In this way, in the related art, the first control signal HS and the second control signal LS can be delayed respectively through the signal generating module 15, thereby avoiding the problem that the high-side switch 12 and the low-side switch 14 are turned on at the same time, causing the half-bridge circuit 1 to be short-circuited, thereby generating a large current loss.

[0054] However, in the related art, when a dead time DT is inserted between the first control signal HS and the second control signal LS, Figure 5As shown, there may be a problem that the width of the first control signal HS received by the high-side switch 12 is smaller than the pulse width PW of the input voltage VIN, that is, the delayed first control signal HS may have a signal width loss problem, thereby reducing the charging time, resulting in poor reliability of the laser radar emitting laser. Moreover, in the related art, the rising edge of the first control signal HS is delayed by 2 times the dead time DT, so that the pulse width PW of the input voltage VIN needs to be at least greater than 2 times the dead time DT to avoid generating erroneous information, so that the pulse width PW of the input voltage VIN is limited by the signal generating module 15.

[0055] To this end, an embodiment of the present application provides a drive signal generating circuit, a half-bridge drive circuit and a laser radar. The drive signal generating circuit determines the dead time of the first drive signal and the second drive signal through an edge signal, and the rising edge and the falling edge of the first drive signal are delayed by the same time, so that the width of the delayed first drive signal is consistent with the pulse width of the input voltage, thereby ensuring the charging stability of the load and further ensuring the reliability of the laser radar.

[0056] The following is an exemplary introduction to the drive signal generating circuit, half-bridge drive circuit, laser radar and movable device provided in the present application in conjunction with the accompanying drawings.

[0057] like Figure 6 As shown, the half-bridge driving circuit 3 provided in the embodiment of the present application may include a load 31, a driving signal generating circuit 32, a high-side driving module 33 and a low-side driving module 34. The input end of the driving signal generating circuit 32 is used to access the input voltage VIN, and obtain the first driving signal 32A and the second driving signal 32B according to the input voltage VIN. The input end of the high-side driving module 33 is connected to the first output end of the driving signal generating circuit 32 for accessing the first driving signal 32A. The output end of the high-side driving module 33 is connected to the load 31. The input end of the low-side driving module 34 is connected to the second output end of the driving signal generating circuit 32 for accessing the second driving signal 32B. The output end of the low-side driving module 34 is connected to the load 31. The high-side driving module 33 can charge the load 31 according to the first driving signal 32A, and the low-side driving module 34 can control the load 31 to discharge according to the second driving signal 32B to ensure the reliability of the load 31.

[0058] The load 31 may be a laser diode, the high-side driving module 33 controls the laser diode to emit light according to the first driving signal 32A, and the low-side driving module 34 controls the laser diode to reset according to the second driving signal 32B to ensure the reliability of the laser diode.

[0059] In order to avoid the first drive signal 32A and the second drive signal 32B being at high levels at the same time, resulting in a short circuit of the half-bridge drive circuit 3, thereby generating a large current loss problem, in serious cases, it may even cause thermal failure of the high-side drive module 33 and the low-side drive module 34, affecting the reliability of the half-bridge drive circuit 3, and further affecting the reliability of the laser radar using the half-bridge drive circuit 3. In one example, Figure 7 As shown, the drive signal generating circuit 32 may include a first delay module 321, a second delay module 322 and an edge acquisition module 323. The input end of the first delay module 321 is used to access the input voltage VIN, the input end of the second delay module 322 is connected to the output end of the first delay module 321, the first input end of the edge acquisition module 323 is connected to the output end of the second delay module 322, and the second input end is used to access the input voltage VIN.

[0060] Among them, the first delay module 321 can delay the input voltage VIN to obtain the first drive signal 32A, and the first drive signal 32A at this time is a signal after delay processing. Here, it can be understood that the time for the first delay module 321 to control the delayed response of the first drive signal 32A can be a dead time DT, and the first delay module 321 can set the dead time DT according to different requirements, and there is no limitation on this.

[0061] Optional, such as Figure 8 As shown, the first delay module 321 may include a plurality of third inverters INV3 and a first capacitor C1 connected in series in sequence, one end of the first third inverter INV3 among the plurality of third inverters INV3 is connected to the input voltage VIN, the other end of the first third inverter INV3 is connected to the input end of the last third inverter INV3, the output end of the last third inverter INV3 outputs the first drive signal 32A to the high-side driver module 33, one end of the first capacitor C1 is connected to the output end of the last third inverter INV3, the other end of the first capacitor C1 is grounded, and the first capacitor C1 is used to limit the delay time of the first delay module 321, that is, the dead time DT of the first delay module 321 can be set by changing the capacitance of the first capacitor C1.

[0062] Here, it is worth explaining that the first delay module 321 only delays the input voltage VIN without inverting it. Therefore, the number of multiple third inverters INV3 connected in series is an even number, so that the first drive signal 32A output by the multiple third inverters INV3 connected in series is the same as the edge signal of the input voltage VIN, that is, assuming that the input voltage VIN is initially an upper edge signal, the first drive signal 32A after delay by multiple third inverters INV3 connected in series in sequence is also initially an upper edge signal, so as to ensure the consistency of the first drive signal 32A and the input voltage VIN edge signal, and avoid the problem that the load 21 cannot be charged normally due to different edge signals. Figure 8 Taking setting two third inverters INV3 as an example, the number of the third inverters INV3 can be set according to actual needs, and this application does not make any specific limitation on this.

[0063] The input end of the second delay module 322 is connected to the output end of the first delay module 321, and is used to delay the first drive signal 32A and invert it into an inverted control signal 321A, that is, the second delay module 322 needs to delay and invert the first drive signal 32A.

[0064] Optional, such as Fig. 9 As shown, the second delay module 322 may include a plurality of fourth inverters INV4 and a second capacitor C2 connected in series in sequence. The first fourth inverter INV4 among the plurality of fourth inverters INV4 connected in series in sequence is connected to the output end of the first delay module 321, and the output end of the last fourth inverter INV4 among the plurality of fourth inverters INV4 outputs an inversion control signal 321A. One end of the second capacitor C2 is connected to the output end of the last fourth inverter INV4, and the other end of the second capacitor C2 is grounded. The second capacitor C2 is used to limit the delay time of the second delay module 322, that is, the dead time DT of the second delay module 322 can be set by changing the capacitance of the second capacitor C2.

[0065] Here, it is worth explaining that the second delay module 322 needs to delay and invert the first drive signal 32A. Therefore, the number of multiple fourth inverters INV4 connected in series is an odd number, so that the inverted control signal 321A output by the multiple fourth inverters INV4 connected in series is different from the edge signal of the first drive signal 32A, that is, assuming that the first drive signal 32A is initially an upward edge signal, the inverted control signal 321A after delay and inversion by multiple fourth inverters INV4 connected in series in sequence is initially a falling edge signal. Fig. 9 Taking the setting of three fourth inverters INV4 as an example, the number of the fourth inverters INV4 can be set according to actual needs, and this application does not make any specific limitation on this.

[0066] In order to avoid the problem that the second drive signal 32B and the first drive signal 32A are both at high level, the embodiment of the present application can determine the edge signal of the second drive signal 32B through the edge acquisition module 323, and then obtain the width of the second drive signal 32B. The first input end of the edge acquisition module 323 is connected to the output end of the second delay module 322, and the second input end of the edge acquisition module 323 is used to access the input voltage VIN. The edge acquisition module 323 can determine the edge signal of the second drive signal 32B according to the input voltage VIN and the inverted control signal 321A, and then obtain the width of the second drive signal 32B.

[0067] In this way, the drive signal generating circuit 32 in the embodiment of the present application can delay the input voltage VIN to obtain the first drive signal 32A and the second drive signal 32B, and the first drive signal 32A and the second drive signal 32B are not high at the same time, avoiding the first drive signal 32A and the second drive signal 32B being high at the same time, so that the half-bridge drive circuit 3 using the drive signal generating circuit 32 is short-circuited, thereby generating a large current loss problem. Further, on the one hand, the present application can delay the input voltage VIN through the first delay module 321 to obtain the first drive signal 32A, and the first delay module 321 can accurately control the dead time DT of the first drive signal 32A, so that the upper edge and the falling edge of the first drive signal are delayed by the same time, and the width of the delayed first drive signal 32A is consistent with the pulse width PW of the input voltage VIN, avoiding the problem of signal width loss in the delayed first drive signal 32A, thereby ensuring the reliability of charging the load. On the other hand, the present application delays and inverts the first drive signal 32A through the second delay module 322 to obtain the inverted control signal 321A, and then determines the edge signal of the second drive signal 32B according to the input voltage VIN and the inverted control signal 321A through the edge acquisition module 323, and then obtains the width of the second drive signal 32B, that is, the width of the second drive signal 32B can be determined according to the distance between the input voltage VIN and the edge signal of the inverted control signal 321A, rather than being determined solely by the level signal of the first drive signal 32A, thereby avoiding the problem that the pulse width PW of the input voltage VIN is limited by the dead time DT of the delay of the drive signal generating circuit 32.

[0068] In order to determine the edge signal of the second drive signal 32B according to the input voltage VIN and the inverted control signal 321A, and then obtain the width of the second drive signal 32B, in one example, as shown in FIG. Fig.10As shown, the edge acquisition module 323 may include an edge acquisition unit 3231. The first input end of the edge acquisition unit 3231 is connected to the output end of the second delay module 322, and is used to collect the rising edge pulse signal of the inverted control signal 321A, and obtain the first edge signal 3231A according to the rising edge pulse signal of the inverted control signal 321A. The second input end of the edge acquisition unit 3231 is connected to the input voltage VIN, and is used to collect the rising edge pulse signal of the input voltage VIN, and obtain the second edge signal 3231B according to the rising edge pulse signal of the input voltage VIN, that is, by determining the distance between the input voltage VIN and the rising edge pulse signal of the inverted control signal 321A, the width of the second drive signal 32B is obtained. Here, it can be understood that the first edge signal 3231A and the second edge signal 3231B are two edge signals of the second drive signal 32B.

[0069] In this way, the edge acquisition unit 3231 can collect the rising edge pulse signals of the input voltage VIN and the inverted control signal 321A, and obtain the first edge signal 3231A and the second edge signal 3231B, thereby obtaining the width of the second drive signal 32B. That is, at this time, the width of the second drive signal 32B is determined by the distance between the edge signals of the input voltage VIN and the inverted control signal 321A, rather than being determined solely by the level signal of the first drive signal 32A, thereby avoiding the problem that the pulse width PW of the input voltage VIN is limited by the dead time DT of the delay of the drive signal generating circuit 32.

[0070] In order to ensure the accuracy of collecting the edge signals of the input voltage VIN and the inverting control signal 321A, in one example, Fig.11 As shown, the edge acquisition unit 3231 may include a first edge acquisition subunit 32311 and a second edge acquisition subunit 32312. The input end of the first edge acquisition subunit 32311 is connected to the output end of the second delay module 322. The first edge acquisition subunit 32311 can acquire the rising edge pulse signal of the inverted control signal 321A and generate the first edge signal 3231A. The input end of the second edge acquisition subunit 32312 is connected to the input voltage VIN. The second edge acquisition subunit 32312 can acquire the rising edge pulse signal of the input voltage VIN and generate the second edge signal 3231B, and determine the width of the second drive signal 32B according to the second edge signal 3231B and the second edge signal 3231B. In this way, the edge signals of the input voltage VIN and the inverted control signal 321A are respectively acquired by the first edge acquisition subunit 32311 and the second edge acquisition subunit 32312, thereby ensuring the accuracy of acquisition.

[0071] Optional, such as Fig.12As shown, the first edge acquisition subunit 32311 may include a plurality of first inverters INV1 and a first NAND gate NANA1, wherein the plurality of first inverters INV1 are sequentially connected in series and then connected in series with the first NAND gate NANA1, the first first inverter INV1 among the plurality of first inverters INV1 is connected to the output end of the second delay module 322, the last first inverter INV1 among the plurality of first inverters INV1 is connected to the first input end of the first NAND gate NANA1, the second input end of the first NAND gate NANA1 is connected to the output end of the second delay module 322, and the output end of the first NAND gate NANA1 is used to output the first edge signal 3231A, wherein the number of the plurality of first inverters INV1 connected in series is an odd number. The inverted control signal 321A is delayed and inverted by the plurality of first inverters INV1 to obtain an inverted signal of the inverted control signal 321A, and the first NAND gate NANA1 obtains the first edge signal 3231A according to the inverted signal and the inverted control signal 321A.

[0072] Optional, such as Fig.13 As shown, the second edge acquisition subunit 32312 may include a plurality of second inverters and a second NAND gate NANA2, wherein the plurality of second inverters INV2 are sequentially connected in series and then connected in series with the second NAND gate NANA2, the first second inverter INV2 among the plurality of second inverters INV2 is connected to the input voltage VIN, the last second inverter INV2 among the plurality of second inverters INV2 is connected to the first input end of the second NAND gate NANA2, the second input end of the second NAND gate NANA2 is connected to the input voltage VIN, and the output end of the second NAND gate NANA2 is used to output the second edge signal 3231B, wherein the number of the plurality of second inverters INV2 connected in series is an odd number. The input voltage VIN is delayed and inverted by the plurality of second inverters INV2 to obtain an inverted signal of the input voltage VIN, and the second NAND gate NANA2 obtains the second edge signal 3231B according to the inverted signal and the input voltage VIN.

[0073] Since the first edge signal 3231A and the second edge signal 3231B obtained by the edge acquisition unit 3231 are narrow pulse signals, and the first drive signal 32A is a short pulse signal, in order to make the second drive signal 32B obtained according to the first edge signal 3231A and the second edge signal 3231B a short pulse signal, in an example, Fig.14As shown, the edge acquisition module 323 may also include a latch unit 3232, wherein the first input end of the latch unit 3232 is connected to the first output end of the edge acquisition unit 3231, and the second input end of the latch unit 3232 is connected to the second output end of the edge acquisition unit 3231. The latch unit 3232 is used to determine the narrow pulse signal (i.e., the first edge signal 3231A and the second edge signal 3231B) to obtain a short pulse signal (i.e., the second drive signal 32B), so that the second drive signal 32B is a short pulse signal corresponding to the first drive signal 32A.

[0074] like Fig.15 The timing diagram of the input voltage VIN, the first drive signal 32A, the second drive signal 32B, the inverting control signal 321A, the first edge signal 3231A and the second edge signal 3231B is shown. As can be seen from the figure, compared with the input voltage VIN, the rising edge of the first drive signal 32A and the falling edge of the second drive signal 32B are delayed by 1 times the dead time DT respectively, and compared with the first drive signal 32A, the rising edge of the second drive signal 32B is delayed by 1 times the dead time DT. In this way, the first drive signal 32A and the second drive signal 32B are avoided to be high at the same time, resulting in a short circuit of the half-bridge drive circuit 3, thereby generating a large current loss problem, and ensuring the reliability of the half-bridge drive circuit 3.

[0075] Optional, such as Fig.16 As shown, the latch unit 3232 may include a first AND gate AND1 and a second AND gate AND2, the first input end of the first AND gate AND1 is connected to the output end of the first edge collection subunit 32311, the second input end of the first AND gate AND1 is connected to the output end of the second AND gate AND2, the first input end of the second AND gate AND2 is connected to the output end of the second edge collection subunit 32312, and the second input end of the second AND gate AND2 is connected to the output end of the first AND gate AND1.

[0076] The present application also provides a laser radar, which can be the half-bridge driving circuit 3 in the above embodiment. It should be noted that technicians can delete, replace or add components in the laser radar according to actual conditions, and this application does not make specific restrictions on this.

[0077] The embodiment of the present application also provides a movable device, which includes the laser radar in the above embodiment and a movable device body, and the laser radar is mounted on the device body. The beneficial effects that can be achieved by the movable device include the beneficial effects that can be achieved by the above laser radar, which will not be described in detail.

[0078] Through the description of the above implementation methods, technical personnel in the relevant field can understand that for the convenience and simplicity of description, only the division of the above-mentioned functional modules is used as an example. In actual applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0079] In the embodiments provided in the present application, it should be understood that the disclosed devices can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of modules or units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0080] The above contents are only specific implementation methods of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A driving signal generating circuit, applied to laser radar, characterized in that: The driving signal generating circuit comprises: A first delay module, whose input end is used to connect an input voltage, and is used to delay the input voltage to obtain a first drive signal, and the first delay module is used to control the time of delayed response of the first drive signal to be a dead time; a second delay module, whose input end is connected to the output end of the first delay module, and is used to delay the first driving signal and invert it into an inverted control signal; and The edge acquisition module has a first input terminal connected to the output terminal of the second delay module, and a second input terminal used to access the input voltage, and is used to determine and derive a second drive signal based on the input voltage and the inverted control signal.

2. The driving signal generating circuit according to claim 1, characterized in that: The edge acquisition module comprises: an edge acquisition unit, wherein the first input end is connected to the output end of the second delay module, and is used to acquire the rising edge pulse signal of the inverted control signal, and derive the first edge signal according to the rising edge pulse signal of the inverted control signal; the second input end of the edge acquisition unit is connected to the input voltage, and is used to acquire the rising edge pulse signal of the input voltage, and derive the second edge signal according to the rising edge pulse signal of the input voltage; and a latch unit, a first input end connected to the first output end of the edge acquisition unit, a second input end connected to the second output end of the edge acquisition unit, and configured to determine a second drive signal according to the first edge signal and the second edge signal; The first edge signal and the second edge signal are narrow pulse signals, and the second driving signal is a short pulse signal.

3. The driving signal generating circuit according to claim 2, characterized in that: The edge acquisition unit comprises: A first edge acquisition subunit, whose input end is connected to the output end of the second delay module, and whose output end is connected to the first input end of the latch unit, is used to acquire the rising edge pulse signal of the inverted control signal and generate the first edge signal, and output it to the latch unit; and The second edge acquisition subunit has an input terminal connected to the input voltage and an output terminal connected to the second input terminal of the latch unit, and is used to acquire the rising edge pulse signal of the input voltage and generate the second edge signal, which is output to the latch unit.

4. The driving signal generating circuit according to claim 3, characterized in that: The first edge acquisition subunit includes a plurality of first inverters and a first NAND gate, wherein the plurality of first inverters are sequentially connected in series and then connected in series with the first NAND gate, the first of the plurality of first inverters is connected to the output end of the second delay module, the last of the plurality of first inverters is connected to the first input end of the first NAND gate, the second input end of the first NAND gate is connected to the output end of the second delay module, and the output end of the first NAND gate is connected to the first input end of the latch unit; The number of the plurality of first inverters connected in series is an odd number.

5. The driving signal generating circuit according to claim 3, characterized in that: The second edge acquisition subunit comprises a plurality of second inverters and a second NAND gate, wherein the plurality of second inverters are sequentially connected in series and then connected in series with the second NAND gate, the first of the plurality of second inverters is connected to the input voltage, the last of the plurality of second inverters is connected to the first input end of the second NAND gate, the second input end of the second NAND gate is connected to the input voltage, and the output end of the second NAND gate is connected to the second input end of the latch unit; The number of the plurality of second inverters connected in series is an odd number.

6. The driving signal generating circuit according to claim 3, characterized in that: The latch unit includes a first AND gate and a second AND gate; The first input end of the first AND gate is connected to the output end of the first edge collection subunit, the second input end of the first AND gate is connected to the output end of the second AND gate, the first input end of the second AND gate is connected to the output end of the second edge collection subunit, and the second input end of the second AND gate is connected to the output end of the first AND gate.

7. The driving signal generating circuit according to any one of claims 1 to 6, characterized in that: The first delay module comprises: a plurality of third inverters connected in series in sequence, wherein a first third inverter among the plurality of third inverters is connected to the input voltage, and an output terminal of a last third inverter among the plurality of third inverters outputs a first driving signal; and A first capacitor, one end of which is connected to the output end of the last third inverter, and the other end of which is grounded, and is used to limit the delay time of the first delay module; The number of the plurality of third inverters connected in series is an even number.

8. The driving signal generating circuit according to claim 7, characterized in that: The second delay module comprises: a plurality of fourth inverters connected in series in sequence, wherein a first fourth inverter among the plurality of fourth inverters is connected to an output end of the first delay module, and an output end of a last fourth inverter among the plurality of fourth inverters outputs an inverting control signal; and A second capacitor, one end of which is connected to the output end of the last fourth inverter, and the other end of which is grounded, and is used to limit the delay time of the second delay module; The number of the plurality of fourth inverters connected in series is an odd number.

9. A half-bridge driving circuit, characterized in that: include: load; The driving signal generating circuit according to any one of claims 1 to 8; A high-side driver module, whose input end is connected to the first output end of the drive signal generating circuit for receiving the first drive signal, and whose output end is connected to the load for charging the load according to the first drive signal; as well as A low-side driving module has an input end connected to the second output end of the driving signal generating circuit for receiving the second driving signal, and an output end connected to the load for controlling the load to discharge according to the second driving signal.

10. A laser radar, characterized in that: Comprising the half-bridge driving circuit as claimed in claim 9.

11. A movable device, characterized in that: It comprises a movable main body and a laser radar as described in claim 10, wherein the laser radar is mounted on the main body.

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