A low mismatch low power charge pump circuit with lock detection module

Abstract

The application belongs to the field of integrated circuits, and particularly relates to a low-mismatch low-power charge pump circuit with a lock detection module. The application improves the suppression capability of phase-locked loop (PLL) spurs by introducing a negative feedback circuit to control the charging and discharging current size in the traditional charge pump structure and by introducing a current replication circuit to improve the switching speed of the charge pump, and simultaneously controls the charging and discharging current size of the charge pump by introducing a lock detection module in the charge pump structure, thereby greatly reducing the power consumption of the charge pump circuit. Finally, the application effectively solves the problems of relatively poor noise, spur performance and power consumption of the existing charge pump circuit.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuits, and specifically relates to a low-mismatch, low-power charge pump circuit with a lock-in detection module. Background Technology

[0002] With the rapid development of wireless communication technology, the demand for high-speed, high-capacity, low-latency, and low-power communication is increasing. Therefore, communication systems need to rely on high-quality frequency sources to handle higher data rates and more complex signal processing tasks. Charge-pump phase-locked loops (CPPLLs), with their excellent performance and stability, have become an ideal choice for realizing high-quality frequency sources. Since the performance of the charge pump circuit directly affects the phase noise and spurious performance of the entire CPPLL system, optimizing the charge pump circuit design to suppress spurious emissions and improve phase noise, while balancing power consumption requirements, plays a crucial role in enhancing the performance of communication systems.

[0003] Currently, the common design approach for CMOS charge pump circuits is to use PMOS and NMOS transistors to handle charging and discharging functions respectively, with the charge pump's charging and discharging process controlled by the output signal of the phase-detector in the charge pump's pre-amplifier circuit within the phase-locked loop (PLL). Since the output signal of the phase-detector reflects the phase difference between the PLL's reference clock and feedback clock signals, a "dead zone" effect occurs when this phase difference is too small, preventing the charge pump from obtaining a stable charging and discharging current. Therefore, a certain delay is introduced into the phase-detector during the initial design of the PLL system, ensuring that the output signal is simultaneously high or low to mitigate the "dead zone" effect. This allows the charge pump to continue periodically conducting even after the PLL is locked. However, if the charge pump's switching speed is too slow, resulting in a long conduction time, the phase difference between the reference clock and feedback clock signals will be large after the PLL is locked, deteriorating the PLL's phase noise and spurious performance. Meanwhile, since the charging and discharging currents of PMOS and NMOS transistors change in opposite directions with their drain voltage, it is difficult to achieve good consistency in the charging and discharging currents. This also increases the phase difference between the reference clock signal and the feedback clock signal after the phase-locked loop (PLL) is locked, thus deteriorating the PLL's spurious performance. Furthermore, although the phase noise performance of the PLL can be optimized by increasing the charging and discharging current of the charge pump, this drastically increases the power consumption of the charge pump.

[0004] With the advancement of integrated circuit process nodes and the demand for miniaturization and low power consumption, balancing the noise performance of phase-locked loops (PLLs) and the power consumption requirements of charge pumps, as well as suppressing PLL spurious emissions by reducing current mismatch in charge pumps and increasing switching speed, have become urgent technical problems to be solved. Summary of the Invention

[0005] To address the aforementioned problems and shortcomings, and to resolve the issues of noise, spurious performance, and relatively poor power consumption in existing charge pump circuits, this invention provides a low-mismatch, low-power charge pump circuit with a lock-in detection module. While maintaining the normal function of the charge pump, this invention improves the suppression of phase-locked loop (PLL) spurious emissions by introducing a negative feedback circuit to control the charging and discharging current magnitude in the traditional charge pump structure, and by introducing a current replication circuit to increase the switching speed of the charge pump. Simultaneously, by introducing a lock-in detection module into the charge pump structure to control the charge pump charging and discharging current magnitude, the power consumption of the charge pump circuit is significantly reduced.

[0006] A low-mismatch, low-power charge pump circuit with a lock-in detection module includes: a charge pump main module, a current tracking module, an auxiliary charging and discharging module, and a lock-in detection module.

[0007] The charge pump main module adjusts the charging and discharging time of the load capacitor of the loop filter in the charge pump's post-stage circuit of the phase-locked loop according to the output signal of the frequency and phase detector of the charge pump's pre-stage circuit in the phase-locked loop, and converts the phase difference between the reference clock signal and the feedback clock signal of the phase-locked loop into a charge quantity signal.

[0008] The current tracking module detects changes in the charging current of the charge pump main module and adjusts the discharge current of the charge pump main module to be the same as the charging current.

[0009] The auxiliary charge-discharge module provides a second path for the charge-discharge current of the main charge pump module, ensuring that the charge-discharge current source transistor in the main charge pump module is always turned on. At the same time, the charge-discharge current source transistor in the second path has the same current as the charge-discharge current source transistor in the main charge pump module, thereby reducing the voltage difference between the drain node and the output node of the charge-discharge current source transistor in the main charge pump module and reducing the charge pump current mismatch.

[0010] The locking detection module determines whether the phase-locked loop is locked based on the output voltage of the charge pump main module, thereby controlling the charge pump main module, the current tracking module, and the auxiliary charging and discharging module to simultaneously flow with a larger current before the phase-locked loop is locked or a smaller current after the phase-locked loop is locked.

[0011] Furthermore, the charge pump main module includes transistors MP4, MP5, MN3, MN4, MP10, MN9 and switches SW2 and SW5.

[0012] The gates of MP4 and MP5 are connected and connected to the bias current IREF. The sources of MP4 and MP5 are both connected to the power supply potential VDD. The drains of MP4 and MP5 are respectively connected to the two ends of switch SW2. The drain of MP4 is also connected to the source of MP10. The gate of MP10 is connected to the output signal UP of the frequency and phase detector of the pre-amplifier circuit. The drain of MP10 is connected to the drain of MN9 and serves as the output node VCTRL. The gate of MN9 is connected to the output signal DN of the frequency and phase detector of the pre-amplifier circuit. The source of MN9 is connected to one end of switch SW5 and the drain of MN3. The gates of MN3 and MN4 are connected and connected to the output of the operational amplifier OP in the current tracking module. The sources of MN3 and MN4 are both grounded to the potential GND. The drains of MN3 and MN4 are respectively connected to the two ends of switch SW5.

[0013] Transistors MP4 and MP5 are charging current sources, while transistors MN3 and MN4 are discharging current sources. Transistors MP10 and MN9 are switched on and off by the output signals UP and DN of the phase-locked loop's charge pump pre-amplifier circuit, thereby controlling the on / off state of the charging current path composed of MP4, MP5, SW2, and MP10, and the discharging current path composed of MN3, MN4, SW5, and MN9.

[0014] Switches SW2 and SW5 are two transmission gate switches, controlled by the output signals VCLK and VCLKB of the lock detection module. This sets a larger current value before or a smaller current value after the phase-locked loop locks the charge pump main module, and charges and discharges the output node VCTRL.

[0015] Furthermore, the current tracking module includes transistors MP6, MP7, MN5, MN6, MP11, and MN10, switches SW3 and SW6, and operational amplifier OP.

[0016] The gates of MP6 and MP7 are connected to the gate of MP5 and are biased by current IREF. The sources of MP6 and MP7 are both connected to the power supply potential VDD. The drains of MP6 and MP7 are connected to the two ends of switch SW3, respectively. The drain of MP6 is also connected to the source of MP11. The gate of MP11 is connected to ground potential GND. The drain of MP11 is connected to the drain of MN10 and the positive input terminal of operational amplifier OP. The gate of MN10 is connected to the power supply potential VDD. The source of MN10 is connected to one end of switch SW6 and the drain of MN5. The gates of MN5 and MN6 are connected to the gates of MN3 and MN4 and are connected to the output terminal of operational amplifier OP. The sources of MN5 and MN6 are both connected to ground potential GND. The drains of MN5 and MN6 are connected to the two ends of switch SW5, respectively. The negative input terminal of operational amplifier OP is connected to the drains of MP10 and MN9.

[0017] Transistors MP6 and MP7 are the charging current sources, and transistors MN5 and MN6 are the discharging current sources. The drains of transistors MP11 and MN10 are grounded to GND and the power supply to VDD, respectively, thus ensuring that the charging current path composed of MP6, MP7, SW3, and MP11, and the discharging current path composed of MN5, MN6, SW6, and MN10 are always conducting. Switches SW3 and SW6 are two transmission gate switches, controlled by the output signals VCLK and VCLKB of the lock-in detection module, thereby setting the current tracking module to the same current value as the charge pump main module before or after PLL lock-in, which is either larger or smaller. The operational amplifier OP provides negative feedback, forcing the actual charging and discharging current of the charge pump main module to be consistent with that of the current tracking module.

[0018] Furthermore, the auxiliary charging and discharging module includes transistors MP1, MP2, MP3, MP8, MN8, MN1, MN2, MN7, MP9 and switches SW1 and SW4.

[0019] The gates of MP1, MP2, and MP3 are connected to the gate of MP4 and then connected to a bias current IREF. The sources of MP1, MP2, and MP3 are all connected to the power supply potential VDD. The drains of MP2 and MP3 are connected to the two ends of switch SW1, respectively. The gate and drain of MP1 are shorted and then connected to the bias current IREF. The drain of MP2 is also connected to the source of MP8. The gate of MP8 is connected to ground potential GND, and the drain of MP8 is connected to the drain of MN8. The gate of MN8 is connected to the output signal DNB of the frequency and phase detector in the pre-amplifier circuit. The source of MN8 is connected to the drain of MN3 and the source of MN9. The gate of MN7 is connected to the power supply potential VDD. The source of MN7 is connected to one end of switch SW4 and the drain of MN1. The drain of MN7 is connected to the drain of MP9. The gate of MP9 is connected to the output signal UPB of the frequency and phase detector in the pre-amplifier circuit. The source of MN9 is connected to the drain of MP4 and the source of MP10. The sources of MN1 and MN2 are both grounded to GND. The drains of MN1 and MN2 are connected to the two ends of switch SW4 respectively. The gates of MN1, MN2, MN3, MN4, MN5 and MN6 are connected and then connected to the output of operational amplifier OP.

[0020] MP1 is a current mirror transistor with its gate and drain shorted. It is responsible for receiving the bias current IREF and copying it to the charge pump main module, the current tracking module, and the charge pump main module.

[0021] Transistors MP2, MP3, MP8, MN8 and switch SW1 constitute an auxiliary charging circuit. This branch is connected to the drain nodes of transistors MN3 and MN4 in the main charge pump module. Under the control of the output signal DNB of the phase detector in the charge pump pre-stage circuit of the phase-locked loop, it is responsible for providing a current path to transistors MN3 and MN4, so that they are always kept in the on state.

[0022] Transistors MN1, MN2, MN7, MP9 and switch SW4 constitute an auxiliary discharge circuit. This branch is connected to the drain nodes of transistors MP4 and MP5 in the main charge pump module. Under the control of the output signal UPB of the frequency and phase detector in the charge pump pre-stage circuit of the phase-locked loop, it is responsible for providing a current path to transistors MP4 and MP5 so that they are always kept in the on state.

[0023] Furthermore, the lock detection module includes comparators COM1 and COM2, logic gates AND1, AND2, and NOT1, and a D flip-flop chain DFF1-DFF10.

[0024] The negative input of comparator COM1 and the positive input of comparator COM2 are both connected to the output node VCTRL of the charge pump main module. The positive input of COM1 is connected to the lower reference voltage VREF- after phase-locked loop (PLL) locking, which is lower than VCTRL. The negative input of COM2 is connected to the higher reference voltage VREF+ after PLL locking, which is higher than VCTRL. The input of AND1 is connected to the outputs of COM1 and COM2. The output of AND1 is connected to the D input of DFF1.

[0025] The Q outputs of DFF1-DFF9 are connected to the D inputs of DFF2-DFF10 in sequence, and the Q outputs of DFF1-DFF10 are connected to the AND2 input. The clock outputs of DFF1-DFF10 are connected to the reference clock signal CLK of the phase-locked loop. The NOT1 input is connected to the AND2 output. The NOT1 input generates the lockout flag signal VLCK. The NOT1 output generates the lockout flag signal VLCKB.

[0026] The lockout detection module determines whether the phase-locked loop is locked by comparing the output voltage of the charge pump main module with the reference voltages VREF+ and VREF-, as well as the output signal level of the D flip-flop chain. It also sets the lockout flag signals VLCK and VLCKB to the larger current value before or after the phase-locked loop in the charge pump main module, the current tracking module, and the charge pump main module by controlling switches SW1-SW6.

[0027] In summary, this invention improves the suppression of phase-locked loop (PLL) spurious emissions by introducing a negative feedback circuit to control the magnitude of the charging and discharging current and by introducing a current replication circuit to increase the switching speed of the charge pump. Simultaneously, by introducing a lock-in detection module into the charge pump structure to control the magnitude of the charging and discharging current, the power consumption of the charge pump circuit is significantly reduced. This invention effectively solves the problems of relatively poor noise, spurious emission performance, and power consumption in existing charge pump circuits. Attached Figure Description

[0028] Figure 1 This is a block diagram of the present invention.

[0029] Figure 2 The circuit diagram is for an example.

[0030] Figure 3 This is an equivalent circuit diagram of the charging process before the phase-locked loop locks in an embodiment.

[0031] Figure 4 This is an equivalent circuit diagram of the embodiment after the phase-locked loop is locked.

[0032] Figure 5 This example demonstrates the operation of the lock detection module.

[0033] Figure 6 This example compares the charging and discharging current mismatch of a conventional drain-switched charge pump with that of a conventional drain-switched charge pump.

[0034] Figure 7 The example compares the phase difference between the reference clock signal and the feedback clock signal and the output voltage ripple of the charge pump after the phase-locked loop is locked, using a conventional drain-switched charge pump. Detailed Implementation

[0035] The technical solution of the present invention will be described in more detail below with reference to the embodiments and accompanying drawings.

[0036] Reference Figure 2 , Figure 3 and Figure 4 The working process of the charge pump before and after phase-locked loop locking will now be described.

[0037] Reference Figure 2 The diagram below shows the specific circuit structure of this embodiment. Before the phase-locked loop (PLL) locks, when the charge pump is charging, the output signals of the phase detector in the charge pump's pre-amplifier circuit are: UP low, DN low, UPB high, and DNB high. At this time, MP9 and MN9 are off, and MP10 and MN8 are on. It is also assumed that before the PLL locks, the charge pump output voltage VCTRL will not remain within the range of VREF- to VREF+ for 10 consecutive reference clock signal cycles. That is, AND gate AND1 will output low for at least one reference clock signal cycle within 10 consecutive reference clock signal cycles, resulting in at least one low Q output signal from the 10 DFFs. This causes AND gate AND2 to output low. Therefore, the lock detection module outputs a low VLCK signal and a high VLCKB signal, indicating that the PLL is not locked, and switches SW1-SW6 are all closed. Therefore, when the charge pump is charging... Figure 2 The circuit shown can be equivalent to Figure 3 The circuit shown.

[0038] Reference Figure 3MP4 and MP5 charge output node a. Due to the negative feedback of the op-amp, the voltages at node a and node b are ideally equal. MP6 and MP4, MP5 and MP7, and MP10 and MP11 have the same width and length, so the current flowing through MP10 can be considered the same as the current flowing through MP11. Furthermore, due to the "virtual open circuit" effect at the positive input of the op-amp, a current path cannot be formed, and the current flowing through MP11 is the same as the sum of the currents flowing through MN5 and MN6.

[0039] When the voltage at node a changes due to the charging of the load capacitor of the loop filter after the charge pump in the phase-locked loop, it affects the drain voltages of the charging current source transistors MP4 and MP5, causing a change in the charging current of the charge pump main module. Since the voltage at node b remains equal to that at node a, the currents flowing through MP11 and MP10 / MN10 will remain equal, thus changing the current tracking module current accordingly. Simultaneously, the voltage at op-amp output node e will also change to adapt to the voltage changes at nodes a and b, as shown in the reference diagram. Figure 2 It is known that the op-amp output node e is connected to the gates of MN1-MN6, therefore, changes in the voltage at node e will regulate the current of transistors MN1-MN6. Since transistors MN1, MN3, and MN5 have the same dimensions, and transistors MN2, MN4, and MN6 have the same dimensions, therefore... Figure 3 The sum of the currents flowing through MN5 and MN6 is the same as the sum of the currents flowing through MN3 and MN4, thus achieving a high degree of matching between the charging and discharging currents of the charge pump main module. Figure 6 Simulation results of the charge-discharge current mismatch also show that, over a wide range of charge pump output voltages, the maximum mismatch of the charge pump structure proposed in this invention is much smaller than that of the traditional drain-switch charge pump structure.

[0040] In addition, since the sum of the currents in MN3 and MN4 is the sum of the currents flowing through MP2 and MP3, and since MP6 and MP2, MP7 and MP3, and MP11 and MP8 have the same width and length, the voltage at node c will be consistent with the voltage at node b, and the voltage at node d will be lower than the voltage at node c by the drain-source voltage Vds of transistor MN8. NN8 ,Right now

[0041] V d =V c -Vds MN8 =V b -Vds MN8 =VCTRL-Vds MN8

[0042] Since MN8 is in the deep linear region when it is turned on, its drain-source voltage Vds MN8The voltage at node d is relatively small, while the voltage at node d represents the drain node voltage of the discharge current source transistors MN3 and MN4 in the main module of the charge pump. Therefore, during the charging process of the charge pump, there is a small voltage difference between the drain node of the discharge current source and the output node. However, in a traditional drain-switched charge pump, the drain node of the discharge current source is discharged to ground potential during the charging process, resulting in a larger voltage difference between the drain node and the output node. This causes charge sharing between the capacitor of the drain node and the output node during the initial discharge process, leading to an error in the charge quantity on the load capacitor of the loop filter in the phase-locked loop, exacerbating the charge pump mismatch. Furthermore, since a traditional drain-switched charge pump requires a certain amount of time to charge the drain node of the discharge current source before the discharge current source can provide the required discharge current, the switching speed of the charge pump is also reduced. Therefore, the introduction of the auxiliary charge / discharge module further reduces the charge pump mismatch and improves the switching speed of the charge pump.

[0043] Before the phase-locked loop is locked, the charge pump circuit operates in a similar manner to the process described above during the charging process.

[0044] Furthermore, referring to Figure 2 After the phase-locked loop (PLL) is locked, ideally, the output signals UP and DNB of the frequency and phase detector periodically go high or low simultaneously. Correspondingly, the output signals UPB and DNB of the frequency and phase detector periodically go low or high simultaneously. At this time, MP10 and MN9 transistors periodically turn on or off simultaneously, and correspondingly, MP9 and MN8 transistors periodically turn off or on simultaneously. It is also assumed that when the charge pump is locked, the output voltage VCTRL of the charge pump remains within the range VREF- to VREF+ for nine consecutive reference clock signal cycles and at the rising edge of the tenth reference clock signal. That is, AND gate AND1 outputs high for ten consecutive reference clock signal cycles, thus the Q output signals of all ten DFFs are high, making the output of AND gate AND2 high. Figure 5 The simulation results of the locking detection module circuit show that the above process runs normally and the locking detection module functions correctly. Therefore, the locking detection module outputs a high VLCK signal and a low VLCKB signal, indicating that the phase-locked loop is locked, and switches SW1-SW6 are all turned off. Figure 2 The circuit shown can be equivalent to Figure 4 The circuit shown.

[0045] Reference Figure 4 When switches SW1-SW6 are all turned off, the charging and discharging current of the charge pump is set to the smaller current value determined by the width-to-length ratio of MP4 and MP1 transistors and the bias current IREF. Assuming... Figure 2 middle

[0046]

[0047] Where n is a real number greater than 1, then under ideal conditions, the static power consumption of the charge pump can be reduced to that before locking.

[0048] After the phase-locked loop (PLL) locks in, when the output signals UP and DN of the frequency and phase detector are both high, and the corresponding UPB and DNB signals are both low, there is a slight deviation in the charge pump charging and discharging current. This causes ripple in the charge pump output voltage VCTRL. After adjustment by the PLL, a small phase difference is created between the reference clock signal and the feedback clock signal to stabilize the charge pump output voltage VCTRL. Due to the introduction of a current tracking module and an auxiliary charging and discharging module, the charge pump charging and discharging current deviation proposed in this invention is smaller than that of a traditional drain-switched charge pump. Furthermore, the charge pump charging and discharging current decreases to the level before locking. Therefore, charge pump

[0049] The output voltage VCTRL ripple and the phase difference between the reference clock signal and the feedback clock signal are greatly reduced compared to traditional drain switches.

[0050] Reflecting on this in a phase-locked loop, assuming the loop filter is of second-order form, the signal acting across the resistor R of the loop filter has a strength of I. cp R, duty cycle is angular frequency is ω ref If we consider only the first harmonic component of the pulse voltage signal and ignore other harmonic components, the signal, after being filtered by the loop filter in the charge pump stage of the phase-locked loop (PLL), acts on the input of the voltage-controlled oscillator (VCO) in the stage following the loop filter, modulating the frequency of the VCO output signal and thus generating spurious signals. Since the amplitude of the first harmonic component can be expressed as... Therefore, the spurious pulse voltage at a frequency deviating from the PLL output signal frequency by one time the reference signal frequency can be expressed as:

[0051]

[0052] Where, ω p1 This represents the first low-pass pole of the loop filter. As can be seen from the above equation, reducing the phase difference between the reference clock signal and the feedback clock signal after loop locking can suppress spurious signals in the phase-locked loop.

[0053] In the charge pump structure proposed in this invention, the phase difference between the reference clock signal and the feedback clock signal, caused by the change in the charge pump output voltage VCTRL, is:

[0054]

[0055] in, This indicates the charge error on the load capacitor of the loop filter in the charge pump stage of the phase-locked loop, caused by non-ideal effects such as switch mismatch, charge sharing, and clock feedthrough. cp T ref Indicates the charge pump charging and discharging current I. cp During the reference clock signal period T ref The amount of charge generated by charging the output node of the internal charge pump. This represents the charge quantity error caused by the mismatch between the charge pump's charge and discharge current sources, where ∈ represents the charge / discharge current relative to I. cp The degree of mismatch, t turn-on This indicates the time during which the charge pumps are simultaneously turned on after the phase-locked loop (PLL) locks in. As can be seen from the above formula, reducing the current mismatch of the charge pumps and increasing the switching speed of the charge pumps can both reduce the phase difference between the reference clock signal and the feedback clock signal after the loop locks in.

[0056] Reference Figure 7 The simulation results of the charge pump proposed in this invention, compared with the traditional drain-switched charge pump, show that the charge pump structure proposed in this invention has better improvements in voltage ripple and phase difference between the reference clock signal and the feedback clock signal after the phase-locked loop is locked.

Claims

1. A low-mismatch, low-power charge pump circuit with a lock-in detection module, characterized in that: It includes a charge pump main module, a current tracking module, an auxiliary charging and discharging module, and a lock-in detection module; The charge pump main module adjusts the charging and discharging time of the load capacitor of the loop filter in the charge pump's post-stage circuit according to the output signal of the frequency and phase detector in the charge pump's pre-stage circuit in the phase-locked loop, and converts the phase difference between the reference clock signal and the feedback clock signal of the phase-locked loop into a charge quantity signal. The current tracking module detects changes in the charging current of the charge pump main module and adjusts the discharge current of the charge pump main module to be the same as the charging current. The auxiliary charging and discharging module provides a second path for the charging and discharging current of the charge pump main module, so that the charging and discharging current source transistor in the charge pump main module is always turned on; at the same time, the charging and discharging current source transistor of the second path has the same current as the charging and discharging current source transistor of the charge pump main module. The locking detection module determines whether the phase-locked loop is locked based on the output voltage of the charge pump main module, thereby controlling the charge pump main module, the current tracking module, and the auxiliary charging and discharging module to simultaneously flow with a larger current before the phase-locked loop is locked or a smaller current after the phase-locked loop is locked.

2. The low-mismatch, low-power charge pump circuit with a lock-in detection module as described in claim 1, characterized in that: The charge pump main module includes transistors MP4, MP5, MN3, MN4, MP10, MN9 and switches SW2 and SW5; The gates of MP4 and MP5 are connected and connected to the bias current IREF. The sources of MP4 and MP5 are both connected to the power supply potential VDD. The drains of MP4 and MP5 are respectively connected to the two ends of switch SW2. The drain of MP4 is also connected to the source of MP10. The gate of MP10 is connected to the output signal UP of the frequency and phase detector of the pre-amplifier circuit. The drain of MP10 is connected to the drain of MN9 and serves as the output node VCTRL. The gate of MN9 is connected to the output signal DN of the frequency and phase detector of the pre-amplifier circuit. The source of MN9 is connected to one end of switch SW5 and the drain of MN3. The gates of MN3 and MN4 are connected and connected to the output of the operational amplifier OP in the current tracking module. The sources of MN3 and MN4 are both ground potential GND. The drains of MN3 and MN4 are respectively connected to the two ends of switch SW5. Transistors MP4 and MP5 are charging current sources, and transistors MN3 and MN4 are discharging current sources. Transistors MP10 and MN9 are controlled by the output signals UP and DN of the frequency and phase detector in the charge pump pre-stage circuit of the phase-locked loop, thereby controlling the on / off state of the charging current path composed of MP4, MP5, SW2 and MP10 and the discharging current path composed of MN3, MN4, SW5 and MN9. Switches SW2 and SW5 are two transmission gate switches, controlled by the output signals VCLK and VCLKB of the lock detection module. This sets a larger current value before or a smaller current value after the phase-locked loop locks the charge pump main module, and charges and discharges the output node VCTRL.

3. The low-mismatch, low-power charge pump circuit with a lock-in detection module as described in claim 2, characterized in that: The current tracking module includes transistors MP6, MP7, MN5, MN6, MP11, and MN10, switches SW3 and SW6, and operational amplifier OP. The gates of MP6 and MP7 are connected to the gate of MP5 and to the bias current IREF. The sources of MP6 and MP7 are both connected to the power supply potential VDD. The drains of MP6 and MP7 are connected to the two ends of switch SW3, respectively. The drain of MP6 is also connected to the source of MP11. The gate of MP11 is connected to the ground potential GND. The drain of MP11 is connected to the drain of MN10 and the positive input terminal of operational amplifier OP. The gate of MN10 is connected to the power supply potential VDD. The source of MN10 is connected to one end of switch SW6 and the drain of MN5. The gates of MN5 and MN6 are connected to the gate of MN4 and to the output terminal of operational amplifier OP. The sources of MN5 and MN6 are both connected to the ground potential GND. The drains of MN5 and MN6 are connected to the two ends of switch SW5, respectively. The negative input terminal of operational amplifier OP is connected to the drains of MP10 and MN9. Transistors MP6 and MP7 are charging current sources, and transistors MN5 and MN6 are discharging current sources. Transistors MP11 and MN10 have their drains grounded at GND and power supply at VDD, respectively, thus ensuring that the charging current path composed of MP6, MP7, SW3, and MP11 and the discharging current path composed of MN5, MN6, SW6, and MN10 are always conducting. Switches SW3 and SW6 are two transmission gate switches, controlled by the output signals VCLK and VCLKB of the lock-in detection module, thereby setting the current tracking module with the same larger current value before or smaller after the phase-locked loop (PLL) lock-in as the charge pump main module. The operational amplifier OP provides negative feedback, forcing the actual charging and discharging current of the charge pump main module to be consistent with that of the current tracking module.

4. The low-mismatch, low-power charge pump circuit with a lock-in detection module as described in claim 3, characterized in that: The auxiliary charging and discharging module includes transistors MP1, MP2, MP3, MP8, MN8, MN1, MN2, MN7, MP9 and switches SW1 and SW4; The gates of MP1, MP2, and MP3 are connected to the gate of MP4 and then connected to a bias current IREF. The sources of MP1, MP2, and MP3 are all connected to the power supply potential VDD. The drains of MP2 and MP3 are connected to the two ends of switch SW1, respectively. The gate and drain of MP1 are shorted and then connected to the bias current IREF. The drain of MP2 is also connected to the source of MP8. The gate of MP8 is connected to ground potential GND, and the drain of MP8 is connected to the drain of MN8. The gate of MN8 is connected to the output signal DNB of the frequency and phase detector in the preceding circuit. The source of MN8 is connected to the drain of MN3 and MN9. The source of MN7 is connected to the power supply potential VDD. The source of MN7 is connected to one end of switch SW4 and the drain of MN1. The drain of MN7 is connected to the drain of MP9. The gate of MP9 is connected to the output signal UPB of the frequency and phase detector of the pre-amplifier circuit. The source of MN9 is connected to the drain of MP4 and the source of MP10. The sources of MN1 and MN2 are both connected to the ground potential GND. The drains of MN1 and MN2 are connected to the two ends of switch SW4 respectively. The gates of MN1, MN2, MN3, MN4, MN5 and MN6 are connected together and then connected to the output of operational amplifier OP. Among them, MP1 is a current mirror transistor with its gate and drain shorted, which is responsible for receiving the bias current IREF and copying it to the charge pump main module, the current tracking module and the charge pump main module. Transistors MP2, MP3, MP8, MN8 and switch SW1 constitute an auxiliary charging circuit. This branch is connected to the drain nodes of transistors MN3 and MN4 in the main charge pump module. It is responsible for providing a current path to transistors MN3 and MN4 under the control of the output signal DNB of the frequency and phase detector in the charge pump pre-stage circuit of the phase-locked loop, so that they always remain in the on state. Transistors MN1, MN2, MN7, MP9 and switch SW4 constitute an auxiliary discharge circuit. This branch is connected to the drain nodes of transistors MP4 and MP5 in the main charge pump module. Under the control of the output signal UPB of the frequency and phase detector in the charge pump pre-stage circuit of the phase-locked loop, it is responsible for providing a current path to transistors MP4 and MP5 so that they are always kept in the on state.

5. The low-mismatch, low-power charge pump circuit with a lock-in detection module as described in claim 1, characterized in that: The lock detection module includes comparators COM1 and COM2, logic gates AND1, AND2, and NOT1, and a D flip-flop chain DFF1-DFF10; The negative input of comparator COM1 and the positive input of comparator COM2 are both connected to the output node VCTRL of the charge pump main module. The positive input of COM1 is connected to the lower reference voltage VREF- after phase-locked loop (PLL) locking, which is lower than VCTRL. The negative input of COM2 is connected to the higher reference voltage VREF+ after PLL locking, which is higher than VCTRL. The input of AND1 is connected to the outputs of COM1 and COM2. The output of AND1 is connected to the D input of DFF1. The Q outputs of DFF1-DFF9 are connected sequentially to the D inputs of DFF2-DFF10, and the Q outputs of DFF1-DFF10 are connected to the AND2 input. The clock inputs of DFF1-DFF10 are connected to the reference clock signal CLK of the phase-locked loop. The NOT1 input is connected to the AND2 output, and the NOT1 input generates the lockout flag signal VLCK. The NOT1 output generates the lockout flag signal VLCKB. The lockout detection module determines whether the phase-locked loop is locked by comparing the output voltage of the charge pump main module with the reference voltages VREF+ and VREF-, as well as the output signal level of the D flip-flop chain. It also sets the lockout flag signals VLCK and VLCKB to the larger current value before or after the phase-locked loop in the charge pump main module, the current tracking module, and the charge pump main module through the control switches SW1-SW6.

Images