Power supply device and memory module including same

Abstract

A power supply device and a memory module are provided. The power supply device comprises a three-level conversion circuit, a dual-path hybrid conversion circuit and an auxiliary switch circuit. The three-level conversion circuit includes a flying capacitor for three-level operation, and generates an intermediate voltage based on an input voltage, a plurality of first control signals, and the flying capacitor. The dual-path hybrid conversion circuit includes a first path, a second path, an inductor in the first path, and a hybrid capacitor in the second path, and generates an output voltage based on the intermediate voltage, the second control signal, the inductor, and the hybrid capacitor. The auxiliary switching circuit controls the current flowing through the hybrid capacitor based on the third control signal. The power supply device operates based on a four-stage scheme or a six-stage scheme according to an operating mode.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2023-0157948 filed on November 5, 2023 in the Korean Intellectual Property Office (KIPO), the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates generally to semiconductor integrated circuits, and more particularly, to a power supply device and a memory module including the power supply device. Background Art

[0004] Semiconductor memory devices can be divided into two categories according to whether they retain stored data when disconnected from power. These categories include volatile memory devices, which lose stored data when disconnected from power, and nonvolatile memory devices, which retain stored data when disconnected from power. Although volatile memory devices can perform read operations and write operations at high speed, the contents stored therein may be lost when power is turned off. Since nonvolatile memory devices retain the contents stored therein even when power is turned off, they can be used to store data that needs to be retained.

[0005] In several market segments, such as semiconductor memory devices, computing devices, charging devices, etc., there is an increasing demand for efficient, voltage-regulated power devices. In particular, it is highly desirable to design power converters with higher efficiency and smaller area than conventional buck converters. The size of the required inductor is an important design parameter for the total area of ​​the power converter. Therefore, reducing the size of the inductor is important. Summary of the invention

[0006] Some example embodiments of the present disclosure provide a power supply apparatus capable of effectively reducing a loss due to an increased direct current resistance (DCR) by reducing a physical size of an inductor.

[0007] Some example embodiments of the present disclosure provide a memory module including a power supply device.

[0008] Some example embodiments of the present invention provide a power supply device, which includes a three-level conversion circuit, a dual-path hybrid conversion circuit, and an auxiliary switch circuit. The three-level conversion circuit includes a flying capacitor for three-level operation, and the three-level conversion circuit generates an intermediate voltage based on an input voltage, a plurality of first control signals, and the flying capacitor. The dual-path hybrid conversion circuit includes a first path, a second path, an inductor in the second path, and a hybrid capacitor in the second path, and the dual-path hybrid conversion circuit generates an output voltage based on the intermediate voltage, the second control signal, the inductor, and the hybrid capacitor. Both the first path and the second path are connected to an output node that provides an output voltage. The first path and the second path are different from each other. The auxiliary switch circuit is located between the three-level conversion circuit and the dual-path hybrid conversion circuit, and controls the current flowing through the hybrid capacitor based on a third control signal. The power supply device selectively operates based on a four-stage scheme and a six-stage scheme according to an operation mode.

[0009] Some example embodiments of the inventive concept also provide a memory module, which includes a circuit board, a plurality of memory devices on the circuit board, and a power supply device on the circuit board. The power supply device provides a power supply voltage to the plurality of memory devices, and includes a three-level conversion circuit, a dual-path hybrid conversion circuit, and an auxiliary switch circuit. The three-level conversion circuit includes a flying capacitor for three-level operation, and generates an intermediate voltage based on an input voltage, a plurality of first control signals, and a flying capacitor. The dual-path hybrid conversion circuit includes a first path, a second path, an inductor in the first path, and a hybrid capacitor in the second path, and generates an output voltage based on the intermediate voltage, a second control signal, an inductor, and a hybrid capacitor. Both the first path and the second path are connected to an output node that provides an output voltage. The first path and the second path are different from each other. The output voltage corresponds to the power supply voltage. The auxiliary switch circuit is located between the three-level conversion circuit and the dual-path hybrid conversion circuit, and controls the current flowing through the hybrid capacitor based on a third control signal. The power supply device selectively operates based on a four-phase scheme and a six-phase scheme according to an operation mode.

[0010] Some example embodiments of the present inventive concept also provide a power supply device, which includes a first transistor, a second transistor, a third transistor, a fourth transistor, a flying capacitor, an inductor, a hybrid capacitor, a fifth transistor, a sixth transistor, and an output capacitor. The first transistor is connected between an input voltage and a first node. The second transistor is connected between the first node and the second node, and the second node provides an intermediate voltage. The third transistor is connected between the second node and the third node. The fourth transistor is connected between the third node and the ground voltage. The flying capacitor is connected between the first node and the third node. The inductor is connected between the second node and the output node, and the output node provides an output voltage. The hybrid capacitor is connected between the second node and the fourth node. The fifth transistor is connected between the fourth node and the output node. The sixth transistor is connected between the third node and the fourth node. The body bias voltage applied to the sixth transistor is variable. The output capacitor is connected between the output node and the ground voltage. The first transistor, the second transistor, the third transistor, the fourth transistor, and the flying capacitor perform a three-level operation. The inductor is included in the first path, and the first path is connected to the output node. The hybrid capacitor is included in the second path, and the second path is connected to the output node. The power supply device generates an output voltage using a dual path including a first path and a second path. The power supply device selectively operates based on a four-phase scheme and a six-phase scheme based on a conversion rate obtained by dividing the output voltage by the input voltage.

[0011] The power supply device according to some example embodiments may include a flying capacitor for three-level operation and an inductor and a hybrid capacitor for dual-path operation. For example, the power supply device can be implemented in the form of a three-level dual-path hybrid buck converter. The AC current component can be reduced by three-level operation, and the DC current component can be reduced by dual-path operation. Therefore, even in an environment where the physical size of the inductor is relatively small and the DC resistance of the inductor is relatively large, the loss caused by the DC resistance can be reduced by reducing the RMS current of the inductor, and thus the reduction in conversion efficiency can be limited and / or prevented. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Illustrative, non-limiting example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0013] Figure 1 is a block diagram illustrating a power supply device according to some example embodiments of the inventive concept.

[0014] Figure 2 is a circuit diagram illustrating a power supply device according to some example embodiments.

[0015] Figure 3 It is shown Figure 2 A circuit diagram of an example of a power supply device.

[0016] Figure 4 , Figure 5A , Figure 5B , Figure 5C , Figure 5D , Fig. 6A and Figure 6B It is shown Figure 3 A diagram of the operation of a power supply device.

[0017] Fig. 7A , Figure 7B , Figure 7C , Fig.7D , Fig. 8A and Figure 8B It is shown Figure 3 A graphical representation of the performance of a power supply unit.

[0018] Fig. 9 , Fig. 10A , Fig. 10B , Fig. 10C , Fig. 10D , Fig. 10E , Fig.10F , Fig.11A and Fig. 11B It is shown Figure 3 A diagram of the operation of a power supply device.

[0019] Fig. 12A and Fig. 12B It is shown Figure 3 A diagram of the operation of a power supply device.

[0020] Fig.13 It is shown Figure 2 A circuit diagram of an example of a power supply device.

[0021] Fig.14 is a block diagram illustrating a power supply device according to some example embodiments.

[0022] Fig.15A and Fig. 15B It is shown that the Fig.14 A block diagram of an example of a control signal generating circuit in a power supply device.

[0023] Fig.16 and Fig.17 is a flowchart illustrating a method of operating a power supply device according to some example embodiments.

[0024] Fig.18 is a block diagram illustrating a memory module according to some example embodiments.

[0025] Fig.19 is a block diagram illustrating an example of a memory device included in a memory module according to some example embodiments.

[0026] Fig. 20 is a block diagram illustrating an integrated circuit including a power supply device according to some example embodiments. DETAILED DESCRIPTION

[0027] Various example embodiments will be described more fully with reference to the accompanying drawings in which some embodiments are shown. However, the inventive concept can be implemented in many different forms and should not be construed as being limited to the example embodiments set forth herein. In this application, the same reference numerals represent the same elements.

[0028] When the term "about" or "substantially" is used in conjunction with a numerical value in this specification, it is intended that the associated numerical value includes manufacturing tolerances or operating tolerances around the numerical value (e.g.,

[0029] ±10%). In addition, when the words "generally" and "substantially" are used in conjunction with geometric shapes, it is intended that the accuracy of the geometric shapes is not required, but the freedom of the shapes is within the scope of the present disclosure. In addition, whether or not a value or shape is modified as "about" or "substantially", it will be understood that these values ​​and shapes should be interpreted as including manufacturing tolerances or operating tolerances (e.g., ±10%) around the value or shape. When a range is specified, the range includes all values ​​therebetween, such as increments of 0.1%.

[0030] In addition, for example, "at least one of A, B, and C" and similar language (e.g., "at least one selected from the group consisting of A, B, and C") may be interpreted as A only, B only, C only, or any combination of two or more of A, B, and C, such as, for example, ABC, AB, BC, and AC.

[0031] Figure 1 is a block diagram illustrating a power supply device according to some example embodiments.

[0032] Reference Figure 1 The power supply device 10 includes a three-level conversion circuit 100 , a dual-path hybrid conversion circuit 200 , and an auxiliary switch circuit 300 .

[0033] The three-level conversion circuit 100 includes a flying capacitor CFLY for a three-level operation. The three-level conversion circuit 100 generates an intermediate voltage VSW by performing a three-level operation using an input voltage VIN, a plurality of first control signals CS1, and the flying capacitor CFLY.

[0034] The three-level operation (or three-level conversion operation) may represent or indicate an operation of generating and / or converting a voltage signal having a logic high level, a logic low level, and a logic middle level (e.g., a voltage signal having three different voltage levels). For example, the intermediate voltage VSW generated by the three-level conversion circuit 100 may have three voltage levels different from each other. When the three-level operation is performed, the inductor alternating current (AC) current component (or term) of the power supply device 10 may be reduced.

[0035] The dual-path hybrid conversion circuit 200 includes a first path 210 and a second path 220 connected to an output node NOUT providing an output voltage VOUT and different from each other. The first path 210 includes an inductor L, and the second path 220 includes a hybrid capacitor CHYBRID. For example, the dual-path hybrid conversion circuit 200 includes an inductor L disposed in the first path 210 and a hybrid capacitor CHYBRID disposed in the second path 220. The dual-path hybrid conversion circuit 200 generates an output voltage VOUT by performing a dual-path operation using an intermediate voltage VSW, a second control signal CS2, an inductor L, and a hybrid capacitor CHYBRID.

[0036] The dual-path operation may refer to an operation of forming or generating an inductor current and a capacitor current substantially simultaneously or in parallel and providing them to the output terminal. For example, the output voltage VOUT generated by the dual-path hybrid conversion circuit 200 may be generated by substantially simultaneously driving the inductor L included in the first path 210 and the hybrid capacitor CHYBRID included in the second path 220. When the dual-path operation is performed, the inductor direct current (DC) current component (or term) of the power supply device 10 may be reduced.

[0037] The auxiliary switch circuit 300 is provided or arranged between the three-level conversion circuit 100 and the dual-path hybrid conversion circuit 200. The auxiliary switch circuit 300 controls a current flowing through the hybrid capacitor CHYBRID based on a third control signal CS3.

[0038] Will refer to Figure 2 , Figure 3 and Fig.13 An example of a detailed circuit configuration of the three-level conversion circuit 100 , the dual-path hybrid conversion circuit 200 , and the auxiliary switching circuit 300 is described.

[0039] In some example embodiments, the voltage level of the output voltage VOUT generated by the power supply device 10 may be lower than the voltage level of the input voltage VIN received by the power supply device 10. For example, the power supply device 10 may be or may have a configuration corresponding to a buck converter or a step-down converter that converts a relatively high DC voltage into a relatively low DC voltage.

[0040] In some example embodiments, the power supply device 10 may operate based on a four-phase scheme (or method) or a six-phase scheme according to the operation mode. For example, the operation mode may be determined based on a conversion rate obtained by dividing the output voltage VOUT by the input voltage VIN. Figure 4 , Figure 5A , Figure 5B , Figure 5C , Figure 5D , Fig. 6A and Figure 6B Describe the four-stage approach. Fig. 9 , Fig. 10A , Fig. 10B , Fig. 10C , Fig. 10D , Fig. 10E , Fig.10F , Fig.11A and Fig. 11B Describe the six-phase approach. Fig. 12A and Fig. 12B Describes the operation that determines the operating mode.

[0041] Power supply devices are widely used in various electronic devices and are implemented using inductors. In order to reduce the loss due to the DC resistance (DCR) of the inductor, an inductor with a relatively large physical size has been used. Various studies have been conducted to reduce the physical size of the inductor, however, there is a problem that when the physical size of the inductor is reduced, the DC resistance of the inductor increases, and the conversion efficiency of the power supply device is reduced.

[0042] The power supply device 10 according to some example embodiments may include a flying capacitor CFLY for three-level operation, and an inductor L and a hybrid capacitor CHYBRID for dual-path operation. For example, the power supply device 10 can be implemented in the form of a three-level dual-path hybrid buck converter. The AC current component can be reduced by three-level operation, and the DC current component can be reduced by dual-path operation. Therefore, even in an environment where the physical size of the inductor is relatively small and the DC resistance of the inductor is relatively large, the loss caused by the DC resistance can be reduced by reducing the root mean square (RMS) current of the inductor, and thus the reduction in conversion efficiency can be limited and / or prevented.

[0043] Figure 2 is a circuit diagram illustrating a power supply device according to some example embodiments.

[0044] Reference Figure 2 The power supply device 10a includes a three-level conversion circuit 100a, a dual-path hybrid conversion circuit 200a, and an auxiliary switch circuit 300a.

[0045] The three-level conversion circuit 100 a may include a first switch S1 , a second switch S2 , a third switch S3 , a fourth switch S4 , and a flying capacitor CFLY.

[0046] The first switch S1 may be connected between the input voltage VIN and the first node N1, and may be turned on and off in response to the control signal CS11. The second switch S2 may be connected between the first node N1 and the second node N2, and may be turned on and off in response to the control signal CS12. The third switch S3 may be connected between the second node N2 and the third node N3, and may be turned on and off in response to the control signal CS13. The fourth switch S4 may be connected between the third node N3 and the ground voltage GND, and may be turned on and off in response to the control signal CS14. The flying capacitor CFLY may be connected between the first node N1 and the third node N3, and may be charged and discharged by the operation of the switches S1, S2, S3 and S4. The control signals CS11, CS12, CS13 and CS14 may correspond to Figure 1 Multiple first control signals CS1 in.

[0047] The dual-path hybrid conversion circuit 200 a may include a fifth switch S5 , an inductor L, and a hybrid capacitor CHYBRID.

[0048] The fifth switch S5 may be connected between the fourth node N4 and the output node NOUT, and may be turned on and off in response to the second control signal CS2. The inductor L may be connected between the second node N2 and the output node NOUT. The resistor RDCR may be the DC resistance of the inductor L, and may represent a parasitic element rather than an actual element. The hybrid capacitor CHYBRID may be connected between the second node N2 and the fourth node N4.

[0049] The first path PTH1 may represent a path between the second node N2 and the output node NOUT, and may include an inductor L. The second path PTH2 may represent a path between the second node N2 and the output node NOUT, and may include a hybrid capacitor CHYBRID and a fifth switch S5.

[0050] The auxiliary switching circuit 300a may include a sixth switch S6. The sixth switch S6 may be connected between the third node N3 and the fourth node N4, and may be turned on and off in response to the third control signal CS3.

[0051] The power supply device 10a may further include an output capacitor COUT connected between the output node NOUT and the ground voltage GND. The resistor RESR may be an equivalent series resistance (ESR) of the output capacitor COUT and may represent a parasitic element rather than an actual element.

[0052] The load resistor RLOAD may not be a component of the power supply device 10 a , and may represent a resistance of an external device that is connected to the power supply device 10 a and receives power (eg, the output voltage VOUT) from the power supply device 10 a .

[0053] Figure 3 It is shown Figure 2 For the sake of simplicity, the circuit diagram of the power supply device is omitted. Figure 2 Descriptions that are repeated or overlapping.

[0054] Reference Figure 3 The power supply device 10b may include a first transistor TR1, a second transistor TR2, a third transistor TR3, a fourth transistor TR4, a fifth transistor TR5, a sixth transistor TR6, a flying capacitor CFLY, an inductor L, a hybrid capacitor CHYBRID, and an output capacitor COUT.

[0055] The first transistor TR1 may be connected between the input voltage VIN and the first node N1, the second transistor TR2 may be connected between the first node N1 and the second node N2, the third transistor TR3 may be connected between the second node N2 and the third node N3, and the fourth transistor TR4 may be connected between the third node N3 and the ground voltage GND. The first transistor TR1, the second transistor TR2, the third transistor TR3, and the fourth transistor TR4 may correspond to Figure 2 The first switch S1, the second switch S2, the third switch S3 and the fourth switch S4 in Figure 2 The control signals CS11, CS12, CS13, and CS14 may be applied to gate electrodes of the first transistor TR1, the second transistor TR2, the third transistor TR3, and the fourth transistor TR4, respectively.

[0056] The fifth transistor TR5 may be connected between the fourth node N4 and the output node NOUT. The fifth transistor TR5 may correspond to Figure 2 The fifth switch S5 in the Figure 2 The second control signal CS2 in may be applied to the gate electrode of the fifth transistor TR5.

[0057] The sixth transistor TR6 may be connected between the third node N3 and the fourth node N4, and may be implemented such that a body bias voltage of the sixth transistor TR6 is changeable or variable (eg, such that a body selection may be performed on the sixth transistor TR6). The sixth transistor TR6 may correspond to Figure 2 The sixth switch S6 in Figure 2 The third control signal CS3 in may be applied to the gate electrode of the sixth transistor TR6.

[0058] In some example embodiments, the first transistor TR1 and the second transistor TR2 may be p-type metal oxide semiconductor (PMOS) transistors, and the third transistor TR3, the fourth transistor TR4, the fifth transistor TR5, and the sixth transistor TR6 may be n-type metal oxide semiconductor (NMOS) transistors. However, some example embodiments are not limited thereto. For example, the first transistor TR1 and the second transistor TR2 may be NMOS transistors. For example, the first transistor TR1 and the second transistor TR2 may be implemented with one of a PMOS transistor and an NMOS transistor.

[0059] As described above, resistors RDCR and RESR may represent parasitic elements rather than actual elements, and load resistor RLOAD may represent the resistance of an external device. Therefore, the power supply device 10b may include six transistors TR1, TR2, TR3, TR4, TR5, and TR6, three capacitors CFLY, CHYBRID, and COUT, and one inductor L.

[0060] Figure 4 , Figure 5A , Figure 5B , Figure 5C , Figure 5D , Fig. 6A and Figure 6B It is shown Figure 3 A diagram of the operation of a power supply device.

[0061] Reference Figure 4 , the power supply device 10b may operate based on a four-phase scheme, and may perform repeated operations at each desired and / or predetermined operation cycle (or switching cycle) T_4P.

[0062] For example, the operation cycle T_4P of the four-phase scheme may include a first phase (or state) PS41, a second phase PS42, a third phase PS43, and a fourth phase PS44.

[0063] In the first stage PS41, the first switch S1, the third switch S3 and the fifth switch S5 (e.g., the first transistor TR1, the third transistor TR3 and the fifth transistor TR5) may be turned on (e.g., closed), and the second switch S2, the fourth switch S4 and the sixth switch S6 (e.g., the second transistor TR2, the fourth transistor TR4 and the sixth transistor TR6) may be turned off (e.g., disconnected).

[0064] In the second stage PS42, the fourth switch S4 and the sixth switch S6 (e.g., the fourth transistor TR4 and the sixth transistor TR6) may be turned on, and the first switch S1, the second switch S2, the third switch S3 and the fifth switch S5 (e.g., the first transistor TR1, the second transistor TR2, the third transistor TR3 and the fifth transistor TR5) may be turned off.

[0065] In the third stage PS43, the second switch S2, the fourth switch S4 and the fifth switch S5 (e.g., the second transistor TR2, the fourth transistor TR4 and the fifth transistor TR5) may be turned on, and the first switch S1, the third switch S3 and the sixth switch S6 (e.g., the first transistor TR1, the third transistor TR3 and the sixth transistor TR6) may be turned off.

[0066] In the fourth stage PS44, as in the second stage PS42, the fourth switch S4 and the sixth switch S6 (e.g., the fourth transistor TR4 and the sixth transistor TR6) may be turned on, and the first switch S1, the second switch S2, the third switch S3 and the fifth switch S5 (e.g., the first transistor TR1, the second transistor TR2, the third transistor TR3 and the fifth transistor TR5) may be turned off.

[0067] Reference Figure 5A , the connection states 10b_PS41 of the components included in the power supply device 10b are shown for the first stage PS41, and operations related thereto are shown.

[0068] As reference Figure 4 As described above, in the first phase PS41, the first transistor TR1 and the third transistor TR3 may be turned on, and the flying capacitor CFLY may be charged based on the input voltage VIN. The input current provided by the input voltage VIN may flow to the second node N2 through the first transistor TR1, the flying capacitor CFLY and the third transistor TR3. The intermediate voltage VSW may be formed by the input current.

[0069] The inductor current may flow through a first path (eg, Figure 2 In the first phase PS41, the fifth transistor TR5 may be turned on, and the second path (eg, Figure 2 The second path PTH2 in the second path PTH2 may be electrically connected to the output node NOUT, and thus, the capacitor current may flow to the output node NOUT through the hybrid capacitor CHYBRID included in the second path PTH2. The output voltage VOUT may be formed by the inductor current and the capacitor current.

[0070] Reference Figure 5B , the connection status 10b_PS42 of the components included in the power supply device 10b is shown for the second stage PS42, and the operations related thereto are shown.

[0071] As reference Figure 4 As described, in the second phase PS42, the fourth transistor TR4 and the sixth transistor TR6 may be turned on, and the capacitor current may flow to the output node NOUT through the hybrid capacitor CHYBRID. For example, in order to limit and / or prevent the capacitor current from accidentally leaking to the ground voltage GND, the body bias voltage of the sixth transistor TR6 may be controlled or adjusted (for example, the body selection may be performed on the sixth transistor TR6). The fifth transistor TR5 may be turned off, and thus the capacitor current may flow to the output node NOUT through the inductor L. The intermediate voltage VSW and the output voltage VOUT may be formed by the capacitor current.

[0072] Reference Figure 5C , the connection state 10b_PS43 of the components included in the power supply device 10b is shown for the third stage PS43, and operations related thereto are shown.

[0073] As reference Figure 4 As described above, in the third phase PS43, the second transistor TR2 and the fourth transistor TR4 may be turned on, and the flying capacitor CFLY charged in the first phase PS41 may be discharged. The input current provided from the flying capacitor CFLY charged by the input voltage VIN may flow to the second node N2 through the second transistor TR2. The intermediate voltage VSW may be formed by the input current.

[0074] The inductor current may flow to the output node NOUT through the inductor L included in the first path PTH1. In the third phase PS43, the fifth transistor TR5 may be turned on, and the capacitor current may flow to the output node NOUT through the hybrid capacitor CHYBRID included in the second path PTH2. The output voltage VOUT may be formed by the inductor current and the capacitor current.

[0075] Reference Figure 5D , the connection state 10b_PS44 of the components included in the power supply device 10b is shown for the fourth stage PS44, and the operations related thereto are shown.

[0076] The operation in the fourth stage PS44 may be similar to the operation in the second stage PS42. Figure 4As described above, in the fourth phase PS44, the fourth transistor TR4 and the sixth transistor TR6 may be turned on, and the capacitor current may flow to the output node NOUT through the hybrid capacitor CHYBRID. The intermediate voltage VSW and the output voltage VOUT may be formed by the capacitor current.

[0077] For example, in Figure 5A and Figure 5C In the first stage PS41 and the third stage PS43 shown, the output voltage VOUT can be generated based on the inductor current of the inductor L and the capacitor current of the hybrid capacitor CHYBRID obtained by the dual path operation. Figure 5B and Figure 5D In the second stage PS42 and the fourth stage PS44 shown, the output voltage VOUT can be generated based on the capacitor current of the hybrid capacitor CHYBRID. For example, the inductor current and the capacitor current in the first stage PS41 can be collectively referred to as the first current, the capacitor current in the second stage PS42 can be referred to as the second current, the inductor current and the capacitor current in the third stage PS43 can be collectively referred to as the third current, and the capacitor current in the fourth stage PS44 can be referred to as the fourth current.

[0078] Reference Fig. 6A , changes of the intermediate voltage VSW, the voltage VCFLY of the flying capacitor CFLY, the voltage VCHYBRID of the hybrid capacitor CHYBRID, and the voltage VL of the inductor L are shown in the first stage PS41, the second stage PS42, the third stage PS43, and the fourth stage PS44. The voltage VCFLY of the flying capacitor CFLY, the voltage VCHYBRID of the hybrid capacitor CHYBRID, and the voltage VL of the inductor L may be referred to as a flying capacitor voltage, a hybrid capacitor voltage, and an inductor voltage, respectively.

[0079] like Fig. 6A As shown, the voltage VCFLY of the flying capacitor CFLY may vary or change depending on whether the flying capacitor CFLY is connected to the input voltage VIN.

[0080] For example, in the first stage P41, the voltage level of the voltage VCF_TOP at the first electrode (e.g., the upper electrode) of the flying capacitor CFLY connected to the first node N1 may be substantially equal to the voltage level of the input voltage VIN, and the voltage level of the voltage VCF_BOT at the second electrode (e.g., the lower electrode) of the flying capacitor CFLY connected to the third node N3 may be substantially equal to half the voltage level of the input voltage VIN (e.g., VIN / 2). In the second stage PS42, the third stage PS43, and the fourth stage PS44, the voltage level of the voltage VCF_TOP at the first electrode of the flying capacitor CFLY may be substantially equal to half the voltage level of the input voltage VIN (e.g., VIN / 2), and the voltage level of the voltage VCF_BOT at the second electrode of the flying capacitor CFLY may be substantially equal to the voltage level of the ground voltage GND (e.g., about 0V). Therefore, in all of the first stage PS41, the second stage PS42, the third stage PS43, and the fourth stage PS44, the voltage level difference between the first electrode and the second electrode of the flying capacitor CFLY may be maintained at about VIN / 2.

[0081] The intermediate voltage VSW may vary depending on whether an input current is supplied. Fig. 6A Changes or alterations shown.

[0082] For example, in the first stage PS41 and the third stage PS43, the voltage level of the intermediate voltage VSW may be substantially equal to half the voltage level of the input voltage VIN (e.g., VIN / 2). In the second stage PS42 and the fourth stage PS44, the voltage level of the intermediate voltage VSW may be substantially equal to the difference between half the voltage level of the input voltage VIN and the voltage level of the output voltage VOUT (e.g., VIN / 2-VOUT). By performing a three-level operation, the intermediate voltage VSW may have three different voltage levels, for example, a voltage level corresponding to a logic high level (e.g., VIN / 2), a voltage level corresponding to a logic low level (e.g., about 0V), and a voltage level corresponding to a logic middle level (e.g., VIN / 2-VOUT).

[0083] Based on the intermediate voltage VSW, the voltage VCHYBRID of the hybrid capacitor CHYBRID and the voltage VL of the inductor L can be as follows Fig. 6A Change or alteration as indicated.

[0084] For example, in the first stage PS41 and the third stage PS43, the voltage level of the voltage VCH_TOP at the first electrode (e.g., the upper electrode) of the hybrid capacitor CHYBRID connected to the second node N2 may be substantially equal to half the voltage level of the input voltage VIN (e.g., VIN / 2), and the voltage level of the voltage VCH_BOT at the second electrode (e.g., the lower electrode) of the hybrid capacitor CHYBRID connected to the fourth node N4 may be substantially equal to the voltage level of the output voltage VOUT. In the second stage PS42 and the fourth stage PS44, the voltage level of the voltage VCH_TOP at the first electrode of the hybrid capacitor CHYBRID may be substantially equal to the difference between half the voltage level of the input voltage VIN and the voltage level of the output voltage VOUT (e.g., VIN / 2-VOUT), and the voltage level of the voltage VCH_BOT at the second electrode of the hybrid capacitor CHYBRID may be substantially equal to the voltage level of the ground voltage GND (e.g., about 0V). Therefore, in all of the first stage PS41 , the second stage PS42 , the third stage PS43 , and the fourth stage PS44 , the voltage level difference between the first electrode and the second electrode of the hybrid capacitor CHYBRID may be maintained at about VIN / 2-VOUT.

[0085] For example, in the first stage PS41 and the third stage PS43, the voltage level of the voltage VL of the inductor L may be substantially equal to the difference between half the voltage level of the input voltage VIN and the voltage level of the output voltage VOUT (e.g., VIN / 2-VOUT). In the second stage PS42 and the fourth stage PS44, the voltage level of the voltage VL of the inductor L may be substantially equal to the difference between half the voltage level of the input voltage VIN and twice the voltage level of the output voltage VOUT (e.g., VIN / 2-2*VOUT).

[0086] In some example embodiments, based on the above-described changes in the voltages VSW, VCFLY, and VCHYBRID and the second voltage balance condition of the inductor L, the duty cycle D of the inductor L may be obtained by Equation 1, Equation 2, and Equation 3.

[0087] [Equation 1]

[0088]

[0089] [Equation 2]

[0090]

[0091] [Equation 3]

[0092]

[0093] The duty cycle D may represent the ratio of the time interval during which the voltage VL of the inductor L has a logic high level (e.g., voltage level VIN / 2-VOUT) to the total time interval, and T may represent the entire operation cycle. For example, the duty cycle D may represent the ratio of the time intervals corresponding to the first stage PS41 and the third stage PS43 within the entire operation cycle T_4P. The time intervals corresponding to the first stage PS41, the second stage PS42, the third stage PS43, and the fourth stage PS44 may be determined based on the duty cycle D.

[0094] In some example embodiments, the relationship between the current IL of the inductor L, the capacitor current IC, and the output current IOUT may be obtained by Equation 4. For example, D'=1-D in Equation 4. Based on the capacitor charge balance condition, the relationship between the current IL of the inductor L and the capacitor current IC may be obtained by Equations 5 and 6. Based on Equations 4, 5, and 6, the current IL of the inductor L may be obtained by Equation 7.

[0095] [Equation 4]

[0096] D*{IL+IC}+D′*IL=IOUT

[0097] [Equation 5]

[0098] D′*IL=D*IC

[0099] [Equation 6]

[0100]

[0101] [Equation 7]

[0102]

[0103] Reference Figure 6B , changes of the current IL of the inductor L, the current ICFLY of the flying capacitor CFLY, and the current ICHYBRID of the hybrid capacitor CHYBRID are shown in the first stage PS41, the second stage PS42, the third stage PS43, and the fourth stage PS44. The current ICFLY of the flying capacitor CFLY and the current ICHYBRID of the hybrid capacitor CHYBRID may be referred to as a flying capacitor current and a hybrid capacitor current, respectively.

[0104] exist Figure 6BIn the current IL of the inductor L in , "IL1" may represent the case of a conventional buck converter that performs neither three-level operation nor dual-path operation, "IL2" may represent the case of a buck converter that performs only dual-path operation, and "IL3" may represent the case of a buck converter that performs both three-level operation and dual-path operation according to some example embodiments. In "IL3", it can be seen that the DC component is reduced compared to "IL1" and "IL2" because the average value of the current is relatively low, and the AC component is reduced because the variation, fluctuation and / or ripple in the current is relatively small. Therefore, in the buck converter according to some example embodiments, the conduction loss can be reduced.

[0105] The current ICFLY of the flying capacitor CFLY and the current ICHYBRID of the hybrid capacitor CHYBRID may vary or be changed, such as Figure 6B As shown in FIG. 1 , for the current ICHYBRID of the hybrid capacitor CHYBRID, the capacitor charge balance condition can be satisfied.

[0106] Fig. 7A , Figure 7B , Figure 7C , Fig.7D , Fig. 8A and Figure 8B It is shown Figure 3 A diagram of the performance of a power supply unit.

[0107] Reference Fig. 7A , Figure 7B , Figure 7C and Fig.7D , the duty cycle, the inductor DC current INDUCTOR_DC_I, the inductor AC current INDUCTOR_AC_I and the inductor RMS current INDUCTOR_RMS_I of the four different types of converters are shown according to the conversion rates of the four different types of converters.

[0108] exist Fig. 7A , Figure 7B , Figure 7C and Fig.7D , “CASE1” may represent the case of a conventional buck converter that performs neither three-level operation nor dual-path operation, “CASE2” may represent the case of a buck converter that performs only dual-path operation, “CASE3” may represent the case of a buck converter that performs only three-level operation, and “CASE4” may represent the case of a buck converter that performs both three-level operation and dual-path operation according to some example embodiments. Fig. 7A , Figure 7B , Figure 7C and Fig.7DAn example is shown where the input voltage VIN, output voltage VOUT and switching frequency are the same for all converters and the load current is approximately 2 A for all converters.

[0109] In "CASE4", it can be seen that the inductor current is reduced in a section where the conversion ratio (=VOUT / VIN) is about 25% to about 40% compared to "CASE1", "CASE2" and "CASE3". Fig.7D The inductor RMS current INDUCTOR_RMS_I illustrated in FIG. 4 can be reduced by up to about 51% in “CASE4” compared to “CASE1”, and can be reduced by up to about 44% in “CASE4” compared to “CASE2”.

[0110] Reference Fig. 8A and Figure 8B , two different types of converter efficiencies and loss ratios due to DC resistance are shown according to the load current LOAD_I of the two different types of converters.

[0111] exist Fig. 8A and Figure 8B , “CASE41” may represent a case where the DC resistance is approximately 10 mΩ in a buck converter that performs both three-level operation and dual-path operation according to some example embodiments, “CASE42” may represent a case where the DC resistance is approximately 120 mΩ in a buck converter that performs both three-level operation and dual-path operation according to some example embodiments, “CASE11” may represent a case where the DC resistance is approximately 10 mΩ in a conventional buck converter that performs neither three-level operation nor dual-path operation, and “CASE12” may represent a case where the DC resistance is approximately 120 mΩ in a conventional buck converter that performs neither three-level operation nor dual-path operation. Fig. 8A and Figure 8B An example is shown where the input voltage VIN and the switching frequency are the same for all converters and the output voltage VOUT is approximately 1.35V for all converters.

[0112] like Fig. 8AAs shown, it can be seen that the conventional buck converter has a relatively large reduction in converter efficiency due to the increase in DC resistance, and the buck converter according to some example embodiments has a relatively small reduction in converter efficiency due to the increase in DC resistance. For example, as shown by "CASE11" and "CASE12", when the load current LOAD_I in the conventional buck converter is about 4A and the DC resistance increases from about 10mΩ to about 120mΩ, the converter efficiency may be reduced by about 33.4%. On the contrary, as shown by "CASE41" and "CASE42", when the load current LOAD_I in the buck converter according to some example embodiments is about 4A and the DC resistance increases from about 10mΩ to about 120mΩ, the converter efficiency may be reduced by about 8.4%.

[0113] like Figure 8B As shown in , in the buck converters according to some example embodiments of “ CASE41 ” and “ CASE42 ”, it can be seen that the loss due to the DC resistance is relatively small compared to the conventional buck converters of “ CASE11 ” and “ CASE12 ”.

[0114] As described above, the power supply device performing three-level operation and dual-path operation according to some example embodiments may have a structure capable of reducing (and / or minimizing) the loss caused by the DC resistance of the inductor. Therefore, when the power supply device performing three-level operation and dual-path operation according to some example embodiments is applied, used or adopted, a relatively small inductor can be used in the power supply device, and a reduction in circuit size and an improvement in power integrity (PI) can be achieved. In addition, the additional space obtained by reducing the physical size of the inductor can be used to increase the physical size of the capacitor.

[0115] Fig. 9 , Fig. 10A , Fig. 10B , Fig. 10C , Fig. 10D , Fig. 10E , Fig.10F , Fig.11A and Fig. 11B It is shown Figure 3 For the sake of brevity, the operation of the power supply device will be omitted. Figure 4 , Figure 5A , Figure 5B , Figure 5C , Figure 5D , Fig. 6A and Figure 6B Descriptions that are repeated or overlapping.

[0116] Reference Fig. 9 , the power supply device 10b may operate based on a six-phase scheme, and may perform repeated operations at each desired and / or predetermined operation period T_6P.

[0117] For example, the operation cycle T_6P of the six-phase scheme may include a first phase PS61, a second phase PS62, a third phase PS63, a fourth phase PS64, a fifth phase PS65, and a sixth phase P66.

[0118] In the first stage PS61, the first switch S1, the third switch S3 and the fifth switch S5 (e.g., the first transistor TR1, the third transistor TR3 and the fifth transistor TR5) may be turned on, and the second switch S2, the fourth switch S4 and the sixth switch S6 (e.g., the second transistor TR2, the fourth transistor TR4 and the sixth transistor TR6) may be turned off.

[0119] In the second stage PS62, the third switch S3 and the fourth switch S4 (e.g., the third transistor TR3 and the fourth transistor TR4) may be turned on, and the first switch S1, the second switch S2, the fifth switch S5 and the sixth switch S6 (e.g., the first transistor TR1, the second transistor TR2, the fifth transistor TR5 and the sixth transistor TR6) may be turned off.

[0120] In the third stage PS63, the fourth switch S4 and the sixth switch S6 (e.g., the fourth transistor TR4 and the sixth transistor TR6) may be turned on, and the first switch S1, the second switch S2, the third switch S3 and the fifth switch S5 (e.g., the first transistor TR1, the second transistor TR2, the third transistor TR3 and the fifth transistor TR5) may be turned off.

[0121] In the fourth stage PS64, the second switch S2, the fourth switch S4 and the fifth switch S5 (e.g., the second transistor TR2, the fourth transistor TR4 and the fifth transistor TR5) may be turned on, and the first switch S1, the third switch S3 and the sixth switch S6 (e.g., the first transistor TR1, the third transistor TR3 and the sixth transistor TR6) may be turned off.

[0122] In the fifth stage PS65, the third switch S3 and the fourth switch S4 (e.g., the third transistor TR3 and the fourth transistor TR4) may be turned on, and the first switch S1, the second switch S2, the fifth switch S5 and the sixth switch S6 (e.g., the first transistor TR1, the second transistor TR2, the fifth transistor TR5 and the sixth transistor TR6) may be turned off.

[0123] In the sixth stage PS66, the fourth switch S4 and the sixth switch S6 (e.g., the fourth transistor TR4 and the sixth transistor TR6) may be turned on, and the first switch S1, the second switch S2, the third switch S3 and the fifth switch S5 (e.g., the first transistor TR1, the second transistor TR2, the third transistor TR3 and the fifth transistor TR5) may be turned off.

[0124] Reference Fig. 10A , the connection states 10b_PS61 of the components included in the power supply device 10b are shown for the first stage PS61, and operations related thereto are shown. Fig. 10A Can be referenced Figure 5A The description is essentially the same.

[0125] Reference Fig. 10B , the connection states 10b_PS62 of the components included in the power supply device 10b are shown for the second stage PS62, and operations related thereto are shown.

[0126] As reference Fig. 9 As described above, in the second phase PS62, the third transistor TR3 and the fourth transistor TR4 may be turned on, and the inductor current may flow to the output node NOUT through the inductor L. The intermediate voltage VSW and the output voltage VOUT may be formed by the inductor current.

[0127] Reference Fig. 10C , the connection state 10b_PS63 of the components included in the power supply device 10b is shown for the third stage PS63, and operations related thereto are shown. Fig. 10C Can be referenced Figure 5B The description is essentially the same.

[0128] Reference Fig. 10D , the connection state 10b_PS64 of the components included in the power supply device 10b is shown for the fourth stage PS64, and the operations related thereto are shown. Fig. 10D Can be referenced Figure 5C Basically the same as described.

[0129] Reference Fig. 10E , the connection state 10b_PS65 of the components included in the power supply device 10b is shown for the fifth stage PS65, and the operations related thereto are shown.

[0130] As reference Fig. 9 As described above, in the fifth phase PS65, the third transistor TR3 and the fourth transistor TR4 may be turned on, and the inductor current may flow to the output node NOUT through the inductor L. The intermediate voltage VSW and the output voltage VOUT may be formed by the inductor current.

[0131] Reference Fig.10F , the connection state 10b_PS66 of the components included in the power supply device 10b is shown for the sixth stage PS66, and the operations related thereto are shown. Fig.10F Can be referenced Figure 5D The description is essentially the same.

[0132] For example, in Fig. 10A and Fig. 10D In the first stage PS61 and the fourth stage PS64 shown in FIG. 1 , the output voltage VOUT can be generated based on the inductor current of the inductor L and the capacitor current of the hybrid capacitor CHYBRID obtained by the dual path operation. Fig. 10B and Fig. 10E In the second stage PS62 and the fifth stage PS65 shown in FIG. 1 , an output voltage VOUT may be generated based on the inductor current of the inductor L. Fig. 10C and Fig.10F In the third stage PS63 and the sixth stage PS66 shown in FIG. 1 , the output voltage VOUT may be generated based on the capacitor current of the hybrid capacitor CHYBRID. For example, the inductor current and the capacitor current in the first stage PS61 may be collectively referred to as the first current, the inductor current in the second stage PS62 may be referred to as the second current, the capacitor current in the third stage PS63 may be referred to as the third current, the inductor current and the capacitor current in the fourth stage PS64 may be collectively referred to as the fourth current, the inductor current in the fifth stage PS65 may be referred to as the fifth current, and the capacitor current in the sixth stage PS66 may be referred to as the sixth current.

[0133] Reference Fig.11A , changes in the intermediate voltage VSW, the voltage VCFLY of the flying capacitor CFLY, the voltage VCHYBRID of the hybrid capacitor CHYBRID, and the voltage VL of the inductor L are shown in the first stage PS61, the second stage PS62, the third stage PS63, the fourth stage PS64, the fifth stage PS65, and the sixth stage PS66.

[0134] The operations in the first stage PS61, the third stage PS63, the fourth stage PS64 and the sixth stage PS66 can be respectively Fig. 6A The operations in the first stage PS41, the second stage PS42, the third stage PS43 and the fourth stage PS44 are basically the same.

[0135] In the second stage PS62 and the fifth stage PS65, the voltage level of the voltage VCF_TOP of the first electrode of the flying capacitor CFLY may be substantially equal to half the voltage level of the input voltage VIN (e.g., VIN / 2), and the voltage level of the voltage VCF_BOT of the second electrode of the flying capacitor CFLY may be substantially equal to the voltage level of the ground voltage GND (e.g., about 0 V). Therefore, in all the first stage PS61, the second stage PS62, the third stage PS63, the fourth stage PS64, the fifth stage PS65, and the sixth stage PS66, the voltage level difference between the first electrode and the second electrode of the flying capacitor CFLY may be maintained at about VIN / 2.

[0136] In the second stage PS62 and the fifth stage PS65 , the voltage level of the intermediate voltage VSW may be substantially equal to the voltage level of the ground voltage GND (eg, about 0 V).

[0137] In the second stage PS62 and the fifth stage PS65, the voltage level of the voltage VCH_TOP at the first electrode of the hybrid capacitor CHYBRID may be substantially equal to the voltage level of the ground voltage GND (e.g., about 0V), and the voltage level of the voltage VCH_BOT at the second electrode of the hybrid capacitor CHYBRID may be substantially equal to the difference between the voltage level of the output voltage VOUT and half the voltage level of the input voltage VIN (e.g., VOUT-VIN / 2). Therefore, in all of the first stage PS61, the second stage PS62, the third stage PS63, the fourth stage PS64, the fifth stage PS65, and the sixth stage PS66, the voltage level difference between the first electrode and the second electrode of the hybrid capacitor CHYBRID may be maintained at about VIN / 2-VOUT.

[0138] In the second stage PS62 and the fifth stage PS65 , the voltage level of the voltage VL of the inductor L may be substantially equal to a voltage level (eg, −VOUT) obtained by multiplying the voltage level of the output voltage VOUT by −1.

[0139] Reference Fig. 11B , changes in the current IL of the inductor L, the current ICFLY of the flying capacitor CFLY, and the current ICHYBRID of the hybrid capacitor CHYBRID are shown in the first stage PS61, the second stage PS62, the third stage PS63, the fourth stage PS64, the fifth stage PS65, and the sixth stage PS66.

[0140] The operations in the first stage PS61, the third stage PS63, the fourth stage PS64 and the sixth stage PS66 can be respectively Figure 6BThe operations in the first stage PS41, the second stage PS42, the third stage PS43 and the fourth stage PS44 are basically the same.

[0141] As reference Figure 6B As described above, in "IL3", it can be seen that the DC component and the AC component are reduced compared to "IL1" and "IL2". The current ICFLY of the flying capacitor CFLY and the current ICHYBRID of the hybrid capacitor CHYBRID may vary or be changed, such as Fig. 11B shown.

[0142] Fig. 12A and Fig. 12B It is shown Figure 3 A diagram of the operation of a power supply device.

[0143] Reference Fig. 12A , the operation region (or range) and the operation mode of the power supply device 10b can be determined based on the conversion rate obtained by dividing the output voltage VOUT by the input voltage VIN.

[0144] For example, the power supply device 10 b may be implemented in the form of a buck converter or a step-down converter, and therefore, the conversion rate of the power supply device 10 b may be greater than zero and less than or equal to one.

[0145] In some example embodiments, the operating region of the power supply device 10b may be within a range where the conversion rate is greater than zero and less than or equal to the first value CRL. For example, when the conversion rate is greater than the first value CRL and less than or equal to one, the power supply device 10b may not operate normally (e.g., the power supply device 10b may be in a non-operating region NOP).

[0146] In some example embodiments, the first value CRL may be about 0.5. However, some example embodiments are not limited thereto. For example, the first value CRL may be any real number greater than zero and less than or equal to one. For example, the operating region of the power supply device 10b may be within a range where the conversion rate is greater than the second value and less than or equal to the first value CRL, and the second value is less than the first value CRL and greater than zero.

[0147] In some example embodiments, when the conversion rate is greater than the reference value CRREF in the operation region of the power supply device 10b, the operation mode may be determined as the first operation mode, and the power supply device 10b may refer to Figures 4 to 6B When the conversion rate is less than or equal to the reference value CRREF in the operation region of the power supply device 10b, the operation mode may be determined as the second operation mode, and the power supply device 10b may refer to Figures 9 to 11B Describes the six-phase scheme OP_6P operation.

[0148] In some example embodiments, the reference value CRREF may be about 0.25. However, some example embodiments are not limited thereto. For example, the reference value CREEF may be any real number greater than zero and less than the first value CRL.

[0149] Reference Fig. 12B , shows the inductor RMS current INDUCTOR_RMS_I of four different types of converters depending on the output voltage of the four different types of converters.

[0150] As reference Fig. 7A , Figure 7B , Figure 7C and Fig.7D As described, “CASE1” may represent the case of a conventional buck converter that performs neither three-level operation nor dual-path operation, “CASE2” may represent the case of a buck converter that performs only dual-path operation, “CASE3” may represent the case of a buck converter that performs only three-level operation, and “CASE4” may represent the case of a buck converter that performs both three-level operation and dual-path operation according to some example embodiments. Fig. 12B An example is shown where the load current is approximately 2A for all converters.

[0151] In "CASE4", it can be seen that the inductor RMS current is reduced compared to "CASE1", "CASE2" and "CASE3". In "CASE4", it can be seen that in a portion where the conversion rate is about 0% to about 50%, the operation mode is changed based on a conversion rate of about 25%. For example, when the input voltage VIN is about 5V, the operation mode may be determined as the second operation mode, and the buck converter according to some example embodiments may operate in a six-phase scheme OP_6P in a portion where the output voltage VOUT is from about 0V to about 1.25V (e.g., in a portion where the conversion rate is about 0% to about 25%). For example, when the input voltage VIN is about 5V, the operation mode may be determined as the first operation mode, and the buck converter according to example embodiments may operate in a four-phase scheme OP_4P in a portion where the output voltage VOUT is from about 1.25V to about 2.5V (e.g., in a portion where the conversion rate is about 25% to about 50%).

[0152] Fig.13 yes Figure 2 For the sake of simplicity, the circuit diagram of the power supply device is omitted. Figure 3 Duplicate or overlapping descriptions.

[0153] Reference Fig.13The power supply device 10c may include a first transistor TR1, a second transistor TR2, a third transistor TR3, a fourth transistor TR4, a fifth transistor TR5, a sixth transistor TR61, a seventh transistor TR62, a flying capacitor CFLY, an inductor L, a hybrid capacitor CHYBRID and an output capacitor COUT.

[0154] Apart from Figure 3 In addition to the sixth transistor TR6 being changed into the sixth transistor TR61 and the seventh transistor TR62, the power supply device 10c can be used with Figure 3 The power supply device 10b is basically the same.

[0155] The sixth transistor TR61 and the seventh transistor TR62 may be connected in series between the third node N3 and the fourth node N4, and may be implemented so that a body bias voltage of each of the sixth transistor TR61 and the seventh transistor TR62 is fixed (e.g., so that body selection is not performed on the sixth transistor TR61 and the seventh transistor TR62). The sixth transistor TR61 and the seventh transistor TR62 may correspond to Figure 2 The sixth switch S6 in Figure 2 The third control signal CS3 in may be applied to the gate electrodes of the sixth transistor TR61 and the seventh transistor TR62.

[0156] The operations of the sixth transistor TR61 and the seventh transistor TR62 can be similar to those in the reference Figures 4 to 6B The four-phase approach described and referenced Figures 9 to 11B The operation of the sixth transistor TR6 in the six-phase scheme described is essentially the same. Fig.13 As shown, the sixth transistor TR61 and the seventh transistor TR62 can be arranged in opposite directions, and they can limit and / or prevent the capacitor current from accidentally leaking to the ground voltage GND due to the parasitic diode without body selection. For example, the sixth transistor TR61 and the seventh transistor TR62 can be NMOS transistors.

[0157] The power supply device 10 c may include seven transistors TR1 , TR2 , TR3 , TR4 , TR5 , TR61 , and TR62 , three capacitors CFLY , CHYBRID , and COUT , and one inductor L.

[0158] Fig.14 is a block diagram showing a power supply device according to some example embodiments. Figure 1 Descriptions that are repeated or overlapping.

[0159] Reference Fig.14The power supply device 12 includes a three-level conversion circuit 100, a dual-path hybrid conversion circuit 200, and an auxiliary switch circuit 300. The power supply device 12 may further include a control signal generating circuit 400.

[0160] In addition to the power supply device 12 including the control signal generating circuit 400, the power supply device 12 can be Figure 1 The power supply devices 10 are basically the same.

[0161] The control signal generating circuit 400 may generate a plurality of first control signals CS1 , second control signals CS2 , and third control signals CS3 .

[0162] In some example embodiments, the three-level conversion circuit 100 , the dual-path hybrid conversion circuit 200 , and the auxiliary switching circuit 300 may form a power domain, and the control signal generating circuit 400 may form a control domain.

[0163] Fig.15A and Fig. 15B It is shown that the Fig.14 A block diagram of an example of a control signal generating circuit in a power supply device.

[0164] Reference Fig.15A , the control signal generating circuit 400 a may include a first comparator 410 , a duty cycle generator 420 , and a switching logic and gate driver 430 .

[0165] The first comparator 410 may generate a first signal COMP1 by comparing the output voltage VOUT with the reference voltage VOUT_REF. The output voltage VOUT may be fed back from the output node NOUT. The duty ratio generator 420 may generate a plurality of phase signals PSS based on the first signal COMP1.

[0166] In some example embodiments, when the power supply device 12 is used with reference to Figures 4 to 6B When the four-phase scheme described above is operated, the plurality of phase signals PSS may include information associated with the first phase PS41, the second phase PS42, the third phase PS43, and the fourth phase PS44 of the four-phase scheme. Figures 9 to 11B When the described six-phase scheme operates, the plurality of phase signals PSS may include information associated with a first phase PS61, a second phase PS62, a third phase PS63, a fourth phase PS64, a fifth phase PS65, and a sixth phase PS66 of the six-phase scheme.

[0167] In some example embodiments, the power supply device 12 may operate in a four-phase scheme or a six-phase scheme based on a comparison result of the output voltage VOUT and the reference voltage VOUT_REF. For example, when the voltage level of the output voltage VOUT is higher than the voltage level of the reference voltage VOUT_REF, the power supply device 12 may operate in a four-phase scheme. For example, when the voltage level of the output voltage VOUT is lower than or equal to the voltage level of the reference voltage VOUT_REF, the power supply device 12 may operate in a six-phase scheme. For example, as shown in FIG. Fig. 12B As described above, when the voltage level of the output voltage VOUT ranges from about 0V to about 2.5V, the voltage level of the reference voltage VOUT_REF may be about 1.25V.

[0168] The switch logic and gate driver 430 may generate a plurality of first control signals CS1, a second control signal CS2, and a third control signal CS3 based on the plurality of phase signals PSS. For example, the plurality of first control signals CS1 may include control signals CS11, CS12, CS13, and CS14. For example, the control signals CS11, CS12, CS13, CS14, CS2, and CS3 may be applied to gate electrodes of transistors TR1, TR2, TR3, TR4, TR5, TR6, TR61, and TR62, and may be used to turn on and off transistors TR1, TR2, TR3, TR4, TR5, TR6, TR61, and TR62, as shown in FIG. Figures 4 to 5D or Figures 9 to 10F shown.

[0169] Reference Fig. 15B , the control signal generating circuit 400 b may include a first comparator 410 , a duty cycle generator 420 , a switching logic and gate driver 430B and a second comparator 440 .

[0170] The control signal generating circuit 400b may be similar to the control signal generating circuit 400b except that the control signal generating circuit 400b further includes the second comparator 440 and the operation of the switching logic and the gate driver 430b is partially changed. Fig.15A The control signal generating circuit 400a is basically the same.

[0171] The second comparator 440 can generate a second signal COMP2 by comparing the ground voltage GND with the sensing voltage VSEN. The second signal COMP2 can indicate whether the current flowing through the inductor L is zero. The sensing voltage VSEN can be provided by the dual-path hybrid conversion circuit 200. The switch logic and gate driver 430b can generate a plurality of first control signals CS1, a second control signal CS2, and a third control signal CS3 based on the second signal COMP2 and a plurality of phase signals PSS.

[0172] When the current flowing through the inductor L becomes less than zero, for example, when the direction of the current flowing through the inductor L changes (or reverses) to the opposite direction, the current may flow from the output node NOUT to the ground voltage GND, and the converter efficiency may decrease or deteriorate. Therefore, in order to limit and / or prevent the situation where the direction of the current flowing through the inductor L changes, the moment when the current flowing through the inductor L becomes zero may be detected, and then the control signals CS1, CS2, and CS3 and the operations of the transistors TR1, TR2, TR3, TR4, TR5, TR6, TR61, and TR62 may be controlled or adjusted.

[0173] In some example embodiments, the node directly connected to the hybrid capacitor CHYBRID and the auxiliary switch circuit 300 (eg, Figure 2 and Figure 3 The fourth node N4 in the circuit is connected to the inductor L instead of the node directly connected to the inductor L (for example, Figure 2 and Figure 3 A second node N2 in the circuit provides a sensing voltage VSEN.

[0174] Fig.16 and Fig.17 is a flowchart illustrating a method of operating a power supply device according to some example embodiments.

[0175] Reference Figure 1 and Fig.16 In the method of operating a power supply device according to some example embodiments, a three-level operation is performed using a flying capacitor CFLY (operation S110), a dual-path operation is performed using an inductor L included in a first path 210 and a hybrid capacitor CHYBRID included in a second path 220 (operation S120), and an output voltage VOUT is generated based on the three-level operation and the dual-path operation (operation S130). In some example embodiments, operations S110 and S120 may be performed substantially simultaneously or in parallel. In some example embodiments, operations S110 and S120 may be performed sequentially and / or alternately. For example, the power supply device may be as described with reference to Figures 1 to 3 and Figures 13 to 15B described and can be implemented as described in Figures 4 to 12B Operate descriptively.

[0176] Reference Figure 1 and Fig.17 In the method of operating a power supply device according to some example embodiments, a four-phase scheme or a six-phase scheme is selected (operation S210), and based on the scheme selected between the four-phase scheme and the six-phase scheme, an output voltage VOUT is provided by performing a three-level operation using a flying capacitor CFLY and a dual-path operation using an inductor L and a hybrid capacitor CHYBRID (operation S220). For example, in operation S210, as shown in reference Fig. 12A As described above, a four-stage solution or a six-stage solution may be selected based on the conversion rate. For example, in operation S220, when a four-stage solution is selected, the power supply device may be configured as shown in FIG. Figures 4 to 6B When the six-phase scheme is selected, the power supply unit can be operated as described in Figures 9 to 11B For example, operation S220 may include Fig.16 Operations S110, S120 and S130 in .

[0177] Fig.18 is a block diagram illustrating a memory module according to some example embodiments.

[0178] Reference Fig.18 , the memory module 500 may include a circuit board 501, a plurality of memory devices 601a, 601b, 601c, 601d, 601e, 602a, 602b, 602c, 602d, 602e, 603a, 603b, 603c, 603d, 604a, 604b, 604c, and 604d, and a power management integrated circuit (PMIC) 580. The memory module 500 may also include a buffer chip (BUF) 590 (e.g., a registered clock driver; RCD) and module resistor units 560 and 570. For example, a plurality of memory devices 601 a to 601 e , 602 a to 602 e , 603 a to 603 d and 604 a to 604 d , the PMIC 580 , the buffer chip 590 and / or the module resistance units 560 and 570 may be provided, arranged or mounted on or in the circuit board 501 .

[0179] The buffer chip 590 may control the plurality of memory devices 601a to 601e, 602a to 602e, 603a to 603d, and 604a to 604d and the PMIC 580 under the control of a memory controller located outside the memory module 500. For example, the buffer chip 590 may receive an address ADDR, a command CMD, and data DAT from the memory controller.

[0180] The circuit board 501 may extend in a second direction D2 perpendicular to the first direction D1 between the first edge portion 503 and the second edge portion 505. The first edge portion 503 and the second edge portion 505 may extend in the first direction D1. For example, the circuit board 501 may be a printed circuit board (PCB). The buffer chip 590 may be arranged at the center of the circuit board 501. The memory devices 601a to 601e and 602a to 602e may be arranged in a plurality of rows or along a plurality of rows between the buffer chip 590 and the first edge portion 503, and the memory devices 603a to 603d and 604a to 604d may be arranged in a plurality of rows or along a plurality of rows between the buffer chip 590 and the second edge portion 505.

[0181] The buffer chip 590 may store data DAT in a plurality of memory devices 601a to 601e, 602a to 602e, 603a to 603d, and 604a to 604d. The buffer chip 590 may provide command / address (CA) signals (e.g., corresponding to commands CMD and addresses ADDR) to the plurality of memory devices 601a to 601e, 602a to 602e, 603a to 603d, and 604a to 604d via CA transmission lines 561, 563, 571, and 573. In some example embodiments, the operations described herein as being performed by the buffer chip 590 may be performed by a processing circuit.

[0182] CA transmission lines 561 and 563 may be commonly connected to module resistance unit 560 adjacent to first edge portion 503, and CA transmission lines 571 and 573 may be commonly connected to module resistance unit 570 adjacent to second edge portion 505. Each of module resistance units 560 and 570 may include a terminal resistor Rtt / 2 connected to a terminal voltage Vtt.

[0183] For example, at least one of each one or more memory devices 601a to 601e, 602a to 602e, 603a to 603d, and 604a to 604d of the plurality of memory devices 601a to 601e, 602a to 602e, 603a to 603d, and 604a to 604d may be or may include a DRAM device.

[0184] The PMIC 580 may be disposed adjacent to the buffer chip 590. The PMIC 580 may generate a power supply voltage VDD based on an input voltage VIN, and may provide the power supply voltage VDD to a plurality of memory devices 601a to 601e, 602a to 602e, 603a to 603d, and 604a to 604d.

[0185] The PMIC 580 may include a power supply device 3LDP PSD. The power supply device 3LDP PSD may be a power supply device according to some example embodiments of the inventive concept. For example, the power supply device 3LDP PSD may generate an output voltage VOUT corresponding to a power supply voltage VDD by performing both a three-level operation and a dual-path operation. Therefore, even if the physical size of the inductor is reduced, the loss due to the DC resistance of the inductor may be reduced, and the additional space obtained by reducing the physical size of the inductor may be used for other components (for example, to increase the physical size of the capacitor).

[0186] although Fig.18 Although not shown in the figure, the memory module 500 may further include a serial presence detection (SPD) chip. For example, the SPD chip may include device information and / or initial information of the memory module 500, such as a module form, module configuration, storage capacity, module type, execution environment, etc. of the memory module 500. When a memory system including the memory module 500 having the SPD chip is started, the device information may be read or retrieved from the SPD chip, and the memory module 500 may be identified, marked, and / or controlled based on the device information.

[0187] Fig.19 is a block diagram illustrating an example of a memory device included in a memory module according to some example embodiments of the inventive concept.

[0188] Reference Fig.19 , the memory device 700 may include a control logic circuit 710, an address register 720, a bank control logic circuit 730, a row address multiplexer (RA MUX) 740, a refresh counter 745, a column address (CA) latch 750, a row decoder 760, a column decoder 770, a memory cell array 800, a sense amplifier unit 785, an input / output (I / O) gating circuit 790, and a data I / O buffer 795. For example, the memory device 700 may be one of various volatile memory devices such as a DRAM device.

[0189] The memory cell array 800 may include a first memory bank array 810 to an eighth memory bank array 880 (e.g., a first memory bank array to an eighth memory bank array 810, 820, 830, 840, 850, 860, 870, and 880). The row decoder 760 may include a first memory bank row decoder 760a to an eighth memory bank row decoder 760h connected to the first memory bank array 810 to the eighth memory bank array 880, respectively. The column decoder 770 may include a first memory bank column decoder 770a to an eighth memory bank column decoder 770h connected to the first memory bank array 810 to the eighth memory bank array 880, respectively. The sense amplifier unit 785 may include a first memory bank sense amplifier 785a to an eighth memory bank sense amplifier 785h connected to the first memory bank array 810 to the eighth memory bank array 880, respectively.

[0190] The first memory bank array 810 to the eighth memory bank array 880, the first memory bank row decoder 760a to the eighth memory bank row decoder 760h, the first memory bank column decoder 770a to the eighth memory bank column decoder 770h, and the first memory bank sense amplifier 785a to the eighth memory bank sense amplifier 785h may form the first memory bank to the eighth memory bank. Each of the first memory bank array 810 to the eighth memory bank array 880 may include a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells MC at intersections of the word lines WL and the bit lines BL.

[0191] although Fig.19 Memory device 700 is shown to include eight memory banks (and eight memory bank arrays, eight row decoders, etc.), but memory device 700 may include any number of memory banks; for example, one, two, four, eight, twelve, or thirty-two, or any number between one and thirty-two.

[0192] The address register 720 may receive an address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR from a memory controller located outside the memory device 700. The address register 720 may provide the received bank address BANK_ADDR to the bank control logic circuit 730, may provide the received row address ROW_ADDR to the row address multiplexer 740, and may provide the received column address COL_ADDR to the column address latch 750.

[0193] The bank control logic circuit 730 may generate a bank control signal in response to the bank address BANK_ADDR. In response to the bank control signal, a bank row decoder corresponding to the bank address BANK_ADDR may be activated among the first to eighth bank row decoders 760a to 760h, and a bank column decoder corresponding to the bank address BANK_ADDR may be activated among the first to eighth bank column decoders 770a to 770h in response to the bank control signal.

[0194] The row address multiplexer 740 may receive the row address ROW_ADDR from the address register 720, and may receive the refresh row address REF_ADDR from the refresh counter 745. The row address multiplexer 740 may selectively output the row address ROW_ADDR or the refresh row address REF_ADDR as the row address RA. The row address RA output from the row address multiplexer 740 may be applied to the first to eighth bank row decoders 760a to 760h.

[0195] The activated bank row decoder among the first to eighth bank row decoders 760a to 760h may decode the row address RA output from the row address multiplexer 740, and may activate a word line WL corresponding to the row address RA in the corresponding bank array. For example, the activated bank row decoder may generate a word line driving voltage, and may apply the word line driving voltage to the word line WL corresponding to the row address RA.

[0196] The column address latch 750 may receive the column address COL_ADDR from the address register 720 and may temporarily store the received column address COL_ADDR. In some example embodiments, in a burst mode, the column address latch 750 may generate a column address incremented from the received column address COL_ADDR. The column address latch 750 may apply the temporarily stored or generated column address to the first to eighth bank column decoders 770a to 770h.

[0197] An activated bank column decoder among the first to eighth bank column decoders 770 a to 770 h may decode the column address COL_ADDR output from the column address latch 750 and may control the I / O gating circuit 790 to output data corresponding to the column address COL_ADDR.

[0198] The I / O gating circuit 790 may include a circuit configured to gate input / output data. The I / O gating circuit 790 may also include a read data latch configured to store data output from the first memory bank array 810 to the eighth memory bank array 880, and may also include a write control device for writing data into the first memory bank array 810 to the eighth memory bank array 880.

[0199] The data DAT read from one of the first to eighth memory bank arrays 810 to 880 may be read by a sense amplifier connected to one memory bank array from which the read data DAT is to be read, and may be stored in a read data latch. The data DAT stored in the read data latch may be provided to a memory controller via a data I / O buffer 795. The data DAT to be written into one of the first to eighth memory bank arrays 810 to 880 may be provided from the memory controller to an I / O gating circuit 790 via the data I / O buffer 795, and the I / O gating circuit 790 may write the data DAT into one memory bank array through a write driver.

[0200] The control logic circuit 710 may control the operation of the memory device 700. For example, the control logic circuit 710 may generate a control signal for the memory device 700 to perform a write operation and / or a read operation. The control logic circuit 710 may include a command decoder 711 that decodes a command CMD received from a memory controller, and a mode register 712 that sets an operation mode of the memory device 700. In some example embodiments, the operations described herein as being performed by the control logic circuit 710 may be performed by a processing circuit. For example, the command decoder 711 may generate a control signal corresponding to the command CMD by decoding a write enable signal, a row address strobe signal, a column address strobe signal, a chip select signal, etc.

[0201] Fig. 20 is a block diagram illustrating an integrated circuit including a power supply device according to some example embodiments.

[0202] Reference Fig. 20 , the integrated circuit 900 includes a power supply device (3LDP PSD) 910 and an internal circuit 920.

[0203] The power supply device 910 may be a power supply device according to some example embodiments. For example, the power supply device 910 may generate an output voltage VOUT by performing both a three-level operation and a dual-path operation. Therefore, even if the physical size of the inductor is reduced, the loss due to the DC resistance of the inductor may be reduced, and the additional space obtained by reducing the physical size of the inductor may be used for other components (e.g., for increasing the physical size of the capacitor). The internal circuit 920 may perform a specific (e.g., desired and / or predetermined) operation based on the output voltage (or power supply voltage) VOUT provided from the power supply device 910.

[0204] Example embodiments may be applied to various electronic devices and systems including power supply devices. For example, some example embodiments may be applied to systems such as personal computers (PCs), server computers, data centers, workstations, mobile phones, smart phones, tablet computers, laptop computers, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, portable game consoles, music players, video cameras, video players, navigation devices, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-book readers, virtual reality (VR) devices, augmented reality (AR) devices, robotic devices, drones, cars, etc.

[0205] One or more elements disclosed above may include or be implemented in a processing circuit, such as hardware including a logic circuit, a hardware / software combination of a processor that executes software, or a combination thereof. For example, the processing circuit may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc.

[0206] The above is an illustration of example embodiments and should not be construed as limiting thereof. Although some example embodiments have been described, those skilled in the art will readily appreciate that many modifications may be made in the example embodiments without materially departing from the novel teachings and advantages of the example embodiments. Therefore, all such modifications are intended to be included within the scope of the example embodiments defined in the claims. Therefore, it will be understood that the foregoing is an illustration of various example embodiments and should not be construed as being limited to the specific example embodiments disclosed, and modifications to the disclosed example embodiments as well as other example embodiments are intended to be included within the scope of the appended claims.

Claims

1. A power supply device, comprising: A three-level conversion circuit including a flying capacitor configured for three-level operation, the three-level conversion circuit being configured to generate an intermediate voltage based on an input voltage, a plurality of first control signals, and the flying capacitor; a dual-path hybrid conversion circuit, comprising a first path, a second path, an inductor in the first path, and a hybrid capacitor in the second path, the dual-path hybrid conversion circuit being configured to generate an output voltage based on the intermediate voltage, a second control signal, the inductor, and the hybrid capacitor, the first path and the second path both being connected to an output node providing the output voltage, the first path and the second path being different from each other; as well as an auxiliary switch circuit between the three-level conversion circuit and the dual-path hybrid conversion circuit, the auxiliary switch circuit being configured to control a current flowing through the hybrid capacitor based on a third control signal, Wherein, the power supply device is configured to selectively operate based on a four-phase scheme and a six-phase scheme according to an operation mode.

2. The power supply device according to claim 1, in, The four-stage program includes a first stage, a second stage, a third stage, and a fourth stage, and The power supply device is configured to perform the following operations in response to a plurality of first control signals, the second control signal, and the third control signal: operating during the first phase in which the flying capacitor is charged and a first current flows through the inductor and the hybrid capacitor, operating during the second phase in which a second current flows through the hybrid capacitor, operating during the third phase in which the flying capacitor is discharged and a third current flows through the inductor and the hybrid capacitor, and Operating during the fourth phase a fourth current flows through the hybrid capacitor.

3. The power supply device according to claim 1, in, The six-stage program includes a first stage, a second stage, a third stage, a fourth stage, a fifth stage, and a sixth stage, and The power supply device is configured to perform the following operations in response to the plurality of first control signals, the second control signal, and the third control signal: operating during the first phase in which the flying capacitor is charged and a first current flows through the inductor and the hybrid capacitor, operating during the second phase in which a second current flows through the inductor, operating during the third phase in which a third current flows through the hybrid capacitor, operating during the fourth phase in which the flying capacitor is discharged and a fourth current flows through the inductor and the hybrid capacitor, operating during the fifth phase in which a fifth current flows through the inductor, and Operating during the sixth phase a sixth current flows through the hybrid capacitor.

4. The power supply device according to claim 1, wherein: The three-level conversion circuit further includes: a first transistor connected between the input voltage and a first node; a second transistor connected between the first node and a second node; a third transistor connected between the second node and a third node; and a fourth transistor connected between the third node and a ground voltage, and The flying capacitor is connected between the first node and the third node.

5. The power supply device according to claim 4, wherein: The dual-path hybrid conversion circuit also includes: a fifth transistor connected between the fourth node and the output node, wherein the inductor is connected between the second node and the output node, and The hybrid capacitor is connected between the second node and the fourth node.

6. The power supply device according to claim 5, wherein: The auxiliary switch circuit comprises: A sixth transistor is connected between the third node and the fourth node, and a body bias voltage applied to the sixth transistor is variable.

7. The power supply device according to claim 6, in, The four-stage program includes a first stage, a second stage, a third stage, and a fourth stage, and The power supply device is configured to perform the following operations in response to the plurality of first control signals, the second control signal, and the third control signal: operating during the first phase in which the first transistor, the third transistor, and the fifth transistor are turned on and the second transistor, the fourth transistor, and the sixth transistor are turned off, operating during the second phase in which the fourth transistor and the sixth transistor are turned on and the first transistor, the second transistor, the third transistor, and the fifth transistor are turned off, operating during the third phase in which the second transistor, the fourth transistor, and the fifth transistor are turned on and the first transistor, the third transistor, and the sixth transistor are turned off, and operates during the fourth phase in which the fourth transistor and the sixth transistor are turned on and the first transistor, the second transistor, the third transistor, and the fifth transistor are turned off.

8. The power supply device according to claim 6, in, The six-stage program includes a first stage, a second stage, a third stage, a fourth stage, a fifth stage, and a sixth stage, and The power supply device is configured to perform the following operations in response to the plurality of first control signals, the second control signal, and the third control signal: operating during the first phase in which the first transistor, the third transistor, and the fifth transistor are turned on and the second transistor, the fourth transistor, and the sixth transistor are turned off, operating during the second phase in which the third transistor and the fourth transistor are turned on and the first transistor, the second transistor, the fifth transistor, and the sixth transistor are turned off, operating during the third phase in which the fourth transistor and the sixth transistor are turned on and the first transistor, the second transistor, the third transistor, and the fifth transistor are turned off, operating during the fourth phase in which the second transistor, the fourth transistor, and the fifth transistor are turned on and the first transistor, the third transistor, and the sixth transistor are turned off, operating during the fifth phase in which the third transistor and the fourth transistor are turned on and the first transistor, the second transistor, the fifth transistor, and the sixth transistor are turned off, and operates during the sixth phase in which the fourth transistor and the sixth transistor are turned on and the first transistor, the second transistor, the third transistor, and the fifth transistor are turned off.

9. The power supply device according to claim 6, in, The first transistor and the second transistor are P-type metal oxide semiconductor transistors, and Wherein, the third transistor, the fourth transistor, the fifth transistor and the sixth transistor are n-type metal oxide semiconductor transistors.

10. The power supply device according to claim 5, wherein: The auxiliary switch circuit comprises: A sixth transistor and a seventh transistor are connected in series between the third node and the fourth node, and a body bias voltage applied to each of the sixth transistor and the seventh transistor is fixed.

11. The power supply device according to claim 1, further comprising: A control signal generating circuit is configured to generate the plurality of first control signals, the second control signal and the third control signal.

12. The power supply device according to claim 11, wherein: The control signal generating circuit comprises: a first comparator configured to generate a first signal by comparing the output voltage with a reference voltage; a duty cycle generator configured to generate a plurality of phase signals based on the first signal; and A switching logic and a gate driver are configured to generate the plurality of first control signals, the second control signal, and the third control signal based on the plurality of phase signals.

13. The power supply device according to claim 12, wherein: The control signal generating circuit further includes: a second comparator configured to generate a second signal by comparing a ground voltage with a sense voltage provided from the dual-path hybrid conversion circuit, the second signal indicating whether the current flowing through the inductor is zero, and The switch logic and the gate driver are configured to generate the plurality of first control signals, the second control signal, and the third control signal based on the plurality of phase signals and the second signal.

14. The power supply device according to claim 13, wherein: The sensing voltage is provided from a node directly connected to the hybrid capacitor and the auxiliary switching circuit, rather than from a node directly connected to the inductor.

15. The power supply device according to claim 1, wherein: The operation mode is determined based on a conversion rate obtained by dividing the output voltage by the input voltage.

16. The power supply device according to claim 15, in, When the conversion rate is greater than a reference value in the operation region, the operation mode is determined to be a first operation mode, and the power supply device operates in the four-phase scheme, and Wherein, when the conversion rate is less than or equal to the reference value within the operation region, the operation mode is determined to be the second operation mode, and the power supply device operates in the six-phase scheme.

17. The power supply device according to claim 1, wherein: A voltage level of the output voltage is lower than a voltage level of the input voltage.

18. A memory module comprising: Circuit boards; a plurality of memory devices on said circuit board; as well as a power supply device on the circuit board, the power supply device being configured to provide a power supply voltage to the plurality of memory devices, Wherein, the power supply device comprises: A three-level conversion circuit including a flying capacitor for three-level operation, the three-level conversion circuit being configured to generate an intermediate voltage based on an input voltage, a plurality of first control signals and the flying capacitor, a dual-path hybrid conversion circuit, comprising a first path, a second path, an inductor in the first path, and a hybrid capacitor in the second path, the dual-path hybrid conversion circuit being configured to generate an output voltage based on the intermediate voltage, a second control signal, the inductor, and the hybrid capacitor, the first path and the second path both being connected to an output node providing the output voltage, the first path and the second path being different from each other, the output voltage corresponding to the power supply voltage, and an auxiliary switch circuit between the three-level conversion circuit and the dual-path hybrid conversion circuit, the auxiliary switch circuit being configured to control a current flowing through the hybrid capacitor based on a third control signal, Wherein, the power supply device is configured to selectively operate based on a four-phase scheme and a six-phase scheme according to an operation mode.

19. The memory module of claim 18, wherein: The plurality of memory devices are dynamic random access memory devices.

20. A power supply device, comprising: a first transistor connected between an input voltage and a first node; a second transistor connected between the first node and a second node, the second node providing an intermediate voltage; a third transistor connected between the second node and a third node; a fourth transistor connected between the third node and a ground voltage; a flying capacitor connected between the first node and the third node; an inductor connected between the second node and an output node, the output node providing an output voltage; a hybrid capacitor connected between the second node and a fourth node; a fifth transistor connected between the fourth node and the output node; a sixth transistor connected between the third node and the fourth node, and a body bias voltage applied to the sixth transistor is variable; as well as an output capacitor connected between the output node and the ground voltage, wherein the first transistor, the second transistor, the third transistor, the fourth transistor and the flying capacitor are configured to perform a three-level operation, wherein the inductor is included in a first path connected to the output node, wherein the hybrid capacitor is included in a second path connected to the output node, wherein the power supply device is configured to generate the output voltage using a dual path including the first path and the second path, and The power supply device is configured to selectively operate based on a four-phase scheme and a six-phase scheme based on a conversion rate obtained by dividing the output voltage by the input voltage.

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