Level conversion circuit and level conversion method

Abstract

The invention provides a level conversion circuit and a level conversion method, and belongs to the technical field of semiconductor integrated circuits. The circuit comprises a conversion module and a voltage supply module, when an input signal is a low level from a previous voltage domain, the voltage supply module can reduce a second power supply voltage by a certain threshold value, so that current can be completely cut off at the joint of the conversion module and the voltage supply module, and when the input signal is a high level from the previous voltage domain, the voltage supply module can reduce the second power supply voltage by a certain threshold value. The second power supply voltage from the voltage supply module can output a voltage converted into a signal suitable for a second voltage domain. And on a high-level voltage conversion output path, the number of the MOS tubes and the distance between the adjacent MOS tubes are controlled, so that the number of the MOS tubes can be greatly reduced, the layout is saved, the resistance is reduced, and the power consumption is reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit technology, and in particular to a level conversion circuit and a level conversion method having the circuit. Background Technology

[0002] A level shifter circuit is a circuit used to convert digital signals bidirectionally or unidirectionally between different voltage levels. Its core function is to adapt the high and low levels of an input signal to the target voltage domain while keeping the logic signals (0 / 1) unchanged. In other words, a level shifter circuit can convert a signal from one power supply voltage domain to another, facilitating signal processing within each respective voltage domain. In semiconductor integrated circuits, multiple power supply voltage domains often exist, and numerous level shifter circuits exist within each of these domains.

[0003] There are many existing level conversion circuit designs, for example, patent CN202011282717.1 mentions it in the background section and appendix. Figure 1 Traditional level-shifting circuits are simple in structure, but they have inherent drawbacks. Due to their low gate-source voltage and weak driving capability, they reduce the circuit's operating speed. To address this technical problem, patent CN202011282717.1 proposes a solution. Traditional level-shifting circuits also include... Figure 1 The circuit designs shown are numerous, but these solutions involve a large number of MOSFETs and interconnects, thus occupying a significant area. Current chip design prioritizes smaller dimensions, so these existing solutions result in low chip layout utilization and high power consumption. Furthermore, for high-level voltage conversion circuits, additional drivers are typically required to output high-voltage signals; otherwise, there will be excessive delays. However, adding too many drivers also leads to a large layout area and even higher power consumption. Summary of the Invention

[0004] The technical problem to be solved by this invention is to address the shortcomings of the prior art by providing a level conversion circuit, mainly used in driving sense amplifiers. By using an inverter as the conversion module and designing the connection between the power supply module and the conversion module, a level conversion circuit with high layout utilization and low power consumption is obtained. At the same time, the circuit itself can also serve as a driver, speeding up timing and saving drive power for the next stage circuit.

[0005] The technical solution adopted by the present invention to solve the above-mentioned technical problem is as follows: a level conversion circuit, comprising a conversion module and a voltage supply module, wherein the conversion module is configured to receive an input signal of a first voltage domain at the input terminal and provide an output signal suitable for a second voltage domain at the output terminal, wherein the first voltage domain has a first ground voltage and a first power supply voltage, characterized in that:

[0006] The conversion module also has a first port, and the power supply module is connected to the first port. The power supply module is configured to receive a second power supply voltage suitable for the second voltage domain and supply power to the conversion module through the first port. The second power supply voltage is higher than the first power supply voltage.

[0007] For the conversion module, when the input signal is low, the voltage of the signal is the first ground voltage Vss, and no conversion is needed to directly output the low-level signal provided at the output terminal, which is the second voltage domain. When the input signal is high, the voltage of the input signal is the first power supply voltage Vcc. After the voltage supply module is activated, the voltage of this signal will be converted into a second power supply voltage suitable for the second voltage domain before signal output. At this time, the output signal has the second power supply voltage and can adapt to the next higher voltage domain.

[0008] By using different inverters to receive the first and second power supply voltages respectively, the two different voltage values ​​can be effectively distinguished, preventing mutual interference between the two voltages that could lead to inaccurate input signals and avoiding signal crosstalk at the same receiving end, which could damage the receiver. Furthermore, the two inverters can form two drivers, reducing delay not only for this level conversion circuit but also for the next stage circuit. Directly receiving the second power supply voltage through the power supply module allows for better control of the second power supply voltage. Based on the input signal level, the power supply module can adjust the voltage value and output state of the second power supply voltage within a smaller space, while simultaneously reducing resistance and heat generation in the circuit. The output state referred to here is that when the input signal is low, the second power supply voltage is not used as the output signal's power supply voltage; when the input signal is high, the second power supply voltage serves as the high-level voltage for the output signal.

[0009] Preferably, in order to simplify the circuit without reducing the conversion rate, the conversion module includes a first inverter and a second inverter connected in series. The input terminal of the first inverter is the input terminal of the conversion module, and the output terminal of the second inverter is the output terminal of the conversion module.

[0010] The first port of the conversion module is located on the second inverter.

[0011] By setting the input terminal and the first port on the first inverter and the second inverter respectively, the mutual interference between different power supply voltage values ​​can be further reduced. Furthermore, by connecting the two inverters in series, two circuit modules with driving functions can be generated, which allows for the addition of another driving stage on top of the first stage, reducing circuit delay, ensuring signal strength in the circuit, and eliminating the need for external driving, thus simplifying the circuit, reducing power consumption, and lowering costs.

[0012] Preferably, the second power supply voltage is Viso, and the first power supply voltage is Vcc, characterized in that...

[0013] The voltage supply module includes a third PMOS transistor. The source of the third PMOS transistor is connected to the second power supply voltage, and the drain is connected to the first port. When the input signal is high, the gate of the third PMOS transistor is grounded. When the input signal is low, the gate and drain of the third PMOS transistor are connected. The threshold voltage of the third PMOS transistor is Vth. When the input signal is low, Vcc ≥ Viso - Vth is satisfied.

[0014] The threshold voltage referred to here is a characteristic of MOSFETs. The threshold voltage value can be measured, and the threshold voltage of the same type of MOSFET is the same. In addition, the threshold voltage is related to the size and type of MOSFET, and the threshold voltage value can also be adjusted during the design stage.

[0015] The voltage supply module also functions as a voltage regulator, allowing the second power supply voltage to be adjusted before entering the conversion module. When the input signal is low, the output signal voltage is ground, suitable for the second voltage domain, and no conversion is needed. The voltage supply module can reduce the value of the second power supply voltage. In fact, the second inverter includes a second PMOS transistor. The source of the second PMOS transistor is connected to the first port, the gate is connected to the output of the first inverter, and the drain is connected to the output of the conversion module. Therefore, under the condition that Vcc ≥ Viso - Vth, when the input signal is low, the second PMOS transistor is off, completely cutting off the current. At this time, the voltage supplied by the voltage supply module will not enter the conversion module, avoiding leakage. When both the gate and source voltages of the second PMOS transistor are high, leakage is reduced.

[0016] Furthermore, the voltage supply module also includes a third NMOS transistor, the gate and drain of which are respectively connected to the source and drain of the third NMOS transistor.

[0017] The connection method here is such that when the gate of the third PMOS transistor is connected to the drain of the third NMOS transistor, the drain of the third PMOS transistor is connected to the source of the third NMOS transistor; conversely, when the gate of the third PMOS transistor is connected to the source of the third NMOS transistor, the drain of the third PMOS transistor is connected to the drain of the third NMOS transistor. This configuration allows the third PMOS transistor to perform different functions depending on the operating state of the third NMOS transistor. When the third NMOS transistor is off, the third PMOS transistor can transmit the second power supply voltage to the second PMOS transistor in the conversion module as its source voltage. At this time, both the second and third PMOS transistors are turned on simultaneously, increasing the resistance and reducing the quiescent current and power consumption. When the third NMOS transistor is in the operating state, the gate and drain of the third PMOS transistor are connected, forming a diode-like structure. This allows the output voltage to be lower than the input second power supply voltage by a certain threshold, causing the second PMOS transistor to completely cut off the current.

[0018] Furthermore, the third NMOS transistor is a symmetrical transistor, and there is a connection line between the gate of the third PMOS transistor and the source or drain of the third NMOS transistor. The voltage supply module includes a fourth NMOS transistor, the source of which is grounded, the drain of which is connected to the connection line, and the gate of which receives the input signal; and / or,

[0019] The gate of the third NMOS transistor is connected to the output of the first inverter.

[0020] By making the third NMOS transistor a symmetrical transistor, its source and drain can be interchanged, allowing it to function differently in conjunction with the power supply module when different input voltage levels are applied. Furthermore, based on this setup, the operating state of the MOS transistor can be controlled by using the inverted voltage generated by the first power supply voltage as its gate voltage, eliminating the need for excessive additional voltage input and simplifying the circuit by utilizing the voltage generated within the circuit. The fourth NMOS transistor can control the operating state of the power supply module under different first power supply voltage values. Moreover, under the action of the fourth NMOS transistor, the gate of the third PMOS transistor is forcibly pulled low by the NMOS transistor, resulting in a larger voltage difference between the gate and source of the third PMOS transistor. This reduces the on-resistance, accelerates the rise time of the voltage rise edge, stabilizes the gate voltage of the third PMOS transistor, and further reduces leakage current.

[0021] Preferably, the voltage supply module includes a third PMOS transistor and a fourth PMOS transistor, characterized in that,

[0022] When the input signal is low, the third PMOS transistor is active and the fourth PMOS transistor is off; when the input signal is high, the third PMOS transistor is off and the fourth PMOS transistor is active; and / or,

[0023] The source voltages of the third PMOS transistor and the fourth PMOS transistor are both the second power supply voltage. The drain of the third PMOS transistor is connected to the gate of the fourth PMOS transistor. The gate of the third PMOS transistor is connected to the output terminal of the second inverter. The drain of the fourth PMOS transistor is connected to the second inverter.

[0024] With this setup, the negative feedback circuit, as part of the voltage supply module, can achieve the same effect as a diode, and the fourth PMOS transistor can completely cut off the current.

[0025] Further, the second inverter includes a second PMOS transistor and a second NMOS transistor. The gates of both the second PMOS transistor and the second NMOS transistor are connected to the output terminal of the first inverter. The source of the second PMOS transistor is connected to the first port, the source of the second NMOS transistor is grounded, and the drains of the second PMOS transistor and the drain of the second NMOS transistor are connected and connected to the output terminal of the conversion module; and / or,

[0026] The first inverter includes a first PMOS transistor and a first NMOS transistor. The input terminal is connected to the gate of the first PMOS transistor and the gate of the first NMOS transistor. The drain of the first PMOS transistor is connected to the drain of the first NMOS transistor. The source voltage of the first PMOS transistor is Vcc, and the source of the first NMOS transistor is grounded.

[0027] With this configuration, when the input signal is low, only two inverters are needed to output voltage, resulting in a simple structure. Furthermore, the voltage supply module only connects to the conversion module to perform level conversion when the input signal is high. The wiring is simple, and compared to existing technologies, there are no intersecting wires, thus avoiding potential short circuits between wires.

[0028] Preferably, the path from the receiving terminal I at the voltage supply module where the second power supply voltage is received to the output terminal O of the conversion module is the first path, the number of MOS transistors passing through the first path is n, and the distance between the two farthest adjacent MOS transistors on the path is d, satisfying d*(n-1)≤0.20μm, where n is a positive integer greater than or equal to 2.

[0029] The ultimate goal of this level conversion circuit is to output a higher voltage level, which can be called the target voltage. Therefore, in this level conversion circuit, the fewer MOSFETs the target voltage source point passes through to the final output terminal without affecting the conversion rate, conversion signal strength, and conversion accuracy, the better. This can save costs, reduce power consumption, and reduce the impact of coupling capacitance. The distance between adjacent MOSFETs should also be as short as possible, which can save more layout area, reduce chip size, reduce circuit resistance, reduce quiescent current, and thus reduce power consumption.

[0030] Furthermore, in the direction of supplying voltage from the voltage supply module to the conversion module, the number of wires connecting the voltage supply module and the conversion module is m, satisfying m≤1; and / or,

[0031] The level conversion circuit has only one receiving terminal for receiving the second power supply voltage.

[0032] This setup more intuitively demonstrates the simplicity of the winding in the level conversion circuit. Minimizing the number of wires reduces circuit resistance, heat generation, and power consumption. Using only one second power supply voltage reduces voltage division, saving energy and power consumption.

[0033] The second technical solution of the present invention to solve the above-mentioned technical problem is: a level conversion method, characterized in that,

[0034] An input signal suitable for a first voltage domain is input to the input terminal of the conversion module. The first voltage domain has a first ground voltage Vss and a first power supply voltage Vcc.

[0035] The voltage supply module is configured to receive a second power supply voltage Viso suitable for the second voltage domain, and the voltage supply module provides the power supply voltage to the conversion module through a first port.

[0036] The conversion module outputs a signal to the second voltage domain.

[0037] The voltage supply module provides the second power supply voltage Viso to the conversion module in the first state, and steps down the second power supply voltage Viso in the second state.

[0038] This configuration allows the pressure supply module to perform different functions under different conditions.

[0039] The conversion module includes a first inverter and a second inverter, the first inverter and the second inverter are connected in series, and the input terminal of the conversion module is connected to the first inverter. The characteristic of this module is that...

[0040] The source voltage of the third PMOS transistor in the power supply module is the second power supply voltage Viso, and the second power supply voltage Viso is transmitted to the second inverter through the drain of the third PMOS transistor.

[0041] The gate and drain of the third PMOS transistor are connected, and a third NMOS transistor is disposed between the gate and drain. The output voltage of the first inverter is used as the gate voltage of the third NMOS transistor.

[0042] The gate of the third PMOS transistor and the third NMOS transistor are connected by a connection line. The voltage supply module includes a fourth NMOS transistor. The gate of the fourth NMOS transistor receives the input signal. When the gate is turned on, the ground voltage connected to the source of the fourth NMOS transistor is transmitted to the drain.

[0043] Compared with the prior art, the advantages of the present invention are as follows: On the one hand, by connecting the voltage supply module to the first port of the conversion module, mutual interference between different power supply voltages is avoided, and different functions can be achieved by the voltage supply module under different first power supply voltage input values. When high-level voltage conversion is not required, the voltage supply module can reduce the second power supply voltage value, thereby completely cutting off current at the connection between the conversion module and the voltage supply module and preventing leakage. On the other hand, by limiting the number of MOSFETs on the voltage conversion path and the distance between adjacent MOSFETs, the area occupied by the level conversion circuit on the layout can be effectively reduced, and power consumption can also be reduced. Attached Figure Description

[0044] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of these embodiments. In these drawings, similar reference numerals are used to denote similar elements. The drawings described below are some embodiments of the present disclosure, but not all embodiments. Other drawings will be readily available to those skilled in the art based on these drawings without inventive effort.

[0045] Figure 1 A schematic diagram of a traditional level conversion circuit is shown.

[0046] Figure 2 A basic schematic diagram of a level conversion scheme according to an embodiment of the present invention is shown;

[0047] Figure 3 A schematic diagram of a level conversion circuit according to an embodiment of the present invention is shown;

[0048] Figure 4A schematic diagram of a level conversion circuit according to another embodiment of the present invention is shown;

[0049] Figure 5 A schematic diagram of the voltage regulation structure in the voltage supply module of a level conversion circuit according to an embodiment of the present invention is shown;

[0050] Figure 6 A schematic diagram of signal timing variation according to an embodiment of the present invention is shown;

[0051] Figure 7 A schematic diagram of a level conversion circuit including different conversion modules is shown in one embodiment of the present invention;

[0052] Figure 8 This diagram illustrates a schematic of a level conversion circuit according to an embodiment of the present invention, showing the shared source and drain of adjacent MOS transistors on the first path.

[0053] Figure 9 A schematic diagram of the level conversion method steps according to an embodiment of the present invention is shown. Detailed Implementation

[0054] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below with reference to the accompanying drawings. It should be understood that these descriptions are merely exemplary and not intended to limit the scope of the invention. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other. Furthermore, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily obscuring the concepts of the invention.

[0055] This application discusses certain specific configurations and arrangements, but it should be understood that these are for illustrative purposes only. Therefore, other configurations and arrangements can be used without departing from the scope of this disclosure. Furthermore, this disclosure can be used in a variety of other applications. The functional and structural features described in this disclosure can be combined, adjusted, and modified, and can be combined, adjusted, and modified in ways not specifically described in the figures, but such combinations, adjustments, and modifications are all within the scope of this disclosure.

[0056] Generally, the understanding of terms depends at least in part on their context. For example, the term "one or more" as used herein, depending at least in part on the context, can be used to describe any feature, structure, or characteristic in the singular or in the plural form to describe a combination of features, structures, or characteristics. Similarly, terms such as "a," "an," or "the" can also be understood to express either a singular or plural usage, depending at least in part on the context. Furthermore, the word "based on" can be understood to not necessarily be intended to express an exclusive set of factors, but rather to allow for the presence of other factors that may not be explicitly described; again, this depends at least in part on the context.

[0057] It should be readily understood that the meanings of “on,” “above,” and “above” in this disclosure should be interpreted in the broadest manner, such that “on” means not only “directly on” something, but also includes the meaning of something “on” with an intermediate feature or layer in between, and that “above” or “above” means not only “on top of” or “above” something, but also includes the meaning of “on” or “above” something without any intermediate feature or layer (directly on) in between.

[0058] In addition, for ease of description, this document may use spatially relative terms such as “below,” “under,” “down,” “above,” and “up” to describe the relationship between one element or feature shown in the figure and another. These spatially relative terms are intended to cover different orientations of the device during use or operation other than those shown in the figure. The device may be in other orientations (rotated 90 degrees or other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0059] In some embodiments, the voltage level when the word line is active is a first voltage level, and the voltage level when the signal is inactive is a second voltage level, where the first voltage level is greater than the second voltage level. For example, a signal active is represented by a high voltage level, and an inactive signal is represented by a low voltage level. In the above descriptions of high and low voltage levels, a high voltage level can be a voltage level greater than or equal to the power supply voltage, and a low voltage level can be a voltage level less than or equal to the ground voltage. Moreover, high and low voltage levels are relative, and the specific voltage ranges included in high and low voltage levels can be determined according to the specific device. For example, for an NMOS transistor, a high voltage level refers to the range of gate voltage levels that enable the NMOS transistor to conduct, and a low voltage level refers to the range of gate voltage levels that enable the NMOS transistor to turn off; for a PMOS transistor, a low voltage level refers to the range of gate voltage levels that enable the PMOS transistor to conduct, and a high voltage level refers to the range of gate voltage levels that enable the PMOS transistor to turn off.

[0060] In this application, the source and drain of two adjacent PMOS transistors or two adjacent NMOS transistors can be shared or connected by wires. That is, the source and source, drain and drain, or source and drain of adjacent PMOS transistors can be shared or connected by wires; the same applies to adjacent NMOS transistors.

[0061] Example 1

[0062] First, the basic principle of this level conversion circuit will be explained, such as... Figure 2 The diagram shown illustrates the basic principle of the level conversion scheme in this embodiment. The level conversion circuit includes an input terminal In, where the input signal comes from the previous voltage domain and has a first power supply voltage Vcc and a first ground voltage Vss. It also includes a second power supply voltage Viso suitable for the next voltage domain, an output terminal Out for the converted signal, and two inverters, a first inverter A and a second inverter B, connected in series. The input terminal In is connected to the first inverter A, the first inverter A and the second inverter B are connected in series, and the second inverter B is connected to the signal output terminal Out. Specifically, the first inverter A includes a first PMOS transistor P1 and a first NMOS transistor N1, and the second inverter B includes a second PMOS transistor P2 and a second NMOS transistor N2. The input terminal In is connected to the gates of the first PMOS transistor P1 and the first NMOS transistor N1 for signal transmission. The source voltage of the first PMOS transistor P1 is the first power supply voltage Vcc. The source of the first NMOS transistor N1 is grounded, i.e., connected to the ground voltage Vss. The drains of the first PMOS transistor P1 and the first NMOS transistor N1 are connected, and an inverted signal InN is output at any point on the drain connection line. The input terminal of the output inverted signal InN is connected to the second inverter B, specifically, the input terminal of the inverted signal InN is connected to the gates of the second PMOS transistor P2 and the second NMOS transistor N2, used to input signals to the second inverter. The source of the second PMOS transistor P2 can receive the second power supply voltage Viso. The source of the second NMOS transistor N2 is grounded, i.e., connected to the ground voltage Vss. The drains of the second PMOS transistor P2 and the second NMOS transistor N2 are connected, and the output terminal Out can be connected at any point on the drain connection line.

[0063] Compared with traditional level conversion circuits, the level conversion circuit of this invention has two series-connected inverters connected to the input terminal, resulting in a simple circuit connection structure. At the same time, the inverters also serve as drivers in the circuit, reducing the delay in this circuit. They can also be used as drivers for the next stage circuit, reducing the number of drivers in the next stage circuit, lowering costs, and reducing power consumption.

[0064] In this embodiment, as Figure 3As shown, based on the basic principle, a third PMOS transistor P3, a third NMOS transistor N3, and a fourth NMOS transistor N4 are added. The third NMOS transistor N3 is a low-threshold (Vth) NMOS transistor and is a symmetrical transistor, with the higher voltage terminal serving as the source. The source voltage of the third PMOS transistor P3 is the high-level second power supply voltage Viso, and the drain and gate of the third PMOS transistor P3 can be connected. The gate of the fourth NMOS transistor N4 is connected to the input terminal In, its source is grounded, and its drain is connected to the gate of the third PMOS transistor P3.

[0065] In this embodiment, the drain and gate of the third PMOS transistor P3 are connected through the third NMOS transistor N3. The gate of the third NMOS transistor N3 receives an inverted voltage signal InN, and its source or drain is connected to the drain of the third PMOS transistor P3, while its drain or source is connected to the gate of the third PMOS transistor P3. The drain of the fourth NMOS transistor N4 is also connected to the drain or source of the third NMOS transistor N3. When the input signal is low, the gate voltage of the third NMOS transistor N3 is an inverted voltage, with a voltage value VinN = Vcc, and it is in the working state. At this time, the drain and gate of the third PMOS transistor P3 are connected, forming an approximately diode-like connection structure. This configuration ensures that the drain voltage of the third PMOS transistor P3 is lower than the threshold voltage Vth compared to the higher voltage of the second power supply voltage Viso, where Vth ≤ Vcc.

[0066] In this embodiment, the drain of the third PMOS transistor P3 is also connected to the source of the second PMOS transistor P2. This connection can be made via a wire, or the drain of the third PMOS transistor P3 and the source of the second PMOS transistor P2 can be shared. This configuration allows the second inverter B to receive a high-level voltage suitable for another voltage domain, thus achieving a high-level voltage conversion output.

[0067] This embodiment uses a total of 7 MOSFETs to achieve level conversion, which greatly reduces the number of MOSFETs compared to traditional level conversion circuits with the same conversion effect, without affecting the conversion rate, signal strength, etc. It can save layout space, reduce costs, reduce power consumption and heat dissipation.

[0068] Example 2

[0069] Regarding the above embodiments, the connection between the third PMOS transistor and the third NMOS transistor can be replaced with other structures and connection methods that have equivalent effects. For example, a negative feedback circuit can be used, such as... Figure 4As shown, the input terminal In, the first inverter A, the second inverter B, and the final signal output terminal Out of the level conversion circuit remain unchanged. The gate of the third NMOS transistor N3 is connected to the input terminal In, the source is grounded, and the drain is connected to the drain of the third PMOS transistor P3. At the same time, the drain of the third NMOS transistor N3 is also connected to the gate of the fourth PMOS transistor P4. The source voltages of the third PMOS transistor P3 and the fourth PMOS transistor P4 are both the second power supply voltage Viso. The drain of the fourth PMOS transistor P4 is connected to the source of the second PMOS transistor P2 in the second inverter B. The gate of the third PMOS transistor P3 is connected to the signal output terminal Out of the level conversion circuit.

[0070] When the input signal is low, the first inverter outputs an inverted voltage VinN = Vcc. At this time, the second NMOS transistor N2 of the second inverter is in the working state, transmitting the source-to-ground voltage Vss to the signal output terminal Out of the level conversion circuit. At this time, the gate of the third PMOS transistor P3 connected to the signal output terminal Out is turned on, and the second power supply voltage Viso is transmitted from the source to the drain of the third PMOS transistor P3. Since Vin = Vss, the third NMOS transistor N3 is in the non-working state at this time. At this time, the gate voltage of the fourth PMOS transistor P4 is Viso, and the source voltage is also Viso. Therefore, the current is completely cut off at the fourth PMOS transistor P4. Therefore, the output voltage of the signal output terminal Out of the level conversion circuit is Vss.

[0071] When the input signal is high, the first inverter A outputs an inverted voltage VinN = Vss. At this time, the second NMOS transistor N2 is off, the second PMOS transistor P2 is on, and the third NMOS transistor N3 is also on. Therefore, the ground voltage Vss is transmitted to the gate of the fourth PMOS transistor P4, making the fourth PMOS transistor P4 operational. This allows the second power supply voltage Viso from the source to the drain. At this time, the source voltage of the second PMOS transistor P2 is Viso, and the gate voltage is Vss. Therefore, the second power supply voltage Viso is ultimately transmitted as the conversion voltage from the signal output terminal Out. When the voltage at the signal output terminal Out is Viso, the gate voltage of the third PMOS transistor P3 is Viso, and the source voltage of the third PMOS transistor P3 is also Viso. Therefore, the third PMOS transistor P3 is in a non-operating state, completely cutting off current and not generating leakage voltage. Thus, it does not affect the gate voltage of the fourth PMOS transistor P4 at this time.

[0072] Example 3

[0073] Regarding the above embodiment 1, in conjunction with the appendix Figure 3When the input signal is high, the voltage of the input signal is the first power supply voltage Vcc. After passing through the first inverter A, the inverted voltage VinN = Vss is obtained. At this time, the second PMOS transistor P2 is turned on, the second NMOS transistor N2 is turned off, the third NMOS transistor N3 is disconnected, and the fourth NMOS transistor N4 is in the working state. Then, the gate of the third PMOS transistor P3 is connected to the ground voltage Vss and turned on. The second PMOS transistor P2 and the third PMOS transistor P3 are turned on at the same time, pulling the signal output terminal Out to the high level of the second power supply voltage Viso.

[0074] like Figure 5 The dashed box in the diagram refers to the voltage regulation structure in the power supply module. When the input signal is low, the input signal voltage is the first ground voltage Vss. After passing through the first inverter A, the inverted voltage VinN = Vcc is obtained. At this time, the third NMOS transistor N3 is turned on, the fourth NMOS transistor N4 is turned off, and the drain and gate of the third PMOS transistor P3 are connected, forming an approximate diode structure. This causes the drain voltage of the third PMOS transistor P3 to decrease from the high-level second power supply voltage Viso to the threshold voltage Vth, where Vth ≤ Vcc. At this time, the gate voltage of the second PMOS transistor P2 is the first power supply voltage Vcc. Therefore, the second PMOS transistor P2 can completely cut off the current with the gate voltage Vcc. When both the gate voltage and the source voltage are high, leakage current is reduced. Meanwhile, the second NMOS transistor N2 is in the working state and can output the ground voltage Vss to the signal output terminal Out.

[0075] In this embodiment, when the input signal is low, the second PMOS transistor P2 can completely cut off the current, avoiding the voltage division problem caused by the voltage at the source of the second PMOS transistor P2 at the output terminal Out of the entire circuit. When the input signal is high, the second PMOS transistor P2 and the third PMOS transistor P3 are turned on simultaneously, thus increasing the resistance, reducing the quiescent current and power consumption. At the same time, under the action of the fourth NMOS transistor N4, the gate of the third PMOS transistor P3 is forcibly pulled low by the fourth NMOS transistor N4, and the voltage difference VGS between the gate and source of the third PMOS transistor P3 is larger, thereby reducing the on-resistance, increasing the rise time, stabilizing the gate voltage of the third PMOS transistor P3, and further reducing the leakage current.

[0076] like Figure 6The signal timing diagram shown illustrates the following: the signal between the drain of the fourth NMOS transistor N4 and the gate of the third PMOS transistor P3 is net1; the signal between the drain of the third PMOS transistor P3 and the source of the third NMOS transistor N3 is net2; the input signal is In; and the output signal is Out. The lowest voltage in the first voltage domain is the first ground voltage Vss, and the highest voltage is the first power supply voltage Vcc. After passing through the level conversion circuit, these voltages are converted to a voltage suitable for the second voltage domain. The second power supply voltage is Viso, which is suitable for the second voltage domain. In the first inverter A, the source voltage of the first PMOS transistor P1 is Vcc, and the ground voltage is Vss. The voltage at net1 is inversely proportional to the voltage at the input terminal In. The voltage at net2 is always the second power supply voltage Viso. After passing through the level conversion circuit, the final output signal voltage is either Viso or Vss.

[0077] Example 4

[0078] Compared with the prior art, the solution of this embodiment can reduce the number of transistors, thereby saving the area occupied by the level conversion circuit on the chip, and achieving the effect of quickly converting high-level voltage.

[0079] In this embodiment, as Figure 7 As shown, the level conversion circuit includes a conversion module M1 and a voltage supply module M2. Conversion module M1 includes an input terminal, a first port, a first inverter A, a second inverter B, and a signal output terminal Out after voltage conversion. The input terminal is connected to the first inverter A and receives the input signal from a first voltage domain. The first voltage domain has a first ground voltage Vss and a first power supply voltage Vcc. The first inverter A outputs an inverted voltage VinN with a value of either Vcc or Vss. When the input signal is low, the inverted voltage VinN output by the first inverter A is Vcc; when the input signal is high, the inverted voltage VinN output by the first inverter A is Vss. The inverted voltage VinN can be used as the input signal voltage of the second inverter B, or as the input signal voltage of other parts of the circuit. This configuration increases the types of signals, thereby enabling more diverse functions. For example, the inverted signal can be used to control the operating state of a MOS transistor.

[0080] The first inverter A and the second inverter B are connected in series, that is, the output of the first inverter A is used as the input of the second inverter B. The signal output by the second inverter B has a first ground voltage Vss or a second power supply voltage Viso. The second power supply voltage Viso is a high-level voltage. The power supply module M2 receives the second power supply voltage Viso and can provide power supply voltage to the conversion module M1 through the first port of the second inverter B. Finally, it provides a suitable power supply voltage to the second voltage domain through the output terminal Out.

[0081] In this embodiment, the second power supply voltage Viso is higher than the first power supply voltage Vcc, thereby achieving the conversion from low level to high level.

[0082] The voltage supply module M2 also has a voltage regulation function. It receives the second power supply voltage Viso and connects to the first port, which is located on the second inverter B of the conversion module M1. Specifically, the voltage supply module M2 is connected to the source of the second PMOS transistor P2 of the second inverter B. The voltage supply module M2 includes a third PMOS transistor P3 and a third NMOS transistor N3. The third NMOS transistor N3 is a symmetrical transistor, with the higher voltage end serving as its source. The second power supply voltage Viso is the source voltage of the third PMOS transistor P3. The drain of the third PMOS transistor P3 is connected to the source of the second PMOS transistor P2, and the drain of the third PMOS transistor P3 is also connected to either the source or drain of the third NMOS transistor N3. The drain or source of the third NMOS transistor N3 is connected to the gate of the third PMOS transistor P3, and the gate voltage of the third NMOS transistor N3 is the inverted voltage VinN. With this setup, when the inverting voltage VinN is Vcc, the third NMOS transistor N3 is in operation. At this time, the gate and drain of the third PMOS transistor P3 are connected, forming an approximate diode structure. The second power supply voltage Viso is reduced by a certain threshold value Vth after passing through the third PMOS transistor P3. Meanwhile, the gate voltage of the second PMOS transistor P2 is also the inverting voltage VinN, so the gate voltage of the second PMOS transistor P2 is Vcc. Its source voltage is the voltage after the second power supply voltage Viso is reduced by a certain value through the voltage regulation of the voltage supply module M2, i.e., Viso - Vth ≤ Vcc. Under these conditions, the second PMOS transistor P2 can completely cut off the current using the gate voltage Vcc, and there will be no leakage voltage phenomenon. When the value of the inverting voltage VinN is Vcc, that is, when the input signal is "0", the second PMOS transistor P2 in the second inverter B cuts off the current, the source of the second NMOS transistor N2 is grounded, and it is turned on because the gate voltage is the inverting voltage VinN. Therefore, the voltage output by the level conversion circuit is the first ground voltage Vss.

[0083] The voltage supply module M2 also includes a fourth NMOS transistor N4. The drain of the fourth NMOS transistor N4 is connected to the gate of the third PMOS transistor P3 and the third NMOS transistor N3 via a wire. The drain of the fourth NMOS transistor N4 can also share the source or drain of the third NMOS transistor N3. This saves source and drain resources, reduces circuit size, and avoids problems caused by short circuits or disconnections in the wires. The source of the fourth NMOS transistor N4 is grounded, and its gate is connected to the signal input terminal In. When the input signal is "1", the gate voltage of the fourth NMOS transistor N4 is Vcc, and it is in the working state. Its source voltage Vss is transmitted to the gate of the third PMOS transistor P3, and the third PMOS transistor P3 is in the working state. Since the inverted voltage VinN obtained after passing through the first inverter A of the conversion module M1 is Vss, the gate voltage of the third NMOS transistor N3 is Vss, and the third NMOS transistor N3 is in the off state. At this time, the second power supply voltage Viso flows from the source to the drain of the third PMOS transistor P3 and reaches the source of the second PMOS transistor P2. Meanwhile, the gate voltage of the second PMOS transistor P2 in the second inverter B is the inverted voltage Vss, so the second PMOS transistor P2 is in the working state, and the signal output from the drain has the second power supply voltage Viso. However, the second NMOS transistor N2 is in the non-working state. Therefore, the voltage of the signal finally output by the level conversion circuit is the second power supply voltage Viso. Under the action of the fourth NMOS transistor N4, the gate of the third PMOS transistor P3 is forced to be pulled low. The voltage difference between the gate and source of the third PMOS transistor P3 is larger, which can reduce the on-resistance and increase the rise time. The gate voltage of the third PMOS transistor P3 is stable, which can reduce the leakage current.

[0084] When the input signal is high, the second PMOS transistor P2 and the third PMOS transistor P3 are turned on simultaneously, which increases the resistance, thereby reducing the quiescent current and power consumption.

[0085] The approximate diode structure composed of the third PMOS transistor P3 and the third NMOS transistor N3 in the voltage supply module of this embodiment can be replaced by the scheme of embodiment 2, or the third NMOS transistor N3 can be replaced by a conventional switch, or the same effect can be achieved by combining a switch and a diode. This description and similar structures composed of the third PMOS transistor P3 and the third NMOS transistor N3 are all within the protection scope of this application.

[0086] Example 5

[0087] refer to Figure 7In this embodiment, the voltage supply module M2 has a receiving terminal I for receiving the second power supply voltage Viso. The second power supply voltage Viso can supply power to the conversion module M1 through the voltage supply module M2. Finally, the voltage of the signal output by the output terminal O of the conversion module M1 is the converted voltage. The path that the second power supply voltage Viso travels from the receiving terminal I to the output terminal O is the first path. The first path includes transistors and / or wires. The number of transistors included in the first path is n. On the first path, no two adjacent transistors will completely overlap, that is, there is a distance between any two adjacent transistors. The distance between the two farthest adjacent transistors is d, which satisfies d*(n-1)≤0.20μm, where n is a positive integer greater than or equal to 2. Further, it satisfies 0.07μm≤d*(n-1)≤0.14μm. Here, "adjacent" means that there is no third transistor between the two transistors. When two adjacent transistors do not share a common source and drain, or a common source and a common drain, the distance here refers to the distance between the farthest points of the two adjacent transistors. For example, if transistors P3 and P2 are adjacent, and the farthest point on transistor P3 from transistor P2 is 'a', and the farthest point on transistor P2 from transistor P3 is 'b', then the distance 'd' from transistor P3 to transistor P2 is the distance from point a to point b. When two adjacent transistors are independent and do not share a common source or drain, their gates are usually parallel. Figure 8 As shown, the distance here refers to the minimum distance between the two gates.

[0088] like Figure 8 The diagram illustrates two adjacent transistors sharing a source and / or drain. When the source and drain are shared, the source 1 of the first transistor is independent, the shared portion 2 is the drain of the first transistor and the source of the second transistor, and the drain 3 of the second transistor is also independent. The distance d between the first and second transistors is shown in the diagram. Alternatively, the drain 1 of the first transistor is independent, the shared portion 2 is the source of the first transistor and the drain of the second transistor, and the source 3 of the second transistor is also independent. The distance d between the first and second transistors is shown in the diagram. When the source is shared, the shared portion 2 is the source of the first transistor and the source of the second transistor, and the drains 1 and 3 of the first transistor are independent. The distance d between the first and second transistors is shown in the diagram. When the drain is shared, the shared portion 2 is the drain of the first transistor and the drain of the second transistor, and the sources 1 and 3 of the first transistor are independent. The distance d between the first and second transistors is shown in the diagram. A dummy PG 5 is provided around the gate and periphery of the transistors as a filler or auxiliary structure related to the peripheral gate.

[0089] The smaller the distance between transistors, the less space they occupy on the chip, which helps save space. On the other hand, it can reduce resistance, speed up timing, reduce buffering, reduce power consumption, and also reduce costs.

[0090] The voltage supply module M2 is connected to the conversion module M1 to convert the second power supply voltage Viso. In the direction from the voltage supply module M2 to the conversion module M1, the number of wires connecting the two modules is m, satisfying m ≤ 1. In this direction, the number of wires can be 1 or 0. When the number is 0, the drain of the third PMOS transistor P3 and the source of the second PMOS transistor P2 share the same terminal. This configuration simplifies the wiring between the voltage supply module M2 and the conversion module M1, eliminating intersecting wires compared to existing technologies. This reduces resistance and power consumption, and the simpler connection method effectively reduces interference between functional modules. The level conversion circuit has only one receiving terminal for the second power supply voltage; therefore, it only needs to be connected to one input port with the second power supply voltage Viso, saving resources.

[0091] Example 6

[0092] In this embodiment, the level conversion circuit is applied to the driving of the sense amplifier of the DRAM chip. The prior art includes applying the level conversion circuit in the semiconductor circuit, but multiple driving stages need to be added after the level conversion circuit. The solution in this application can combine the level conversion circuit and the driver, reduce the number of drivers, thereby saving layout area and reducing costs. The level conversion circuit in the foregoing embodiment can be used as part of the next stage circuit. The level conversion circuit includes an input terminal In, a first-stage driver, a second-stage driver, and a signal output terminal Out. The first-stage driver is a first inverter A, with the input terminal serving as the input of the first inverter A. The output of the first inverter A serves as the input of the second-stage driver. The second-stage driver includes a second inverter B, a third NMOS transistor N3, and a third PMOS transistor P3. The second inverter B is connected to the first inverter A. The drain of the third PMOS transistor P3 is connected to the source of the PMOS transistor P2 in the second inverter. The source of the third NMOS transistor N3 is connected to the drain of the third PMOS transistor P3. The drain of the third NMOS transistor N3 is connected to the gate of the third PMOS transistor P3. The second inverter B of the second-stage driver is connected to the signal output terminal Out.

[0093] In the prior art, additional drivers are required in the circuits adjacent to the level conversion circuit. However, the level conversion circuit in this application has two driving stages, which can reduce the number of drivers in the level conversion circuit and the next stage circuit.

[0094] Example 7

[0095] refer to Figure 9 This embodiment is a level conversion method. Based on embodiments one to six, in step S1, an input signal suitable for the first voltage domain is input to the input terminal of the conversion module. The first voltage domain has a first ground voltage Vss and a first power supply voltage Vcc.

[0096] Next, in step S2, the power supply module is configured to receive a second power supply voltage Viso suitable for the second voltage domain.

[0097] Then in step S3, the power supply module provides power supply voltage to the conversion module through the first port;

[0098] Finally, in step S4, the conversion module outputs a signal to the second voltage domain.

[0099] Specifically, in step S3, the voltage supply module provides the second power supply voltage Viso to the conversion module in the first state, and in the second state, the second power supply voltage Viso is stepped down.

[0100] Specifically, when the input signal is low, the voltage of the output signal of the level conversion circuit is Vout = Vss;

[0101] When the input signal is high, the voltage of the output signal of the level conversion circuit is Vout = Viso, where Viso is the second power supply voltage.

[0102] In the above embodiments, the second power supply voltage is greater than the first power supply voltage.

[0103] The conversion module M1 includes a first inverter A and a second inverter B. The first inverter A and the second inverter B are connected in series. The input terminal of the conversion module M1 is connected to the first inverter A to input the signal from the previous voltage domain.

[0104] The source voltage of the first PMOS transistor P1 of the first inverter A is Vcc, and the source of the first NMOS transistor N1 is grounded. The drains of the first PMOS transistor P1 and the first NMOS transistor N1 are connected to output an inverted voltage VinN. The inverted voltage VinN serves as the input signal voltage of the second inverter B and can control the operating state of the second PMOS transistor P2 and the second NMOS transistor N2. The source of the second NMOS transistor N2 is grounded, and the source of the second PMOS transistor P2 is connected to the voltage supply module M2. The drains of the second PMOS transistor P2 and the second NMOS transistor N2 are connected to serve as the signal output terminal Out of the level conversion circuit.

[0105] The source voltage of the third PMOS transistor P3 in the power supply module M2 is the second power supply voltage Viso. The second power supply voltage Viso supplies power to the second inverter B through the drain of the third PMOS transistor P3.

[0106] The gate and drain of the third PMOS transistor P3 are connected, and a third NMOS transistor N3 is placed between the gate and drain. The inverted voltage VinN output by the first inverter A is used as the gate voltage of the third NMOS transistor N3.

[0107] The third NMOS transistor N3 is a symmetrical transistor, with the end that has a higher voltage at the connection between the source and drain being the source.

[0108] There is a connection line between the gate of the third PMOS transistor P3 and the third NMOS transistor N3. The voltage supply module M2 includes a fourth NMOS transistor N4. The first power supply voltage Vin serves as the gate voltage of the fourth NMOS transistor N4. When the gate is turned on, the ground voltage Vss connected to the source of the fourth NMOS transistor N4 is transmitted to the drain and continues to serve as the gate voltage input of the third PMOS transistor P3 and the source voltage input of the third NMOS transistor N3.

[0109] In practical applications, the circuits provided in embodiments one through seven above can be applied to various types of memory. As an example, they can be applied to, but are not limited to, dynamic random access memory (DRAM) and static random access memory (SRAM). Exemplarily, DRAM includes, but is not limited to, any one of various generations of Double Data Rate Memory (DDR) and various generations of Low Power Double Data Rate Synchronous Dynamic Random Access Memory (LPDDR), etc., without specific limitations.

Claims

1. A level conversion circuit, comprising a conversion module and a voltage supply module, the conversion module being configured to receive an input signal of a first voltage domain at an input terminal and provide an output signal suitable for a second voltage domain at an output terminal, the first voltage domain having a first ground voltage Vss and a first power supply voltage Vcc, characterized in that: The conversion module also has a first port, and the voltage supply module is connected to the first port. The voltage supply module is configured to receive a second power supply voltage Viso suitable for the second voltage domain and provide a power supply voltage to the conversion module through the first port. The second power supply voltage Viso is higher than the first power supply voltage Vcc. When the input signal is low, the voltage at the first port is less than or equal to the first power supply voltage Vcc, and the output signal provided at the output terminal is a low-level signal in the second voltage domain. When the input signal is high, the voltage at the first port is the second power supply voltage Viso, and the output signal provided at the output terminal is the second power supply voltage Viso.

2. The level conversion circuit according to claim 1, wherein the conversion module includes a first inverter and a second inverter, the first inverter and the second inverter are connected in series, the input terminal of the first inverter is the input terminal of the conversion module, and the output terminal of the second inverter is the output terminal of the conversion module, characterized in that, The first port of the conversion module is located on the second inverter.

3. The level conversion circuit according to claim 2, characterized in that, The voltage supply module includes a third PMOS transistor. The source of the third PMOS transistor is connected to the second power supply voltage, and the drain is connected to the first port. When the input signal is high, the gate of the third PMOS transistor is grounded. When the input signal is low, the gate and drain of the third PMOS transistor are connected. The threshold voltage of the third PMOS transistor is Vth. When the input signal is low, Vcc ≥ Viso - Vth is satisfied.

4. The level conversion circuit according to claim 3, characterized in that, The voltage supply module also includes a third NMOS transistor, the gate and drain of which are connected to the source and drain of the third NMOS transistor, respectively.

5. The level conversion circuit according to claim 4, characterized in that, The gate of the third PMOS transistor is connected to the source or drain of the third NMOS transistor. The voltage supply module further includes a fourth NMOS transistor, the source of which is grounded, the drain of which is connected to the connection line, and the gate of which receives the input signal; and / or, The gate of the third NMOS transistor is connected to the output of the first inverter.

6. The level conversion circuit according to claim 2, wherein the voltage supply module comprises a third PMOS transistor and a fourth PMOS transistor, characterized in that, When the input signal is low, the third PMOS transistor is active and the fourth PMOS transistor is off; when the input signal is high, the third PMOS transistor is off and the fourth PMOS transistor is active; and / or, The source voltages of the third PMOS transistor and the fourth PMOS transistor are both the second power supply voltage. The drain of the third PMOS transistor is connected to the gate of the fourth PMOS transistor. The gate of the third PMOS transistor is connected to the output terminal of the second inverter. The drain of the fourth PMOS transistor is connected to the second inverter.

7. The level conversion circuit according to claim 2, characterized in that, The second inverter includes a second PMOS transistor and a second NMOS transistor. The gates of both the second PMOS transistor and the second NMOS transistor are connected to the output of the first inverter. The source of the second PMOS transistor is connected to the first port, the source of the second NMOS transistor is grounded, and the drains of the second PMOS transistor and the second NMOS transistor are connected together and connected to the output of the conversion module; and / or, The first inverter includes a first PMOS transistor and a first NMOS transistor. The input terminal is connected to the gate of the first PMOS transistor and the gate of the first NMOS transistor. The drain of the first PMOS transistor is connected to the drain of the first NMOS transistor. The source of the first PMOS transistor is connected to the first power supply voltage Vcc. The source of the first NMOS transistor is grounded.

8. The level conversion circuit according to any one of claims 1-7, characterized in that, The path from the receiving terminal I at the voltage supply module where the second power supply voltage is received to the output terminal O of the conversion module is the first path. The number of MOS transistors passing through the first path is n. The distance between the two farthest adjacent MOS transistors on the path is d, which satisfies d*(n-1)≤0.20μm, where n is a positive integer greater than or equal to 2.

9. The level conversion circuit according to claim 8, characterized in that, In the direction of supplying voltage from the voltage supply module to the conversion module, the number of wires connecting the voltage supply module and the conversion module is m, satisfying m≤1; and / or, The level conversion circuit has only one receiving terminal for receiving the second power supply voltage.

10. A level conversion method, characterized in that, An input signal suitable for a first voltage domain is input to the input terminal of the conversion module. The first voltage domain has a first ground voltage Vss and a first power supply voltage Vcc. The voltage supply module is configured to receive a second power supply voltage Viso suitable for the second voltage domain, and the voltage supply module provides the power supply voltage to the conversion module through a first port. The conversion module outputs a signal to the second voltage domain. The voltage supply module provides the second power supply voltage Viso to the conversion module in the first state, and steps down the second power supply voltage Viso in the second state.

11. The level conversion method according to claim 10, wherein the conversion module includes a first inverter and a second inverter, the first inverter and the second inverter are connected in series, and the input terminal of the conversion module is connected to the first inverter, characterized in that, The source voltage of the third PMOS transistor in the power supply module is the second power supply voltage Viso, and the second power supply voltage Viso is transmitted to the second inverter through the drain of the third PMOS transistor. The gate and drain of the third PMOS transistor are connected, and a third NMOS transistor is disposed between the gate and drain. The signal output from the first inverter serves as the input signal to the gate of the third NMOS transistor. The gate of the third PMOS transistor and the third NMOS transistor are connected by a connection line. The voltage supply module includes a fourth NMOS transistor. The gate of the fourth NMOS transistor receives the input signal. When the gate is turned on, the ground voltage connected to the source of the fourth NMOS transistor is transmitted to the drain.

Images