ESD protection circuit and method, and electronic device

Abstract

The invention provides an ESD protection circuit and method and an electronic device. Wherein the ESD protection circuit comprises a bleeder circuit and a control circuit, and when an ESD event occurs, the control circuit connects the other end, opposite to a first capacitor, of a bleeder transistor to a grid electrode of the bleeder transistor, so that the bleeder circuit is of a GCCNMOS structure and has the advantage of high response speed; and during normal work, the control circuit disconnects the other end opposite to the first capacitor from the grid electrode of the bleeder transistor, so that the bleeder circuit is of a GGNMOS structure and has the advantage of resisting high-power signal interference. Therefore, under the action of the control circuit, the ESD protection circuit can realize the switching of the two structures, has the advantages of the two structures, and abandons the respective defects. The ESD protection circuit not only can make a quick response to an ESD event and protect a voltage port, but also enhances the anti-interference capability of the whole circuit to a high-power signal and effectively avoids leakage current.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to an ESD protection circuit and method, and an electronic device. Background Art

[0002] Static electricity is the static charge accumulated on the surface of an object. The transfer of static charge when different objects come into contact with each other is called electrostatic discharge. The electrostatic discharge process is characterized by high voltage, low power and short time. Since semiconductor devices have poor voltage tolerance, semiconductor products need to use electrostatic discharge (ESD) devices to protect external ports.

[0003] The external ports of RF products are divided into RF ports and DC ports. The RF port is responsible for the input and output of high-power signals, and the DC port is the power supply port and the state control port. Among them, the power supply port is responsible for connecting the power supply, and the state control port controls the working state of the switch according to different state signals. Different types of ports use different ESD protection methods. For example: stacking multiple MOS tubes between the RF port and the chip ground port can effectively protect the RF port. The typical ESD protection device of the DC port is usually GGNMOS or GCNMOS.

[0004] See also Figure 1 In the GGNMOS protection method, the discharge transistor NM1 is an NMOS device. Taking the power supply port as an example, when an ESD event occurs at the VDD port, the voltage of the VDD port rises rapidly, and the parasitic transistor in the substrate of the discharge transistor NM1 will be turned on to quickly discharge the electrostatic charge of the VDD port, thereby protecting the VDD port. When the product is working normally, the gate and source of the discharge transistor NM1 are zero, and the discharge transistor NM1 remains closed, which does not affect the normal operation of the product. The advantage of the GGNMOS device is its simple structure, but its disadvantage is the high ESD protection turn-on voltage, which limits the use of GGNMOS in advanced processes.

[0005] See also Figure 2 In the GCNMOS protection mode, the discharge transistor NM1 is an NMOS device, and its gate is connected to the first capacitor C1 and the first resistor R1 respectively. Continuing with the power supply port as an example, when an ESD event occurs at the DC port, the voltage of the VDD port rises rapidly. By taking advantage of the fact that the voltage across the first capacitor C1 cannot change suddenly, the voltage at the gate point A of the discharge transistor NM1 will rise rapidly, so that the discharge transistor NM1 is turned on, and relying on the opening of the NMOS channel, the electrostatic charge can be quickly discharged, thereby protecting the DC port.

[0006] The advantage of GCNMOS devices is that the ESD protection turn-on voltage is low. When the product is working normally, the first resistor R1 discharges the gate charge of the discharge transistor NM1, keeps the gate voltage at zero, and the discharge transistor NM1 remains closed, which does not affect the normal operation of the product. However, when the product works in a high-power scenario, the ground terminal or the VDD terminal is interfered by a large signal power. Since the gate potential cannot quickly follow the interference signal, the discharge transistor NM1 will be turned on periodically, resulting in a large leakage current, which increases the power consumption of the product in a high-power state. This limits the use of GCNMOS in small-size, high-power RF switches. In addition, as the size of the RF switch becomes smaller and smaller, the isolation between the RF port and the DC port becomes worse and worse, and the high-power signal flowing through the RF port will leak to the DC port. The DC port of advanced process products usually chooses GCNMOS as an ESD protection device, but under the influence of a large RF signal, the GCNMOS will be briefly turned on, forming a large leakage current.

[0007] Therefore, a new ESD protection circuit is urgently needed to solve the above technical problems. Summary of the invention

[0008] The object of the present invention is to provide an ESD protection circuit and method, and an electronic device to solve at least one of the problems of how to avoid the formation of leakage current under high-power signal interference and how to improve the response speed of the ESD protection circuit.

[0009] In order to solve the above technical problems, the present invention provides an ESD protection circuit, comprising: a discharge circuit and a control circuit;

[0010] The discharge circuit includes a discharge transistor, a first resistor and a first capacitor; the source and drain of the discharge transistor are respectively connected to the ground and the voltage port; the opposite ends of the first resistor are respectively connected to the ground and the gate of the discharge transistor; one end of the first capacitor is connected to the voltage port, and the other opposite end of the first capacitor is connected to the control circuit; and,

[0011] The control circuit is used to connect the other end of the first capacitor to the gate of the discharge transistor when an ESD event occurs, so that the discharge transistor is turned on and discharges electrostatic charge; and in normal operation, disconnect the other end of the first capacitor from the gate of the discharge transistor to keep the discharge transistor turned off.

[0012] Optionally, in the ESD protection circuit, the discharge transistor includes an NMOS; and the control circuit includes a control transistor; and the control transistor is connected to the other end opposite to the first capacitor and the gate of the discharge transistor.

[0013] Optionally, in the ESD protection circuit, the control transistor includes a PMOS; and the source of the control transistor is connected to the other end opposite to the first capacitor, and the drain of the control transistor is connected to the gate of the discharge transistor; wherein,

[0014] When an ESD event occurs, the gate of the control transistor is connected to a low potential, and the control transistor is turned on; and when working normally, the gate of the control transistor is connected to a high potential, and the control transistor remains turned off.

[0015] Optionally, in the ESD protection circuit, the control transistor includes a PMOS; and the source and gate of the control transistor are connected to the other end opposite to the first capacitor and the gate of the discharge transistor, and the drain of the control transistor is grounded; wherein,

[0016] When an ESD event occurs, the control transistor is turned off; and when operating normally, the control transistor remains on.

[0017] Optionally, in the ESD protection circuit, the control transistor includes a PMOS; and the source of the control transistor is connected to the other end opposite to the first capacitor and the gate of the discharge transistor, and the drain of the control transistor is grounded; wherein,

[0018] When an ESD event occurs, the gate of the control transistor is connected to a high potential, and the control transistor is turned off; and when working normally, the gate of the control transistor is connected to a low potential, and the control transistor remains turned on.

[0019] Optionally, in the ESD protection circuit, the control transistor includes an NMOS; and the source of the control transistor is grounded, and the drain of the control transistor is connected to the other end opposite to the first capacitor and the gate of the discharge transistor; wherein,

[0020] When an ESD event occurs, the gate of the control transistor is connected to a low potential, and the control transistor is turned off; and when working normally, the gate of the control transistor is connected to a high potential, and the control transistor remains turned on.

[0021] Optionally, in the ESD protection circuit, the control transistor includes an NMOS; and the drain of the control transistor is connected to the other end opposite to the first capacitor, and the source of the control transistor is connected to the gate of the discharge transistor; wherein,

[0022] When an ESD event occurs, the gate of the control transistor is connected to a high potential, and the control transistor is turned on; and when working normally, the gate of the control transistor is connected to a low potential, and the control transistor remains turned off.

[0023] Optionally, in the ESD protection circuit, the control circuit also includes a second capacitor and a second resistor; one end of the second capacitor is connected to the voltage port, and the other end of the second capacitor is connected to the gate of the control transistor and one end of the second resistor; and the other end of the second resistor is grounded.

[0024] Based on the same concept, the present invention also provides an ESD protection method, using the ESD protection circuit, and the ESD protection method includes:

[0025] When an ESD event occurs, the control circuit connects the other end of the first capacitor to the gate of the discharge transistor, so that the discharge transistor is turned on and discharges electrostatic charge; and

[0026] During normal operation, the control circuit disconnects the other end of the first capacitor from the gate of the discharge transistor to keep the discharge transistor turned off.

[0027] Based on the same concept, the present invention also provides an electronic device including the ESD protection circuit.

[0028] In summary, the present invention provides an ESD protection circuit and method, and an electronic device. Compared with the prior art, the ESD protection circuit includes a discharge circuit and a control circuit, and when an ESD event occurs, the control circuit connects the other end of the first capacitor to the gate of the discharge transistor, so that the discharge circuit is a GCNMOS structure, which has the advantage of fast response speed; and when working normally, the control circuit disconnects the other end of the first capacitor from the gate of the discharge transistor, so that the discharge circuit is a GGNMOS structure, which has the advantage of resisting high-power signal interference. Therefore, under the action of the control circuit, the ESD protection circuit can realize the switching of these two structures, and has the advantages of both structures, and abandons their respective shortcomings. Not only can it respond quickly to ESD events and protect voltage ports, but it also enhances the anti-interference ability of the entire circuit to high-power signals and effectively avoids leakage current. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Those skilled in the art will appreciate that the drawings are provided for a better understanding of the present invention, but do not constitute any limitation on the scope of the present invention.

[0030] Figure 1 It is a schematic diagram of a GGNMOS structure in the prior art.

[0031] Figure 2 It is a schematic diagram of a GCNMOS structure in the prior art.

[0032] Figure 3 is an ESD protection circuit diagram corresponding to the first example in the embodiment of the present invention.

[0033] Figure 4 4 is an ESD protection circuit diagram corresponding to the second example in the embodiment of the present invention.

[0034] Figure 5 4 is an ESD protection circuit diagram corresponding to the third example in the embodiment of the present invention.

[0035] Figure 6 4 is an ESD protection circuit diagram corresponding to the fourth example in the embodiment of the present invention.

[0036] Figure 7 4 is an ESD protection circuit diagram corresponding to the fifth example in the embodiment of the present invention.

[0037] Figure 8 4 is an ESD protection circuit diagram corresponding to the sixth example in the embodiment of the present invention.

[0038] Fig. 9 It is a comparison diagram of leakage current between the ESD protection circuit in the embodiment of the present invention and the GCNMOS structure in the prior art under high-power signal interference.

[0039] And, in the attached drawings:

[0040] PM1-first switch tube; NM1-discharge transistor; NM2-second switch tube; C1-first capacitor; C2-second capacitor; R1-first resistor; R2-second resistor; VDD-voltage port. DETAILED DESCRIPTION

[0041] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different proportions are used. It should also be understood that, unless otherwise specified or indicated, the terms "first", "second", "third", etc. in the specification are only used to distinguish between the various components, elements, steps, etc. in the specification, and are not used to represent the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0042] See also Figure 3, this embodiment provides an ESD protection circuit, including: a discharge circuit and a control circuit; the discharge circuit includes a discharge transistor NM1, a first resistor R1 and a first capacitor C1; the source and drain of the discharge transistor are respectively connected to the ground and the voltage port VDD; the opposite ends of the first resistor R1 are respectively connected to the ground and the gate of the discharge transistor NM1; one end of the first capacitor C1 is connected to the voltage port VDD, and the other end of the first capacitor C1 is connected to the control circuit; and the control circuit is used to connect the other end of the first capacitor C1 to the gate of the discharge transistor NM1 when an ESD event occurs, so that the discharge transistor NM1 is turned on and discharges electrostatic charge; and in normal operation, the other end of the first capacitor C1 is disconnected from the gate of the discharge transistor NM1, so that the discharge transistor NM1 remains turned off.

[0043] Based on this, when an ESD event occurs, the discharge circuit is in a GCNMOS structure, which has the advantage of fast response speed; and when working normally, the discharge circuit is in a GGNMOS structure, which has the advantage of resisting high-power signal interference. Therefore, under the action of the control circuit, the ESD protection circuit can realize the switching of these two structures, and has the advantages of both structures and abandons their respective disadvantages. Not only can it respond quickly to ESD events and protect the voltage port VDD, but it also enhances the anti-interference ability of the entire circuit to high-power signals and effectively avoids leakage current.

[0044] The following is combined with Figures 3 to 9 , specifically describe the ESD protection circuit provided in this embodiment.

[0045] Please continue reading Figure 3 The ESD protection circuit provided in this embodiment includes a discharge circuit and a control circuit; the discharge circuit is used to discharge the electrostatic charge when an ESD event occurs. The control circuit is used to switch the discharge circuit between the GCNMOS structure and the GGNMOS structure to ensure that the discharge circuit has the advantages of fast response speed and resistance to high-power signal interference.

[0046] Specifically, the discharge circuit includes a discharge transistor NM1, a first resistor R1 and a first capacitor C1. The discharge transistor NM1 is an NMOS, and the source of the discharge transistor NM1 is grounded, the drain of the discharge transistor NM1 is connected to the voltage port VDD, the gate of the discharge transistor NM1 is connected to one end of the first resistor R1; the other end of the first resistor R1 is grounded; one end of the first capacitor C1 is connected to the voltage port VDD, and the other end of the first capacitor C1 is connected to the control circuit to be controlled by the control circuit to achieve the switching between the GCNMOS structure and the GGNMOS structure. And, the control circuit includes a control transistor; and the control transistor is connected to the other end of the first capacitor C1 and the gate of the discharge transistor NM1. Wherein, the control transistor can be PMOS or NMOS.

[0047] In the first example, if Figure 3 As shown, the control transistor is a PMOS, and in this embodiment, it is named the first switch tube PM1. The source of the first switch tube PM1 is connected to one end of the first capacitor C1. That is, the opposite ends of the capacitor C1 are connected to the voltage port VDD and the source of the first switch tube PM1 respectively. The drain of the first switch tube PM1 is connected to the gate of the discharge transistor NM1 and the non-grounded end of the first resistor R1. And the gate of the first switch tube PM1 is provided with other circuits inside the electronic device, such as: circuit operation enable signal or product control signal, etc. And in order to realize that when an ESD event occurs, the discharge circuit is a GCNMOS structure; when working normally, the discharge circuit is a GGNMOS structure; then the first switch tube PM1 needs to be turned on when an ESD event occurs, and turned off when working normally.

[0048] Based on this, when an ESD event occurs, that is, an ESD pulse arrives, the potential of the voltage port VDD rises. The gate of the first switch tube PM1 is connected to a low potential to turn on the first switch tube PM1, and the first capacitor C1 is connected to the discharge circuit to make the discharge circuit present a GCNMOS structure. And because the potential at both ends of the capacitor has a delay and cannot change suddenly, the end of the first capacitor C1 connected to the gate of the discharge transistor NM1 through the first switch tube PM1 will rise as the potential of the voltage port VDD rises. That is, the potential at point A at the gate of the discharge transistor NM1 will rise and can reach the turn-on voltage of the discharge transistor NM1, then the discharge transistor NM1 will be turned on when the ESD event occurs, and the electrostatic charge will be discharged quickly.

[0049] When working normally, the potential of the voltage port VDD is a normal voltage and will not rise. Also, a high potential is connected to point B at the gate of the first switch tube PM1, so that the first switch tube PM1 is in a closed state, then the discharge circuit is a GGNMOS structure, and the first capacitor C1 is not connected to the discharge circuit. When a high-power signal interference comes, the potential of the voltage port VDD will also rise, but it is much smaller than the voltage of the voltage port VDD when the ESD event occurs, and the high-power signal interference time is extremely short and the energy is also small. Therefore, based on the large turn-on voltage of the GGNMOS structure, the first switch tube PM1 and the discharge transistor NM1 are both kept closed, thereby achieving effective resistance to high-power signals and avoiding leakage current problems.

[0050] See also Figure 4 , in the second example, the continuation Figure 3 The control circuit shown in the figure still only includes the first switch tube PM1. However, the connection mode of the first switch tube PM1 is different from Figure 3 and Figure 4 The connection method in the circuit shown is different. Specifically, the source and gate of the first switch tube PM1 are connected to the other end opposite to the first capacitor C1 and the gate of the discharge transistor NM1, and the drain of the first switch tube PM1 is grounded. Based on this, when an ESD event occurs, the potential of the voltage port VDD rises. Since the voltage across the first capacitor C1 cannot change suddenly, the potential of point A where the first capacitor C1 is connected to the source and gate of the first switch tube PM1 and the gate of the discharge transistor NM1 will rise with the increase of the potential of the voltage port VDD. That is, the potential of the gate of the first switch tube PM1 quickly responds to a high potential, which causes the first switch tube PM1 to be turned off. At this time, the discharge circuit has a GCNMOS structure. And since the potential of point A rises and causes the discharge transistor NM1 to turn on, the discharge transistor NM1 quickly discharges the electrostatic charge. When working normally, the potential of the voltage port VDD is a normal voltage and will not rise. Then, under the action of the first resistor R1, the potential of point A will be pulled down, and the gate of the first switch tube PM1 will be at a low potential, causing the first switch tube PM1 to turn on. At the same time, the discharge transistor NM1 remains closed. And, based on the principle of current priority, the current will preferentially choose a path with a smaller resistance to flow, so at this time the discharge circuit is a GGNMOS structure. Similarly, when a high-power signal arrives, since the turn-on voltage of the GGNMOS structure is relatively large, the rising potential of the voltage port VDD cannot drive the potential of point A to drive the discharge transistor NM1 to turn on, and at the same time, the first switch tube PM1 remains in the on state, effectively resisting the interference of the high-power signal and avoiding the leakage current problem.

[0051] In the third example, if Figure 5 As shown, in Figure 4 Based on the circuit structure shown in FIG. 1 , the control circuit also only includes the first switch tube PM1. The connection mode of the source and drain of the first switch tube PM1 is the same as that of Figure 4 The connection mode of the first switch tube PM1 is the same as shown, but its gate is not connected to the other end opposite to the first capacitor C1 and the gate of the discharge transistor NM1, but directly provides signals from other circuits inside the electronic device, such as: circuit operation enable signal or product control signal, etc. And when an ESD event occurs, the gate of the first switch tube PM1 is connected to a high potential, and the first switch tube PM1 is turned off; when normal operation or a high-power signal arrives, the gate of the first switch tube PM1 is connected to a low potential, and the first switch tube PM1 remains turned on. Among them, Figure 5 The specific operation process of the circuit shown can be referred to above Figure 4 The operation process of this embodiment will not be described in detail here.

[0052] See also Figure 6 ,exist Figure 5 On the basis of the circuit structure shown, the control transistor can be replaced by NMOS, and in this embodiment, it is named as the second switch tube NM2. Since the characteristics of NMOS and PMOS are basically opposite, in order to realize the switching between the GCNMOS structure and the GGNMOS structure, when an ESD event occurs, the gate of the second switch tube NM2 needs to be connected to a low potential to turn off the second switch tube NM2, and the discharge circuit has a GCNMOS structure; when working normally, the gate of the second switch tube NM2 needs to be connected to a high potential to turn on the second switch tube NM2, and the discharge circuit has a GGNMOS structure.

[0053] Therefore, if Figure 6As shown, in the fourth example, the control circuit only includes the second switch tube NM2. The drain of the second switch tube NM2 is connected to the gate of the discharge transistor NM1 and the other end opposite to the first capacitor C1, and the source of the second switch tube NM2 is grounded. The gate of the second switch tube NM2 can be directly provided with other circuits inside the electronic device, such as: circuit operation enable signal or product control signal. And when an ESD event occurs, the potential of the voltage port VDD rises. The gate of the second switch tube NM2 is connected to a low potential to turn off the second switch tube NM2. At this time, the discharge circuit is a GCNMOS structure. Since the voltage across the capacitor cannot change suddenly, the potential of point A at one end of the first capacitor C1 will rise with the rise of the voltage port VDD, and the discharge transistor NM1 will be turned on to quickly discharge the electrostatic charge. When working normally, the potential of the voltage port VDD is a normal voltage and will not rise, and the gate of the second switch tube NM2 is connected to a high potential to turn on the second switch tube NM2. At the same time, under the action of the first resistor R1, the potential at point A at the gate of the discharge transistor NM1 is low, and the discharge transistor NM1 remains closed. At this time, the discharge circuit is a GGNMOS structure. And based on the high turn-on voltage of the GGNMOS structure, the discharge transistor NM1 can be kept in a closed state under the interference of a high-power signal, effectively resisting the interference of the high-power signal and avoiding the formation of leakage current.

[0054] It should be noted that if Figure 4 , Figure 5 and Figure 6 As shown, based on the characteristics of the capacitor, when an ESD event occurs, the voltage of the voltage port VDD changes, which is equivalent to connecting the first capacitor C1 to the discharge circuit, and the discharge circuit has a GCNMOS structure; when working normally, the voltage of the voltage port VDD does not change, and the first capacitor C1 is equivalent to an open circuit, then it can be considered that the first capacitor C1 is not connected to the discharge circuit, and the discharge circuit has a GGNMOS structure.

[0055] For further information, see Figure 7 and Figure 8 ,based on Figure 3 The circuit design idea can be Figure 3 The first switch tube PM1 in the corresponding circuit is replaced by the second switch tube NM2. Similarly, since the characteristics of NMOS and PMOS are basically opposite, the connection mode of the second switch tube NM2 needs to be appropriately adjusted. Specifically, Figure 7As shown, in the fifth example, the control circuit includes the second switch tube NM2, the second capacitor C2 and the second resistor R2. And the drain of the second switch NM2 is connected to the other end opposite to the first capacitor C1, and the source of the second switch NM2 is connected to the gate of the discharge transistor and the non-grounded end of the first resistor R1. One end of the second capacitor C2 and one end of the second resistor R2 are connected to the gate of the second switch NM2, and the other end opposite to the second capacitor C2 is connected to the voltage port VDD, and the other end opposite to the second resistor R2 is grounded. Based on this, when an ESD event occurs, the potential of the voltage port VDD rises. Since the voltage across the capacitor cannot change suddenly, the potential at point B at one end of the second capacitor C2 rises rapidly, that is, the gate potential of the second switch NM2 rises, and the second switch NM2 is turned on. And under the action of turning on the second switch NM2, the first capacitor C1 is connected to the discharge circuit, and the discharge circuit is a GCNMOS structure. At the same time, the potential at point A at the gate of the discharge transistor NM1 also rises as the potential of the voltage port VDD rises, so that the discharge transistor NM1 is turned on and discharges the electrostatic charge quickly.

[0056] When working normally, the potential of the voltage port VDD is a normal voltage and will not rise, and under the action of the second resistor R2, the potential at point B at one end of the second capacitor C2 is pulled down, that is, the gate of the second switch NM2 is at a low potential, and the second switch NM2 is turned off. At this time, the first capacitor C1 is not connected to the discharge circuit, and the discharge circuit is a GGNMOS structure. And, under the action of the first resistor R1, point A at the gate of the discharge transistor NM1 is at a low potential, and the discharge transistor NM1 remains closed. Based on the high turn-on voltage of the GGNMOS structure, the discharge transistor NM1 always remains in a closed state under the interference of high-power signals, effectively resisting the interference of high-power signals and avoiding the formation of leakage current.

[0057] Similarly, in order to simplify the circuit structure, in the sixth example, Figure 8 As shown, the control circuit only includes the second switch NM2, and its connection mode is the same as Figure 7The connection mode of the second switch NM2 shown is the same. It is just that the gate of the second switch NM2 can be directly provided with other circuits inside the electronic device, such as: circuit operation enable signal or product control signal, etc., and it can also be realized that when an ESD event occurs, the second switch NM2 is turned on; when normal operation or a high-power signal arrives, the second switch NM2 remains closed. Specifically, when an ESD event occurs, the potential of the voltage port VDD rises. The gate of the second switch NM2 is connected to a high potential to turn on the second switch NM2, and the first capacitor C1 is connected to the discharge circuit to make the discharge circuit present a GCNMOS structure. And because the potential at both ends of the capacitor has a delay and cannot change suddenly, the end of the first capacitor C1 connected to the gate of the discharge transistor NM1 through the second switch NM2 will rise as the potential of the voltage port VDD rises. That is, the potential at point A at the gate of the discharge transistor NM1 will rise and reach the turn-on voltage of the discharge transistor NM1, then the discharge transistor NM1 will turn on when an ESD event occurs to quickly discharge the electrostatic charge. When working normally, the potential of the voltage port VDD is a normal voltage and will not rise. Also, a low potential is connected to point B at the gate of the second switch NM2 to make the second switch NM2 in a closed state, then the discharge circuit is a GGNMOS structure, and the first capacitor C1 is not connected to the discharge circuit. Also, based on the large turn-on voltage of the GGNMOS structure, when high-power signal interference arrives, the second switch NM2 and the discharge transistor NM1 remain closed, thereby achieving effective resistance to high-power signals and avoiding leakage current problems.

[0058] Furthermore, in order to verify the ability of the ESD protection circuit provided in this embodiment to resist high-power interference, the applicant conducted a simulation test. Fig. 9 As shown, the red line is the leakage current generated by the common GCNMOS device as the interference power increases, and the blue line is the leakage current generated by the ESD protection circuit provided by this embodiment as the interference power increases. Obviously, the ESD protection circuit provided by this embodiment will not generate leakage current under the condition of large interference power.

[0059] It should be noted that this embodiment does not limit the specific models and parameter value ranges of each resistor, capacitor and transistor in the ESD protection circuit. The high potential and low potential referred to in this embodiment are relative values, which are not specifically limited in this embodiment, but must meet the corresponding opening and closing driving functions during the operation of the above circuit.

[0060] Based on the same concept, this embodiment also provides an ESD protection method. The ESD protection method uses the above-mentioned ESD protection circuit and includes: when an ESD event occurs, the control circuit connects the other end of the first capacitor to the gate of the discharge transistor to turn on the discharge transistor and discharge the electrostatic charge; and, in normal operation, the control circuit disconnects the other end of the first capacitor from the gate of the discharge transistor to keep the discharge transistor closed. The specific operation process of the ESD protection method can refer to the specific operation process of the corresponding circuits of the above six examples, and this embodiment will not be repeated here.

[0061] Based on the same concept, this embodiment further provides an electronic device. The electronic device includes the above-mentioned ESD protection circuit. Exemplarily, the electronic device is a radio frequency device.

[0062] In summary, this embodiment provides an ESD protection circuit and method, and an electronic device. The ESD protection circuit includes a discharge circuit and a control circuit, and when an ESD event occurs, the control circuit connects the other end of the first capacitor C1 to the gate of the discharge transistor NM1, so that the discharge circuit is in a GCNMOS structure, which has the advantage of fast response speed; and when working normally, the control circuit disconnects the other end of the first capacitor C1 from the gate of the discharge transistor NM1, so that the discharge circuit is in a GGNMOS structure, which has the advantage of resisting high-power signal interference. Therefore, under the action of the control circuit, the ESD protection circuit can realize the switching of these two structures, and has the advantages of both structures, and abandons their respective disadvantages. Not only can it respond quickly to ESD events and protect the voltage port VDD, but it also enhances the anti-interference ability of the entire circuit to high-power signals and effectively avoids leakage current.

[0063] In addition, it should be recognized that although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiment according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still belongs to the scope of protection of the technical solution of the present invention.

Claims

1. An ESD protection circuit, characterized in that: include: Discharge circuit and control circuit; The discharge circuit includes a discharge transistor, a first resistor and a first capacitor; the source and drain of the discharge transistor are respectively connected to the ground and the voltage port; the opposite ends of the first resistor are respectively connected to the ground and the gate of the discharge transistor; one end of the first capacitor is connected to the voltage port, and the other opposite end of the first capacitor is connected to the control circuit; and, The control circuit is used for connecting the other end of the first capacitor to the gate of the discharge transistor when an ESD event occurs, so that the discharge transistor is turned on and discharges the electrostatic charge; And in normal operation, the other end of the first capacitor is disconnected from the gate of the discharge transistor, so that the discharge transistor remains turned off.

2. The ESD protection circuit according to claim 1, characterized in that: The discharge transistor includes an NMOS; and the control circuit includes a control transistor; and the control transistor is connected to the other end of the first capacitor and the gate of the discharge transistor.

3. The ESD protection circuit according to claim 2, characterized in that: The control transistor includes a PMOS; and the source of the control transistor is connected to the other end opposite to the first capacitor, and the drain of the control transistor is connected to the gate of the discharge transistor; wherein, When an ESD event occurs, the gate of the control transistor is connected to a low potential, and the control transistor is turned on; and when working normally, the gate of the control transistor is connected to a high potential, and the control transistor remains turned off.

4. The ESD protection circuit according to claim 2, characterized in that: The control transistor includes a PMOS; the source and the gate of the control transistor are connected to the other end opposite to the first capacitor and the gate of the discharge transistor, and the drain of the control transistor is grounded; wherein, When an ESD event occurs, the control transistor is turned off; and when operating normally, the control transistor remains on.

5. The ESD protection circuit according to claim 2, characterized in that: The control transistor includes a PMOS; the source of the control transistor is connected to the other end opposite to the first capacitor and the gate of the discharge transistor, and the drain of the control transistor is grounded; wherein, When an ESD event occurs, the gate of the control transistor is connected to a high potential, and the control transistor is turned off; and when working normally, the gate of the control transistor is connected to a low potential, and the control transistor remains turned on.

6. The ESD protection circuit according to claim 2, characterized in that: The control transistor includes an NMOS; the source of the control transistor is grounded, and the drain of the control transistor is connected to the other end opposite to the first capacitor and the gate of the discharge transistor; wherein, When an ESD event occurs, the gate of the control transistor is connected to a low potential, and the control transistor is turned off; and when working normally, the gate of the control transistor is connected to a high potential, and the control transistor remains turned on.

7. The ESD protection circuit according to claim 2, characterized in that: The control transistor includes an NMOS; the drain of the control transistor is connected to the other end opposite to the first capacitor, and the source of the control transistor is connected to the gate of the discharge transistor; wherein, When an ESD event occurs, the gate of the control transistor is connected to a high potential, and the control transistor is turned on; and when working normally, the gate of the control transistor is connected to a low potential, and the control transistor remains turned off.

8. The ESD protection circuit according to claim 7, characterized in that: The control circuit also includes a second capacitor and a second resistor; one end of the second capacitor is connected to the voltage port, and the other end of the second capacitor is connected to the gate of the control transistor and one end of the second resistor; and the other end of the second resistor is grounded.

9. An ESD protection method, characterized in that: Using the ESD protection circuit as described in any one of claims 1 to 8, and the ESD protection method comprises: When an ESD event occurs, the control circuit connects the other end of the first capacitor to the gate of the discharge transistor, so that the discharge transistor is turned on and discharges electrostatic charge; and During normal operation, the control circuit disconnects the other end of the first capacitor from the gate of the discharge transistor to keep the discharge transistor turned off.

10. An electronic device, characterized in that: The invention comprises the ESD protection circuit as claimed in any one of claims 1 to 8.

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