High-speed hybrid architecture ADC based on parallel margin amplification and quantization
By adopting a hybrid architecture of parallel margin amplification and quantization in Pipelined SAR ADCs, the problems of lower speed and higher op amp power consumption are solved, and more efficient analog-to-digital conversion is achieved.
Patent Information
- Application Number
- CN202510057824.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-14
- Publication Date
- 2025-05-16
AI Technical Summary
The Pipelined SAR ADC has a lower speed and high op amp power consumption, mainly because the quantization of the next-level SAR ADC needs to wait for the current level to be amplified.
A high-speed hybrid architecture ADC based on parallel margin amplification and quantization, including first-stage, second-stage and third-stage SAR ADC, allows parallel quantization and amplification of the first-stage margin voltage to be performed simultaneously.
Through parallel quantization and amplification, the speed of the ADC is improved and the power consumption of the op amp is reduced, achieving more efficient analog-to-digital conversion.
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Figure CN120017062A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a high-speed hybrid architecture analog to digital converter (ADC) based on parallel residual amplification and quantization. Background Art
[0002] High-speed and high-precision ADCs can be widely used in communication systems and high-performance instrument applications. Generally, pipeline architecture is used to achieve high-speed and high-precision ADC index requirements. The traditional ADC structure using pipeline architecture is pipelined analog to digital converter (Pipelined Analog to Digital Converter, Pipelined ADC). Pipelined ADC has many stages and uses a large number of comparators and op amps. The overhead and power consumption of Pipelined ADC are relatively large. Based on Pipelined ADC, pipelined successive approximation analog to digital converter (Pipeline Successive Approximation Register Analog to Digital Converter, Pipelined SAR ADC) appeared. Compared with pipelined ADC, pipelined SAR ADC has fewer stages, generally 2-3 stages, and each stage of SAR ADC only requires one comparator, which greatly reduces power consumption and area overhead.
[0003] At present, the quantization of the next stage SAR ADC in the pipelined SAR ADC needs to wait for the margin amplification of the current stage to proceed. The existing serial timing limits the speed of the pipelined SAR ADC to a certain extent; the op amp amplification time of the pipelined SAR ADC is shortened and the op amp power consumption is higher. Summary of the invention
[0004] The purpose of the embodiment of the present invention is to provide a high-speed hybrid architecture ADC based on parallel residual amplification and quantization, so as to solve the problems of low speed and high power consumption of operational amplifier of Pipelined SAR ADC.
[0005] To solve the above technical problems, the embodiments of the present invention provide the following technical solutions:
[0006] The present invention provides a high-speed hybrid architecture ADC based on parallel residual amplification and quantization, comprising a first-stage SAR ADC, a second-stage SAR ADC and a third-stage SAR ADC;
[0007] A first-stage SAR ADC, for collecting an input signal, quantizing the input signal to generate a first-stage quantization code, generating a first-stage residual voltage according to the first-stage quantization code, and amplifying the first-stage residual voltage to generate an amplified residual voltage;
[0008] a second-stage SAR ADC connected to the first-stage SAR ADC, for parallel quantizing the first-stage residual voltage to generate a second-stage quantization code, and generating a second-stage residual voltage according to the second-stage quantization code and the amplified residual voltage;
[0009] The third-stage SAR ADC is connected to the second-stage SAR ADC and is used for quantizing the second-stage residual voltage to generate a third-stage quantization code.
[0010] In some embodiments, the first stage SAR ADC includes a switch S1, a switch S2, a residual amplifier, a switch array S a 、Capacitor array C a , a first SAR logic and a first comparator;
[0011] One end of the switch S1 is connected to the input signal, and the other end of the switch S1 and the capacitor array C a The top plate, one end of the switch S2, the input end of the first comparator and the second stage SAR ADC are all connected, the other end of the switch S2 is connected to the input end of the residual amplifier, the output end of the residual amplifier is connected to the second stage SAR ADC, and the capacitor array C a The bottom plate and switch array S a One end of the switch array S a The other end of is connected to one end of the first SAR logic, and the other end of the first SAR logic is connected to the output end of the first comparator.
[0012] In some embodiments, the second stage SAR ADC includes a switch S3, a SAR ADC, a switch array S b and capacitor array C b ;
[0013] One end of the switch S3 is connected to the output end of the residual amplifier, and the other end of the switch S3 and the capacitor array C b The top plate and the third-stage SAR ADC are connected to the capacitor array C b The bottom plate and switch array S b One end of the switch array S b The other end of is connected to the output end of the SAR ADC, and the input end of the SAR ADC is connected to the other end of the switch S1, the capacitor array C a The top plate, one end of the switch S2, and the input end of the first comparator are connected.
[0014] In some embodiments, the third-stage SAR ADC includes a capacitor array C c , switch array S c , a second SAR logic and a second comparator;
[0015] Capacitor array C c The top plate is connected to the other end of switch S3 and the capacitor array C b The top plate of the second comparator is connected to the input terminal of the capacitor array C c The bottom plate and switch array S c One end of the switch array S c The other end of is connected to one end of the second SAR logic, and the other end of the second SAR logic is connected to the output end of the second comparator.
[0016] In some embodiments, the SAR ADC includes a switch S4, an attenuation capacitor C S , bridge capacitor C B 、Capacitor array C d , switch array S d , a third SAR logic and a third comparator;
[0017] One end of the switch S4 is connected to the other end of the switch S1 and the capacitor array C a The top plate, one end of the switch S2, and the input end of the first comparator are connected, and the other end of the switch S4 and the attenuation capacitor C S One end of the bridge capacitor C B One end of the attenuation capacitor C is connected to the input end of the third comparator. S The other end is grounded and the bridge capacitor C B The other end of the capacitor array C d The top plate of the capacitor array C d The bottom plate and switch array S d One end of the switch array S d The other end of is connected to one end of the third SAR logic, and the other end of the third SAR logic is connected to the output end of the third comparator.
[0018] In some embodiments, the switch array S a The plurality of first switches and capacitor array C a The number of the first capacitors in the switch array S is the same. b The plurality of second switches and capacitor arrays C b The number of the second capacitors in the capacitor array C is the same. c The plurality of third capacitors and switch arrays S c The number of the third switches in the capacitor array C is the same as that in the d The plurality of fourth capacitors and switch arrays S dThe number of the multiple fourth switches in is the same.
[0019] In some embodiments, the number of the plurality of first switches and the plurality of first capacitors is the same as the number of bits of the first level quantization code, and the number of the plurality of fourth switches and the plurality of fourth capacitors is the same as the number of bits of the second level quantization code.
[0020] In some embodiments, the number of the third capacitors and the number of the third switches are both equal to the number of bits of the third level quantization code minus 1.
[0021] In some embodiments, the number of bits of the first level quantization code is 5 bits, the number of bits of the second level quantization code is 4 bits, and the number of bits of the third level quantization code is 5 bits.
[0022] In some embodiments, the magnification of the first-stage residual voltage is 16 times, and the capacitor array C b and capacitor array C c Form a combined capacitor array.
[0023] Compared with the prior art, the high-speed hybrid architecture ADC based on parallel residue amplification and quantization provided by the present invention includes a first-stage SAR ADC, a second-stage SAR ADC and a third-stage SAR ADC; the first-stage SAR ADC is used to collect input signals, quantize the input signals to generate a first-stage quantization code, generate a first-stage residue voltage according to the first-stage quantization code, and amplify the first-stage residue voltage to generate an amplified residue voltage; the second-stage SAR ADC is connected to the first-stage SAR ADC, and is used to quantize the first-stage residue voltage in parallel to generate a second-stage quantization code, and generate a second-stage residue voltage according to the second-stage quantization code and the amplified residue voltage; the third-stage SAR ADC is connected to the second-stage SAR ADC, and is used to quantize the second-stage residue voltage to generate a third-stage quantization code. Compared with the traditional Pipelined SAR ADC, the high-speed hybrid architecture ADC based on parallel residue amplification and quantization provided by the present invention can perform the parallel quantization of the first-stage residue voltage and the amplification of the first-stage residue voltage simultaneously, that is, it allows the SAR ADC quantization and residue amplification to be performed simultaneously, so that the high-speed hybrid architecture ADC has a higher speed and lower power consumption of the operational amplifier. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] By reading the detailed description below with reference to the accompanying drawings, the above and other objects, features and advantages of the exemplary embodiments of the present invention will become readily understood. In the accompanying drawings, several embodiments of the present invention are shown in an exemplary and non-limiting manner, and the same or corresponding reference numerals represent the same or corresponding parts, wherein:
[0025] Figure 1 The schematic diagram of a high-speed hybrid architecture ADC based on parallel residual amplification and quantization is schematically shown;
[0026] Figure 2 The schematic diagram of the SAR ADC in the high-speed hybrid architecture ADC based on parallel residual amplification and quantization is schematically shown;
[0027] Figure 3 The timing diagram of a high-speed hybrid architecture ADC based on parallel residue amplification and quantization is schematically shown. DETAILED DESCRIPTION
[0028] The following is a further detailed description of the embodiments of the present invention in conjunction with the accompanying drawings and examples. The detailed description of the following embodiments and the accompanying drawings are used to exemplarily illustrate the principles of the present invention, but cannot be used to limit the scope of the present invention. The present invention can be implemented in many different forms and is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.
[0029] A high-speed hybrid architecture ADC based on parallel residue amplification and quantization in an embodiment of the present invention is described in detail below.
[0030] See also Figure 1 As shown, Figure 1 A schematic diagram of a high-speed hybrid architecture ADC based on parallel residual amplification and quantization is schematically shown. An embodiment of the present invention proposes a high-speed hybrid architecture ADC based on parallel residual amplification and quantization, including a first-stage SAR ADC, a second-stage SAR ADC, and a third-stage SAR ADC;
[0031] A first-stage SAR ADC, for collecting an input signal, quantizing the input signal to generate a first-stage quantization code, generating a first-stage residual voltage according to the first-stage quantization code, and amplifying the first-stage residual voltage to generate an amplified residual voltage;
[0032] a second-stage SAR ADC connected to the first-stage SAR ADC, for parallel quantizing the first-stage residual voltage to generate a second-stage quantization code, and generating a second-stage residual voltage according to the second-stage quantization code and the amplified residual voltage;
[0033] The third-stage SAR ADC is connected to the second-stage SAR ADC and is used for quantizing the second-stage residual voltage to generate a third-stage quantization code.
[0034] Specifically, the high-speed hybrid architecture ADC based on parallel margin amplification and quantization is composed of a three-stage SAR ADC, which includes a first-stage SAR ADC, a second-stage SAR ADC and a third-stage SAR ADC. The resolution of the first-stage SAR ADC is 5 bits, the resolution of the second-stage SAR ADC is 4 bits, and the resolution of the third-stage SAR ADC is 5 bits. There is one bit of redundancy between each stage, and the resolution of the entire high-speed hybrid architecture ADC based on parallel margin amplification and quantization is 12 bits.
[0035] In this embodiment, the first stage SAR ADC includes a switch S1, a switch S2, a residual amplifier, a switch array S a 、Capacitor array C a , a first SAR logic and a first comparator;
[0036] One end of the switch S1 is connected to the input signal, and the other end of the switch S1 and the capacitor array C a The top plate, one end of the switch S2, the input end of the first comparator and the second stage SAR ADC are all connected, the other end of the switch S2 is connected to the input end of the residual amplifier, the output end of the residual amplifier is connected to the second stage SAR ADC, and the capacitor array C a The bottom plate and switch array S a One end of the switch array S a The other end of is connected to one end of the first SAR logic, and the other end of the first SAR logic is connected to the output end of the first comparator.
[0037] In this embodiment, the second stage SAR ADC includes a switch S3, a SAR ADC, a switch array S b and capacitor array C b ;
[0038] One end of the switch S3 is connected to the output end of the residual amplifier, and the other end of the switch S3 and the capacitor array C b The top plate and the third-stage SAR ADC are connected to the capacitor array C b The bottom plate and switch array S b One end of the switch array S b The other end of is connected to the output end of the SAR ADC, and the input end of the SAR ADC is connected to the other end of the switch S1, the capacitor array C a The top plate, one end of the switch S2, and the input end of the first comparator are connected.
[0039] In this embodiment, the third-stage SAR ADC includes a capacitor array C c , switch array S c , a second SAR logic and a second comparator;
[0040] Capacitor array C c The top plate is connected to the other end of switch S3 and the capacitor array C b The top plate of the second comparator is connected to the input terminal of the capacitor array C c The bottom plate and switch array S c One end of the switch array S c The other end of is connected to one end of the second SAR logic, and the other end of the second SAR logic is connected to the output end of the second comparator.
[0041] In this embodiment, Figure 2 The schematic diagram of the SAR ADC in the high-speed hybrid architecture ADC based on parallel residual amplification and quantization is shown schematically, see Figure 2 As shown, the SAR ADC includes switch S4, attenuation capacitor C S , bridge capacitor C B 、Capacitor array C d , switch array S d , a third SAR logic and a third comparator. One end of the switch S4 is connected to the other end of the switch S1, the capacitor array C a The top plate, one end of the switch S2, and the input end of the first comparator are connected, and the other end of the switch S4 and the attenuation capacitor C S One end of the bridge capacitor C B One end of the attenuation capacitor C is connected to the input end of the third comparator. S The other end is grounded and the bridge capacitor C B The other end of the capacitor array C d The top plate of the capacitor array C d The bottom plate and switch array S d One end of the switch array S d The other end of is connected to one end of the third SAR logic, and the other end of the third SAR logic is connected to the output end of the third comparator.
[0042] Specifically, the attenuation capacitor C S and bridge capacitor C B The function is to equivalently attenuate the quantization range of the SAR ADC. Since the quantization margin of the SAR ADC has not been amplified, in order to maintain a one-bit redundant range, the quantization range of the SAR ADC needs to be reduced to 1 / 16 of the original.
[0043] In this embodiment, the switch array S a The plurality of first switches and capacitor array C a The number of the first capacitors in the switch array S is the same. b The plurality of second switches and capacitor arrays C bThe number of the second capacitors in the capacitor array C is the same. c The plurality of third capacitors and switch arrays S c The number of the third switches in the capacitor array C is the same as that in the d The plurality of fourth capacitors and switch arrays S d The number of the multiple fourth switches in is the same.
[0044] In this embodiment, the number of the first switches and the first capacitors is the same as the number of bits of the first level quantization code, and the number of the fourth switches and the fourth capacitors is the same as the number of bits of the second level quantization code.
[0045] In this embodiment, the number of the plurality of third capacitors and the number of the plurality of third switches are both equal to the number of bits of the third level quantization code minus 1.
[0046] In this embodiment, the number of bits of the first-level quantization code is 5 bits, the number of bits of the second-level quantization code is 4 bits, and the number of bits of the third-level quantization code is 5 bits.
[0047] Specifically, the number of bits of the first-level quantization code, the number of bits of the second-level quantization code, and the number of bits of the third-level quantization code are not specifically limited.
[0048] When the number of bits of the first-level quantization code is 5, the switch array S a The number of the first switches in the capacitor array C is 5. a The number of the first capacitors in the capacitor array C is 5. When the number of bits of the second-level quantization code is 4 bits, the capacitor array C d The number of the plurality of fourth capacitors is 3, and the switch array S d The number of the plurality of fourth switches in is 3. When the number of bits of the third-level quantization code is 5 bits, the capacitor array C c The number of the plurality of third capacitors is 4, and the switch array S c The number of the multiple third switches is 4.
[0049] In this embodiment, the magnification of the first-stage residual voltage is 16 times, and the capacitor array C b and capacitor array C c Form a combined capacitor array.
[0050] Specifically, after the first-stage SAR ADC samples and quantizes the input signal, the capacitor array C in the first-stage SAR ADC aAfter the first-level residual voltage is cut out, the second-level SAR ADC instantly captures the first-level residual voltage and starts to quantize the first-level residual voltage to generate the second-level quantization code, i.e., the 4-bit quantization code. At the same time, the residual amplifier in the first-level SAR ADC amplifies the first-level residual voltage by 16 times. After the first-level residual voltage is amplified, the second-level SAR ADC transmits the 4-bit quantization code to the combined capacitor array, cuts out the second-level residual voltage, and then the third-level SAR ADC performs 5-bit quantization on the cut-out second-level residual voltage to generate a 5-bit quantization code.
[0051] The high-speed hybrid architecture ADC based on parallel residual amplification and quantization of the present invention is composed of three-stage SAR ADC and uses only one residual amplifier, allowing SAR ADC quantization and residual amplification to be performed simultaneously, thereby improving the speed and energy efficiency of the high-speed hybrid architecture ADC.
[0052] See also Figure 1 and Figure 2 As shown, the clock Φ S Control switch S1, clock Φ A Control the margin amplifier, clock Φ C1 Control the first comparator, clock Φ C2 Control the second comparator, clock Φ C3 Controls the third comparator.
[0053] Figure 3 The timing diagram of the high-speed hybrid architecture ADC based on parallel margin amplification and quantization is schematically shown. S , clock Φ A , clock Φ C1 , clock Φ C2 and clock Φ C3 The working process of the high-speed hybrid architecture ADC based on parallel residual amplification and quantization is described. The specific working process is: the clock Φ S When it is high level, the control switch S1 is turned on, and the input signal V IN is sampled to the capacitor array C a The top plate, then the clock Φ C1 The first comparator is controlled to compare five times in succession to generate the first-level quantization code, i.e., the first-level 5-bit quantization code; then, the capacitor array C a The top plate cuts out the first level margin voltage V RES . In the first stage margin voltage V RES Before the generation, the SAR ADC has been connected to the capacitor array C through switch S4. a The top plate is connected to the clock Φ A When it is high, switch S4 is disconnected, and the SAR ADC instantly samples the first-level margin voltage V RES , then the third comparator is at clock ΦC3 Under the control, the comparison is performed four times in succession to generate the second-level quantization code, that is, the second-level 4-bit quantization code; at the same time, the switch S2 and the switch S3 are closed, and the residual amplifier converts the first-level residual voltage V RES The amplified residual voltage is amplified 16 times and sampled by the combined capacitor array. RES After the amplification is completed, the SAR ADC transmits the 4-bit quantization code to the combined capacitor array, cuts out the second-level residual voltage, and then the second comparator is clocked at Φ C2 The second-stage residual voltage is quantized under control to generate a 5-bit quantization code for the third stage. At this point, the quantization of the three-stage SAR ADC is completed.
[0054] Specifically, the clock Φ C1 Control the first comparator to compare the input signal V IN Is greater than 0 or less than 0, get the corresponding 1-bit quantization code, and switch the switch array S according to the 1-bit quantization code a , switch array S a The corresponding capacitor array C after cutting a The bottom plate will also be cut, and after cutting the capacitor array C a The bottom plate makes the input signal V IN The second comparison is performed based on the changed input signal. The second to fifth comparisons are the same as the first comparisons to generate the first-level quantization code, i.e., the first-level 5-bit quantization code. The corresponding capacitor array C a The top plate cuts out the first level margin voltage V RES .
[0055] The third comparator is at clock Φ C3 Under control, compare the first level margin voltage V RES Is greater than 0 or less than 0, get the corresponding 1-bit quantization code, and switch the switch array S according to the 1-bit quantization code d , switch array S d The corresponding capacitor array C after cutting d The bottom plate will also be cut, and after cutting the capacitor array C d The bottom plate makes the first-stage margin voltage V RES Change, and then perform the second comparison based on the changed first-level residual voltage. The second to fourth comparisons are the same as the first comparison method to generate the second-level quantization code, that is, the second-level 4-bit quantization code.
[0056] The second comparator is at clock Φ C2 Under control, compare whether the second-stage residual voltage is greater than 0 or less than 0, obtain the corresponding 1-bit quantization code, and switch the switch array S according to the 1-bit quantization code c , switch array S c The corresponding capacitor array C after cutting cThe bottom plate will also be cut, and after cutting the capacitor array C c The bottom plate causes the second-level residual voltage to change, and then the second comparison is performed based on the changed second-level residual voltage. The second to fifth comparisons are the same as the first comparison method, generating a third-level quantization code, that is, a 5-bit quantization code of the third level.
[0057] After the quantization of the three-level SAR ADC is completed, the first-level quantization code, the second-level quantization code, and the third-level quantization code may be concatenated to obtain a concatenated quantization code.
[0058] The high-speed hybrid architecture ADC based on parallel residual amplification and quantization of the embodiment of the present invention includes a first-stage SAR ADC, a second-stage SAR ADC and a third-stage SAR ADC; the first-stage SAR ADC is used to collect input signals, quantize the input signals to generate a first-stage quantization code, generate a first-stage residual voltage according to the first-stage quantization code, and amplify the first-stage residual voltage to generate an amplified residual voltage; the second-stage SAR ADC is connected to the first-stage SAR ADC, and is used to parallel quantize the first-stage residual voltage to generate a second-stage quantization code, and generate a second-stage residual voltage according to the second-stage quantization code and the amplified residual voltage; the third-stage SAR ADC is connected to the second-stage SAR ADC, and is used to quantize the second-stage residual voltage to generate a third-stage quantization code. In this way, the high-speed hybrid architecture ADC based on parallel residual amplification and quantization is composed of three-stage SAR ADC, and the parallel quantization of the first-stage residual voltage and the amplification of the first-stage residual voltage can be performed simultaneously, allowing the SAR ADC quantization and the residual amplification to be performed simultaneously, so that the speed of the high-speed hybrid architecture ADC is higher and the power consumption of the operational amplifier is lower.
[0059] Although some specific embodiments of the present invention have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present invention. It should be understood by those skilled in the art that the above embodiments may be modified or some technical features may be replaced by equivalents without departing from the scope and spirit of the present invention. In particular, the various technical features mentioned in the various embodiments may be combined in any manner as long as there is no structural conflict.
[0060] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.
Claims
1. A high-speed hybrid architecture ADC based on parallel residual amplification and quantization, characterized in that: Including a first-stage SAR ADC, a second-stage SAR ADC and a third-stage SAR ADC; The first-stage SAR ADC is used to collect an input signal, quantize the input signal to generate a first-stage quantization code, generate a first-stage residual voltage according to the first-stage quantization code, and amplify the first-stage residual voltage to generate an amplified residual voltage; The second-stage SAR ADC is connected to the first-stage SAR ADC and is used to parallel quantize the first-stage residual voltage to generate a second-stage quantization code, and generate a second-stage residual voltage according to the second-stage quantization code and the amplified residual voltage; The third-level SAR ADC is connected to the second-level SAR ADC and is used to quantize the second-level residual voltage to generate a third-level quantization code.
2. The high-speed hybrid architecture ADC based on parallel residual amplification and quantization according to claim 1, characterized in that: The first-stage SAR ADC includes a switch S1, a switch S2, a residual amplifier, a switch array S a 、Capacitor array C a , a first SAR logic and a first comparator; One end of the switch S1 is connected to the input signal, and the other end of the switch S1 and the capacitor array C a The top plate of the switch S2, one end of the switch S2, the input end of the first comparator and the second stage SAR ADC are all connected, the other end of the switch S2 is connected to the input end of the residual amplifier, the output end of the residual amplifier is connected to the second stage SAR ADC, and the capacitor array C a The bottom plate and the switch array S a One end of the switch array S a The other end of is connected to one end of the first SAR logic, and the other end of the first SAR logic is connected to the output end of the first comparator.
3. The high-speed hybrid architecture ADC based on parallel residue amplification and quantization according to claim 2, characterized in that: The second stage SAR ADC includes a switch S3, a SAR ADC, a switch array S b and capacitor array C b ; One end of the switch S3 is connected to the output end of the residual amplifier, and the other end of the switch S3 and the capacitor array C b The top plate and the third-stage SAR ADC are connected to the capacitor array C b The bottom plate and the switch array S b One end of the switch array S b The other end of the switch S1 is connected to the output end of the SAR ADC, and the input end of the SAR ADC is connected to the other end of the switch S1, the capacitor array C a The top plate, one end of the switch S2, and the input end of the first comparator are connected.
4. The high-speed hybrid architecture ADC based on parallel residual amplification and quantization according to claim 3, characterized in that: The third-stage SAR ADC includes a capacitor array C c , switch array S c , a second SAR logic and a second comparator; The capacitor array C c The top plate is respectively connected to the other end of the switch S3 and the capacitor array C b The top plate of the second comparator is connected to the input terminal of the capacitor array C c The bottom plate and the switch array S c One end of the switch array S c The other end of is connected to one end of the second SAR logic, and the other end of the second SAR logic is connected to the output end of the second comparator.
5. The high-speed hybrid architecture ADC based on parallel residual amplification and quantization according to claim 4, characterized in that: The SAR ADC includes a switch S4, an attenuation capacitor C S , bridge capacitor C B 、Capacitor array C d , switch array S d , a third SAR logic and a third comparator; One end of the switch S4 is connected to the other end of the switch S1 and the capacitor array C a The top plate of the switch S2 is connected to the input end of the first comparator, and the other end of the switch S4 is connected to the attenuation capacitor C S One end of the bridge capacitor C B One end of the attenuation capacitor C is connected to the input end of the third comparator. S The other end of the bridge capacitor C B The other end of the capacitor array C d The top plate of the capacitor array C d The bottom plate and the switch array S d One end of the switch array S d The other end of is connected to one end of the third SAR logic, and the other end of the third SAR logic is connected to the output end of the third comparator.
6. The high-speed hybrid architecture ADC based on parallel residual amplification and quantization according to claim 5, characterized in that: The switch array S a The plurality of first switches and the capacitor array C a The number of the first capacitors in the switch array S is the same. b The plurality of second switches and the capacitor array C b The number of the plurality of second capacitors is the same, and the capacitor array C c The plurality of third capacitors and the switch array S c The number of the third switches is the same as that of the capacitor array C d The plurality of fourth capacitors and the switch array S d The number of the multiple fourth switches in is the same.
7. The high-speed hybrid architecture ADC based on parallel residue amplification and quantization according to claim 6, characterized in that: The number of the plurality of first switches and the plurality of first capacitors is the same as the number of bits of the first-level quantization code, and the number of the plurality of fourth switches and the plurality of fourth capacitors is the same as the number of bits of the second-level quantization code.
8. The high-speed hybrid architecture ADC based on parallel residue amplification and quantization according to claim 6, characterized in that: The number of the plurality of third capacitors and the number of the plurality of third switches are both equal to the number of bits of the third-level quantization code minus 1.
9. The high-speed hybrid architecture ADC based on parallel residual amplification and quantization according to claim 1, characterized in that: The number of bits of the first-level quantization code is 5 bits, the number of bits of the second-level quantization code is 4 bits, and the number of bits of the third-level quantization code is 5 bits.
10. The high-speed hybrid architecture ADC based on parallel residual amplification and quantization according to claim 4, characterized in that: The magnification of the first-stage residual voltage is 16 times, and the capacitor array C b and the capacitor array C c Form a combined capacitor array.