Analog-to-digital conversion device

Abstract

The present disclosure provides an analog-to-digital conversion device including the following elements. The sensing circuit is coupled to a bit line of the memory array and is used for sensing current of the bit line to generate a bit sequence, and the bit sequence has a thermometer code type to represent an analog value. A latch logic circuit includes a plurality of latches and a plurality of logic circuits to form a page buffer of a memory array, and is configured to generate bytes according to a bit sequence, the bytes having a pattern of binary codes to represent digital values. The latch and logic circuit is configured to perform a conversion process to convert the bit sequence into bytes, the conversion process having a bit width.

Description

Technical Field

[0001] The present disclosure relates to an electronic device, and more particularly to an analog-to-digital conversion device. Background Art

[0002] With the advancement of semiconductor technology, memory arrays have the ability to perform in memory computing (IMC) or in memory searching (IMS). The results of in memory computing and in memory searching usually need to be converted from analog to digital to obtain digital values; and an analog to digital conversion device must be used to perform the analog to digital conversion.

[0003] Analog-to-digital converters include several commonly used types: flash analog-to-digital converters (flash ADCs), time-to-digital converters (TDCs), or successive-approximation registers (SARs). However, the above analog-to-digital converters have operational disadvantages. For example, the flash analog-to-digital converter performs parallel input, so the area of ​​its hardware circuit is larger. In addition, when performing the conversion between thermometer code and binary code, the time-to-digital converter performs logical operations based on a flip-flop (DFF), so the area of ​​its hardware circuit is larger and the operation time is longer. Furthermore, the SAR analog-to-digital converter must perform complex output storage and must generate a reference voltage additionally.

[0004] In view of the above issues, an improved analog-to-digital conversion device is needed, which can have a smaller hardware circuit area and a shorter operation time, and can adapt to the architecture of a standard page buffer of a memory array. Summary of the invention

[0005] According to one aspect of the present disclosure, an analog-to-digital conversion device is provided, comprising the following elements: a sensing circuit coupled to a bit line of a storage array and used to sense a current of the bit line to generate a bit sequence, the bit sequence having a thermometer code format to represent an analog value; a latch logic circuit comprising a plurality of latches and a plurality of logic circuits to form a page buffer of the storage array, and used to generate a byte according to the bit sequence, the byte having a binary code format to represent a digital value; the latch and the logic circuit are used to perform a conversion process to convert the bit sequence into a byte, the conversion process having a bit width. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Other aspects and advantages of the present disclosure will become apparent from a review of the following drawings, detailed description, and claims.

[0007] Figure 1 A circuit diagram of an analog-to-digital conversion device according to an embodiment of the present disclosure is schematically shown;

[0008] Figure 2 Schematically shows an embodiment of the present disclosure Figure 1 Circuit diagram of the induction circuit;

[0009] Figure 3A-1 A schematic diagram schematically shows the change of voltage at a node of a sensing circuit relative to time according to an embodiment of the present disclosure;

[0010] Figure 3A-2 A schematic diagram schematically shows the voltage of a node and the change of the voltage of the node according to an embodiment of the present disclosure;

[0011] Figure 3B-1 A schematic diagram schematically shows the change of the voltage of a node relative to time when the analog-to-digital conversion device according to an embodiment of the present disclosure performs two-bit analog-to-digital conversion;

[0012] Figure 3B-2 A schematic diagram schematically shows a voltage of a node and a change of the voltage of a node when the analog-to-digital conversion device according to an embodiment of the present disclosure performs two-bit analog-to-digital conversion;

[0013] Figure 4 A circuit diagram of an analog-to-digital conversion device according to another embodiment of the present disclosure is schematically shown;

[0014] Figure 5 Schematically shows an embodiment of the present disclosure Figure 4 A schematic diagram showing a change in voltage of a node with respect to time when the analog-to-digital conversion device performs three-bit analog-to-digital conversion;

[0015] Figure 6 A circuit diagram of an analog-to-digital conversion device according to another embodiment of the present disclosure is schematically shown;

[0016] Fig. 7A Schematically shows an embodiment of the present disclosure Figure 6 A schematic diagram showing a change in voltage of a node with respect to time when the analog-to-digital conversion device performs four-bit analog-to-digital conversion;

[0017] Figure 7B Schematically illustrates a method for adjusting the initial charge amount of a node in a process in which a latch logic circuit processes a bit to generate a bit according to an embodiment of the present disclosure;

[0018] Figure 7C Schematically shows an embodiment of the present disclosure Fig. 7A A schematic diagram of the time taken to perform input quantization at three time points in an embodiment of the present invention;

[0019] Fig. 8A Schematically shows an embodiment of the present disclosure Figure 6 A schematic diagram of a node voltage and a change in a node voltage when the analog-to-digital conversion device uses a faster input quantization mechanism;

[0020] Figure 8B Schematically shows an embodiment of the present disclosure Figure 6 A schematic diagram showing the change of the voltage of a node with respect to time when the analog-to-digital conversion device uses a faster input quantization mechanism;

[0021] Figure 8C Schematically shows an embodiment of the present disclosure Figure 8B A schematic diagram of the time consumption of performing input quantization at a single time point in an embodiment of the present invention;

[0022] Fig. 9 A circuit diagram of an analog-to-digital conversion device according to another embodiment of the present disclosure is schematically shown;

[0023] Fig.10 Schematically shows an embodiment of the present disclosure Fig. 9 A schematic diagram showing a change in voltage of a node with respect to time when the analog-to-digital conversion device performs five-bit analog-to-digital conversion;

[0024] Fig.11 The diagram schematically shows how the initial charge amount of a node is adjusted during the process of a latch logic circuit processing a bit to generate a bit according to an embodiment of the present disclosure.

[0025] Description of reference numerals:

[0026] 1000, 1001, 1002, 1003: Analog-to-digital conversion device

[0027] 100: Induction circuit

[0028] 110: Sense Amplifier

[0029] 200: Latch logic circuit

[0030] BL: Bit Line

[0031] I BL :Current

[0032] a1: simulation value

[0033] d1: digital value

[0034] {O i}: bit sequence

[0035] O 0 ,O 1 ,O2 ,O 3 :Bit

[0036] {B i}:byte

[0037] B 0 ,B 1 ,B 2 :Bit

[0038] P_IO: Data input / output path

[0039] DL,L1,L2,L3,CDL: latch

[0040] 210: Reverse

[0041] 220,230:NAND gate

[0042] 112,212,223,233: Output

[0043] 111,211,221,222,231,232: Input

[0044] EN INV ,EN AND0 ,EN AND1 :Enable signal

[0045] 120: Capacitor

[0046] 121: One end

[0047] 122: The other end

[0048] 130,140,150,160: Transistors

[0049] SEN,Boost:Node

[0050] BLC 1 ,BLC 2 ,BLC 3 ,SET: Gate voltage

[0051] V SEN ,V Boost :Voltage

[0052] t00,t01,t1,t2,t3,t Defaut ,tMSB1,tMSB2,tMSB3: time point

[0053] tQTZ1, tQTZ2: processing time

[0054] V SEN01 ,V' SEN01 : Initial voltage

[0055] SA_V TH :Threshold voltage

[0056] tSEN: operating time

[0057] strobe: flash control

[0058] V L :Low Voltage

[0059] Q1, Q2, Q3: latching elements

[0060] TDC: Time Domain to Digital Converter

[0061] SAR: Continuous Asymptotic Storage

[0062] 1.5Q, 2.5Q, 3.5Q, 4.5Q, 5.5Q, 6.5Q, ​​7.5Q: equivalent charge

[0063] 1Q, 2Q, 3Q, 4Q, 5Q, 6Q, 7Q, 8Q: equivalent charge

[0064] ∆(V Boost )_0,∆(V Boost )_1,(V Boost )_2: Voltage difference. DETAILED DESCRIPTION

[0065] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0066] The terms used herein are only for describing specific embodiments and are not intended to limit the present disclosure. The terms "comprise", "include", etc. used herein indicate the existence of the features, steps, operations and / or components, but do not exclude the existence or addition of one or more other features, steps, operations or components.

[0067] The technical terms in this specification refer to the customary terms in the technical field. If some terms are explained or defined in this specification, the interpretation of these terms shall be based on the explanation or definition in this specification. Each embodiment of the present disclosure has one or more technical features. Under the premise of possible implementation, a person with ordinary knowledge in the technical field can selectively implement some or all of the technical features in any embodiment, or selectively combine some or all of the technical features in these embodiments.

[0068] Figure 1 FIG. 1 is a circuit diagram of an analog-to-digital conversion device 1000 according to an embodiment of the present disclosure. Figure 1 As shown, the analog-to-digital conversion device 1000 is coupled to one of the bit lines BL ( Figure 1 The memory array is not shown. The memory array is, for example, an array of NAND flash or an array of NOR flash, etc. In the memory array, the memory string corresponding to the bit line BL performs in memory computing (IMC) or in memory searching (IMS), and the bit line BL generates a current I BL To indicate the operation result or search result. BL Has a simulated value a1.

[0069] The analog-to-digital conversion device 1000 includes a sensing circuit 100 and a latch logic circuit 200. The sensing circuit 100 is coupled to the bit line BL. BL The sensing is performed and a sensing result is generated. The sensing result can be represented as a bit sequence {O i} to reflect the current I BL The analog value a1. The bit sequence {O i} includes multiple bits O 0 , O 1 , O 2 ,etc.

[0070] The analog-to-digital conversion device 1000 is used to perform analog-to-digital conversion to convert the current I BL The analog value a1 is converted into a digital value d1. The digital value d1 can be represented as a byte {B i}. Byte {B i} includes multiple bits B 1 , B 2 , etc. The analog-to-digital conversion device 1000 of this embodiment performs two-bit (i.e., the bit width is equal to two) analog-to-digital conversion according to the mechanism of time to digital conversion (TDC), and the generated digital value d1 includes two bits B 1 With B 0 .

[0071] The sensing circuit 100 includes a sensing amplifier (SA) 110. An input terminal 111 of the sensing amplifier 110 is coupled to a bit line BL. An output terminal 112 of the sensing amplifier 110 is coupled to a latch logic circuit 200. The latch logic circuit 200 is coupled to the output terminal 112 of the sensing amplifier 110. The latch logic circuit 200 is used to process the sensing result generated by the sensing circuit 100 to convert the bit sequence {0 i} represents the analog value a1 converted into a byte {B i} represents the digital value d1. Furthermore, the latch logic circuit 200 transmits the generated digital value d1 to the external circuit ( Figure 1 (External circuit is not shown). In one example, the external circuit is an accumulator, and the data input / output path P_IO is provided corresponding to the bit line BL.

[0072] More specifically, the latch logic circuit 200 has a circuit architecture of a "page buffer". The page buffer can be adapted to the architecture and operation of the memory array. The latch logic circuit 200 includes a latch DL, latches L1-L3, and a latch CDL to perform a latching function. In addition, the latch logic circuit 200 includes a plurality of logic circuits to perform logic operations, such as an inverter 210, a NAND gate 220, and a NAND gate 230. The latch DL is coupled to the output terminal 112 of the sense amplifier 110 to receive and store the bit sequence {0 generated by the sense circuit 100}. i The latch CDL outputs the byte {B via the data input / output path P_IO i}.

[0073] In this embodiment, the input terminal 211 of the inverter 210, the input terminal 221 of the NAND gate 220 and the input terminal 231 of the NAND gate 230 are commonly coupled to the latch DL, the latch L2 and the latch L3. Another input terminal 222 of the NAND gate 220 is coupled to the latch L3, and another input terminal 232 of the NAND gate 230 is coupled to the latch CDL. In addition, the output terminal 212 of the inverter 210 is coupled to the latch L1, and the output terminal 223 of the NAND gate 220 and the output terminal 233 of the NAND gate 230 are commonly coupled to the latch CDL. In addition, the inverter 210, the NAND gate 220 and the NAND gate 230 receive the enable signal EN respectively. INV , enable signal EN AND0 With the enable signal EN AND1 .

[0074] Figure 2 for Figure 1 The circuit diagram of the sensing circuit 100 is shown in FIG. Figure 2 As shown, the sensing circuit 100 includes a sensing amplifier 110, four transistors 130, 140, 150 and 160, and a capacitor 120. The current I BL Flows through transistors 150 and 160. Transistor 160 is coupled in series to transistor 150, and transistor 150 is connected to input terminal 111 of sense amplifier 110. One terminal of transistor 140 is coupled between transistors 150 and 160. Transistor 130 has a gate voltage SET, and transistor 140 has a gate voltage BLC. 2, transistor 150 has a gate voltage BLC 3 , transistor 160 has a gate voltage BLC 1 .

[0075] One terminal 121 of the capacitor 120, one terminal of the transistor 130 and the input terminal 111 of the sense amplifier 110 are coupled to a node SEN. The node SEN has a voltage V SEN Voltage V SEN The other end 122 of the capacitor 120 is coupled to the node Boost. The node Boost has a voltage V Boost Voltage V Boost It can be called the "second node voltage".

[0076] The sensing circuit 100 can detect the voltage V SEN Set to the initial voltage V SEN01 Furthermore, the sensing circuit 100 can set the node SEN to have an initial charge amount Q SEN . Initial charge Q SEN Equal to the initial voltage V SEN01 Multiply by the equivalent capacitance C of node SEN SEN , as shown in formula (1-1).

[0077] (1-1)

[0078] Figure 3A-1 is the voltage V at the node SEN of the sensing circuit 100 SEN Schematic diagram of the change with respect to time t. Please also see Figure 2 and Figure 3A-1 If the sensing circuit 100 is in the off state (also called "OFF cell"), the sensing circuit 100 does not allow current to flow, so the node SEN will not discharge, and the voltage V SEN Maintain the initial voltage V SEN01 On the contrary, if the sense amplifier 110 is in the on state (also called “ON cell”), the current I BL can flow through the sensing circuit 100 and can pass the current I BL The node SEN is discharged to make the voltage V SEN decline.

[0079] The sense amplifier 110 has a threshold voltage SA_V TH The sense amplifier 110 may include a differential amplifier ( Figure 2 The differential amplifier is not shown), the threshold voltage SA_V of the sense amplifier 110 THFor example, it is a reference voltage at one of the input terminals of a differential amplifier. In the on state “ON cell” of the sense amplifier 110, the voltage V SEN As time t continues to decrease, the voltage V SEN At the time point tDefault, it drops to the threshold voltage SA_V TH The period tSEN from the time point t01 to the time point tDefault may be referred to as an "execution period".

[0080] Figure 3A-2 is the voltage V at the node SEN SEN The voltage V Boost See also Figure 2 and Figure 3A-2 In the initial stage of the operation of the sensing circuit 100, the sensing circuit 100 charges the node SEN so that the voltage V SEN At time t00, the voltage is raised to the initial voltage V SEN01 Through the coupling effect of capacitor 120, the voltage V Boost At time t00, it is also increased to the initial voltage V' SEN01 .

[0081] Then, the current I flowing through the bit line BL BL The node SEN is discharged, and the voltage V SEN The voltage starts to decrease from the time point t01 and decreases to the threshold voltage SA_V of the sense amplifier 110 at the time point tDefault. TH During the execution period tSEN between the time point t01 and the time point tDefault, the operation of the sensing circuit 100 may be referred to as “bit line toggling”.

[0082] The voltage V of the node Boost Boost At time tDefault, it drops to the low voltage V L , through the coupling effect of capacitor 120, the voltage V SEN At time tDefault, the voltage V Boost Drops to low voltage V L The operation may be referred to as “strobe” of the sense amplifier 110 .

[0083] When the sense amplifier 110 performs flash control at the time point tDefault, the sense amplifier 110 generates a voltage V SEN and threshold voltage SA_V TH The relationship between the corresponding bit O iIf the voltage of the node SEN at time point tDefault is greater than the threshold voltage SA_V TH (as shown in equation (1-2)), the bit O generated by the sense amplifier 110 is i is the logical value "0". Among them, the current I BL Multiplying by the execution period tSEN equals the difference in the amount of charge discharged from the node SEN . Charge difference Divide by the equivalent capacitance C of node SEN SEN Equal to the voltage difference of the node SEN discharge . Initial voltage V SEN01 Subtract the voltage difference is equal to the voltage of the node SEN at time point tDefault.

[0084] (1-2)

[0085] On the contrary, if the voltage of the node SEN at the time point tDefault is less than the threshold voltage SA_V TH (as shown in equation (1-3)), the bit O generated by the sense amplifier 110 is i The logical value is "1".

[0086] (1-3)

[0087] Figure 3B-1 When the analog-to-digital conversion device 1000 performs two-bit analog-to-digital conversion, the voltage V SEN Schematic diagram of the changes with respect to time t. Figure 3B-2 When the analog-to-digital conversion device 1000 performs two-bit analog-to-digital conversion, the voltage V SEN The voltage V Boost See also Figure 2 , Figure 3B-1 and Figure 3B-2 In order to perform two-bit analog-to-digital conversion, the sensing circuit 100 sets three time points t2, t1 and t0 to perform sequential input quantization. The time points t2, t1 and t0 can be referred to as "sensing time points". The sensing circuit 100 performs flash control operations at the time points t2, t1 and t0 to generate three bits O respectively. 2 , O 1 With O 0 The sensing circuit 100 performs a bit line recovery operation on the bit line BL at time points t2, t1, and t0, respectively.

[0088] For example, the current I of the sensing circuit 100 through the bit line BL BL For node SEN to discharge, the voltage V SEN The voltage starts to decrease from time point t01 and decreases to the threshold voltage SA_V of the sense amplifier 110 at time point t2. TH , and executes the flash control operation at time point t2 to generate bit O 2 At time point t2, the difference in the amount of charge discharged from node SEN is Equal to the current I BL Multiply the time difference between time point t2 and time point t01. Similarly, the sensing circuit 100 performs a flash control operation at time point t1 to generate bit O 1 , the difference in charge discharged from node SEN at time point t1 Equal to the current I BL The time difference between the time point t1 and the time point t01 is multiplied. Furthermore, the sensing circuit 100 performs a flash control operation at the time point t0 to generate a bit O 0 , the charge difference of node SEN discharged at time t0 Equal to the current I BL Multiply by the time difference between time point t0 and time point t01.

[0089] The three bits O generated by the sensing circuit 100 at time points t2, t1 and t0 are 2 , O 1 With O 0 The latch logic circuit 200 includes a plurality of latches and a plurality of logic circuits for performing a conversion process to convert the bit 0 of the thermometer code to the bit 1 of the thermometer code. 2 , O 1 With O 0 Converted into two bits B in binary code 1 With B 0 , to form the digital value d1. That is, the latch logic circuit 200 performs a conversion process to convert the bit sequence {0 i}Converted into binary byte {B i The bit width of the conversion process performed by the latch logic circuit 200 is equal to the bit width of the analog-to-digital conversion performed by the analog-to-digital conversion device 1000. The bit width of this embodiment is equal to two.

[0090] Table 1-1

[0091]

[0092] Table 1-1 shows the position O of the thermometer code 2 , O 1 With O 0 Converted into binary code bit B1 With B 0 For example, when bit 0 2 , O 1 With O 0 When it is "0,0,0", it is converted to bit B 1 With B 0 is "0,0". 2 , O 1 With O 0 When it is "0,0,1", it is converted to bit B 1 With B 0 is "0,1", and so on. According to Table 1-1, we can get bit O 2 , O 1 With O 0 With position B 1 With B 0 The truth value conversion is as shown in equation (2-1) and equation (2-2).

[0093] (2-1)

[0094] (2-2)

[0095] Please see again Figure 1 The inverter 210, NAND gate 220 and NAND gate 230 of the latch logic circuit 200 are used to perform the truth value conversion between the thermometer code and the binary code in Table 1-1. More specifically, the inverter 210, NAND gate 220 and NAND gate 230 are respectively activated according to the enable signal EN. INV , enable signal EN AND0 With the enable signal EN AND1 It is enabled to perform logic operations in different operation cycles and cooperates with latches DL, L1, L2, L3 and CDL to convert bit 0 of the thermometer code to 2 , O 1 With O 0 According to equation (2-1) and equation (2-2), the bit B converted into binary code 1 With B 0 Please refer to Table 1-2 and Table 1-3 for the logic operation of the latch logic circuit 200. First, in the operation cycle "Cycle 1", the following operations are performed: (1) The bit O obtained at time point t2 2 Stored in latch DL. (2) Bit 0 stored in latch DL 2 Sent to latch L3.

[0096] Then, in the next operation cycle "Cycle 2", the following operations are performed: (1) The bit O obtained at time point t1 1 Stored in latch DL. (2) Bit 0 stored in latch DL1 The latch L3 stores bit 0. 2 The NAND operation is performed by the NAND gate 220 to obtain . And the result of the operation is (3) Inverter 210 stores bit 0 in latch DL. 1 Reverse and stored in latch L1. (4) Bit O stored in latch DL 1 is transmitted to latch L2. (5) Latch L3 stores Transferred to latch CDL.

[0097] Then, in the next operation cycle "Cycle 3", the following operations are performed: (1) Bit 0 stored in latch DL is 1 Transferred to latch L3. (2) Bit O obtained at time t1 0 Stored in latch DL. (3) Bit O stored in latch DL 0 The latch L3 stores bit 0. 1 The NAND operation is performed by the NAND gate 220 to obtain , and the result of the operation Stored in latch L3. (4) Latch CDL stores The latch L3 stores The NAND operation is performed by the NAND gate 230 to obtain And stored in the latch CDL.

[0098] Table 1-2

[0099]

[0100] Table 1-3

[0101]

[0102] Figure 4 FIG. 1 is a circuit diagram of an analog-to-digital conversion device 1001 according to another embodiment of the present disclosure. The analog-to-digital conversion device 1001 according to this embodiment is used to perform three-bit (i.e., the bit width is equal to three) analog-to-digital conversion, and the generated digital value d1 may include three bits B 2 , B 1 With B 0 Compared to Figure 1 The analog-to-digital conversion device 1000 of this embodiment further includes a latch element Q1. The latch element Q1 is coupled to the latch DL of the latch logic circuit 200 and the sensing circuit 100. The latch element Q1 is used to set the initial charge Q of the node SEN of the sensing circuit 100. SEN .

[0103] Figure 5 for Figure 4 When the analog-to-digital conversion device 1001 performs three-bit analog-to-digital conversion, the voltage V at the node SEN SEN Schematic diagram of the change with respect to time t. Please also see Figure 4 and Figure 5 The sensing circuit 100 of the present embodiment sets four time points tMSB1, t2, t1 and t0 to perform sequential input quantization. More specifically, according to the mechanism of successive-approximation register (SAR), the analog-to-digital conversion device 1001 generates the most significant bit (MSB) of bit B at time point tMSB1. 2 After the sensing circuit 100 senses at time tMSB1, the initial charge Q of the node SEN is latched by the latch element Q1. SEN is set to an equivalent charge amount Q or an equivalent charge amount 2Q. In one example, the equivalent capacitance C of the node SEN can be SEN Set to 2 times, or the voltage difference that discharges node SEN Set it to 2 times. Alternatively, set the equivalent capacitance C SEN Set to 1.4 times, or the discharge voltage difference Set to 1.4 times.

[0104] Then, according to the mechanism of time domain to digital conversion (TDC), the analog-to-digital conversion device 1001 generates two bits B of the least significant bit (LSB) at time points t2, t1 and t0. 1 With B 0 .

[0105] Table 2-1

[0106]

[0107] Table 2-1 shows the position O of the thermometer code 0 ~O 6 Converted into binary code bit B 0 ~B 2 According to Table 2-1, we can get the truth table of bit O 0 ~O 6 With position B 0 ~B 2 The conversion relationship is as shown in Formula (3-1) to Formula (3-3).

[0108] (3-1)

[0109] (or O 5) (3-2)

[0110] (or ) (3-3)

[0111] The inverter 210, the NAND gate 220 and the NAND gate 230 of the latch logic circuit 200 perform a logic operation to convert the bit 0 of the thermometer code to 0 ~O 6 According to formula (3-1) ~ formula (3-3), the bit B converted into binary code 0 ~B 2 Please refer to Table 2-2 and Table 2-3 for the logic operation of the latch logic circuit 200. First, in the operation cycle "Cycle 1", the following operations are performed: (1) The bit O obtained at time point t3 3 Stored in latch DL, bit 0 3 Transmitted to latch CDL. (2) Latch element Q1 stores bit O 3 To replace the originally stored logical value "1".

[0112] Then, in operation cycle "Cycle 2", the following operations are performed: (1) Bit 0 stored in latch DL is 3 Sent to latch L3.

[0113] Then, in the next operation cycle "Cycle 3", the following operations are performed: (1) Bit 0 stored in latch DL is 1 The latch L3 stores bit 0. 2 The NAND operation is performed by the NAND gate 220 to obtain . And the result of the operation is Stored in latch L3. (2) Latch L3 stores (3) Inverter 210 converts the bit 0 stored in latch DL into 1 Reverse and stored in latch L1. (4) Bit O stored in latch DL 1 Transferred to latch L2.

[0114] Then, in the next operation cycle "Cycle 4", the following operations are performed: (1) The O stored in latch L1 0 Transmitted to latch L3. (2) Latch L3 stores O 0 The latch DL stores The NAND operation is performed by the NAND gate 220 to obtain , and stored in latch L3. (3) Latch L3 stores The latch CDL stores The NAND operation is performed by the NAND gate 220 to obtain .

[0115] Table 2-2

[0116]

[0117] Table 2-3

[0118]

[0119] Figure 6 FIG. 1 is a circuit diagram of an analog-to-digital conversion device 1002 according to another embodiment of the present disclosure. The analog-to-digital conversion device 1002 according to this embodiment is used to perform analog-to-digital conversion of four bits (ie, the bit width is equal to four), and the generated digital value d1 may include four bits B 3 , B 2 , B 1 With B 0 Compared to Figure 4 The analog-to-digital conversion device 1001 of the present embodiment further includes another latch element Q2. The latch element Q2 and Q1 are both coupled to the latch DL of the latch logic circuit 200 and the sensing circuit 100. The latch element Q2 and Q1 are used to set the initial charge Q of the node SEN of the sensing circuit 100. SEN .

[0120] Fig. 7A for Figure 6 When the analog-to-digital conversion device 1002 performs a four-bit analog-to-digital conversion, the voltage V at the node SEN SEN Schematic diagram of the change with respect to time t. Please also see Figure 6 and Fig. 7A The sensing circuit 100 of this embodiment sets five time points tMSB2, tMSB1, t2, t1 and t0 to perform sequence input quantization. The initial charge Q of the node SEN is latched by latch elements Q2 and Q1. SEN The equivalent charge is set to 2.5Q. According to the mechanism of continuous asymptotic register (SAR), the analog-to-digital converter 1002 generates the most significant bit (MSB) bit B3 at time point tMSB2. Then, it is selectively adjusted to the equivalent charge of 3.5Q or 1.5Q, and according to the mechanism of continuous asymptotic register, the most significant bit (MSB) bit B is generated at time point tMSB1. 2Then, the initial charge QSEN of the node SEN is set to an equivalent charge Q through latch elements Q1 and Q2. Then, it is selectively adjusted to an equivalent charge of 2Q, 3Q or 4Q. According to the mechanism of time domain to digital conversion (TDC), the analog-to-digital conversion device 1002 generates two bits B of the least significant bit (LSB) at time points t2, t1 and t0 respectively. 1 With B 0 Table 3-1 shows the position O of the thermometer code 0 ~O 14 Converted into binary code bit B 0 ~B 3 Truth table of .

[0121] Table 3-1

[0122]

[0123]

[0124] The inverter 210, the NAND gate 220 and the NAND gate 230 of the latch logic circuit 200 perform a logic operation to convert the bit 0 of the thermometer code to 0 ~O 14 Convert the bit B to binary code 0 ~B 3 , as shown in Table 3-2.

[0125] Table 3-2

[0126]

[0127] and, Figure 7B The latch logic circuit 200 processes bit 0 0 ~O 14 To generate bit B 0 ~B 3 During the process, the initial charge of node SEN is Q SEN Also refer to Table 3-2 and Figure 7B First, the following operations are performed in the operation cycle "Cycle MSB1": (1) The initial charge QSEN of the node SEN is pre-set to an equivalent charge of 2.5Q. (2) The storage data of the latch DL and the storage data of the latch element Q2 are subjected to a "NAND" operation, and the operation result is stored in the latch element Q2. (3) The storage data of the latch DL and the storage data of the latch element Q1 are subjected to a "NAND" operation, and the operation result is stored in the latch element Q1.

[0128] If the latch element Q2 stores a logic value "1", the "NAND" operation of the stored data of the latch DL and the stored data of the latch element Q1 is performed in the subsequent operation cycle "Cycle MSB2", and the operation result is stored in the latch element Q1. Accordingly, the initial charge QSEN of the node SEN is set to an equivalent charge of 3.5Q. On the other hand, if the latch element Q2 stores a logic value "0", the initial charge QSEN of the node SEN is set to an equivalent charge of 3.5Q in the subsequent operation cycle "Cycle MSB2". SEN The equivalent charge is set to 1.5Q.

[0129] Then, in the subsequent operation cycle "Cycle LSB1", the stored data of the latch DL is transmitted to the latch L3. SEN The equivalent charge is 3.5Q, and the latch element Q1 stores the logic value "1", then the initial charge Q SEN Set to an equivalent charge of 4Q. If the latch element Q1 stores a logic value of "0", the initial charge Q SEN Set to an equivalent charge of 3Q. On the other hand, if the current initial charge is Q SEN The equivalent charge is 1.5Q, and the latch element Q1 stores the logic value "1", then the initial charge Q SEN Set to an equivalent charge of 2Q. If the latch element Q1 stores a logic value of "0", the initial charge Q SEN The equivalent charge is set to 1Q.

[0130] Then, in the subsequent operation cycle "Cycle LSB2", the current initial charge Q SEN For example, if the current initial charge Q SEN If the current initial charge is Q SEN If the equivalent charge is 3Q, then the equivalent charge is maintained at 3Q, and so on. More specifically, the following operations are performed in the operation cycle "CycleLSB2": (1) The bit O obtained at time point t1 1 Stored in latch DL. (2) Bit 0 stored in latch DL 1 The latch L3 stores bit 0. 2 The NAND operation is performed via the NAND gate 220, and the operation result is stored in the latch L3. (3) The inverter 210 converts the bit 0 stored in the latch DL into 1 Reverse and stored in latch L1. (4) Bit O stored in latch DL 1 Transferred to latch L2. (5) The stored data in latch L3 is transferred to latch CDL.

[0131] Then, in the subsequent operation cycle "Cycle LSB3", the current initial charge Q SEN The following operations are performed: (1) Bit O stored in latch DL 1 Transferred to latch L3. (2) Bit O obtained at time t1 0 Stored in latch DL. (3) Bit O stored in latch DL 0 The latch L3 stores bit 0. 1 A “NAND” operation is performed via the NAND gate 220, and the operation result is stored in the latch L3. (4) A “NAND” operation is performed on the storage data of the latch CDL and the storage data of the latch L3 via the NAND gate 230, and the operation result is stored in the latch CDL.

[0132] Figure 7C for Fig. 7A 1 is a schematic diagram showing the time taken to perform input quantization at three time points in an embodiment of the present invention. After the bit line BL performs the analog summing operation, the latch logic circuit 200 then generates the bit B 2 , while the sensing circuit 100 performs input quantization at time point t2 to generate bit O 2 Then, at time point t1, input quantization is performed to generate bit O 1 . In office 1 After the input quantization is completed, the latch logic circuit 200 generates bit B 1 , while the sensing circuit 100 performs input quantization at time point t0 to generate bit O 0 . In office 0 After the input quantization is completed, the latch logic circuit 200 generates bit B 0 , and the bit line BL performs the next analog summing operation. In this embodiment, three bit lines 0 are executed at three time points. 2 , O 1 With O 0 To quantize the input, three bit line togglings must be performed. 2 , O 1 With O 0 Quantizing the input may take a processing time tQTZ1.

[0133] When the ADC device 1002 performs four-bit analog-to-digital conversion, a faster input quantization mechanism may also be used. Fig. 8A for Figure 6 When the analog-to-digital conversion device 1002 uses a faster input quantization mechanism, the voltage V SEN The voltage V Boost Schematic diagram of the changes in Fig. 8AAs shown, the voltage V Boost The voltage difference ∆(V Boost )_0、Voltage difference∆(V Boost )_1 and the voltage difference ∆(V Boost )_2, which can be called the "step voltage difference". At the same time, the voltage V SEN According to the above voltage difference ∆(V Boost )_0、Voltage difference∆(V Boost )_1 and the voltage difference ∆(V Boost )_2 gradually decreases.

[0134] Figure 8B for Figure 6 When the analog-to-digital conversion device 1002 uses a faster input quantization mechanism, the voltage V SEN Schematic diagram of the change relative to time t. Fig. 7A The embodiment of the present invention generates two least significant bits (LSB) at time points t2, t1 and t0 respectively. 1 With B 0 , Figure 8B The embodiment is to perform an input quantization mechanism at a single time point t0 to generate two bits B of the least significant bit (LSB) 1 With B 0 , which can reduce the time required for input quantization. At time point t0, according to Figure 8B The three voltage differences ∆(V Boost )_0,∆(V Boost )_1 and ∆(V Boost )_2Perform input quantization.

[0135] At time point t0, the sensing circuit 100 determines the voltage V at the node SEN. SEN The voltage difference between the node Boost and ∆(V Boost )_0 is greater than the threshold voltage SA_V of the sense amplifier 110 TH When the voltage V SEN and the voltage difference ∆(V Boost )_0 is greater than the threshold voltage SA_V TH When (as shown in formula (4-1)), the bit O generated by the sensing circuit 100 0 It is the logical value "0".

[0136] (4-1)

[0137] On the other hand, when the voltage V SEN and the voltage difference ∆(V Boost )_0 is less than the threshold voltage SA_VTH When (as shown in formula (4-2)), the bit O generated by the sensing circuit 100 0 It is a logical value "1".

[0138] (4-2)

[0139] Similarly, at time t0, when the voltage V SEN and the voltage difference ∆(V Boost )_1 is greater than or less than the threshold voltage SA_V TH When the sensing circuit 100 generates a bit O 1 is a logic value "0" or a logic value "1". At time point t0, when the voltage V SEN and the voltage difference ∆(V Boost )_2 is greater than or less than the threshold voltage SA_V TH When the sensing circuit 100 generates a bit O 2 It is a logical value "0" or a logical value "1".

[0140] Furthermore, the most significant bit (MSB) bit B is generated by a sequential asymptotic register (SAR) mechanism. 2 and B 3 . When position B 2 When the logic value is "0", the initial charge Q of the node SEN is latched by the latch elements Q2 and Q1. SEN Set to the equivalent charge Q. When position B 2 When the logic value is "1", the initial charge Q SEN The equivalent charge is set to 2Q.

[0141] Figure 8C for Figure 8B A schematic diagram of the time taken to perform input quantization at a single time point in an embodiment of FIG. Figure 7C In the embodiment of the present invention, the three bits O 2 , O 1 With O 0 The input quantization of can be performed at the same time point, so the three bits O 2 , O 1 With O 0 The processing time tQTZ2 of the input quantization can be reduced. For example, Figure 8C The processing time tQTZ2 for the input quantization of the example is less than Figure 7C The processing time tQTZ1 of the input quantization example is shown in FIG. 2 , O 1 With O 0 The processing time of the input quantization can overlap with the latch logic circuit 200 to generate bit B 1 In the present embodiment, the three bits O2 , O 1 With O 0 During the input quantization process, except that the sense amplifier 110 performs two flashing operations, the sense circuit 100 only needs to perform one bit line triggering, thereby saving operation time.

[0142] Fig. 9 FIG. 1 is a circuit diagram of an analog-to-digital conversion device 1003 of another embodiment of the present disclosure. The analog-to-digital conversion device 1003 of this embodiment is used to perform five-bit (ie, the bit width is equal to five) analog-to-digital conversion, and the generated digital value d1 may include five bits B 4 , B 3 , B 2 , B 1 With B 0 Compared to Figure 6 The analog-to-digital conversion device 1002 of this embodiment further includes a latch element Q3. The latch elements Q1-Q3 are used to set the initial charge amount Q of the node SEN of the sensing circuit 100. SEN .

[0143] Fig.10 for Fig. 9 When the analog-to-digital conversion device 1003 performs five-bit analog-to-digital conversion, the voltage V at the node SEN SEN Schematic diagram of the change relative to time t. Fig. 7A In the embodiment of the present invention, the sensing circuit 100 of the present embodiment further adds a time point tMSB3 to generate the most significant bit (MSB) of the bit B 4 .

[0144] Table 4-1

[0145]

[0146] As shown in Table 4-1, the inverter 210, the NAND gate 220 and the NAND gate 230 of the latch logic circuit 200 perform a logic operation to generate bit B of the binary code. 0 ~B 4 The operation of the latch logic circuit 200 of this embodiment is similar to that of the embodiment of Table 3-2. The difference between the two embodiments is that in Table 4-1, the following operations are performed in the operation cycle "Cycle MSB1": (1) The initial charge QSEN of the node SEN is pre-set to an equivalent charge of 4.5Q. (2) The storage data of the latch DL and the storage data of the latch element Q3 are subjected to a "NAND" operation, and the operation result is stored in the latch element Q3. (3) The storage data of the latch DL and the storage data of the latch element Q2 are subjected to a "NAND" operation, and the operation result is stored in the latch element Q2.

[0147] Fig.11 The latch logic circuit 200 of this embodiment processes bit 0. 0 ~O 14 To generate bit B 0 ~B 3 During the process, the initial charge of node SEN is Q SEN See Fig.11 , the initial charge QSEN of the node SEN is pre-set to an equivalent charge of 4.5Q.

[0148] Then, in the subsequent operation cycle "Cycle MSB2", if the latch element Q3 stores the logic value "1", the initial charge Q SEN Adjust to an equivalent charge of 6.5Q. If the latch element Q3 stores a logic value of "0", the initial charge Q SEN Adjusted to an equivalent charge of 2.5Q.

[0149] Then, in the subsequent operation cycle "Cycle MSB3", if the initial charge Q SEN The equivalent charge is 6.5Q, ​​and the latch element Q2 stores the logic value "1", then the initial charge Q SEN Adjust to an equivalent charge of 7.5Q. If the latch element Q2 stores a logic value of "0", the initial charge Q SEN Adjusted to an equivalent charge of 5.5Q.

[0150] On the other hand, if the initial charge Q SEN The equivalent charge is 2.5Q, and the latch element Q2 stores the logic value "1", then the initial charge Q SEN Adjust to an equivalent charge of 3.5Q. If the latch element Q2 stores a logic value of "0", the initial charge Q SEN Adjusted to an equivalent charge of 1.5Q.

[0151] Then, in the subsequent operation cycle "Cycle LSB1", if the initial charge Q SEN The equivalent charge is 7.5Q, and the latch element Q1 stores the logic value "1", then the initial charge Q SEN If the latch element Q1 stores the logic value "0", the initial charge Q SEN Adjust to an equivalent charge of 7Q. And if the initial charge Q SEN If the equivalent charge is 5.5Q and the latch element Q1 stores the logic value "1", the equivalent charge is adjusted to 6Q. If the latch element Q1 stores the logic value "0", the equivalent charge is adjusted to 5Q. In addition, if the initial charge Q SENIf the equivalent charge is 3.5Q and the latch element Q1 stores the logic value "1", the equivalent charge is adjusted to 4Q. If the latch element Q1 stores the logic value "0", the equivalent charge is adjusted to 3Q. Furthermore, if the initial charge Q SEN If the equivalent charge is 1.5Q and the latch element Q1 stores a logic value of "1", the equivalent charge is adjusted to 2Q. If the latch element Q1 stores a logic value of "0", the equivalent charge is adjusted to 1Q.

[0152] In summary, the analog-to-digital conversion devices of the above-mentioned different embodiments of the present disclosure can adapt to the architecture of a standard page buffer of a memory array (especially a NAND flash memory array), thereby achieving high computing bandwidth and having lower energy consumption.

[0153] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the present disclosure. It should be understood that the above description is only a specific embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure should be included in the protection scope of the present disclosure.

Claims

1. An analog-to-digital conversion device, comprising: a sensing circuit coupled to a bit line of a memory array and used to sense a current of the bit line to generate a bit sequence having a thermometer code format to represent an analog value; and a latch logic circuit, comprising a plurality of latches and a plurality of logic circuits to form a page buffer of the memory array, and used for generating a byte according to the bit sequence, the byte having a binary code format to represent a digital value; The latches and the logic circuits perform a conversion process to convert the bit sequence into the byte, and the conversion process has a one-bit width.

2. The analog-to-digital conversion device according to claim 1, wherein the logic circuits of the latch logic circuit include an inverter and two NAND gates, and the inverter and the NAND gates perform truth value conversion between the thermometer code and the binary code.

3. The analog-to-digital conversion device according to claim 1, wherein the sensing circuit comprises: a sense amplifier having an input terminal coupled to the bit line, the input terminal having a first node having a first node voltage; The sensing circuit generates the bit sequence according to the first node voltage and a threshold voltage of the sensing amplifier.

4. The analog-to-digital conversion device according to claim 3, wherein one of the latches of the latch logic circuit is coupled to an output terminal of the sense amplifier to receive the bit sequence, and another one of the latches is coupled to a data input / output path to transmit the byte.

5. The analog-to-digital conversion device according to claim 3, wherein when the first node voltage is greater than or less than the threshold voltage, the bit sequence has a logic value "0" or a logic value "1". 6 . The analog-to-digital conversion device as claimed in claim 3 , wherein the sensing circuit generates the bit sequence according to a plurality of sensing time points when the first node voltage drops to the threshold voltage. 7 . The analog-to-digital conversion device according to claim 6 , wherein when the bit width of the conversion process is equal to two, the sensing circuit generates the bit sequence according to a first time point, a second time point and a third time point of the sensing time points. 8 . The analog-to-digital conversion device according to claim 7 , wherein the latch logic circuit generates the two least significant bits of the byte through a time domain to digital conversion mechanism according to the first time point, the second time point and the third time point. 9 . The analog-to-digital conversion device according to claim 6 , wherein when the bit width of the conversion process is greater than or equal to three, the sensing circuit generates one bit of the bit sequence according to at least a fourth time point of the sensing time points. 10 . The analog-to-digital conversion device as claimed in claim 9 , wherein the latch logic circuit generates at least one most significant bit of the byte through a continuous asymptotic temporary storage mechanism according to the at least one fourth time point.

11. The analog-to-digital conversion device according to claim 3, further comprising: At least one latch element is coupled to the sensing circuit and is used to set an initial charge amount of the first node.

12. The analog-to-digital conversion device according to claim 11, wherein when the at least one latch element stores a logic value "1" or a logic value "0", the initial charge amount of the first node increases or decreases to an equivalent charge amount. 13 . The analog-to-digital conversion device as claimed in claim 11 , wherein the number of the at least one latch element is equal to the bit width of the conversion process minus two. 14 . The analog-to-digital conversion device as claimed in claim 3 , wherein the first node is coupled to a second node via a capacitor, the second node has a second node voltage, and the first node voltage and the second node voltage gradually decrease according to at least one step voltage difference. 15 . The analog-to-digital conversion device as claimed in claim 14 , wherein the sensing circuit generates the bit sequence according to a difference between the first node voltage and the at least one step voltage difference and the threshold voltage. 16 . The analog-to-digital conversion device as claimed in claim 15 , wherein the sensing circuit generates the bit sequence according to a sensing time point when the first node voltage drops to the threshold voltage.

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