A magnetically isolated codec circuit

Abstract

This invention relates to the field of analog integrated circuit technology, and particularly to a magnetically isolated encoding / decoding circuit, including a transmitter circuit, an isolation transformer, and a receiver circuit. The transmitter circuit includes a logic control circuit, an oscillator, a pulse generation circuit, and a drive circuit. The receiver circuit includes a pulse filtering circuit, a bandgap reference circuit, a comparator circuit, an inverter, and a D flip-flop. This invention, by adding amplitude variation, further pulls up high pulse signals and pulls low pulse signals to ground, filters out common-mode signals, and adds an additional refresh pulse to help monitor signals in real time, greatly improving the anti-interference and reliability of signal transmission, and effectively protecting power switching devices.

Description

Technical Field

[0001] This invention relates to the field of analog integrated circuit technology, and in particular to a magnetically isolated encoding / decoding circuit. Background Technology

[0002] In existing technologies, magnetically coupled digital isolators employ four traditional modulation methods: set-reset modulation, polarity pulse modulation, pulse counting modulation, and on / off keying modulation. Set-reset modulation works by modulating the rising edge of the data signal into one pulse signal and the falling edge into another. The decoding circuit sets the digital isolator output high upon receiving a rising edge pulse and resets the input upon receiving a falling edge pulse. While this modulation method has a simple circuit structure, it is easily affected by noise, leading to bit errors in the output signal and potentially damaging power devices. Summary of the Invention

[0003] To address the issue of noise interference affecting the modulation of set and reset signals in traditional magnetically coupled digital isolators, this invention proposes a magnetically isolated encoding / decoding circuit, comprising a transmitter circuit, an isolation transformer, and a receiver circuit. The transmitter circuit includes a logic control circuit, an oscillator, a pulse generation circuit, and a driver circuit. The receiver circuit includes a pulse filtering circuit, a bandgap reference circuit, a comparator circuit, an inverter, and a D flip-flop.

[0004] The logic control circuit is used to provide clock and switching signals to the drive circuit and enable signals to the pulse generation circuit based on the oscillator and input signals.

[0005] The pulse generation circuit is used to generate a pulse signal according to the enable signal provided by the logic control circuit, and input the generated pulse signal into the drive circuit.

[0006] The drive circuit is used to provide drive signals for the isolation transformer;

[0007] The pulse filtering circuit is used to receive the high pulse signal and low pulse signal coupled from the secondary coil of the isolation transformer and modulate them into two high pulse signals and low pulse signals presented as negative pulses.

[0008] The bandgap reference circuit is used to provide common-mode voltage for the secondary winding of the isolation transformer and bias voltage for the pulse filtering circuit.

[0009] The comparator circuit includes a first comparator and a second comparator. The pulse signal output from the pulse filtering circuit is input to the two comparators with opposite logic. The outputs of the two comparators generate two non-overlapping pulse signals, and the output of the first comparator is used as the input of the CP terminal of the D flip-flop.

[0010] The inverter is used to process the pulse signal output from the second comparator, and the output of the inverter is used as the input to the RESET terminal of the D flip-flop;

[0011] The output of the D flip-flop is used as the output of the circuit to output the restored data signal. The output of the first comparator is connected to the CP terminal of the D flip-flop, and the output of the second comparator is connected to the RESET terminal of the D flip-flop after being inverted. When the first comparator has a pulse, the D flip-flop follows the high voltage of the output voltage terminal until the RESET terminal receives the inverted pulse signal of the second comparator, and then clears the output to zero.

[0012] This invention improves the anti-interference ability and reliability of signal transmission by adding amplitude variation, further pulling up the high pulse signal and pulling down the low pulse signal to ground, filtering out the common-mode signal, and adding an additional refresh pulse to help monitor the signal in real time, which effectively protects the power switching device. Attached Figure Description

[0013] Figure 1 This is a structural diagram of the gate magnetic isolation encoding / decoding circuit of the present invention;

[0014] Figure 2 This is the schematic diagram of the DRIVER circuit of this invention;

[0015] Figure 3 This is a schematic diagram of the DRIVER working mode 1 of the present invention;

[0016] Figure 4 This is a schematic diagram of the DRIVER working mode 2 of the present invention;

[0017] Figure 5 This is a timing diagram of the DRIVER operation of this invention;

[0018] Figure 6 This is the circuit schematic diagram of the FLITER of this invention;

[0019] Figure 7 This is the simulation result of the digital isolator of this invention completing signal restoration. Detailed Implementation

[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] This invention proposes a magnetically isolated encoding / decoding circuit, including a transmitter circuit, an isolation transformer, and a receiver circuit. The transmitter circuit includes a logic control circuit, an oscillator, a pulse generation circuit, and a drive circuit. The receiver circuit includes a pulse filtering circuit, a bandgap reference circuit, a comparator circuit, an inverter, and a D flip-flop, wherein:

[0022] The logic control circuit is used to provide clock and switching signals to the drive circuit and enable signals to the pulse generation circuit based on the oscillator and input signals.

[0023] The pulse generation circuit is used to generate a pulse signal according to the enable signal provided by the logic control circuit, and input the generated pulse signal into the drive circuit.

[0024] The drive circuit is used to provide drive signals for the isolation transformer;

[0025] The pulse filtering circuit is used to receive the high pulse signal and low pulse signal coupled from the secondary coil of the isolation transformer and modulate them into two high pulse signals and low pulse signals presented as negative pulses.

[0026] The bandgap reference circuit is used to provide common-mode voltage for the secondary winding of the isolation transformer and bias voltage for the pulse filtering circuit.

[0027] The comparator circuit includes a first comparator and a second comparator. The pulse signal output from the pulse filtering circuit is input to the two comparators with opposite logic. The outputs of the two comparators generate two non-overlapping pulse signals, and the output of the first comparator is used as the input of the CP terminal of the D flip-flop.

[0028] The inverter is used to process the pulse signal output from the second comparator, and the output of the inverter is used as the input to the RESET terminal of the D flip-flop;

[0029] The output of the D flip-flop is used as the output of the circuit to output the restored data signal. The output of the first comparator is connected to the CP terminal of the D flip-flop, and the output of the second comparator is connected to the RESET terminal of the D flip-flop after being inverted. When the first comparator has a pulse, the D flip-flop follows the high voltage of the output voltage terminal until the RESET terminal receives the inverted pulse signal of the second comparator, and then clears the output to zero.

[0030] like Figure 1 In this embodiment, the following is provided: Figure 1The illustrated encoder / decoder circuit based on magnetic isolation, used in SiC MOSFET isolation drivers, mainly includes a transmitter circuit, an isolation transformer, and a receiver circuit. The transmitter circuit includes a logic control circuit, an oscillator (OSC), a pulse generator circuit, and a driver circuit. The receiver circuit includes a pulse filter circuit, a bandgap reference circuit (BG2), a comparator circuit, an inverter (INV), and a D flip-flop (DFF). The comparator circuit includes a first comparator COMP1 and a second comparator COMP2. The isolation transformer includes two transformers, namely a first transformer Transformer1 and a second transformer Transformer2.

[0031] This embodiment provides a specific implementation method for a driving circuit, such as... Figure 2 The circuit includes a first transmission gate TG1, a second transmission gate TG2, a third transmission gate TG3, a fourth transmission gate TG4, a first P-type MOSFET PM1, a second P-type MOSFET PM2, a first N-type MOSFET NM1, a second N-type MOSFET NM2, a first transistor Q1, and a second transistor Q2, wherein:

[0032] The input of the first transmission gate TG1 is connected to the high pulse signal HPULSE output by the pulse generation circuit. The positive control terminal of the first transmission gate TG1 is connected to the second clock signal CLKN generated by the logic control circuit. The negative control terminal of the first transmission gate TG1 is connected to the first clock signal CLK generated by the logic control circuit. The output of the first transmission gate TG1 is connected to the output terminal of the third transmission gate TG3, the drain of the first P-type MOSFET PM1, the drain of the first N-type MOSFET NM1, and the base of the first transistor Q1.

[0033] The input of the second transmission gate TG2 is connected to the high pulse signal HPULSE output by the pulse generation circuit. The positive control terminal of the second transmission gate TG2 is connected to the first clock signal CLK generated by the logic control circuit. The negative control terminal of the second transmission gate TG2 is connected to the second clock signal CLKN generated by the logic control circuit. The output terminal of the second transmission gate TG2 is connected to the output terminal of the fourth transmission gate TG4, the drain of the second P-type MOSFET PM2, the drain of the second N-type MOSFET NM2, and the base of the second transistor Q2.

[0034] The input of the third transmission gate TG3 is connected to the low pulse signal LPULSE output by the pulse generation circuit. The positive control terminal of the third transmission gate TG3 is connected to the first clock signal CLK generated by the logic control circuit. The negative control terminal of the third transmission gate TG3 is connected to the second clock signal CLKN generated by the logic control circuit.

[0035] The input of the fourth transmission gate TG4 is connected to the low pulse signal LPULSE output by the pulse generation circuit. The positive control terminal of the fourth transmission gate TG4 is connected to the second clock signal CLKN generated by the logic control circuit. The negative control terminal of the fourth transmission gate TG4 is connected to the first clock signal CLK generated by the logic control circuit.

[0036] The gate of the first P-type MOSFET PM1 is connected to the first control signal A output by the logic control circuit, and the source is connected to the power supply terminal VCC and the collector of the first transistor Q1.

[0037] The gate of the second P-type MOSFET PM2 is connected to the third control signal C output by the logic control circuit, and the source is connected to the power supply terminal VCC and the collector of the second transistor Q2.

[0038] The gate of the first N-type MOSFET NM1 is connected to the second control signal B output by the logic control circuit, and the source is connected to the ground terminal GND.

[0039] The gate of the second N-type MOSFET NM2 is connected to the fourth control signal D output by the logic control circuit, and the source is connected to the ground terminal GND.

[0040] The emitter of the first transistor Q1 is connected to the first primary input signal IFP of the isolation transformer; the emitter of the second transistor Q2 is connected to the second primary input signal IFM of the isolation transformer.

[0041] The first clock signal CLK and the second clock signal CLKN are two complementary clock signals. The first control signal A, the second control signal B, the third control signal C, and the fourth control signal D are four signals used to control whether the gates of the first P-type MOSFET, the first N-type MOSFET, the second P-type MOSFET, and the second N-type MOSFET are turned on.

[0042] In this embodiment, the driving circuit has two operating modes, controlled by a first clock signal CLK and a second clock signal CLKN. The first operating mode is as follows: Figure 3 In this operating mode, the first clock signal CLK and the second clock signal CLKN are used to control the opening of the first and fourth transmission gates and the closing of the second and third transmission gates. At this time:

[0043] like Figure 3(a) When the transistor is in the charging state, the first P-type MOSFET and the second N-type MOSFET are turned on by the first control signal A and the fourth control signal D, and the second P-type MOSFET and the first N-type MOSFET are turned off by the second control signal B and the third control signal C. At this time, the high pulse signal HPULSE generated by the pulse generation circuit flows into the first transistor Q1 through the first transmission gate TG1. The first P-type MOSFET PM1 assists in pulling up, so that the high pulse signal HPULSE path obtains a higher pulse amplitude. Therefore, the first transformer Transformer1 induces a high pulse level. The low pulse signal flows into the second transistor Q2 through the fourth transmission gate TG4. The second N-type MOSFET NM2 assists in pulling down, so that the low pulse signal path obtains a downward pulse. Therefore, the second transformer Transformer2 induces a low pulse level.

[0044] like Figure 3 (b) When the transistor is in the discharge state, that is, the first P-type MOSFET, the second P-type MOSFET, the first N-type MOSFET, and the second N-type MOSFET are turned off by the first control signal A, the second control signal B, the third control signal C, and the fourth control signal D. The base voltage of the first transistor and the second transistor follow the falling edge of the high and low pulses respectively, and the current in the transformer gradually decreases, coupling out a negative pulse.

[0045] The second operating mode of the drive circuit is as follows Figure 3 In this operating mode, the first clock signal CLK and the second clock signal CLKN are used to control the opening of the second and third transmission gates and the closing of the first and fourth transmission gates. At this time:

[0046] like Figure 4 (a) When the transistor is in the charging state, the first N-type MOSFET and the second P-type MOSFET are turned on using the second control signal B and the third control signal C, respectively, and the first P-type MOSFET and the second N-type MOSFET are turned off using the first control signal A and the fourth control signal D, respectively. At this time, the high pulse signal HPULSE generated by the pulse generation circuit flows into the second transistor Q2 through the second transmission gate TG2. The second P-type MOSFET PM2 assists in pulling up, so that the high pulse signal HPULSE path obtains a higher pulse amplitude. Therefore, the second transformer Transformer 2 induces a high pulse level. The low pulse signal flows into the first driver transistor Q1 through the third transmission gate TG3. The first N-type MOSFET NM1 assists in pulling down, so that the low pulse signal path obtains a downward pulse. Therefore, the first transformer Transformer 1 induces a low pulse level.

[0047] like Figure 4(b) When the transistor is in the discharge state, that is, the first P-type MOSFET, the first N-type MOSFET, the second P-type MOSFET, and the second N-type MOSFET are turned off by the first control signal A, the second control signal B, the third control signal C, and the fourth control signal D respectively. The base voltages of the first transistor Q1 and the second transistor Q2 follow the falling edge of the high and low pulses respectively. The current in the transformer gradually decreases, and a negative pulse is coupled out.

[0048] like Figure 5 This embodiment provides the timing relationship of the first clock signal CLK, the second clock signal CLKN, the first control signal A, the second control signal B, the third control signal C, and the fourth control signal D in two modes of the driving circuit. The first mode is when the first clock signal CLK is low and the second clock signal CLKN is high; the second mode is when the first clock signal CLK is high and the second clock signal CLKN is low. When the first control terminal A outputs a low pulse signal, the first P-type MOSFET is turned on; when the fourth control terminal outputs a high pulse signal, the second N-type MOSFET is turned on; when the second control terminal B remains low, the first N-type MOSFET is turned off; and when the third control terminal C remains high, the second P-type MOSFET is turned off. Similarly, when the first control terminal A remains high, the first P-type MOSFET is turned off; when the fourth control signal D remains low, the second N-type MOSFET is turned off; when the second control terminal B outputs a high pulse signal, the first N-type MOSFET is turned on; and when the third control terminal C outputs a low pulse signal, the second P-type MOSFET is turned on.

[0049] This embodiment also provides a specific implementation of a pulse filtering circuit, which includes a third N-type MOSFET NM3, a fourth N-type MOSFET NM4, a fifth N-type MOSFET NM5, a sixth N-type MOSFET NM6, a seventh N-type MOSFET NM7, an eighth N-type MOSFET NM8, a ninth N-type MOSFET NM9, a tenth N-type MOSFET NM10, an eleventh N-type MOSFET NM11, a twelfth N-type MOSFET NM12, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6, as follows. Figure 6 ,in:

[0050] The gate of the third N-type MOSFET NM3, the bias voltage VO1 provided by the bandgap reference circuit, the gate of the fourth N-type MOSFET NM4, the gate of the fifth N-type MOSFET NM5, and the gate of the sixth N-type MOSFET NM6 are connected together.

[0051] The drain of the third N-type MOSFET, the power supply terminal VCC, the upper end of the first resistor R1, the upper end of the second resistor R2, and the drain of the sixth N-type MOSFET NM6 are connected together.

[0052] The source of the third N-type MOSFET is connected to the upper end of the third resistor R3;

[0053] The drain of the fourth N-type MOSFET NM4, the lower end of the first resistor R1, and the drain of the twelfth N-type MOSFET NM12 are connected together and serve as the second pulse output terminal OUTM of the pulse filtering circuit. The source of the fourth N-type MOSFET NM4 is connected to the upper end of the fourth resistor R4.

[0054] The drain of the fifth N-type MOSFET NM5, the lower end of the second resistor R2, and the drain of the eleventh N-type MOSFET NM11 are connected together and serve as the first pulse output terminal OUTP of the pulse filtering circuit; the source of the fifth N-type MOSFET NM5 is connected to the upper end of the fifth resistor R5.

[0055] The source of the sixth N-type MOSFET NM6 is connected to the upper end of the sixth resistor R6;

[0056] The gate of the seventh N-type MOSFET NM7 is connected to the drain, the lower end of the third resistor R3, the lower end of the fourth resistor R4, the drain of the tenth N-type MOSFET NM10, and the first pulse input terminal INP of the isolation transformer receiver are connected together; the source of the seventh N-type MOSFET NM7, the drain and gate of the ninth N-type MOSFET NM9, the gate of the tenth N-type MOSFET NM10, and the gate of the eleventh N-type MOSFET NM11 are connected together.

[0057] The gate and drain of the eighth N-type MOSFET NM8, the lower end of the fifth resistor R5, the lower end of the sixth resistor R6, the drain of the thirteenth N-type MOSFET NM13, and the second pulse input terminal INM of the isolation transformer receiver are connected together.

[0058] The source of the eighth N-type MOSFET NM8, the drain and gate of the fourteenth N-type MOSFET NM14, the gate of the thirteenth N-type MOSFET NM13, and the gate of the twelfth N-type MOSFET NM12 are connected together.

[0059] The source of the ninth N-type MOSFET NM9, the source of the tenth N-type MOSFET NM10, the source of the eleventh N-type MOSFET NM11, the source of the twelfth N-type MOSFET NM12, the source of the thirteenth N-type MOSFET NM13, and the source of the fourteenth N-type MOSFET NM14 are connected to the ground terminal GND.

[0060] Because the circuit has a symmetrical structure, this embodiment will describe the left half of the circuit. The working principle of the circuit is as follows:

[0061] When a positive pulse appears at the first pulse input terminal INP of the isolation transformer receiver, the signal is stepped down by the fifth N-type MOSFET MN5 and the seventh N-type MOSFET MN7, and then passed through the common-source amplifier composed of the ninth N-type MOSFET MN9. An inverted output is obtained at the first pulse output terminal OUTP of the pulse filtering circuit. At this time, the first pulse output terminal OUTP is a negative pulse, and the higher the amplitude of the input positive pulse, the smaller the minimum value of the resulting negative pulse output. A small negative pulse will appear immediately after the positive pulse at the first pulse input terminal INP of the isolation transformer receiver. At this time, the first N-type MOSFET MN1 and the second N-type MOSFET MN2 act as current sources to provide the current flowing out of the first pulse input terminal INP. This negative pulse should generate a positive pulse signal after passing through the ninth N-type MOSFET MN9. However, since the first pulse output terminal OUTP is biased at a level close to the power supply voltage, there is no voltage margin to generate this positive pulse, so the negative pulse can be filtered out. Therefore, when a high pulse is input to the first pulse input terminal INP, a negative pulse with a large swing is generated at the first pulse output terminal OUTP. Similarly, at this time, a low pulse is input to the second pulse output terminal OUTM of the pulse filtering circuit, and a negative pulse with a small swing is obtained at the second pulse output terminal OUTM.

[0062] Having described the driving circuit and pulse filtering circuit of the present invention above, this embodiment further explains the working principle of a magnetic isolation encoding / decoding circuit of the present invention, including:

[0063] In the transmitting circuit, the input data signal IN and the refresh clock signal REFCLK generated by the oscillator are input together to the logic control circuit. After processing by the logic control circuit, they are modulated into two signals. One signal is the data clock signal and control signal input to the driver circuit, including the first clock signal CLK and the second clock signal CLKN, as well as the first control signal A, the second control signal B, the third control signal C, and the fourth control signal D. The other signal is the enable signal input to the pulse generation circuit, including the first enable signal EN, the second enable signal ENP0, the third enable signal ENP1, and the fourth enable signal ENN1. The pulse generation circuit is divided into two channels. Under the action of the control signals, when the rising edge, falling edge of the data signal, and the rising edge of the refresh clock signal arrive, respectively... The system generates high pulse signals HPULSE and LPULSE. The drive circuit receives control signals from the logic control circuit and high and low pulse signals generated by the pulse generation circuit. When the rising edge of the data signal arrives, the first transistor Q1 is driven by a high pulse to transmit the set signal to the primary coil, while the second transistor Q2 is driven by a low pulse. When the falling edge of the data signal arrives, the second transistor Q2 is driven by a high pulse to transmit the reset signal to the primary coil, while the first transistor Q1 is driven by a low pulse. When the rising edge of the clock signal arrives, if the data signal is high, a high pulse is generated on the path for transmitting the set signal; if the data signal is low, a high pulse is generated on the path for transmitting the reset signal. This allows the data signal recognition to be refreshed in real time, ensuring the accuracy of signal transmission.

[0064] In the receiving circuit, a bandgap reference circuit provides a common-mode voltage VO1 to the secondary coil and a bias voltage VO0 to the pulse filtering circuit. The pulse filtering circuit receives the first pulse input terminal INP and the second pulse input terminal INM coupled from the secondary coil, modulates them into two negative pulse output terminals OUTP and OUTM, and inputs the two signals into the first comparator COMP1 and the second comparator COMP2 respectively with opposite logic. The output terminals of the first comparator COMP1 and the second comparator COMP2 generate two non-overlapping first pulse signals Z and second pulse signals ZN. The output terminal of the first comparator COMP1 is connected to the CP terminal of the D flip-flop, and the output terminal of the second comparator COMP2 is connected to the RESET terminal of the D flip-flop after inversion. That is, when the first comparator COMP1 has a pulse, the D flip-flop follows and outputs a high voltage of VCC until the RESET terminal receives the inverted pulse signal of the second comparator COMP2, at which point the output is cleared to zero. Finally, the restored data signal is obtained at the output terminal OUT of a magnetically isolated encoder / decoder circuit, and the whole process ends.

[0065] like Figure 7This embodiment provides a schematic diagram of the simulation results of the entire process. The input signal IN is modulated into two high and low pulse signals IFM and INP by the transmitting circuit. After being isolated by the isolation transformer, it is demodulated into the set signal Z and the reset signal ZN of the D flip-flop by the receiving circuit, and finally the restored signal OUT is obtained, which meets the design expectations.

[0066] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A magnetically isolated encoding / decoding circuit, characterized in that, The circuitry includes a transmitter circuit, an isolation transformer, and a receiver circuit. The transmitter circuitry includes a logic control circuit, an oscillator, a pulse generation circuit, and a driver circuit. The receiver circuitry includes a pulse filtering circuit, a bandgap reference circuit, a comparator circuit, an inverter, and a D flip-flop. The logic control circuit is used to provide clock and switching signals to the drive circuit and enable signals to the pulse generation circuit based on the oscillator and input signals. The pulse generation circuit is used to generate a pulse signal according to the enable signal provided by the logic control circuit, and input the generated pulse signal into the drive circuit. The drive circuit is used to provide drive signals for the isolation transformer; The pulse filtering circuit is used to receive the high pulse signal and low pulse signal coupled from the secondary coil of the isolation transformer and modulate them into two high pulse signals and low pulse signals presented as negative pulses. The bandgap reference circuit is used to provide common-mode voltage for the secondary winding of the isolation transformer and bias voltage for the pulse filtering circuit. The comparator circuit includes a first comparator and a second comparator. The pulse signal output from the pulse filtering circuit is input to the two comparators with opposite logic. That is, the high pulse output terminal generated by the pulse filtering circuit is used as the positive input terminal of the first comparator and the negative input terminal of the second comparator, and the low pulse output terminal generated by the pulse filtering circuit is used as the negative input terminal of the first comparator and the positive input terminal of the second comparator. The output terminals of the two comparators generate two non-overlapping pulse signals, and the output of the first comparator is used as the input of the CP terminal of the D flip-flop. The inverter is used to process the pulse signal output from the second comparator, and the output of the inverter is used as the input to the RESET terminal of the D flip-flop; The output of the D flip-flop is used as the output of the circuit to output the restored data signal. The output of the first comparator is connected to the CP terminal of the D flip-flop, and the output of the second comparator is connected to the RESET terminal of the D flip-flop after being inverted. When the first comparator has a pulse, the D flip-flop follows the high voltage of the output voltage terminal until the RESET terminal receives the inverted pulse signal of the second comparator, and then clears the output to zero.

2. The magnetically isolated encoding / decoding circuit according to claim 1, characterized in that, The driving circuit includes a first transmission gate, a second transmission gate, a third transmission gate, a fourth transmission gate, a first P-type MOSFET, a second P-type MOSFET, a first N-type MOSFET, a second N-type MOSFET, a first transistor, and a second transistor, wherein: The high pulse signal HPULSE generated by the pulse generation circuit is used as the input signal for the first transmission gate and the second transmission gate, and the low pulse signal LPULSE generated by the pulse generation circuit is used as the input signal for the third transmission gate and the fourth transmission gate. The first clock signal CLK generated by the logic control circuit is used as the positive control input of the second and third transmission gates, and the negative control input of the first and fourth transmission gates. The second clock signal CLKN, generated by the logic control circuit and complementary to the first pulse signal CLK, serves as the positive control input for the first and fourth transmission gates, and the negative control input for the second and third transmission gates. The logic control circuit generates four switching signals, which are used to control the conduction of the gates of the first P-type MOSFET, the second P-type MOSFET, the first N-type MOSFET, and the second N-type MOSFET, respectively. The source of the first P-type MOSFET is connected to the power supply terminal and the collector of the first transistor. The drain of the first P-type MOSFET is connected to the output terminal of the first transmission gate, the output terminal of the second transmission gate, the drain of the first N-type MOSFET, and the base of the first transistor. The emitter of the first transistor serves as the first primary input signal IFP of the isolation transformer. The source of the second P-type MOSFET is connected to the power supply terminal and the collector of the second transistor. The drain of the second P-type MOSFET is connected to the output terminal of the third transmission gate, the output terminal of the fourth transmission gate, the drain of the second N-type MOSFET, and the base of the second transistor. The emitter of the second transistor serves as the second primary input signal IFM of the isolation transformer. The sources of the first N-type MOS transistor and the second N-type MOS transistor are grounded respectively.

3. The magnetically isolated encoding / decoding circuit according to claim 2, characterized in that, When the first and fourth transmission gates are open and the second and third transmission gates are closed, the drive circuit is in the first operating mode. At this time: When the first P-type MOSFET and the second N-type MOSFET are turned on, and the second P-type MOSFET and the first N-type MOSFET are turned off, the first transistor and the second transistor are in a charging state. The coil of the isolation transformer connected to the first transistor induces a high pulse level, and the coil connected to the second transistor induces a low pulse level. When the gates of the first P-type MOSFET, the second P-type MOSFET, the first N-type MOSFET, and the second N-type MOSFET are all turned off, the first transistor and the second transistor are in a discharging state, the current of the isolation transformer gradually decreases, and a negative pulse is coupled out.

4. The magnetically isolated encoding / decoding circuit according to claim 2, characterized in that, When the second and third transmission gates are open and the first and fourth transmission gates are closed, the drive circuit is in the second operating mode. At this time: When the first N-type MOSFET and the second P-type MOSFET are turned on, and the second N-type MOSFET and the first P-type MOSFET are turned off, the first transistor and the second transistor are in a charging state. The coil of the isolation transformer connected to the first transistor induces a low pulse level, and the coil connected to the second transistor induces a high pulse level. When the gates of the first P-type MOSFET, the second P-type MOSFET, the first N-type MOSFET, and the second N-type MOSFET are all turned off, the first transistor and the second transistor are in a discharging state, the current of the isolation transformer gradually decreases, and a negative pulse is coupled out.

5. A magnetically isolated encoding / decoding circuit according to claim 1, characterized in that, The pulse filtering circuit includes a third N-type MOSFET, a fourth N-type MOSFET, a fifth N-type MOSFET, a sixth N-type MOSFET, a seventh N-type MOSFET, an eighth N-type MOSFET, a ninth N-type MOSFET, a tenth N-type MOSFET, an eleventh N-type MOSFET, a twelfth N-type MOSFET, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, and a sixth resistor, wherein: The gates of the third to sixth N-type MOSFETs are connected to the bias voltage provided by the bandgap reference circuit. The drain of the third N-type MOSFET is connected to one end of the first resistor, one end of the second resistor, and the drain of the sixth N-type MOSFET. The source of the third N-type MOSFET is connected to one end of the third resistor. The source of the sixth N-type MOSFET is connected to one end of the sixth resistor. The drain of the fourth N-type MOSFET is connected to the other end of the first resistor and the drain of the twelfth N-type MOSFET, and serves as the second pulse output terminal OUTM of the pulse filtering circuit; the source of the fourth N-type MOSFET is connected to one end of the fourth resistor. The drain of the fifth N-type MOSFET is connected to the other end of the second resistor and the drain of the eleventh N-type MOSFET, and serves as the first pulse output terminal OUTP of the pulse filtering circuit; the source of the fifth N-type MOSFET is connected to one end of the fifth resistor. The drain and gate of the seventh N-type MOSFET, the other end of the third resistor, the other end of the fourth resistor, and the drain of the tenth N-type MOSFET are connected to the first pulse input terminal INP of the isolation transformer receiver; the source of the seventh N-type MOSFET is connected to the drain and gate of the ninth N-type MOSFET, the gate of the tenth N-type MOSFET, and the gate of the eleventh N-type MOSFET. The drain and gate of the eighth N-type MOSFET, the other end of the fifth resistor, the other end of the sixth resistor, and the drain of the thirteenth N-type MOSFET are connected to the second pulse input terminal INM of the isolation transformer receiver; the source of the eighth N-type MOSFET is connected to the drain and gate of the fourteenth N-type MOSFET, the gate of the thirteenth N-type MOSFET, and the gate of the twelfth N-type MOSFET. The sources of the ninth to fourteenth MOSFETs are grounded.

6. A magnetically isolated encoding / decoding circuit according to claim 5, characterized in that, When the first pulse input terminal INP of the isolation transformer receiver is a high pulse, the first pulse output terminal OUTP of the pulse filtering circuit generates a negative pulse with a large swing. When the second pulse input terminal INM of the isolation transformer receiver is a low pulse, the second pulse output terminal OUTM of the pulse filtering circuit generates a negative pulse with a small swing.

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