PSI5 interface circuit current threshold control method, device and equipment and storage medium

Abstract

The invention discloses a PSI5 interface circuit current threshold control method, device and equipment and a storage medium, and relates to the field of sensing detection, gradient current thresholds are set for N current comparators, each current comparator generates a Manchester signal based on a sampling current value and a corresponding current threshold, and a corresponding decoding success rate is recorded through a register group; determining a target current comparator based on the decoding success rate recorded by the N paths of current comparators after power-on; obtaining a target current comparator and a current threshold, outputting a Manchester coded signal, and calculating a duty ratio value; and updating the current threshold value of the target current comparator according to the duty ratio value gradient, and updating the N-path decoding success rate. According to the scheme, Manchester encoding signals are not directly and continuously monitored, different current threshold values are set in a gradient mode, the current comparators are screened according to the decoding success rate, then the duty ratio is adjusted, chip computing resources can be optimized to the maximum extent, and the encoding and decoding accuracy can be improved to the maximum extent.

Description

Technical Field

[0001] The present application relates to the field of sensor detection, and in particular to a method, device, equipment and storage medium for controlling current threshold of a PSI5 interface circuit. Background Art

[0002] In the automotive industry, the Peripheral Sensor Interface (PSI5) is the most common automotive sensor interface. PSI5 is an open standard that is widely used in airbag systems. Its sensor data is transmitted at a preset baud rate through Manchester code. Manchester coding, also known as split phase code, synchronization code, and phase coding, is a coding method that uses level jumps to represent 1 or 0.

[0003] In the sensor detection circuit, when the ECU chip collects Manchester-encoded sensor data, it will inevitably be affected by various external interferences, thereby affecting the level signal judgment of the current comparator. In the traditional solution, the ECU chip reversely controls the output to adjust the current threshold of the current comparator to identify the Manchester signal and determine the sensor data content. For details, see Figure 1 In the circuit structure shown in the figure, the current comparator U2 in this scheme is mainly adjusted periodically, focusing on the active adjustment of the abnormal situation of the PSI5 sensor, and the real-time performance and adjustment accuracy are average. In addition, this adjustment mechanism is mainly based on the duty cycle value to infer and adjust the current, which requires real-time calculation and analysis of the duty cycle, and takes up more ECU chip resources. Summary of the invention

[0004] The present application provides a PSI5 interface circuit current threshold control method, device, equipment and storage medium to improve the decoding accuracy of Manchester code transmitted by the PSI5 interface and optimize chip resources.

[0005] On the one hand, the present application provides a PSI5 interface circuit current threshold control method, the method is used for a PSI5 interface circuit including N current comparators, the method comprising: A gradient-changing current threshold is set for N current comparators. When working, each current comparator generates a Manchester signal based on the sampled current value and the corresponding current threshold, and records the corresponding decoding success rate through a register group. In the first detection cycle of power-on, a target current comparator is determined based on the decoding success rate recorded by the N current comparators; In the second detection cycle, the target current comparator and the corresponding current threshold output Manchester coded signal are obtained and the duty cycle value is calculated; the current threshold of the target current comparator is updated according to the duty cycle value gradient, and the decoding success rate recorded by the N-way current comparator is updated; After the second detection cycle, the decoding success rates recorded by the N current comparators are acquired in real time, the target current comparator is re-determined, and the steps of calculating the duty cycle and updating the current threshold are performed on the target current comparator.

[0006] Specifically, each current comparator is provided with a register group, including a first register and a second register; the first register stores the number of successful decoding times, and the second register stores the decoding success rate; In the working stage, the decoding result of each current comparator is obtained in real time, and the number of successful decoding in the first register and the decoding success rate data in the second register are recorded and updated.

[0007] Specifically, in the first detection cycle of power-on, determining the target current comparator based on the decoding success rate recorded by the N current comparators includes: After the system is powered on, the N current comparators are controlled to generate Manchester signals according to the initial current threshold set by the gradient. After reaching the target set data frame length, the current comparator with the highest decoding success rate is determined as the target current comparator. After the second detection cycle, the number of successful decodings and the decoding success rate of the N current comparators are obtained in real time, the current comparator with the highest decoding success rate is continuously updated and determined as the target current comparator, and the duty cycle of the target comparator is calculated and the current threshold is gradient updated; the gradient update value is determined based on the length of the second detection cycle.

[0008] Specifically, the decoding results recorded by the N-way current comparator are determined according to the verification mechanism of the chip. When the number of successfully decoded ways is 0, the decoding error of this round is reported and the decoding success rate is updated; When the number of successfully decoded paths is not 0 and the results are consistent, report the correct results and update the number of successful decoding and the decoding success rate; When the number of successfully decoded paths is not 0 and the results are inconsistent, all errors are reported and the decoding success rate is updated.

[0009] Specifically, after acquiring the Manchester signal, the edge signal of the Manchester signal is monitored, and when the initial edge signal is monitored, the clock counting is started; When the timing does not reach the clock threshold specified by the filtering parameters, monitor whether there is an edge signal opposite to the initial edge signal; When an edge signal opposite to the initial edge signal is detected within the clock counting cycle, the clock count value is reduced by the step value and the edge signal is continued to be detected; when an edge signal identical to the initial edge signal is detected within the clock counting cycle, the clock count value is increased by one; When the timing reaches the clock threshold specified by the filtering parameters and no edge signal opposite to the initial edge signal is detected within all clock counting cycles, the level value after the initial edge signal is used as the output level value.

[0010] Specifically, 1024 frames of Manchester data are received in the first detection cycle, the decoding success rate of the N-way register group is updated according to the decoding results of the 1024 frames, and the target current comparator is determined based on the way with the highest decoding success rate; 250 frames of Manchester data are received in the second detection cycle, and the decoding success rate of the N-way register group is continuously updated according to the decoding results of the 250 frames; the duty cycle of the target current comparator is calculated in each data cycle, and the current threshold is updated according to the difference gradient with the target duty cycle.

[0011] Specifically, after the second detection cycle, when there are at least two current comparators with the same decoding success rate, the current comparator with the smallest difference between the current threshold and the corresponding initial threshold current is selected to determine the target current comparator.

[0012] On the other hand, the present application provides a PSI5 interface circuit current threshold control device, the device is used for a PSI5 interface circuit including N current comparators, the device comprising: A setting module is used to set a gradient-changing current threshold for N current comparators. When working, each current comparator generates a Manchester signal based on the sampled current value and the corresponding current threshold, and records the corresponding decoding success rate through a register group; A determination module, used to determine a target current comparator based on a decoding success rate recorded by N current comparators during a first detection cycle after power-on; The first updating module is used to obtain the Manchester coded signal output by the target current comparator and the corresponding current threshold and calculate the duty cycle value in the second detection cycle; update the current threshold of the target current comparator according to the duty cycle value gradient, and update the decoding success rate recorded by the N-way current comparator; The second updating module is used to obtain the decoding success rate recorded by the N current comparators in real time after the second detection cycle, and to re-determine the target current comparator, and to perform the steps of calculating the duty cycle and updating the current threshold for the target current comparator.

[0013] On the other hand, the present application provides a computer device, comprising a processor and a memory, wherein the memory stores at least one instruction, at least one program, a code set or an instruction set, and the at least one instruction, the at least one program, the code set or the instruction set are loaded and executed by the processor to implement the PSI5 interface circuit current threshold control method described in any of the above aspects.

[0014] On the other hand, the present application provides a computer-readable storage medium, which stores at least one instruction, at least one program, code set or instruction set. The at least one instruction, the at least one program, the code set or instruction set is loaded and executed by a processor to implement the PSI5 interface circuit current threshold control method described in any of the above aspects.

[0015] The beneficial effects brought by the technical solution provided by the embodiment of the present application include at least: the solution does not directly and continuously monitor the Manchester coded signal, but sets different current thresholds in gradients, first screens the current comparator with the highest decoding effect based on the decoding success rate, and then analyzes the duty cycle difference to adjust the current threshold. The subsequent adjustment process always uses the decoding success rate as the first reference dimension for initial screening, and then adjusts the duty cycle for the second time. This adjustment mechanism can optimize the CPU computing resources to the greatest extent, and the entire process can ensure that data is output with the maximum decoding success rate. Compared with the traditional single-channel threshold adjustment method, the output is always the one with the best decoding ability. Compared with negative feedback adjustment, the method based on the decoding success rate output has no delay in the adjustment action, and the adjustment process is faster and smoother. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a simplified circuit diagram of the vehicle PSI5 sensor detection system circuit; Figure 2 It is a schematic diagram of Manchester data encoding; Figure 3 It is a simplified schematic diagram of the data input of the five-way current comparator; Figure 4 is a flow chart of a current threshold control method for a PSI5 interface circuit provided in an embodiment of the present application; Figure 5 It is a schematic diagram of the Manchester coded signal output when different current thresholds are applied to the current signal; Figure 6 It is the flow chart of the filtering algorithm for Manchester coded signal; Figure 7 This is a comparison chart of noise filtering generated after a low-level to high-level transition; Figure 8 It is a structural block diagram of a current threshold control device for a PSI5 interface circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0017] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0018] The term "multiple" as used herein refers to two or more than two. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the related objects are in an "or" relationship.

[0019] Manchester coding, also known as split-phase code, synchronous code, and phase coding, is a coding method that uses level jumps to represent 1 or 0. Its change rule is very simple, that is, each code element is represented by two level signals with different phases, that is, a square wave of one cycle, but the phases of code 0 and code 1 are exactly opposite. It is stipulated that a bit that jumps from low level to high level is Bit 0, and a bit that jumps from high level to low level is Bit 1.

[0020] In this scheme, the algorithm of the vehicle PSI5 sensor detection system circuit is improved. The vehicle PSI5 sensor detection system circuit can be simplified as follows: Figure 1 The content (which can be other forms of circuit structure) is that several sensor devices are mounted on the PSI5 bus. The data of these sensor devices are sent to the current comparator U2 for comparison through the sampling circuit (R5 sampling resistor) and the amplification circuit (op amp U1), etc., and the sampled current I1 is sent to the current comparator U2 for comparison, and the Manchester data is generated and sent to the ECU chip for detection. The reference current I is the amplified current, which is used to determine the amplification factor; the current threshold I2 is the reverse output of the ECU to the current comparator, and the Manchester data is generated based on the current threshold I2 and the size of the sampled current I1. See Figure 2 As shown in the Manchester data encoding schematic, when the sampling signal (the current input to U2) is less than the current threshold, U2 outputs a low-level signal, otherwise it outputs a high-level signal.

[0021] In order to solve the problems of current threshold adjustment accuracy and ECU resource occupation mentioned in the background technology, this application chooses to set up a current comparator U2 with different current comparison thresholds and corresponding filtering and decoding parts. The corresponding current thresholds of each current comparator are adaptively adjusted according to actual conditions, and the most suitable output is selected as the final target input through an algorithm. Figure 3 It is a simplified schematic diagram of the data input of the five-way current comparator. The amplifier circuit U1 multiplexes the input into the five-way current comparator circuit, and its output Manchester data is sent to the ECU chip. The ECU chip uses internal algorithms to feedback and adjust the corresponding current thresholds of the five channels.

[0022] Figure 4 : is a flow chart of a PSI5 interface circuit current threshold control method provided in an embodiment of the present application, comprising the following steps: S1. Setting a gradient-changing current threshold for N current comparators. When working, each current comparator generates a Manchester signal based on the sampled current value and the corresponding current threshold, and records the corresponding decoding success rate through a register group. In the initial stage of circuit setting, the current thresholds of the N-way current comparators are set by default according to the gradient change, that is, there is a certain interval between the current thresholds of the 5-way comparators. For example, the current threshold of P3 (middle road) is set to Ibase, P2 and P4 are set to Ibase ± 5%, and P2 and P4 are set to Ibase ± 10%. Such current thresholds are set in the form of a direct proportional function, which can cover the conventional current adjustment range.

[0023] Figure 5 This is a schematic diagram of the Manchester coded signal output when different current thresholds are applied to the current signal. This embodiment takes a 5-way current comparator as an example. After setting current thresholds of different values ​​in the positive cycle of the sine wave, the Manchester coded signals obtained are also different. In particular, there is a huge difference in the length and time ratio of the effective data between 1-way Manchester coding and 5-way Manchester coding, which is also the key to the accuracy of signal encoding and decoding.

[0024] The decoding success rate is generated after the chip receives and decodes the Manchester data. This stage mainly depends on the verification mechanism specified by the PSI5 protocol, such as CRC verification. This application does not introduce this in detail. The decoding success rate determined after decoding is stored in a register group, which can be an internal register group of the ECU or can be set separately externally. It is mainly used to record the decoding success rate of the N-way current comparator. Figure 3 In the figure, five groups of registers are set to respectively record the decoding success rates of Manchester data generated by five groups of current comparators.

[0025] S2. In the first detection cycle of power-on, a target current comparator is determined based on the decoding success rate recorded by the N current comparators; During the power-on phase, the system will reset the current threshold and decoding success rate of the N-way current comparators. In the first detection cycle after power-on, the ECU will continuously record and update the decoding success rate of each other based on the Manchester data output by each channel. After continuously recording the duration of the first detection cycle, one channel will be selected from the decoding success rate corresponding to the N-way current comparators as the target current comparator for subsequent key adjustment targets.

[0026] In this embodiment, the higher the decoding success rate is, the more reasonable the current threshold is set, so a current comparator with the highest decoding success rate is selected as the target current comparator, and the content of S3 is further executed.

[0027] S3, in the second detection cycle, obtaining the target current comparator and the corresponding current threshold output Manchester coded signal and calculating the duty cycle value; updating the current threshold of the target current comparator according to the duty cycle value gradient, and updating the decoding success rate recorded by the N-way current comparator; After entering the second detection cycle, the system mainly fine-tunes the target current comparator determined in step S2, and does not perform any operation on the other N-1 current comparators. However, the decoding success rate of the N current comparators is still recorded and updated in real time.

[0028] For the fine-tuning process of the selected target current comparator, this stage is operated by duty cycle adjustment. Figure 5 The Manchester coded signal shown, within a complete signal cycle (consisting of a high level duration t1 and a low level signal duration t1), the ratio of the high level signal duration to the low level signal duration is the duty cycle. The system usually sets an ideal duty cycle according to the actual situation (for example, 50% is used as an example in this application), because a duty cycle that is too large or too small will affect the encoding and decoding operation of the system. In this embodiment, the current comparison threshold with the highest decoding success rate is further adjusted in the second detection cycle, that is, the square wave duty cycle is further adjusted to 50%. The principle is: if the duty cycle obtained by the duty cycle calculation logic is greater than 50%, the current comparator threshold is increased; if the duty cycle obtained by the duty cycle calculation logic is less than 50%, the current comparator threshold is reduced; if the duty cycle is 50%, it will not increase or decrease. For example Figure 5 The duty cycle of the fifth path t1 / (t1+t2) is closest to 50%, and the target current comparator is selected for this path.

[0029] The significant difference between the present application and the traditional solution is that, although both directly detect the duty cycle value of the Manchester coded signal to reversely adjust the current threshold, the traditional solution is continuous monitoring, and reverse adjustment is based on the negative feedback mechanism when the duty cycle deviates from the target range. This solution requires calling more ECU resources to monitor the level signal and calculate the duty cycle in real time, and the negative feedback trigger adjustment mechanism has a certain delay. However, the present embodiment does not monitor the level signal value all the time, but first selects the target current comparator with the highest decoding success rate, which is equivalent to preliminarily screening the target comparator closest to the target duty cycle, and then fine-tuning the target current comparator. Since the data in the first detection cycle of the system power-on process is usually system test data, it will not affect the actual sensor data reception and judgment, and the entire adjustment cycle is shorter and the adjustment process is smoother. The fine-tuning process can last for one or more complete signal cycles, which is specifically determined by the duty cycle difference.

[0030] In the above steps, because there is no need to call additional ECU resources to monitor the level signal and calculate the duty cycle during the first detection cycle, the decoding situation is directly determined according to the back-end decoding verification, and the decoding success rate is used to replace the level signal monitoring and duty cycle calculation, thereby saving the ECU's computing resources.

[0031] It should be noted that the target current comparator determined in step S2 is only temporary, because circuit and noise fluctuations, or sensor disconnection abnormalities will affect the amplitude of the sampled signal, so large signal fluctuations may also occur at this stage. Although this step monitors and fine-tunes the duty cycle, it is only monitored during the fine-tuning phase and does not require continuous monitoring, because the process register group during the fine-tuning process and after the fine-tuning is completed has been recording the decoding success rate. As mentioned earlier, the decoding success rate is a direct indicator of system stability and is positively correlated with the duty cycle difference. The decoding situation can be obtained directly without the need for level signal monitoring and calculation, which is also the key to saving ECU resources in this application.

[0032] S4. After the second detection cycle, the decoding success rates recorded by the N current comparators are obtained in real time, a target current comparator is re-determined, and the steps of calculating the duty cycle and updating the current threshold are performed on the target current comparator.

[0033] This step is the judgment mechanism of the cyclic operation S2, that is, the target current comparator is not fixed. Although the duty cycle of a temporarily selected current comparator is calculated and fine-tuned in step S3, after the detection cycle, if the system or line fluctuations cause the subsequent decoding success rate to change, the target current comparator will be reselected.

[0034] For example, in the first detection cycle after the system is powered on, the Manchester coded signal output by the fourth current comparator is determined by cumulative calculation to have the highest decoding success rate (98%) after subsequent decoding verification, and this current comparator is used as the target current comparator. When entering the second detection cycle, the level signal of the fourth current comparator is briefly detected and the duty cycle is calculated, and fine-tuning is performed after the duty cycle threshold is determined. The fine-tuning process will use the Manchester data output by this channel as the collected sensor data for vehicle analysis. Although the sensor data of other channels are not analyzed, the decoding success power of all Manchester coded signals is still updated.

[0035] After the second detection cycle, assuming that the decoding success rate of the second channel exceeds that of the fourth channel due to system fluctuations and error accumulation (the decoding success rate of the fourth channel may also fluctuate and decrease), the second channel current comparator is determined as the target current comparator. In the subsequent steps, the level signal and threshold fine-tuning of this channel are detected.

[0036] In general, this solution does not directly and continuously monitor the Manchester coded signal, but sets different current thresholds in gradients. First, the current comparator with the highest decoding effect is selected based on the decoding success rate, and then the duty cycle difference is analyzed to adjust the current threshold. The subsequent adjustment process always uses the decoding success rate as the first reference dimension for initial screening, and then adjusts the duty cycle for the second time. This adjustment mechanism can optimize the CPU computing resources to the greatest extent, and the entire process can ensure that data is output with the maximum decoding success rate. Compared with the traditional single-channel threshold adjustment method, the output is always the one with the best decoding ability. Compared with negative feedback adjustment, the method based on the decoding success rate output has no delay in the adjustment action, and the adjustment process is faster and smoother.

[0037] In some embodiments, the ECU chip can set a register group for each current comparator, including a first register and a second register. The first register is used to store the number of successful decodings, and the second register stores the decoding success rate (the ratio of the number of successful decodings to the total number of decodings). In the subsequent entire working stage, the ECU will obtain the decoding results of each current comparator in real time, record and update the number of successful decodings in the first register and the decoding success rate data in the second register. The total number of decodings (i.e., the received Manchester data frame) can be additionally stored through a register or an ECU chip.

[0038] The process of determining the target current comparator can be summarized as follows: 1. After the system is powered on, the N current comparators are controlled to generate Manchester signals according to the initial current threshold set by the gradient. After reaching the target set data frame length, the current comparator with the highest decoding success rate is determined as the target current comparator; The time of the first detection cycle process can be set. For example, the present application takes the time of receiving 1024 frames of Manchester data as the basis, updates the decoding success rate of the N-way register group after obtaining the decoding result of the 1024th frame, and determines the target current comparator for the way with the highest decoding success rate.

[0039] The decoding results recorded by the N-way current comparator are determined according to the chip's verification mechanism 1) If the number of successfully decoded paths = 0, report the decoding error of this round and update the decoding success rate of each path.

[0040] 2) If the number of successfully decoded paths = 1, report the correct result of the path, and update the number of successful decoding of the path and the decoding success rate of each path.

[0041] 3) If the number of successfully decoded paths is greater than 1 and the results are consistent, the correct result is reported and the number of successful decodings and the decoding success rate of each path are updated.

[0042] 4) If the number of successfully decoded paths is greater than 1, and the results are inconsistent, all errors will be reported and the decoding success rate of each path will be updated. (In this case, at least one of the results is wrong, and all errors will be reported to ensure accuracy).

[0043] 2. After the second detection cycle, the number of successful decodings and the decoding success rate of the N current comparators are obtained in real time, and the current comparator with the highest decoding success rate is continuously updated as the target current comparator, and the duty cycle of the target comparator is calculated and the current threshold is updated by gradient.

[0044] The second detection cycle of this application is based on 250 frames of Manchester data, and the decoding success rate of the N-way register group is continuously updated and the threshold is fine-tuned within these 250 frames. During fine-tuning, the duty cycle of the target current comparator is calculated within each complete data cycle, and the current threshold is updated according to the difference gradient with the target duty cycle.

[0045] Considering some special cases, during the second detection cycle and in the later stage, when there are at least two current comparators with the same decoding success rate, the one with the smallest difference between the current current threshold and the corresponding initial threshold current can be selected to determine the target current comparator, that is, the one closest to Ibase is selected. This is also to facilitate subsequent circuit fine-tuning. The closer the current value is to Ibase, the larger the free adjustment range at both ends and the stronger the anti-fluctuation ability.

[0046] In order to achieve precise control, the present application provides an adjustment mechanism combining fast adjustment and slow adjustment, wherein the fast adjustment mechanism is enabled only when the device is powered on. In this example, the fast adjustment period is set to 250 frames of data, that is, 1024+250 frames of data are sent by the PSI5 host when powered on, and the first 1024 frames of data are used to obtain the current comparator threshold with the highest decoding success rate, and the latter 250 frames of data are fast adjusted. For example, in this example, the adjustment step size is set to 0.02% each time, that is, the target comparator adjusts 0.02% of Ibase at a time. In the formal adjustment stage after the second cycle, because the sensor data needs to be transmitted and the group with the highest decoding success rate has been preliminarily screened, a slow adjustment mechanism is adopted until the device is powered off, and the slow adjustment step size is set to 0.001% of Ibase each time. It should be noted that slow adjustment and fast adjustment always act on the current comparison threshold with the highest decoding success rate, and will not adjust the current threshold of other roads. Moreover, the adjusted current threshold will not change when other comparators are reselected later, because it may be reselected later, and the current adjustment is more convenient, and the initial current threshold will only be restored after power failure and restart.

[0047] In this solution, the impact of noise interference on encoding and decoding also needs to be considered, especially the high-frequency noise fluctuations that affect encoding and decoding and duty cycle calculation. To this end, this application provides a more accurate noise filtering solution. For the specific discrimination and filtering process, see Figure 6 As shown, including the following: S1. After acquiring the Manchester signal, monitor the edge signal of the Manchester signal, and start the clock counting when the initial edge signal is detected; It should be noted that Figure 6 The flowchart is judged and counted one by one according to the clk clock sequence. To facilitate the explanation of the working principle, this application uses Figure 7 This is explained by comparing the noise filtering generated after the transition from medium-low level to high level. Figure 7 The glitch signal in the signal will produce a much lower low-level signal, which will cause the system to mistake it for a normal signal jump. The traditional solution is to collect the half-bit signal duration and combine it with the overall data to confirm the actual signal. Although it can also achieve the purpose of filtering, the algorithm is too complicated. This application chooses to filter based on the most basic clock clk signal, because the noise signal is usually dense and short-lived, and generally does not reach a certain number (20 are used as an example in the embodiment) of clk signals, so this application uses the clk signal count threshold as the filter count parameter to determine whether it is a noise signal.

[0048] exist Figure 7 In the example, the initial edge signal is the rising edge signal at the 4th clk moment, at which time the clock count begins (starting from 0 and incrementing by 1).

[0049] S2. Detect the signals one by one according to the clock cycle. When the clock count does not reach the threshold specified by the filtering parameter, monitor whether there is an edge signal opposite to the initial edge signal. It is obvious that the threshold specified by the filtering parameters is not reached within the clk period when the initial edge signal is detected (for example, 20 clks are used as the standard in this application), so the edge signal opposite to the initial signal continues to be detected in the subsequent clk.

[0050] 1) When no edge signal opposite to the initial edge signal is detected, the clock count is updated based on the clock signal and detection continues one by one according to the clock cycle. This step corresponds to the signal at the 5th clk moment. Obviously, there is no falling edge signal, so after the clock count +1, it continues to determine whether the filter threshold is reached and detect the falling edge. If there is no falling edge, the signal detection, judgment and timing of the 6th clk are continued.

[0051] 2) When an edge signal opposite to the initial edge signal is detected, the clock count value is reduced by the step value, and the detection continues one by one according to the clock cycle; At a certain clk moment, an edge signal opposite to the initial edge signal is detected (corresponding to Figure 7When the falling edge of the 7th clk moment in the clock is detected, the clock count value is reduced by the step value (for example, the application will count -1), and then only the edge signal that is the same as the initial edge signal can be detected (that is, Figure 7 When the next clk remains at a low level, the count is +1, otherwise the count is set to -1. It should be noted that when the low level continues for multiple clks, the count will continue to be +1.

[0052] S3. When the clock count does not reach the threshold value specified by the filtering parameters, the level value corresponding to the clock cycle is used as the output level.

[0053] by Figure 7 For example, at the 12th clk, the signal returns to a high level and then stabilizes. Because there are multiple noises between the 7th and 12th clks, assuming that all are rising and falling edge signals, the cumulative value is 3 at the 12th clk, and the subsequent high level continues until the 30th clk, reaching the set filter threshold. Therefore, from this moment on, it is defined as the formal effective output level, that is, the high level. So at Figure 7 There is a certain delay between the output filtered signal and the ideal signal. The delay time is Ts, and the maximum delay time is T 噪声 +T 滤波阈值 In practice, the noise appears for a very short time, usually only a few clks. If the noise lasts for a long time, it means that there is a big problem with the circuit itself. Therefore, the entire delay time is very small compared to the duty cycle and has no effect on the codec.

[0054] In summary, the filtering method can use the filtering threshold counting method to quickly filter the output, and the clock count value can be increased or decreased according to the actual situation by reducing the step value. As a result, the delay time is correspondingly lengthened or shortened, which reasonably balances the monitoring accuracy and delay requirements.

[0055] Figure 8 : is a structural block diagram of a current threshold control device for a PSI5 interface circuit provided in an embodiment of the present application, wherein the device is used for a PSI5 interface circuit including N current comparators, and the device includes: A setting module 810 is used to set a current threshold value that changes in a gradient for N current comparators. When working, each current comparator generates a Manchester signal based on the sampled current value and the corresponding current threshold value, and records the corresponding decoding success rate through a register group; A determination module 820, configured to determine a target current comparator based on decoding success rates recorded by N current comparators during a first detection cycle after power-on; The first updating module 830 is used to obtain the Manchester coded signal output by the target current comparator and the corresponding current threshold and calculate the duty cycle value in the second detection cycle; update the current threshold of the target current comparator according to the duty cycle value gradient, and update the decoding success rate recorded by the N-way current comparator; The second updating module 840 is used to obtain the decoding success rate recorded by the N current comparators in real time after the second detection cycle and to re-determine the target current comparator, and to perform the steps of calculating the duty cycle and updating the current threshold for the target current comparator.

[0056] In some embodiments, the present application further provides a computer device, which may optionally include: a peripheral device interface and at least one peripheral device. The processor, the memory, and the peripheral device interface may be connected via a bus or a signal line. Each peripheral device may be connected to the peripheral device interface via a bus, a signal line, or a circuit board. Specifically, the peripheral device includes: at least one of a radio frequency circuit, a display screen, and a keyboard.

[0057] The peripheral device interface can be used to connect at least one peripheral device related to I / O (Input / Output) to the processor and the memory. In some embodiments, the processor, the memory, and the peripheral device interface are integrated on the same chip or circuit board; in some other embodiments, any one or two of the processor, the memory, and the peripheral device interface can be implemented on a separate chip or circuit board, which is not limited in this embodiment.

[0058] The display screen is used to display the UI (User Interface). The UI may include graphics, text, icons, videos, and any combination thereof. When the display screen is a touch screen, the display screen also has the ability to collect touch signals on the surface or above the surface of the display screen. The touch signal can be input to the processor as a control signal for processing. At this time, the display screen can also be used to provide virtual buttons and / or virtual keyboards, also known as soft buttons and / or soft keyboards. In some embodiments, the display screen can be one, which is set on the front panel of the computer device; in other embodiments, the display screen can be at least two, which are respectively set on different surfaces of the computer device or are folded; in other embodiments, the display screen can be a flexible display screen, which is set on the curved surface or folded surface of the computer device. Even the display screen can be set into a non-rectangular irregular shape, that is, a special-shaped screen. The display screen can be made of materials such as LCD (Liquid Crystal Display), OLED (Organic Light-Emitting Diode), etc.

[0059] The power supply is used to power various components in the computer device. The power supply can be AC, DC, a disposable battery, or a rechargeable battery. When the power supply includes a rechargeable battery, the rechargeable battery can be a wired rechargeable battery or a wireless rechargeable battery. A wired rechargeable battery is a battery that is charged through a wired line, and a wireless rechargeable battery is a battery that is charged through a wireless coil. The rechargeable battery can also be used to support fast charging technology.

[0060] Those skilled in the art will appreciate that the structure shown in this embodiment does not constitute a limitation on the computer device, and may include more or fewer components than shown in the figure, or combine certain components, or adopt a different component arrangement.

[0061] The embodiment of the present application also discloses a computer-readable storage medium. Specifically, the computer-readable storage medium is used to store a computer program, and when the computer program is executed by the processor, the method in the above-mentioned method implementation is implemented. Those skilled in the art can understand that the implementation of all or part of the process in the above-mentioned implementation method of the present application can be completed by instructing the relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium, and when the program is executed, it can include the process of the implementation of the above-mentioned methods. Among them, the storage medium can be a disk, an optical disk, a read-only memory (ROM), a random access memory (RAM), a flash memory (Flash Memory), a hard disk (Hard Disk Drive, abbreviated: HDD) or a solid-state drive (SSD), etc.; the storage medium can also include a combination of the above-mentioned types of memory.

[0062] The preferred embodiments of the present invention are described above; it should be understood that the present invention is not limited to the above-mentioned specific embodiments, and the devices and structures not described in detail should be understood to be implemented in a common manner in the art; any technician familiar with the art can make many possible changes and modifications without departing from the technical solution of the present invention, or modify them into equivalent embodiments with equivalent changes, which does not affect the essential content of the present invention; therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of protection of the technical solution of the present invention.

Claims

1. A PSI5 interface circuit current threshold control method, characterized in that: The method is used for a PSI5 interface circuit including N-channel current comparators, and the method comprises: A gradient-changing current threshold is set for N current comparators. When working, each current comparator generates a Manchester signal based on the sampled current value and the corresponding current threshold, and records the corresponding decoding success rate through a register group. In the first detection cycle of power-on, a target current comparator is determined based on the decoding success rate recorded by the N current comparators; In the second detection cycle, the target current comparator and the corresponding current threshold output Manchester coded signal are obtained and the duty cycle value is calculated; the current threshold of the target current comparator is updated according to the duty cycle value gradient, and the decoding success rate recorded by the N-way current comparator is updated; After the second detection cycle, the decoding success rates recorded by the N current comparators are acquired in real time, the target current comparator is re-determined, and the steps of calculating the duty cycle and updating the current threshold are performed on the target current comparator.

2. The method according to claim 1, characterized in that Each current comparator is provided with a register group, including a first register and a second register; the first register stores the number of successful decoding times, and the second register stores the decoding success rate; In the working stage, the decoding result of each current comparator is obtained in real time, and the number of successful decoding in the first register and the decoding success rate data in the second register are recorded and updated.

3. The method according to claim 2, characterized in that The method of determining a target current comparator based on decoding success rates recorded by N current comparators during the first detection cycle of power-on includes: After the system is powered on, the N current comparators are controlled to generate Manchester signals according to the initial current threshold set by the gradient. After reaching the target set data frame length, the current comparator with the highest decoding success rate is determined as the target current comparator. After the second detection cycle, the number of successful decodings and the decoding success rate of the N current comparators are obtained in real time, the current comparator with the highest decoding success rate is continuously updated and determined as the target current comparator, and the duty cycle of the target comparator is calculated and the current threshold is gradient updated; the gradient update value is determined based on the length of the second detection cycle.

4. The method according to any one of claims 1 to 3, characterized in that: The decoding results recorded by the N-channel current comparators are determined according to the chip verification mechanism. When the number of successfully decoded channels is 0, the decoding error of this round is reported and the decoding success rate is updated; When the number of successfully decoded paths is not 0 and the results are consistent, report the correct results and update the number of successful decoding and the decoding success rate; When the number of successfully decoded paths is not 0 and the results are inconsistent, all errors are reported and the decoding success rate is updated.

5. The method according to any one of claims 1 to 3, characterized in that: After acquiring the Manchester signal, the edge signal of the Manchester signal is monitored, and when the initial edge signal is detected, the clock counting is started; The signals are detected one by one according to the clock cycle. When the clock count does not reach the threshold specified by the filtering parameters, it is monitored whether there is an edge signal opposite to the initial edge signal. When an edge signal opposite to the initial edge signal is not detected, the clock count is updated based on the clock signal and detection continues one by one according to the clock cycle; when an edge signal opposite to the initial edge signal is detected, the clock count value is reduced by the step value and detection continues one by one according to the clock cycle; When the clock count does not reach the threshold value specified by the filtering parameters, the level value of the corresponding clock cycle is used as the output level.

6. The method according to claim 1, characterized in that 1024 frames of Manchester data are received in a first detection cycle, the decoding success rate of the N-way register group is updated according to the decoding results of the 1024 frames, and the target current comparator is determined based on the way with the highest decoding success rate; 250 frames of Manchester data are received in the second detection cycle, and the decoding success rate of the N-way register group is continuously updated according to the decoding results of the 250 frames; The duty cycle of the target current comparator is calculated in each data cycle, and the current threshold is updated according to the gradient of the difference with the target duty cycle.

7. The method according to claim 4, characterized in that After the second detection cycle, when there are at least two current comparators with the same decoding success rate, the current comparator with the smallest difference between the current threshold and the corresponding initial threshold current is selected to determine the target current comparator.

8. A PSI5 interface circuit current threshold control device, characterized in that: The device is used for a PSI5 interface circuit including N-way current comparators, and the device comprises: A setting module is used to set a gradient-changing current threshold for N current comparators. When working, each current comparator generates a Manchester signal based on the sampled current value and the corresponding current threshold, and records the corresponding decoding success rate through a register group; A determination module, used to determine a target current comparator based on a decoding success rate recorded by N current comparators during a first detection cycle after power-on; The first updating module is used to obtain the Manchester coded signal output by the target current comparator and the corresponding current threshold and calculate the duty cycle value in the second detection cycle; update the current threshold of the target current comparator according to the duty cycle value gradient, and update the decoding success rate recorded by the N-way current comparator; The second updating module is used to obtain the decoding success rate recorded by the N current comparators in real time after the second detection cycle, and to re-determine the target current comparator, and to perform the steps of calculating the duty cycle and updating the current threshold for the target current comparator.

9. A computer device, characterized in that: The computer device includes a processor and a memory, wherein the memory stores at least one instruction, at least one program, a code set or an instruction set, and the at least one instruction, the at least one program, the code set or the instruction set is loaded and executed by the processor to implement the PSI5 interface circuit current threshold control method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The readable storage medium stores at least one instruction, at least one program, a code set or an instruction set, and the at least one instruction, the at least one program, the code set or the instruction set is loaded and executed by the processor to implement the PSI5 interface circuit current threshold control method as described in any one of claims 1 to 7.

Images