Implementation method of high-speed serialization based on processor parallel bus

Abstract

The invention belongs to the technical field of computer interfaces, and particularly relates to a high-speed serialization implementation method based on a processor parallel bus. The method comprises the steps that 1, in the write operation process of a monitoring branch processor, a monitoring branch FPGA generates a high-speed clock, when the processor initiates a write command, serial addresses and data are converted into Manchester codes, and the coded addresses and data are sent to an instruction branch FPGA through data lines; 2, in the read operation process of the monitoring branch processor, after an instruction receiving module of the instruction branch FPGA receives the address, data to be sent are uniformly arranged on a plurality of receiving data lines in a serial mode, and then the data to be sent are converted into Manchester codes through an encoding module and then sent to the monitoring branch FPGA.

Description

Technical Field

[0001] This invention belongs to the field of computer interface technology, specifically relating to a method for implementing high-speed serialization based on a processor parallel bus. Background Technology

[0002] The processor parallel bus is used by the processor to access peripherals and is widely used in various computer systems. It has advantages such as high transmission speed, low timing requirements for asynchronous transmission, and large data transmission capacity. However, because the processor bus is a parallel bus, it also has disadvantages such as a large number of signals, difficult wiring, and susceptibility to external interference.

[0003] To address these shortcomings, when the processor needs to access devices or components on the board, anti-crosstalk code value encoding can be used to serialize the parallel transmission medium between boards at high speed. This involves converting the processor bus into a high-speed serial bus for communication with other boards, and then converting the high-speed serial bus into a bus interface for the processor on the device to enable read and write operations between the processor and the device. Summary of the Invention

[0004] Purpose of the invention: This paper provides a method for implementing high-speed serialization based on a processor parallel bus. In the application scenario of processor writing to access external devices, the processor's parallel bus (including enable, address, and data) is converted into a high-speed serial bus through FPGA logic to access other devices in a serial transmission manner. In the application scenario of processor reading to access external devices, the processor's enable and address signals are converted into a high-speed serial bus, and the system waits for data feedback from the device. The high-speed serial bus data is then converted into parallel data for the processor and sent to the processor, thereby simplifying wiring, reducing design difficulty, and improving communication reliability.

[0005] Technical solution: A method for implementing high-speed serialization based on a processor parallel bus, the method being used to implement high-speed serialization of an instruction branch and a monitoring branch, wherein the instruction branch includes an instruction sending module and an instruction receiving module, and the monitoring branch includes a monitoring sending module and a monitoring receiving module, the method comprising: Step 1: During the write operation of the monitoring branch processor, the monitoring branch FPGA generates a high-speed clock. When the processor initiates a write command, it converts the serial address and data into Manchester encoding and sends the encoded address and data to the instruction branch FPGA through each data line. Step 2: During the read operation of the monitoring branch processor, after the instruction receiving module of the instruction branch FPGA receives the address, it serially and evenly arranges the data to be sent on multiple receiving data lines. Then, the encoding module converts the data to be sent into Manchester encoding and sends it to the monitoring branch FPGA.

[0006] Further, step 1 specifically includes: Step 11: After the reset signal of the monitoring branch FPGA becomes invalid, a synchronization clock is generated through the local clock and sent to the instruction branch FPGA; Step 12: The data conversion module monitors the processor. When the processor has no read or write commands, the control encoding module continuously sends out an idle state signal. Step 13: When the processor initiates a write command, the chip select signal is pulled low, the write enable is pulled low, and the read enable remains high. The processor sends in valid address and data. When the data conversion module detects a write operation, it converts the write command into a read / write enable for the instruction branch FPGA to recognize. The address and data are arranged on each serial data line through a shift register. The encoding module converts the serial data into Manchester encoding and sends the encoded data to the instruction branch FPGA through each data line. Step 14: After receiving the data sent by the monitoring branch FPGA, the instruction receiving module decodes the write data using a synchronous clock to obtain the serial data of each channel. After synchronizing with the local clock, it saves the encoding format of the write command, address, and data write operation in the shift register. Finally, after serial-to-parallel conversion, it parses out the read enable, address, and data. After receiving the instruction, the instruction branch FPGA sends it to the internal module to complete a write operation.

[0007] Furthermore, in step 11, the frequency of the transmitted synchronization clock is 100MHz.

[0008] Furthermore, in step 12, the idle signal is: logic 1 for 2 consecutive clock cycles, logic 0 for 2 consecutive clock cycles, and continuously loops.

[0009] Further, step 2 specifically includes: Step 21: The read operation requires the monitoring branch FPGA to send an address to the instruction branch FPGA and wait for feedback on the read data; Step 22: After receiving the address, the instruction receiving module of the instruction branch FPGA sends the data to the internal module. The internal module sends the data to the instruction sending module. The data conversion module of the instruction sending module arranges the data to be sent in the shift register. The feedback data format is evenly arranged serially on multiple receiving data lines. Then, it is converted into Manchester encoding by the encoding module and sent to the monitoring branch FPGA. Step 23: After receiving the data, the monitoring and receiving module identifies the start flag consisting of three high-level and three low-level signals. After identification, the data is decoded by the decoding module and finally converted into parallel data transmission via the shift register in the data conversion module and transmitted to the processor's data bus, completing one read operation.

[0010] Further, step 21 specifically includes: When the processor initiates a read command, the chip select signal is pulled low, the write enable remains high, the read enable is pulled low, the processor sends a valid address, and waits for feedback on the read data.

[0011] Further, step 21 specifically includes: When the data conversion module of the monitoring and sending module detects a read operation, the data conversion module converts the read command into a read / write enable. The address is evenly arranged serially on multiple data transmission lines. The address information is converted into Manchester encoding and sent to the instruction branch FPGA.

[0012] Furthermore, in step 21, the read / write enable is continuously low for 3 clock cycles and high for 3 clock cycles.

[0013] Furthermore, in step 22, the start flag for the feedback data is a high level for 3 clock cycles and a low level for 3 clock cycles, where X is an arbitrary value.

[0014] Beneficial effects: 1. High-speed serial communication is achieved between the instruction FPGA and the monitoring FPGA on the interface board to meet the large data volume read and write requirements of the monitoring processor to the instruction FPGA; 2. Converting a parallel bus to a high-speed serial bus simplifies circuit design and reduces wiring complexity; 3. Manchester encoding is used to achieve high-speed serial communication with strong anti-interference ability.

[0015] 4. Using synchronous data transmission simplifies the design and ensures the correctness of data transmission. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. The drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram illustrating the implementation method of high-speed serialization of the processor bus.

[0018] Figure 2This is a schematic diagram of the monitoring and sending module.

[0019] Figure 3 This diagram illustrates the clock sequence for the write operation and the order of the four transmit data lines.

[0020] Figure 4 This is a schematic diagram of the instruction receiving module.

[0021] Figure 5 This is a schematic diagram of the instruction sending module; Figure 6 A schematic diagram showing the data arrangement order of the read operation clock, 4 transmit data lines, and 4 receive data lines; Figure 7 This is a schematic diagram of the monitoring and receiving module. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0023] The features and illustrative embodiments of various aspects of the present invention will now be described in detail. Numerous specific details are set forth in the following detailed description to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without requiring some of these specific details. The following description of embodiments is merely intended to provide a better understanding of the invention by illustrating examples of the invention. The invention is by no means limited to any specific setups and methods set forth below, but covers any improvements, substitutions, and modifications to structures, methods, and devices without departing from the spirit of the invention. Well-known structures and techniques are not shown in the drawings and the following description to avoid unnecessarily obscuring the invention.

[0024] In the description of this invention, it should be noted that the directions or positional relationships indicated by terms such as "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer" are based on the directions or positional relationships shown in the accompanying drawings and are only for the convenience of describing and simplifying the invention, and should not be construed as limiting the invention. Furthermore, the use of ordinal numbers (e.g., "first and second," etc.) is for distinguishing objects and is not limited to this order, and should not be construed as indicating or implying relative importance.

[0025] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly, encompassing both direct connection and indirect connection via an intermediate medium. Those skilled in the art can understand the specific meaning of these terms in this invention based on the specific circumstances.

[0026] It should be noted that, unless otherwise specified, the embodiments of the present invention and the features thereof can be combined with each other, and the various embodiments can be referenced and cited in each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0027] The present invention will be further described in detail below with reference to the embodiments and accompanying drawings, but the embodiments of the present invention are not limited thereto.

[0028] This invention distributes processor bus read / write commands and data evenly across four high-speed buses and uses Manchester encoding to achieve data communication. On the monitoring branch FPGA, the FPGA receives read / write access transactions sent by the monitoring processor, generates serial communication protocol data after Manchester encoding, and the instruction branch FPGA receives and decodes the data, generating a read / write response. If a read operation is decoded, read data is sent to the monitoring branch FPGA, which then generates serial communication protocol data after Manchester encoding. The monitoring branch FPGA receives and decodes the data and feeds it back to the monitoring processor.

[0029] Figure 1 A schematic diagram illustrating a method for high-speed serialization of the processor bus, as shown below. Figure 1 As shown, the high-speed serialization implementation method of the processor bus in this patent includes two parts: the interface board instruction branch FPGA logic and the monitoring branch FPGA logic. The instruction branch FPGA and the monitoring branch FPGA each include a transmitting module and a receiving module. Among them, the monitoring branch FPGA is the master device, responsible for initiating read and write operations, and the instruction branch FPGA is the slave device, responsible for executing the read and write operations initiated by the monitoring branch.

[0030] The following describes a specific implementation method of the high-speed serialization based on a processor parallel bus according to the present invention, using the data flow of reading and writing data as an example.

[0031] Monitor processor write operations: Figure 2 This is a schematic diagram of the monitoring and sending module, as shown below. Figure 2 As shown, the monitoring and sending module includes a data conversion module and an encoding module.

[0032] Step 1: After the reset signal of the monitoring branch FPGA becomes invalid, a synchronization clock (a high-speed clock of greater than or equal to 50MHz) is generated through the local clock and sent to the instruction branch FPGA. The frequency of sending the synchronization clock is 100MHz.

[0033] Step 2: The data conversion module monitors the processor. When the processor has no read or write commands, the control encoding module continuously sends an idle state signal, which is logic 1 for 2 clock cycles and logic 0 for 2 clock cycles, and then repeats continuously.

[0034] Step 3: When the processor initiates a write command, the chip select signal is pulled low, the write enable signal is pulled low, and the read enable signal remains high. The processor then sends in valid address and data. Figure 3 To synchronize the write operation with the clock and the transmission order of the four data lines, when the data conversion module detects a write operation, it converts the write command into... Figure 3 The read / write enable signal, which is a flag signal that remains high for three clock cycles followed by low for three clock cycles, is used by the instruction branch FPGA for identification. Address and data are processed according to... Figure 3 As shown, the shift registers are arranged in Figure 2 The serial data consists of serial data 1, serial data 2, serial data 3, and serial data 4. The encoding module converts the serial data into Manchester encoding and sends the encoded data to the instruction branch FPGA via data transmission lines 1, 2, 3, and 4. The instruction receiving module then receives and decodes the data.

[0035] Step Four: Figure 4 The instruction receiving module receives data sent by the monitoring branch FPGA, decodes the write data using a synchronous clock to obtain serial data 1, serial data 2, serial data 3, and serial data 4, and then synchronizes it with the local clock before sending the write command, address, and data according to... Figure 3 The data is stored in a shift register and then parsed through serial-to-parallel conversion to extract the read enable, address, and data. After the instruction branch of the FPGA receives the data, it sends it to the internal module to complete a write operation.

[0036] Monitor processor read operations: Step 1: The read operation requires the monitoring branch FPGA to send an address to the instruction branch FPGA and wait for feedback on the read data. When the processor initiates a read command, the chip select signal is pulled low, the write enable remains high, the read enable is pulled low, the processor sends a valid address, and waits for feedback on the read data. Figure 6 For the read operation clock, the arrangement of the 4 transmit data lines and the 4 receive data lines, when Figure 2 When the data conversion module of the monitoring and sending module detects a read operation, the data conversion module converts the read command into a read command. Figure 6The read / write enable in the address is maintained at a low level for 3 clock cycles followed by a high level for 3 clock cycles. Figure 6 The data is arranged in the order shown and converted into Manchester encoding before being sent to the instruction branch FPGA.

[0037] Step 2: After the instruction receiving module of the FPGA receives the address, it... Figure 4 The instruction receiving module sends the data to the internal module, and the internal module sends the data to... Figure 5 The instruction sending module, the data conversion module of the instruction sending module according to Figure 6 The data to be sent is arranged in the shift register, and the feedback data format is as follows: Figure 6 The data receiving lines 1, 2, 3, and 4 are shown in the diagram. The start flag consists of a high level for 3 clock cycles and a low level for 3 clock cycles. X is an arbitrary value. The data is then converted into Manchester encoding by the encoding module and sent to the monitoring branch FPGA.

[0038] Step 3: Figure 7 After receiving the data, the monitoring and receiving module identifies the start flags of three high-level and three low-level signals. After identification, the data is decoded by the decoding module and finally converted into parallel data transmission through the shift register in the data conversion module and transmitted to the processor's data bus, completing one read operation.

[0039] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for implementing high-speed serialization based on a processor parallel bus, characterized in that, The method is used to achieve high-speed serialization of the instruction branch and the monitoring branch. The instruction branch includes an instruction sending module and an instruction receiving module, and the monitoring branch includes a monitoring sending module and a monitoring receiving module. The method includes: Step 1: During the write operation of the monitoring branch processor, the monitoring branch FPGA generates a high-speed clock. When the processor initiates a write command, it converts the serial address and data into Manchester encoding and sends the encoded address and data to the instruction branch FPGA through each data line. Step 2: During the read operation of the monitoring branch processor, after the instruction receiving module of the instruction branch FPGA receives the address, it serially and evenly arranges the data to be sent on multiple receiving data lines. Then, the encoding module converts the data to be sent into Manchester encoding and sends it to the monitoring branch FPGA.

2. The method according to claim 1, characterized in that, Step 1, specifically: Step 11: After the reset signal of the monitoring branch FPGA becomes invalid, a synchronization clock is generated through the local clock and sent to the instruction branch FPGA; Step 12: The data conversion module monitors the processor. When the processor has no read or write commands, the control encoding module continuously sends out an idle state signal. Step 13: When the processor initiates a write command, the chip select signal is pulled low, the write enable is pulled low, and the read enable remains high. The processor sends in valid address and data. When the data conversion module detects a write operation, it converts the write command into a read / write enable for the instruction branch FPGA to recognize. The address and data are arranged on each serial data line through a shift register. The encoding module converts the serial data into Manchester encoding and sends the encoded data to the instruction branch FPGA through each data line. Step 14: After receiving the data sent by the monitoring branch FPGA, the instruction receiving module decodes the write data using a synchronous clock to obtain the serial data of each channel. After synchronizing with the local clock, it saves the encoding format of the write command, address, and data write operation in the shift register. Finally, after serial-to-parallel conversion, it parses out the read enable, address, and data. After receiving the instruction, the instruction branch FPGA sends it to the internal module to complete a write operation.

3. The method according to claim 2, characterized in that, In step 11, the frequency of the transmitted synchronization clock is 100MHz.

4. The method according to claim 3, characterized in that, In step 12, the idle signal is: logic 1 for 2 consecutive clock cycles, logic 0 for 2 consecutive clock cycles, and this cycle continues.

5. The method according to claim 4, characterized in that, Step 2 specifically includes: Step 21: The read operation requires the monitoring branch FPGA to send an address to the instruction branch FPGA and wait for feedback on the read data; Step 22: After receiving the address, the instruction receiving module of the instruction branch FPGA sends the data to the internal module. The internal module sends the data to the instruction sending module. The data conversion module of the instruction sending module arranges the data to be sent in the shift register. The feedback data format is evenly arranged serially on multiple receiving data lines. Then, it is converted into Manchester encoding by the encoding module and sent to the monitoring branch FPGA. Step 23: After receiving the data, the monitoring and receiving module identifies the start flag consisting of three high-level and three low-level signals. After identification, the data is decoded by the decoding module and finally converted into parallel data transmission via the shift register in the data conversion module and transmitted to the processor's data bus, completing one read operation.

6. The method according to claim 5, characterized in that, Step 21, specifically: When the processor initiates a read command, the chip select signal is pulled low, the write enable remains high, the read enable is pulled low, the processor sends a valid address, and waits for feedback on the read data.

7. The method according to claim 6, characterized in that, Step 21, specifically: When the data conversion module of the monitoring and sending module detects a read operation, the data conversion module converts the read command into a read / write enable. The address is evenly arranged serially on multiple data transmission lines. The address information is converted into Manchester encoding and sent to the instruction branch FPGA.

8. The method according to claim 7, characterized in that, In step 21, the read / write enable is continuously low for 3 clock cycles and high for 3 clock cycles.

9. The method according to claim 8, characterized in that, In step 22, the start flag for the feedback data is a high level for 3 clock cycles and a low level for 3 clock cycles, where X is any value.

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