FPGA-based SDRAM time sequence parameter adaptive configuration system and method

Abstract

The invention relates to an FPGA-based SDRAM time sequence parameter adaptive configuration system and method. The FPGA-based SDRAM time sequence parameter adaptive configuration system comprises a signal acquisition module and a signal time sequence calculation and correction module, the signal acquisition module is used for realizing time sequence waveform acquisition of various signals of the SDRAM; the output end of the signal acquisition module is connected with the signal time sequence calculation and correction module, and the signal acquisition module is used for phase analysis and clock phase correction value calculation of each time sequence waveform of the SDRAM; the output end of the signal time sequence calculation and correction module is connected with the FPGA module, and the signal time sequence calculation and correction module is used for transmitting a clock phase correction value to the FPGA module; an SDRAM time sequence adjusting module is arranged in the FPGA module and is used for adjusting an SDRAM time sequence parameter according to the received clock phase correction value; and the SDRAM time sequence adjusting module is connected with the SDRAM module and is used for controlling a signal time sequence during data transmission of the SDRAM. According to the invention, the problems of complex configuration and low efficiency of SDRAM time sequence parameters can be solved.

Description

Technical Field

[0001] The invention belongs to the technical field of computer data transmission, and relates to a SDRAM timing parameter adaptive configuration system and method, in particular to a SDRAM timing parameter adaptive configuration system and method based on FPGA. Background Art

[0002] At present, SDRAM (Synchronous Dynamic Random Access Memory) is widely used in embedded devices to expand the memory space of embedded devices. However, before the processor can read the SDRAM chip normally, the SDRAM initialization needs to be completed, including the configuration of parameters such as timing parameters, data bit width, column address bit, row address bit, and bank address bit. Among them, parameters such as data bit width, column address bit, row address bit, and bank address bit are called static parameters. After determining the SDRAM model, the static parameters can be determined. However, the timing parameter configuration is related to the timing characteristics of the SDRAM itself and the actual design of the embedded system, which is a relatively complex configuration process.

[0003] In different embedded devices, the objects mounted by SDRAM are different. The mounted objects are mainly divided into two categories. One is the processor with integrated SDRAM controller, such as DSP, ARM, etc. These processors have SDRAM controller integrated inside. Users can directly configure the registers corresponding to the SDRAM controller according to the various parameters provided by the SDRAM manufacturer to complete the configuration of the SDRAM chip, so that the processor can correctly read and write the SDRAM chip mounted outside the chip; the other is the processor without integrated SDRAM controller, such as FPGA, etc. Users need to use software code to implement the function of the SDRAM controller by themselves and configure the relevant parameters of the SDRAM chip to achieve correct read and write operations on the SDRAM chip.

[0004] During the initial configuration of SDRAM in an embedded device, or when the SDRAM is replaced due to changes in external requirements, if the processor object to which the SDRAM is mounted has an SDRAM controller integrated inside, the user can directly configure the registers corresponding to the SDRAM controller according to the various parameters provided by the SDRAM manufacturer to complete the parameter configuration of the SDRAM chip; if the processor object to which the SDRAM is mounted does not have an SDRAM controller integrated inside, the user needs to modify the software code adapted to different SDRAM chips, reconfigure the static parameters and timing parameters of the SDRAM, and perform a timing parameter stability test to achieve correct read and write operations on the SDRAM chip, which will have a significant impact on the R&D progress and efficiency of the system.

[0005] Therefore, for processors without an integrated SDRAM controller, the process of configuring SDRAM parameters is cumbersome and complicated, which seriously affects the efficiency of development and debugging. Among them, static parameters can be easily modified according to the data sheet provided by the SDRAM manufacturer, and no analysis is required; for timing parameter configuration, it is closely related to the timing characteristics of SDRAM itself and the actual design of the embedded system, and timing optimization and timing stability analysis are required, which is also the focus and difficulty of SDRAM debugging.

[0006] However, the existing SDRAM timing parameter adaptive configuration system and method have the following defects and shortcomings:

[0007] Only the static parameters of SDRAM can be automatically configured, but the timing parameters of SDRAM cannot be adaptively configured according to the actual design and application of the embedded system. Moreover, it is very inefficient to modify different timing parameters of SDRAM according to different embedded systems.

[0008] Therefore, the present invention proposes an FPGA-based SDRAM timing parameter adaptive configuration system and method to solve the above technical problems. Summary of the invention

[0009] The purpose of the present invention is to overcome the deficiencies of the prior art and to provide an FPGA-based SDRAM timing parameter adaptive configuration system and method, which can solve the problems of complex and low efficiency of SDRAM timing parameter configuration.

[0010] The present invention solves the practical problem by adopting the following technical solutions:

[0011] A FPGA-based SDRAM timing parameter adaptive configuration system comprises: a signal acquisition module and a signal timing calculation and correction module; the signal acquisition module is used to realize the timing waveform acquisition of various SDRAM signals; the output end of the signal acquisition module is connected to the signal timing calculation and correction module, which is used for phase analysis of various SDRAM timing waveforms and calculation of clock phase correction values; the output end of the signal timing calculation and correction module is connected to the FPGA module, which is used to transfer the clock phase correction value to the FPGA module; the FPGA module is provided with an SDRAM timing adjustment module, which is used to adjust the SDRAM timing parameters according to the received clock phase correction value; the SDRAM timing adjustment module is connected to the SDRAM module, which is used to control the signal timing during SDRAM data transmission.

[0012] A method for adaptively configuring SDRAM timing parameters based on FPGA, comprising the following steps:

[0013] Step 1: According to the theoretical calculation model of SDRAM timing parameters, the initial theoretical adjustment value of the clock phase in the SDRAM timing adjustment module is set;

[0014] Step 2, FPGA executes SDRAM read and write access self-test commands;

[0015] Step 3: While performing SDRAM read and write access, the signal acquisition module in the timing parameter adaptive configuration system collects the timing information of each signal through the signal acquisition probe, and sends the timing data to the signal timing calculation and correction module;

[0016] Step 4: The signal timing calculation and correction module parses out the signals that do not meet the timing requirements according to the setup time and hold time requirements of each signal, and sends the timing phase correction value to the FPGA. Then the SDRAM timing adjustment module adjusts the clock phase according to the timing correction value.

[0017] Step 5: Repeat steps 2 to 4 until all signals of the SDRAM meet their respective setup time and hold time requirements, thereby ensuring that the FPGA can stably read and write data to the SDRAM.

[0018] Moreover, the specific method of step 1 is:

[0019] Firstly, according to the requirements of setup and hold time of various signals provided by SDRAM chip manufacturers, including control signals, address signals and data signals, as well as the wiring delay of various signals and clock signals on the actual printed circuit board, the initial theoretical adjustment value of the clock phase in the SDRAM timing adjustment module is configured based on the theoretical calculation model of SDRAM timing parameters.

[0020] Moreover, the specific steps of configuring the initial theoretical adjustment value of the clock phase in the SDRAM timing adjustment module include:

[0021] (1) Based on the way FPGA mounts SDRAM and the logic of data sending and receiving, a theoretical calculation model of SDRAM timing parameters for FPGA accessing SDRAM is established;

[0022] Among them, T c2i_fp is the routing delay of the clock signal from the FPGA clock input pin to the flip-flop 1 clock input pin, T Launch_Edge is the launch edge delay of trigger 1 in FPGA, T reg2pin is the routing delay of a signal from the output pin of trigger 1 to the output pin of FPGA, T d_pcb is the PCB routing delay of a signal from the FPGA output pin to the SDRAM input pin, T c2j_fpis the routing delay of the clock signal from the FPGA clock input pin to the FPGA clock output pin, T c2j_pcb is the PCB routing delay of the clock signal from the FPGA clock output pin to the SDRAM clock input pin, T Latch_Edge is the data latch edge delay of trigger 2 in SDRAM, T su The setup time required by the SDRAM chip, T h The hold time requirement for SDRAM chips.

[0023] (2) Based on the SDRAM timing parameter theoretical calculation model established in step (1), a formula for calculating the setup time margin is given;

[0024] The actual arrival time of a signal from FPGA to SDRAM is calculated as:

[0025] T Data_Arrival =T Launch_Edge +T c2i_fp +T reg2pin +T d_pcb (Formula 1)

[0026] Only when the signal meets the setup time requirement of SDRAM can FPGA stably access data to SDRAM. Therefore, the required arrival time calculation formula of a signal from FPGA to SDRAM is:

[0027]

[0028] Then, the formula for calculating the margin of a signal setup time is:

[0029]

[0030] In formula 3, T c2j_fp , T c2i_fp , T reg2pin is the internal wiring delay of FPGA, let

[0031]

[0032] After completing the layout and routing, the FPGA development tool will automatically calculate The value of .

[0033] In formula 3, let

[0034]

[0035] After the FPGA and SDRAM are selected and the actual PCB layout and routing are determined, T can be obtained based on the chip data sheet and the actual PCB wiring length. Latch_Edge , T c2j_pcb, T su , T Clock_Uncertainty , T Launch_Edge , T d_pcb Given the value of , we can get The value of .

[0036] In summary, the formula for calculating the margin of a signal setup time is:

[0037]

[0038] (3) Based on the SDRAM timing parameter theoretical calculation model established in step (1), a calculation formula for the hold time margin is given;

[0039] The actual arrival time calculation formula of a signal from FPGA to SDRAM is shown in Formula 1;

[0040] Only when the signal meets the hold time requirement of SDRAM can FPGA stably access data to SDRAM. Therefore, the required arrival time calculation formula of a signal from FPGA to SDRAM is:

[0041]

[0042] Then, the calculation formula for the margin of a signal holding time is:

[0043]

[0044] In formula 8, T c2i_fp , T reg2pin , T c2j_fp is the internal wiring delay of FPGA, let

[0045]

[0046] After completing the layout and routing, the FPGA development tool will automatically calculate The value of .

[0047] In formula 8, let

[0048]

[0049] After the FPGA and SDRAM are selected and the actual PCB layout and routing are determined, T can be obtained based on the chip data sheet and the actual PCB wiring length. Launch_Edge , T d_pcb , T Latch_Edge , T c2j_pcb , T h , T Clock_Uncertainty Given the value of , we can get The value of .

[0050] In summary, the margin calculation formula for a signal holding time is:

[0051]

[0052] (4) Perform setup time and hold time margin analysis;

[0053] To meet the setup time and hold time requirements of SDRAM, it is necessary to

[0054]

[0055]

[0056] After the FPGA and SDRAM are selected and the actual PCB layout and routing are determined, The value of has been determined, so the only way to make Formula 12 and Formula 13 valid is to adjust the internal wiring delay of the FPGA. However, in most cases, it is not possible to make Formula 12 and Formula 13 valid at the same time by simply adjusting the internal wiring delay of the FPGA.

[0057] Introduce an SDRAM timing adjustment module inside the FPGA:

[0058] After the SDRAM timing adjustment module is introduced, the margin calculation formula for the setup time of a certain SDRAM signal (Formula 6) is modified as follows:

[0059]

[0060] The margin calculation formula for the hold time of a certain signal in SDRAM (Formula 11) is modified as follows:

[0061]

[0062] To meet the setup time and hold time requirements of SDRAM, it is necessary to

[0063]

[0064] From formula 16, we can get:

[0065]

[0066] The theoretical adjustment value of the clock phase that satisfies the signal setup time and hold time is obtained. In order to ensure that both the setup time and the hold time have a large time margin, the initial theoretical adjustment value of the clock phase is generally taken as:

[0067]

[0068] Moreover, the calculation method of the clock phase correction value in step 4 is:

[0069] In order to meet the setup time and hold time requirements of SDRAM, set the clock phase correction value, which needs to satisfy the following formula:

[0070]

[0071] Among them, T s ' u , T h ' are the actual measured values ​​of setup time and hold time given by the signal timing calculation and correction module, T su , T h The setup time and hold time required by the SDRAM data sheet.

[0072] From formula 19, we can get:

[0073] (T su -T s ' u )<ΔT Phase_Adjust <(T h '-T h )(Formula 20)

[0074] In order to ensure that both the setup time and the hold time have a large time margin, the clock phase correction value is generally taken as

[0075]

[0076] Combined with formula 18, the clock phase correction value can be obtained as follows:

[0077]

[0078] Advantages and beneficial effects of the present invention:

[0079] 1. Compared with the existing SDRAM parameter automatic configuration method, the FPGA-based SDRAM timing parameter adaptive configuration method proposed in the present invention can solve the key technical problem that the existing SDRAM parameter automatic configuration technology cannot adaptively configure the SDRAM timing parameters through the timing parameter adaptive configuration system, and can greatly improve the efficiency of adjusting the complex timing parameters of SDRAM in different embedded systems.

[0080] 2. The present invention is based on an FPGA logic processor and designs an FPGA-based SDRAM timing parameter adaptive configuration method. First, a SDRAM timing parameter theoretical calculation model is established for the SDRAM signal, and then the timing parameters are corrected using the FPGA-based SDRAM timing parameter adaptive configuration system to ensure that each signal of the SDRAM meets the setup time and hold time requirements, thereby ensuring the stability of SDRAM data access.

[0081] 3. The present invention proposes a theoretical calculation model for SDRAM timing parameters, which provides theoretical calculation values ​​for adjusting signal timing parameters while meeting signal setup time and hold time requirements, thereby realizing adaptive adjustment of SDRAM timing parameters to ensure the stability of SDRAM data access.

[0082] 4. The present invention proposes an FPGA-based SDRAM timing parameter adaptive configuration system, including a signal acquisition module and a signal timing calculation and correction module. The device can realize the correction and adaptive adjustment of SDRAM timing parameters according to the collected SDRAM actual signal timing information.

[0083] 5. The present invention proposes an FPGA-based SDRAM timing parameter adaptive configuration system and method, which can realize SDRAM timing parameter adaptive adjustment. The system includes: a signal acquisition module, a signal timing calculation and correction module, and the signal acquisition module and the signal timing calculation and correction module are integrated in the timing parameter adaptive configuration system. BRIEF DESCRIPTION OF THE DRAWINGS

[0084] Figure 1 The present invention is a block diagram of the FPGA-based SDRAM timing parameter adaptive configuration system.

[0085] Figure 2 A schematic diagram of a theoretical calculation model of SDRAM timing parameters of the present invention;

[0086] Figure 3 It is a schematic diagram of a theoretical calculation model of SDRAM timing parameters after the clock phase adjustment module is introduced into the present invention;

[0087] Figure 4 The present invention is a flow chart of the SDRAM timing parameter adaptive configuration; DETAILED DESCRIPTION

[0088] The embodiments of the present invention are further described in detail below with reference to the accompanying drawings:

[0089] An FPGA-based SDRAM timing parameter adaptive configuration system, such as Figure 1As shown, it includes: a signal acquisition module and a signal timing calculation and correction module; the signal acquisition module is used to realize the timing waveform acquisition of various SDRAM signals; the output end of the signal acquisition module is connected to the signal timing calculation and correction module, which is used for phase analysis of various SDRAM timing waveforms and calculation of clock phase correction values; the output end of the signal timing calculation and correction module is connected to the FPGA module, which is used to transfer the clock phase correction value to the FPGA module; the FPGA module is provided with an SDRAM timing adjustment module, which is used to adjust the SDRAM timing parameters according to the received clock phase correction value; the SDRAM timing adjustment module is connected to the SDRAM module, and is used to control the signal timing during SDRAM data transmission.

[0090] In this embodiment, when the FPGA actually accesses the SDRAM, due to the influence of various factors such as chip batch differences, PCB processing errors, and the use environment, the clock phase theoretical adjustment value given by formula 18 still causes the FPGA to access the SDRAM unstably in some cases. Therefore, the present invention designs an SDRAM timing parameter adaptive configuration system based on FPGA, which uses the actual collected signal timing information to correct the clock phase theoretical adjustment value, so that the FPGA can always achieve stable access to the SDRAM during actual application.

[0091] The timing parameter adaptive configuration system mainly realizes the functions of SDRAM timing signal acquisition, calculation and correction, including: signal acquisition module, signal timing calculation and correction module. Among them, the signal acquisition module arranges three signal acquisition probes on the signal pins of SDRAM, namely control signal probe, address signal probe and data signal probe, so as to realize the timing waveform acquisition of various SDRAM signals.

[0092] After completing the acquisition of the signal timing waveform, the signal acquisition module sends the timing waveform data information to the signal timing calculation and correction module. This module implements the analysis of the signal timing waveform and gives the correction value of the SDRAM timing adjustment module according to the analysis result.

[0093] A method for adaptively configuring SDRAM timing parameters based on FPGA, such as Figure 4 As shown, the following steps are included:

[0094] Step 1: According to the theoretical calculation model of SDRAM timing parameters, the initial theoretical adjustment value of the clock phase in the SDRAM timing adjustment module is set;

[0095] The specific method of step 1 is:

[0096] First, according to the setup time and hold time requirements of each signal (including control signal, address signal, and data signal) provided by the SDRAM chip manufacturer, as well as the wiring delay of each signal and the clock signal on the actual printed circuit board, based on the SDRAM timing parameter theoretical calculation model, the initial theoretical adjustment value of the clock phase in the SDRAM timing adjustment module is configured.

[0097] The specific steps of configuring the initial theoretical adjustment value of the clock phase in the SDRAM timing adjustment module include:

[0098] (1) Based on the way FPGA mounts SDRAM and the logic of data sending and receiving, a theoretical calculation model of SDRAM timing parameters for FPGA access to SDRAM is established, such as Figure 2 shown.

[0099] Among them, T c2i_fp is the routing delay of the clock signal from the FPGA clock input pin to the flip-flop 1 clock input pin, T Launch_Edge is the launch edge delay of trigger 1 in FPGA, T reg2pin is the routing delay of a signal from the output pin of trigger 1 to the output pin of FPGA, T d_pcb is the PCB routing delay of a signal from the FPGA output pin to the SDRAM input pin, T c2j_fp is the routing delay of the clock signal from the FPGA clock input pin to the FPGA clock output pin, T c2j_pcb is the PCB routing delay of the clock signal from the FPGA clock output pin to the SDRAM clock input pin, T Latch_Edge is the data latch edge delay of trigger 2 in SDRAM, T su The setup time required by the SDRAM chip, T h The hold time requirement for SDRAM chips.

[0100] In this embodiment, in order to ensure that the FPGA chip can stably read and write data to the SDRAM, each signal needs to meet the setup time and hold time requirements of the SDRAM. Figure 2 The SDRAM timing parameter theoretical calculation model can be used to obtain the setup time margin calculation formula and the hold time margin calculation formula for a certain signal.

[0101] (2) Based on the SDRAM timing parameter theoretical calculation model established in step (1), a formula for calculating the setup time margin is given;

[0102] according to Figure 2 As shown in Figure 1, the actual arrival time calculation formula of a signal from FPGA to SDRAM is:

[0103] T Data_Arrival =T Launch_Edge +T c2i_fp +T reg2pin +T d_pcb (Formula 1)

[0104] Only when the signal meets the setup time requirement of SDRAM can FPGA stably access data to SDRAM. Therefore, the required arrival time calculation formula of a signal from FPGA to SDRAM is:

[0105]

[0106] Then, the formula for calculating the margin of a signal setup time is:

[0107]

[0108] In formula 3, T c2j_fp , T c2i_fp , T reg2pin is the internal wiring delay of FPGA, let

[0109]

[0110] After completing the layout and routing, the FPGA development tool will automatically calculate The value of .

[0111] In formula 3, let

[0112]

[0113] After the FPGA and SDRAM are selected and the actual PCB layout and routing are determined, T can be obtained based on the chip data sheet and the actual PCB wiring length. Latch_Edge , T c2j_pcb , T su , T Clock_Uncertainty , T Launch_Edge , T d_pcb Given the value of , we can get The value of .

[0114] In summary, the formula for calculating the margin of a signal setup time is:

[0115]

[0116] (3) Based on the SDRAM timing parameter theoretical calculation model established in step (1), a calculation formula for the hold time margin is given;

[0117] The actual arrival time calculation formula of a signal from FPGA to SDRAM is shown in Formula 1;

[0118] Only when the signal meets the hold time requirement of SDRAM can FPGA stably access data to SDRAM. Therefore, the required arrival time calculation formula of a signal from FPGA to SDRAM is:

[0119]

[0120] Then, the calculation formula for the margin of a signal holding time is:

[0121]

[0122] In formula 8, T c2i_fp , T reg2pin , T c2j_fp is the internal wiring delay of FPGA, let

[0123]

[0124] After completing the layout and routing, the FPGA development tool will automatically calculate The value of .

[0125] In formula 8, let

[0126]

[0127] After the FPGA and SDRAM are selected and the actual PCB layout and routing are determined, T can be obtained based on the chip data sheet and the actual PCB wiring length. Launch_Edge , T d_pcb , T Latch_Edge , T c2j_pcb , T h , T Clock_Uncertainty Given the value of , we can get The value of .

[0128] In summary, the calculation formula for the margin of a signal holding time is:

[0129]

[0130] (4) Perform setup time and hold time margin analysis;

[0131] To meet the setup time and hold time requirements of SDRAM, it is necessary to

[0132]

[0133] After the FPGA and SDRAM are selected and the actual PCB layout and routing are determined, The value of has been determined, so the only way to make Formula 12 and Formula 13 valid is to adjust the internal wiring delay of the FPGA. However, in most cases, it is not possible to make Formula 12 and Formula 13 valid at the same time by simply adjusting the internal wiring delay of the FPGA.

[0134] Therefore, the present invention introduces a SDRAM timing adjustment module inside the FPGA, such as Figure 3 shown.

[0135] After the SDRAM timing adjustment module is introduced, the margin calculation formula for the setup time of a certain SDRAM signal (Formula 6) is modified as follows:

[0136]

[0137] The margin calculation formula for the hold time of a certain signal in SDRAM (Formula 11) is modified as follows:

[0138]

[0139] To meet the setup time and hold time requirements of SDRAM, it is necessary to

[0140]

[0141] From formula 16, we can get:

[0142]

[0143] Therefore, the theoretical adjustment value of the clock phase that satisfies the signal setup time and hold time can be obtained. In order to ensure that both the setup time and the hold time have a large time margin, the initial theoretical adjustment value of the clock phase is generally taken as:

[0144]

[0145] Step 2, FPGA executes SDRAM read and write access self-test commands;

[0146] Step 3: While performing SDRAM read and write access, the signal acquisition module in the timing parameter adaptive configuration system collects the timing information of each signal through the signal acquisition probe, and sends the timing data to the signal timing calculation and correction module;

[0147] Step 4: The signal timing calculation and correction module parses out the signals that do not meet the timing requirements according to the setup time and hold time requirements of each signal, and sends the timing phase correction value to the FPGA. Then the SDRAM timing adjustment module adjusts the clock phase according to the timing correction value.

[0148] The calculation method of the clock phase correction value in step 4 is:

[0149] In order to meet the setup time and hold time requirements of SDRAM, set the clock phase correction value, which needs to satisfy the following formula:

[0150]

[0151] Among them, T s ' u , T h ' are the actual measured values ​​of setup time and hold time given by the signal timing calculation and correction module, T su , T h The setup time and hold time required by the SDRAM data sheet.

[0152] From formula 19, we can get:

[0153] (T su -T' su )<ΔT Phase_Adjust <(T' h -T h ) (Formula 20)

[0154] In order to ensure that both the setup time and the hold time have a large time margin, the clock phase correction value is generally taken as

[0155]

[0156] Combined with formula 18, the clock phase correction value can be obtained as follows:

[0157]

[0158] Step 5: Repeat steps 2 to 4 until all signals of the SDRAM meet their respective setup time and hold time requirements, thereby ensuring that the FPGA can stably read and write data to the SDRAM.

[0159] In this embodiment, the present invention is further described by using specific examples:

[0160] According to formula 18, the initial theoretical adjustment value of the clock phase is first set, and then when the SDRAM read and write access self-test command is executed, the signal acquisition module collects various signal timing waveforms and sends the timing waveform data information to the signal timing calculation and correction module;

[0161] 1) The signal timing calculation and correction module analyzes the signal timing waveform and calculates the signal setup time and hold time according to the clock latch edge;

[0162] 2) Compare the actual measured setup time and hold time with the time required by the SDRAM data sheet. If the data sheet time requirements are met, no clock phase adjustment is performed.

[0163] 3) If the setup time and hold time actually measured and calculated do not meet the time requirements, it is necessary to calculate the clock phase correction value and send the correction value to the timing adjustment module of the FPGA for clock phase adjustment operation;

[0164] 4) Repeat steps 1 to 4 until the signal setup time and hold time actually measured and calculated meet the time required by the SDRAM data sheet, completing the SDRAM timing parameter adaptive configuration.

[0165] It should be emphasized that the embodiments of the present invention are illustrative rather than restrictive. Therefore, the present invention includes but is not limited to the embodiments described in the specific implementation modes. Any other implementation modes derived by those skilled in the art based on the technical solutions of the present invention also fall within the scope of protection of the present invention.

Claims

1. An FPGA-based SDRAM timing parameter adaptive configuration system, characterized in that: include: Signal acquisition module and signal timing calculation and correction module; The signal acquisition module is used to acquire the timing waveforms of various SDRAM signals; The output end of the signal acquisition module is connected to the signal timing calculation and correction module, which is used for phase analysis of each SDRAM timing waveform and calculation of the clock phase correction value; the output end of the signal timing calculation and correction module is connected to the FPGA module, which is used to transfer the clock phase correction value to the FPGA module; the FPGA module is provided with an SDRAM timing adjustment module, which is used to adjust the SDRAM timing parameters according to the received clock phase correction value; the SDRAM timing adjustment module is connected to the SDRAM module, which is used to control the signal timing during SDRAM data transmission.

2. A method for adaptively configuring SDRAM timing parameters based on FPGA, characterized in that: The following steps are involved: Step 1: According to the theoretical calculation model of SDRAM timing parameters, the initial theoretical adjustment value of the clock phase in the SDRAM timing adjustment module is set; Step 2, FPGA executes SDRAM read and write access self-test commands; Step 3: While performing SDRAM read and write access, the signal acquisition module in the timing parameter adaptive configuration system collects the timing information of each signal through the signal acquisition probe, and sends the timing data to the signal timing calculation and correction module; Step 4: The signal timing calculation and correction module parses out the signals that do not meet the timing requirements according to the setup time and hold time requirements of each signal, and sends the timing phase correction value to the FPGA. Then the SDRAM timing adjustment module adjusts the clock phase according to the timing correction value. Step 5: Repeat steps 2 to 4 until all signals of the SDRAM meet their respective setup time and hold time requirements, thereby ensuring that the FPGA can stably read and write data to the SDRAM.

3. The method for adaptively configuring SDRAM timing parameters based on FPGA according to claim 1, characterized in that: The specific method of step 1 is: Firstly, according to the requirements of setup and hold time of various signals provided by SDRAM chip manufacturers, including control signals, address signals and data signals, as well as the wiring delay of various signals and clock signals on the actual printed circuit board, the initial theoretical adjustment value of the clock phase in the SDRAM timing adjustment module is configured based on the theoretical calculation model of SDRAM timing parameters.

4. The method for adaptively configuring SDRAM timing parameters based on FPGA according to claim 3, characterized in that: The specific steps of configuring the initial theoretical adjustment value of the clock phase in the SDRAM timing adjustment module include: (1) Based on the way FPGA mounts SDRAM and the logic of data sending and receiving, a theoretical calculation model of SDRAM timing parameters for FPGA accessing SDRAM is established; Among them, T c2i_fp is the routing delay of the clock signal from the FPGA clock input pin to the flip-flop 1 clock input pin, T Launch_Edge is the launch edge delay of trigger 1 in FPGA, T reg2pin is the routing delay of a signal from the output pin of trigger 1 to the output pin of FPGA, T d_pcb is the PCB routing delay of a signal from the FPGA output pin to the SDRAM input pin, T c2j_fp is the routing delay of the clock signal from the FPGA clock input pin to the FPGA clock output pin, T c2j_pcb is the PCB routing delay of the clock signal from the FPGA clock output pin to the SDRAM clock input pin, T Latch_Edge is the data latch edge delay of trigger 2 in SDRAM, T su The setup time required by the SDRAM chip, T h The hold time requirement for SDRAM chips; (2) Based on the SDRAM timing parameter theoretical calculation model established in step (1), a formula for calculating the setup time margin is given; The actual arrival time of a signal from FPGA to SDRAM is calculated as: T Data_Arrival =T Launch_Edge +T c2i_fp +T reg2pin +T d_pcb (Formula 1) Only when the signal meets the setup time requirement of SDRAM can FPGA stably access data to SDRAM. Therefore, the required arrival time calculation formula of a signal from FPGA to SDRAM is: Then, the formula for calculating the margin of a signal setup time is: In formula 3, T c2j_fp , T c2i_fp , T reg2pin is the internal wiring delay of FPGA, let After completing the layout and routing, the FPGA development tool will automatically calculate The value of In formula 3, let After the FPGA and SDRAM are selected and the actual PCB layout and routing are determined, T can be obtained based on the chip data sheet and the actual PCB wiring length. Latch_Edge , T c2j_pcb , T su , T Clock_Uncertainty , T Launch_Edge , T d_pcb Given the value of , we can get The value of In summary, the formula for calculating the margin of a signal setup time is: (3) Based on the SDRAM timing parameter theoretical calculation model established in step (1), a calculation formula for the hold time margin is given; The actual arrival time calculation formula of a signal from FPGA to SDRAM is shown in Formula 1; Only when the signal meets the hold time requirement of SDRAM can FPGA stably access data to SDRAM. Therefore, the required arrival time calculation formula of a signal from FPGA to SDRAM is: Then, the calculation formula for the margin of a signal holding time is: In formula 8, T c2i_fp , T reg2pin , T c2j_fp is the internal wiring delay of FPGA, let After completing the layout and routing, the FPGA development tool will automatically calculate The value of In formula 8, let After the FPGA and SDRAM are selected and the actual PCB layout and routing are determined, T can be obtained based on the chip data sheet and the actual PCB wiring length. Launch_Edge , T d_pcb , T Latch_Edge , T c2j_pcb , T h , T Clock_Uncertainty Given the value of , we can get The value of In summary, the calculation formula for the margin of a signal holding time is: (4) Perform setup time and hold time margin analysis; To meet the setup time and hold time requirements of SDRAM, it is necessary to After the FPGA and SDRAM are selected and the actual PCB layout and routing are determined, The value of has been determined, so the only way to make Formula 12 and Formula 13 valid is to adjust the internal wiring delay of the FPGA. However, in most cases, it is not possible to make Formula 12 and Formula 13 valid at the same time by simply adjusting the internal wiring delay of the FPGA. Introduce an SDRAM timing adjustment module inside the FPGA: After the SDRAM timing adjustment module is introduced, the margin calculation formula 6 for the setup time of a certain SDRAM signal is modified as follows: The margin calculation formula for the hold time of a certain signal in SDRAM (Formula 11) is modified as follows: To meet the setup time and hold time requirements of SDRAM, it is necessary to From formula 16, we can get: The theoretical adjustment value of the clock phase that satisfies the signal setup time and hold time is obtained. In order to ensure that both the setup time and the hold time have a large time margin, the initial theoretical adjustment value of the clock phase is generally taken as:

5. The method for adaptively configuring SDRAM timing parameters based on FPGA according to claim 1, characterized in that: The calculation method of the clock phase correction value in step 4 is: In order to meet the setup time and hold time requirements of SDRAM, set the clock phase correction value, which needs to satisfy the following formula: Among them, T s ' u , T h ' are the actual measured values ​​of setup time and hold time given by the signal timing calculation and correction module, T su , T h The setup time and hold time required by the SDRAM data sheet; From formula 19, we can get: (T su -T s ' u )<ΔT Phase_Adjust <(T h '-T h )(Formula 20) In order to ensure that both the setup time and the hold time have a large time margin, the clock phase correction value is generally taken as Combined with formula 18, the clock phase correction value can be obtained as follows:

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