Data transmission controller and method, electronic equipment and computer storage medium

Abstract

The invention discloses a data transmission controller and method, electronic equipment and a computer storage medium. The data transmission controller comprises N protocol layer controllers, an arbiter and a data link layer controller, wherein N is an integer greater than or equal to 2; the N protocol layer controllers are configured to transmit N pieces of protocol layer data; the arbiter is configured to receive N pieces of protocol layer data of the N protocol layer controllers and determine transmission priorities of the N pieces of protocol layer data; the data link layer controller is configured to transmit N protocol layer data according to a transmission priority. According to the data transmission controller, different protocol layers can share the same physical link resource, so that the utilization rate and the flexibility of the link are improved; meanwhile, isolation and protection of data of different protocol layers are realized.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a data transmission controller, method, electronic device, and computer storage medium. Background Art

[0002] With the rapid development of the Internet, more and more devices and systems need to communicate with each other, and different devices and systems often use different protocol layers. The traditional interconnection communication method requires the allocation of independent link resources for each protocol layer, resulting in a serious waste of link resources. At the same time, since each protocol layer requires independent hardware support, the system area and power consumption increase, which brings difficulties to system design and maintenance. Summary of the invention

[0003] At least one embodiment of the present disclosure provides a data transmission controller, comprising N protocol layer controllers, an arbitrator and a data link layer controller, wherein the N protocol layer controllers are configured to transmit N protocol layer data; the arbitrator is configured to receive the N protocol layer data from the N protocol layer controllers and determine the transmission priority of the N protocol layer data; the data link layer controller is configured to transmit the N protocol layer data according to the transmission priority; wherein N is an integer greater than or equal to 2.

[0004] For example, in the data transmission controller provided in at least one embodiment of the present disclosure, the arbitrator includes: a sending module, configured to receive N protocol layer data from the N protocol layer controllers, and after determining the transmission priority of the N protocol layer data, send the protocol layer data to be transmitted to the data link layer controller to communicate data with the protocol layer of the other end; a receiving module, configured to receive the protocol layer data sent by the other end and send it to its own protocol layer to communicate data with the protocol layer of the other end.

[0005] For example, in the data transmission controller provided in at least one embodiment of the present disclosure, the sending module includes: a data clock conversion module, configured to switch the first clock domain of the N protocol layer data to the second clock domain; and a control signal clock conversion module, configured to switch the first clock domain of the control signal corresponding to the N protocol layer data to the second clock domain, wherein the control signal is used to control each protocol layer to communicate with the protocol layer corresponding to the opposite end, wherein the second clock domain is the same as the clock domain of the data link layer controller.

[0006] For example, in the data transmission controller provided in at least one embodiment of the present disclosure, the sending module also includes: a data arbitration module, configured to determine the transmission priority of the N protocol layer data and select the protocol layer data to be transmitted; and a data scheduling module, configured to receive the protocol layer data to be transmitted sent by the data arbitration module and package and transmit it to the data link layer controller to send to the opposite end.

[0007] For example, in the data transmission controller provided in at least one embodiment of the present disclosure, the sending module also includes: a control instruction generating module, configured to receive the control signal converted by the control signal clock conversion module and package it into a first control instruction and transmit it to the data scheduling module; the data scheduling module is also configured to transmit the first control instruction to the data link layer controller and send it to the opposite end to establish a communication connection with the protocol layer corresponding to the opposite end.

[0008] For example, in the data transmission controller provided in at least one embodiment of the present disclosure, the receiving module includes: a multi-channel data selection module, configured to receive the protocol layer data and the first control instruction sent by the opposite end; a data clock restoration module, configured to restore the second clock domain of the protocol layer data sent by the opposite end to the first clock domain; and a control signal clock restoration module, configured to restore the second clock domain of the control signal sent by the opposite end to the first clock domain and then transmit it to the corresponding protocol layer.

[0009] For example, in the data transmission controller provided by at least one embodiment of the present disclosure, the receiving module also includes a control instruction parsing module, which is configured to unpack the first control instruction into a control signal and transmit it to the control signal clock recovery module; the multi-channel data selection module is also configured to transmit the received protocol layer data sent by the opposite end to the data clock recovery module, and transmit the first control instruction to the control instruction parsing module, wherein the transmission priority of the first control instruction is higher than the transmission priority of the protocol layer data.

[0010] For example, in the data transmission controller provided by at least one embodiment of the present disclosure, the transmission priority of the first control instruction is higher than the transmission priority of the protocol layer data, including: in response to receiving the first control instruction for the protocol layer transmission to be transmitted by the other end, the protocol layer data to be transmitted is transmitted.

[0011] For example, in the data transmission controller provided by at least one embodiment of the present disclosure, determining the transmission priority of the N protocol layer data and selecting the protocol layer data to be transmitted includes: in response to selecting the nth protocol layer data among the N protocol layer data, the unselected n+1th protocol layer data is not empty and after a certain period of time, the transmission priority of the n+1th protocol layer data is greater than the nth protocol layer data, and the n+1th protocol layer data is selected as the protocol layer data to be transmitted; or in response to selecting the nth protocol layer data among the N protocol layer data is empty and the unselected n+1th protocol layer data is full, the transmission priority of the n+1th protocol layer data is greater than the nth protocol layer data, and the n+1th protocol layer data is selected as the protocol layer data to be transmitted; wherein n is an integer greater than 0 and less than or equal to N.

[0012] For example, in the data transmission controller provided in at least one embodiment of the present disclosure, the arbitrator also includes: a virtual interface state machine determination module, configured to set the virtual interface state machine of the data scheduling module to a working state in advance in response to at least one of the virtual interface state machines receiving the N protocol layer data being in a working state.

[0013] For example, in the data transmission controller provided in at least one embodiment of the present disclosure, the virtual interface state machine includes any one of a silent state, a working state, and a low power consumption state.

[0014] At least one embodiment of the present disclosure also provides a data transmission method, including: receiving data from N protocol layers; determining the data of the protocol layer to be transmitted according to the transmission priority of the data of the N protocol layers; packaging the data of the protocol layer to be transmitted and transmitting it to the other end via a data transmission link; wherein N is an integer greater than or equal to 2.

[0015] For example, in the data transmission method provided by at least one embodiment of the present disclosure, after receiving data from N protocol layers, the method further includes: converting the clock domain of the data from the N protocol layers to the clock domain of the data transmission link for arbitration.

[0016] For example, in the data transmission method provided by at least one embodiment of the present disclosure, it also includes: receiving a control signal corresponding to the data of the protocol layer to be transmitted, converting the clock domain of the control signal to the clock domain of the data transmission link, and packaging it into a control instruction, which is transmitted to the other end via the data transmission link to communicate with the protocol layer of the other end, wherein the transmission priority of the control instruction is higher than the transmission priority of the data of the protocol layer to be transmitted.

[0017] For example, in the data transmission method provided by at least one embodiment of the present disclosure, the method of determining the data of the protocol layer to be transmitted according to the transmission priority of the data of the N protocol layers includes: in response to selecting the nth protocol layer data among the N protocol layer data, the unselected n+1th protocol layer data is not empty and after a certain period of time, the transmission priority of the n+1th protocol layer data is greater than the nth protocol layer data, and the n+1th protocol layer data is selected as the protocol layer data to be transmitted; or in response to selecting the nth protocol layer data among the N protocol layer data is empty and the unselected n+1th protocol layer data is full, the transmission priority of the n+1th protocol layer data is greater than the nth protocol layer data, and the n+1th protocol layer data is selected as the protocol layer data to be transmitted; wherein n is an integer greater than 0 and less than or equal to N.

[0018] For example, in the data transmission method provided in at least one embodiment of the present disclosure, it also includes: in response to at least one of the virtual interface state machines receiving the N protocol layer data being in a working state, setting the virtual interface state machine connected to the data transmission link to a working state in advance.

[0019] For example, in the data transmission method provided in at least one embodiment of the present disclosure, the virtual interface state machine includes any one of a silent state, a working state, and a low power consumption state.

[0020] At least one embodiment of the present disclosure further provides an electronic device, comprising: a storage device configured to non-temporarily store computer-executable instructions; and a processing device configured to run the computer-executable instructions, wherein the computer-executable instructions, when run by the processing device, execute the data transmission method provided by any of the above embodiments of the present disclosure.

[0021] At least one embodiment of the present disclosure further provides a non-temporary storage medium that non-temporarily stores computer-executable instructions, wherein when the computer-executable instructions are executed by a computer, the data transmission method provided by any of the above embodiments of the present disclosure is executed. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0023] Figure 1 A schematic diagram showing a usage scenario of data transmission in traditional interconnection communication is shown;

[0024] Figure 2A A schematic block diagram of a data transmission controller provided by at least one embodiment of the present disclosure is shown;

[0025] Figure 2B A schematic diagram of a use scenario of a data transmission controller provided by at least one embodiment of the present disclosure is shown;

[0026] Figure 3A A structural block diagram of an arbitrator in a data transmission controller provided by at least one embodiment of the present disclosure is shown;

[0027] Figure 3B An example of an arbitrator in a data transmission controller provided by at least one embodiment of the present disclosure is shown;

[0028] Figure 4 A schematic diagram of arbitration logic of a data arbitration module in an arbitrator in a data transmission controller provided by at least one embodiment of the present disclosure is shown;

[0029] Figure 5 A schematic diagram showing the operation of a virtual interface state machine of an arbitrator in a data transmission controller provided by at least one embodiment of the present disclosure is shown;

[0030] Figure 6 A schematic diagram showing the matching between virtual interface state machines of each port of an arbitrator in a data transfer controller provided by at least one embodiment of the present disclosure is shown;

[0031] Figure 7 A schematic flow chart of a data transmission method provided by at least one embodiment of the present disclosure is shown;

[0032] Figure 8 A schematic block diagram of an electronic device provided for at least one embodiment of the present disclosure; and

[0033] Fig. 9 A schematic diagram of a computer storage medium provided by at least one embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0035] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0036] With the rapid development of the Internet, more and more devices and systems need to communicate with each other. There are usually multiple communication protocols inside a device, such as control protocols and high-speed data communication protocols. Different protocols have different requirements for bandwidth and latency. The traditional interconnection communication method requires the allocation of independent link resources for each protocol layer, resulting in a serious waste of link resources. At the same time, since each protocol layer requires independent hardware support, the system area and power consumption increase, which brings difficulties to system design and maintenance.

[0037] Figure 1 A schematic diagram of a usage scenario of data transmission in traditional interconnection communication is shown.

[0038] like Figure 1 As shown, the following description takes the data transmission between chip (Die) 100 and chip 200 as an example. For example, each chip includes Figure 1The two different types of protocol layer controllers shown, for example, include a Northbridge data network (NBIO, NorthBridge I / O) controller and a system management network (SMN, System Management Network) controller, wherein the system management network controller refers to a control information transmission network controller in the embodiment of the present disclosure. Specifically, chip 100 includes a Northbridge data network controller 110 and a control information transmission network controller 130; chip 200 includes a Northbridge data network controller 210 and a control information transmission network controller 230. The Northbridge data network refers to a high-speed data transmission network managed by the Northbridge chip in a computer system. The Northbridge chip is a key component on the motherboard, mainly responsible for linking the processor (CPU), memory (RAM) and high-speed graphics interface (such as AGP or PCIe), and coordinating data transmission between them. The control information transmission network is a network for control information transmission, which is used to transmit low-speed control information between different modules on the chip. In addition, each chip also includes two independent link layer controllers, which serve the data link layer and the physical layer, and are intended to be responsible for data transmission between chip 100 and chip 200. Specifically, the chip 100 includes a link layer controller 1210 / 1220; the chip 200 includes a link layer controller 2210 / 2220. For the convenience of explanation, the north bridge data network controller is referred to as "NBIO controller" and the control information transmission network controller is referred to as "SMN controller" below.

[0039] like Figure 1 As shown, the NBIO controller and the SMN controller communicate with the corresponding link layer controller through the media access control layer-physical coding sublayer interface (MAC-PCS interface, Media Access Control - Physical Coding Sublayer-Interface), wherein the MAC-PCS interface is a standardized interface in chip data transmission, which is used to connect the media access control layer (MAC, Media Access Control Layer) and the physical coding sublayer (PCS, Physical Coding Sublayer), wherein the MAC layer and the PCS layer are both a sublayer in the data link layer. And the chip 100 and the chip 200 communicate with each other through the chip-to-chip input / output mechanism (C2C IO, Chip-to-Chip Input / Output). C2C IO refers to an interface or communication mechanism for direct data transmission between chips. This type of IO is designed to provide efficient and reliable data exchange between integrated circuits (ICs), and is widely used in high-performance computing, network equipment, storage systems, and various embedded systems.

[0040] The inventors noticed that in the traditional interconnected communication structure, there are four link layer controllers between the two chips, which means that independent link resources need to be allocated to each protocol layer controller, which will cause hardware resource waste and system complexity, and further increase the area and power consumption, bringing difficulties to system design and maintenance.

[0041] At present, there are many studies on high-speed interconnection between chips. Physical layer training is a key initialization step in the communication system. Through processes such as channel estimation, clock synchronization, equalizer training and power control, it ensures that the communication link between the transmitter and the receiver can be correctly established and operate efficiently. At the same time, since reducing the time and power consumption of physical layer training can significantly improve transmission efficiency, this is one of the focuses of many high-speed interconnection studies.

[0042] In view of the above-mentioned research on the physical layer, the inventors noticed that these methods generally require training on the physical layer, which will increase the transmission time and also cause certain power consumption.

[0043] In addition, some studies have used link layer technology to improve transmission efficiency. Although this method reduces the time and power consumption of physical layer training by working on the link layer to improve data transmission efficiency, it will result in slower data transmission speeds and cause data delays.

[0044] At least one embodiment of the present disclosure provides a data transmission controller, comprising N protocol layer controllers, an arbitrator and a data link layer controller, wherein the N protocol layer controllers are configured to transmit N protocol layer data; the arbitrator is configured to receive the N protocol layer data from the N protocol layer controllers and determine the transmission priority of the N protocol layer data; the data link layer controller is configured to transmit the N protocol layer data according to the transmission priority; wherein N is an integer greater than or equal to 2.

[0045] At least one embodiment of the present disclosure also provides a data transmission method, an electronic device, and a computer storage medium corresponding to the data transmission controller.

[0046] The data transmission controller provided by at least one embodiment of the present disclosure, on the one hand, arbitrates data of different protocol layers, reduces the number of data link layer controllers, and transmits the data of different protocol layers through a unique data link layer controller to realize link layer multiplexing, which can save chip area and power consumption, and improve the utilization and flexibility of the data transmission link; on the other hand, through the design of data link layer encapsulation, the isolation and protection of data of different protocol layers are realized, ensuring the security and reliability of data transmission.

[0047] The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0048] Figure 2A A schematic block diagram of a data transmission controller provided by at least one embodiment of the present disclosure is shown.

[0049] For example, Figure 2A As shown, the data transmission controller 300 includes N protocol layer controllers (for example, protocol layer controller 3101, ..., protocol layer controller 310n, ..., and protocol layer controller 310N), an arbitrator 320, and a data link layer controller 330, wherein N is an integer greater than or equal to 2, and n is an integer greater than 0 and less than or equal to N.

[0050] For example, the N protocol layer controllers are configured to transmit N protocol layer data. For example, the data corresponding to the protocol layer can be classified according to its role and content in data communication, for example, it can include two categories: control information and user data. Each type of protocol layer data has a specific purpose and data format to ensure the effectiveness and reliability of data communication. Of course, more or fewer categories can also be included, and the embodiments of the present disclosure are not limited to this.

[0051] For example, the following takes N=2, that is, N protocol layer controllers include two protocol layer controllers 3101 and 3102 as an example for introduction. Of course, more modules may be included, and the embodiments of the present disclosure are not limited to this. For example, the N protocol layer controllers may be as follows: Figure 1 The present disclosure does not limit the NBIO controller, SMN controller, or any other type shown. Figure 2B As shown in the usage scenario diagram, the current end is chip 100 and the opposite end is chip 200 (each chip includes a data transmission controller 300, that is, Figure 2B Take the data transmission controller 108 / 208 in the data link layer 3101 as an example, and the protocol layer controller 3101 is an SMN controller and the protocol layer controller 3102 is an NBIO controller. The protocol layer data transmitted by the protocol layer controller 3101 is SMN data, and the protocol layer data transmitted by the protocol layer controller 3102 is NBIO data. The specific details may depend on the actual situation, and the embodiments of the present disclosure are not limited to this. For example, the arbitrator 320 is configured to receive N protocol layer data from N protocol layer controllers and determine the transmission priority of the N protocol layer data. For example, data from N protocol layers are sent to the arbitrator 320 together. After the arbitrator 320 receives the data from the above-mentioned N protocol layer controllers and determines the transmission priority of the data, it screens out the protocol layer data with the highest transmission priority and sends it to the data link layer controller 330 for package transmission. For example, the arbitrator 320 can be implemented as Figure 2B The arbiter 1083 / 2083 shown in the figure is described in detail below. Figure 2B The relevant introduction will not be elaborated here.

[0052] For example, the data link layer controller 310 is configured to transmit the N protocol layer data according to the transmission priority. For example, the data link layer controller 330 provides reliable data transmission services between adjacent nodes and ensures that data frames between these nodes can be transmitted without error. For example, the data link layer controller 330 achieves error-free transmission of the above data by processing error detection and correction, flow control, and frame encapsulation and decapsulation. The specific transmission process can be referred to the relevant introduction in the field, which will not be repeated here. For example, in some examples, the data link layer controller 330 can be implemented as Figure 2B The link layer controller 1084 / 2084 shown in the figure is described in detail below. Figure 2B The relevant introduction will not be elaborated here.

[0053] Figure 2B A schematic diagram of a usage scenario of a data transmission controller provided by at least one embodiment of the present disclosure is shown.

[0054] like Figure 2B As shown, in addition to the data transfer controller of the present disclosure, the chip 100 and the chip 200 also include a processor, a peripheral, an on-chip control bus, a data bus, and a memory. It should be noted that the chip may include more devices, Figure 2B The devices shown are only examples, and the present disclosure does not limit them. Specifically, chip 100 includes a processor 101, peripherals (0-2) 102-104, an on-chip control bus 105, a data bus 106, a memory 107, and a data transfer controller 108; chip 200 includes a processor 201, peripherals (0-2) 202-104, an on-chip control bus 205, a data bus 206, a memory 207, and a data transfer controller 208. In the data transfer controller 108 / 208, the same Figure 1Compared with the chip 100 and the chip 200, an arbitrator 1083 / 2083 is added respectively, and a link layer controller is reduced. For example, taking the chip 100 as an example, the control bus interconnection protocol layer 1081 receives the protocol layer data transmitted from the on-chip control bus 105, which data can be, for example, NBIO data. Among them, the on-chip control bus (On-Chip Control Bus) is the infrastructure for communication between different functional modules within the system-level chip (SoC, System on Chip). It allows control signals, status information and a small amount of data to be transmitted between various components, thereby achieving coordinated work and resource sharing. The data bus interconnection protocol layer 1082 receives the protocol layer data transmitted from the data bus 106, which data can be, for example, SMN data. Among them, the processor 101 sends all data to the data bus 106 for processing, and the data bus 106 includes control data sent to the on-chip control bus and high-speed user data for interaction. On the one hand, the data bus 106 sends the control data to the on-chip control bus 105; on the other hand, if there is a storage request, the data can also be sent to the storage 107 for storage. The data from the control bus interconnection protocol layer 1081 and the data bus interconnection protocol layer 1082 are sent to the arbitrator 1083 through the media access control layer-physical coding sublayer interface for data arbitration. The arbitration selects the data with higher transmission priority and sends it to the data link layer controller 1084 through the media access control layer-physical coding sublayer interface to be transmitted to the data link layer controller 2084 at the other end through the inter-chip input / output mechanism. Figure 1 Compared with the two data transmission links, there is only one data transmission link between chip 100 and chip 200, which saves link resources. The data link layer controller 2084 sends the received data to the arbitrator 2083 through the media access control layer-physical coding sublayer interface for data screening. The screened data is sent to the control bus interconnection protocol layer 2081 (such as SMN controller) and the data bus interconnection protocol layer 2082 (such as NBIO controller) of the other end through the media access control layer-physical coding sublayer interface. In this way, the SMN controller and NBIO controller in chip 100 and chip 200 can perform two-way data communication.

[0055] exist Figure 2BIn the usage scenario shown, the data transmission controller provided by at least one embodiment of the present disclosure can share the same physical link resources by adding an arbitrator in the middle layer, which greatly improves the utilization and flexibility of the link. At the same time, by reducing the number of data link layer controllers, repeated configuration and debugging and other repeated supporting logic circuits can be avoided, thereby reducing dynamic and static power consumption. In addition, the arbitrator can dynamically and flexibly allocate the bandwidth of data at different protocol layers according to the actual bandwidth of the interface, and supports data isolation and protection to ensure the security and reliability of data transmission.

[0056] Figure 3A A block diagram showing a composition of an arbitrator in a data transmission controller according to at least one embodiment of the present disclosure is shown. Figure 3A As shown, the arbitrator 320 includes a sending module 3210 and a receiving module 3220 .

[0057] For example, in a possible implementation, the sending module 3210 is configured to receive N protocol layer data from N protocol layer controllers, and after determining the transmission priority of the N protocol layer data, send the protocol layer data to be transmitted to the data link layer controller to communicate data with the protocol layer of the other end. For example, the other end is a chip that communicates with the current end, such as Figure 3B In the example shown, when the front end is chip 100 , the opposite end may be, for example, chip 200 .

[0058] For example, the sending module 3210 receives data corresponding to two protocol layer controllers (for example, when N=2) (for example, NBIO data and SMN data), determines the transmission priority of the two protocol layer data (for example, the transmission priority can be determined based on factors such as the size of the data volume, clock cycle, frequency, etc.), and sends the protocol layer data with the highest transmission priority (for example, it can be either NBIO data or SMN data) to the data link layer controller for framing processing, which is packaged into data frames and transmitted one by one to the corresponding protocol layer controller of the opposite end to establish a communication connection to transmit data to each other. For example, the framing processing includes adding data structures such as a frame header, a frame tail, a frame identifier, a frame count, and a checksum. The length of the data frame can be 512 bits (bit), 1024 bits (bit), etc. The specific scheme is based on the actual design, and the present disclosure does not limit this.

[0059] For example, in a possible implementation, the receiving module 3220 is configured to receive the protocol layer data sent by the above-mentioned opposite end and send it to its own protocol layer controller to perform data communication with the protocol layer controller of the above-mentioned opposite end.

[0060] For example, the receiving module 3220 receives data from the NBIO protocol layer controller sent by the sending module of the above-mentioned opposite end. Before the receiving module 3220 receives the NBIO data from the opposite end, the data link layer controller needs to unpack the data frame received from the opposite end to obtain the actual NBIO data (that can be understood as user data), and then send the data to the receiving module 3220. The receiving module 3220 sends the received NBIO data to its own NBIO protocol layer controller to establish a communication connection with the NBIO protocol layer controller of the opposite end, and then the data corresponding to the protocol layer can be transmitted normally.

[0061] Figure 3B An example of an arbitrator in a data transfer controller provided by at least one embodiment of the present disclosure is shown.

[0062] like Figure 3BAs shown, the filling patterns in the box (including "horizontal lines", "vertical lines" and "slashes") represent different clock domains. It can be seen that the arbiter includes a TX (transmit) channel, a control channel and an RX (receive) channel. The TX channel is connected to the transmit module 3210, and the RX channel is connected to the receive module 3220. For example, data from each protocol layer controller enters from the TX channel and flows out from the RX channel. The clocks of the two different protocol layer data entering from the TX channel are unified with the clock domain of the data link layer controller after conversion by the clock conversion modules fifo0 and fifo1 (i.e., the "vertical line" pattern). The two protocol layer data are transmitted to the data arbitration unit ARB after clock conversion to determine the transmission priority. For example, it is determined that the protocol layer data transmission converted by fifo1 has the highest priority, so the data is sent to the data scheduling module for transmission. At this moment, the clock of the wake-up signal OBBwake1 from the protocol layer controller is converted into the clock of the data link layer controller by the clock conversion module Async and then transmitted to the Meta package module for packaging into a wake-up instruction. After receiving the wake-up instruction and data sent by the Meta package module, the data scheduling module preferentially sends the wake-up instruction to the data link layer controller for transmission to the multi-channel data selection unit MUX of the other end. The MUX sends the wake-up instruction to the Meta package parsing module to unpack it into the wake-up signal OBBwake1. The Async conversion module of the other end restores the clock domain of the wake-up signal to the original clock domain of the protocol layer controller and transmits it to the corresponding protocol layer controller of the other end through the RX channel. The protocol layer controllers of both parties complete the handshake mechanism and establish data communication. At this time, the data scheduling module sends the accumulated protocol layer data to the MUX via the data transmission link. The MUX transmits the data to the fifo1 of the other end for clock restoration. Finally, the data is successfully sent to the protocol layer controller of the other end to complete the data transmission and reception. In addition, the control channel includes three virtual interface state machines, namely vLSMS_0, vLSMS_1 and vLSMM. vLSMS_0 and vLSMS_1 represent the interface states connected to the two protocol layer controllers in the TX channel, and vLSMM represents the interface state of the output port of the data scheduling module.

[0063] The data device provided by at least one embodiment of the present disclosure enables data at different protocol layers to reuse the same physical link resources by adding an arbitrator, thereby greatly improving the utilization rate and flexibility of the link.

[0064] For example, in a possible implementation, the sending module 3210 includes: a data clock conversion module configured to switch the first clock domain of the N protocol layer data to the second clock domain.

[0065] For example, the data clock conversion module (eg Figure 3BThe data clock conversion module converts the clock domains corresponding to the above-mentioned protocol layer data into a second clock domain. For example, in one possible implementation, the second clock domain is the same as the clock domain of the above-mentioned protocol layer data. Figure 2A The clock domain of the data link layer controller 330 is the same, so as to meet the transmission requirements of the data link layer controller. It should be noted that the data transmitted by the data link layer controller needs to meet the clock requirements of the data link layer controller to ensure the accuracy and reliability of data transmission. If the data is not properly synchronized when converting between clock domains, it may cause the trigger at the receiving end to enter an uncertain state, namely metastability. This situation will cause system failure, so it is usually necessary to use a synchronization circuit (such as a dual trigger synchronizer) to reduce the risk. For example, in the process of cross-clock domain transmission, when the protocol layer data is converted from the first clock domain to the clock domain of the data link layer controller (ie, the second clock domain) through the data clock conversion module, it is also necessary to use a first-in-first-out (FIFO) memory as an intermediate buffer to smooth data streams of different rates, thereby reducing the risk of metastability.

[0066] For example, in one possible implementation, the sending module 3210 further includes: a control signal clock conversion module, configured to switch the first clock domain of the control signal corresponding to the N protocol layer data to the second clock domain, wherein the control signal is used to control each protocol layer controller to communicate with the corresponding protocol layer controller at the other end.

[0067] For example, the control signal clock conversion module (eg Figure 3B The function of the Async in the data clock conversion module is the same as that of the above-mentioned data clock conversion module. For example, the first clock of the control signal corresponding to each protocol layer controller is converted into the clock domain (i.e., the second clock domain) of the data link layer controller, which will not be repeated here. It should be noted that the function of the control signal is to control each protocol layer controller (for example, NBIO controller) to communicate with the corresponding NBIO controller of the other end. For example, the control signal can be any other control signal such as a wake-up signal (OBBWake1). The existence of this control signal implements a handshake mechanism between the protocol layer controllers at both ends. For example, when the protocol layer controller at the other end (for example, NBIO controller) receives the control signal (for example, a wake-up signal) sent by the sending NBIO controller, it indicates that the communication between the two parties has been established to prepare for sending and receiving data.

[0068] For example, in a possible implementation, the sending module 3210 further includes: a data arbitration module configured to determine the transmission priority of the N protocol layer data and select the protocol layer data to be transmitted.

[0069] For example, in one possible implementation, determining the transmission priority of the N protocol layer data and selecting the protocol layer data to be transmitted includes: in response to selecting the nth protocol layer data from the N protocol layer data, the unselected n+1th protocol layer data is not empty and after a certain period of time, the transmission priority of the n+1th protocol layer data is greater than the nth protocol layer data, and the n+1th protocol layer data is selected as the protocol layer data to be transmitted; or in response to selecting the nth protocol layer data from the N protocol layer data is empty and the unselected n+1th protocol layer data is full, the transmission priority of the n+1th protocol layer data is greater than the nth protocol layer data, and the n+1th protocol layer data is selected as the protocol layer data to be transmitted; wherein n is an integer greater than 0 and less than or equal to N.

[0070] Figure 4 A schematic diagram of arbitration logic of a data arbitration module in an arbitrator in a data transmission controller according to at least one embodiment of the present disclosure is shown.

[0071] like Figure 4 As shown, the data arbitration module 400 (ie Figure 3B The ARB in the data link layer) arbitrates the protocol layer data from channel 0 and channel 1. For example, the protocol layer data of channel 0 comes from the NBIO controller, and the protocol layer data of channel 1 comes from the SMN controller. Among them, the protocol layer data types of channel 0 and channel 1 are determined based on actual conditions, and the present disclosure does not limit this. For example, "!fifo1Empty && counter == 0xf" shown in the figure indicates that the current data arbitration module 400 selects the protocol layer data from channel 0 (for example, the data of the NBIO controller). If the protocol layer data from channel 1 (for example, the SMN controller) is not empty at this time and multiple beats (for example, 16 beats) are continuously sent to the data arbitration module 400 according to the clock cycle of the above-mentioned data link layer controller, in order to prevent excessive accumulation of data in the SMN controller, the transmission priority of the data from the SMN controller is greater than the transmission priority of the data from the NBIO controller. The data arbitration module 400 selects the data from the SMN controller as the protocol layer data to be transmitted.

[0072] For example, "fifo0Empty && fifo1Full" shown in the figure indicates that if the protocol layer data from channel 0 (such as data from the NBIO controller) selected by the current data arbitration module 400 is empty, that is, there is no data in the NBIO controller that needs to be transmitted, and the protocol layer data from channel 1 (such as data from the SMN controller) is full, it indicates that the data of the SMN controller can no longer be accumulated and needs to be transmitted as soon as possible to receive the subsequent data. At this time, the transmission priority of the data from the SMN controller is greater than the transmission priority of the data from the NBIO controller, and the data arbitration module 400 selects the data from the SMN controller as the protocol layer data to be transmitted. It should be noted that if the data arbitration module 400 initially selects the protocol layer data from channel 1, the algorithm logic for switching to selecting the protocol layer data of channel 0 based on the transmission priority is similar and will not be repeated here.

[0073] The data arbitration module provided by at least one embodiment of the present disclosure receives data of multiple protocol layers and reuses a data link layer controller, dynamically and flexibly allocates bandwidth according to the actual bandwidth requirements of the physical interface through an internal arbitration strategy, and supports the isolation and protection of data of different protocol layers, thereby ensuring the security and reliability of data transmission.

[0074] For example, in a possible implementation, the sending module 3210 further includes: a data scheduling module configured to receive the protocol layer data to be transmitted sent by the data arbitration module and transmit it to the data link layer controller to be sent to the other end.

[0075] For example, the data scheduling module (e.g. Figure 3B The data scheduling module in the data arbitration module receives data from the NBIO controller and sends it to the data link layer controller to send it to the peer end. For example, in a possible implementation, as the data in the NBIO controller gradually decreases during the transmission process, and the data in the SMN controller gradually increases, the transmission priority of the data from the SMN controller will be greater than the transmission priority of the data of the NBIO controller. The above-mentioned data arbitration module will transmit the data of the SMN controller to the data scheduling module, and the data scheduling module dynamically allocates resources based on the received protocol layer data to ensure maximum system utilization and reduce transmission delay.

[0076] For example, in a possible implementation, the sending module further includes: a control instruction generating module configured to receive the control signal converted by the control signal clock conversion module and package it into a first control instruction for transmission to the data scheduling module.

[0077] For example, in a possible implementation, the data scheduling module is further configured to transmit the first control instruction to the data link layer controller and send it to the opposite end to establish a communication connection with the protocol layer controller corresponding to the opposite end.

[0078] For example, Figure 3B As shown, the control instruction generation module includes a Meta packet generation module. Since the transmission condition of all data transmitted through the data link layer controller is to meet the relevant data frame format, the Meta packet generation module packages the control signal (such as the wake-up signal OOBwake1) sent by the protocol layer (such as the NBIO controller) into a first control instruction (such as a wake-up instruction) and sends it to the data scheduling module for transmission. Specifically, the Meta packet packages the wake-up signal into the data frame format required by the data link layer controller to form a wake-up instruction, for example, adding a frame header, a frame tail, a frame count, a checksum, etc. on the basis of the control signal.

[0079] For example, the data scheduling module sends the received wake-up instruction to the data link layer controller to transmit it to the NBIO controller at the other end for communication connection, that is, to establish a handshake mechanism, at which time both parties can send and receive data.

[0080] For example, in one possible implementation, the above-mentioned receiving module 3220 includes: a multi-channel data selection module, configured to receive the protocol layer data and the first control instruction sent by the above-mentioned opposite end; a data clock restoration module, configured to restore the second clock domain of the protocol layer data sent by the above-mentioned opposite end to the above-mentioned first clock domain and transmit it to the corresponding protocol layer; and a control signal clock restoration module, configured to restore the second clock domain of the control signal sent by the above-mentioned opposite end to the above-mentioned first clock domain and then transmit it to the corresponding protocol layer.

[0081] For example, the multiplexer module (e.g. Figure 3B The MUX in the structure includes an input port and multiple output ports. The input port receives data sent by the peer NBIO controller and SMN controller and control instructions sent by any protocol layer controller (for example, the wake-up instruction OOBwake1 sent by the NBIO controller), and then filters out the same type of protocol layer data based on the data judgment algorithm and sends them to the corresponding protocol layer controllers through multiple output ports.

[0082] For example, the data clock recovery module (e.g. Figure 3BThe Async in the multi-channel data selection module restores the second clock domain (i.e., the clock domain of the data link layer) of the data output by the multiple ports of the peer NBIO controller and SMN controller to the first clock domain (i.e., the clock domain of the peer that has not been converted by the above data clock conversion module) and transmits it to the corresponding NBIO controller and SMN controller. It should be noted that the clock domains of the data in the protocol layer controllers at both ends need to be consistent in order to perform data parsing and normal communication connection. It should also be noted that Figure 3B The fifo0 and fifo1 in the sending module 3210 and the receiving module 3220 are the same. For the control signal recovery module, its execution logic is similar to that of the data clock recovery module, and Figure 3B The Async in the sending module 3210 and the receiving module 3220 is also the same, which will not be repeated here.

[0083] For example, in one possible implementation, the receiving module further includes: a control instruction parsing module configured to unpack the first control instruction into a control signal and transmit it to the control signal clock recovery module; the multi-channel data selection module is also configured to transmit the received protocol layer data sent by the opposite end to the data clock recovery module, and transmit the first control instruction to the control instruction parsing module, wherein the transmission priority of the first control instruction is higher than the transmission priority of the protocol layer data.

[0084] For example, Figure 3B As shown, the control instruction parsing module includes a Meta packet parsing module, which receives the first control instruction (for example, the wake-up instruction sent by the opposite NBIO controller) sent by the multi-channel data selection module, performs unpacking and parsing, extracts the intermediate control signal (for example, the wake-up signal OBBwake1), and sends it to the control signal clock recovery module for clock domain recovery.

[0085] For example, in a possible implementation, the transmission priority of the first control instruction is higher than the transmission priority of the above-mentioned protocol layer data, including:

[0086] In response to receiving the first control instruction transmitted by the protocol layer controller to be transmitted at the opposite end, the data of the protocol layer controller to be transmitted is transmitted.

[0087] For example, after the multi-channel data selection module receives data from the peer protocol layer (e.g., NBIO controller) and the first control instruction (e.g., wake-up instruction) issued by the NBIO controller, since the NBIO controllers at both ends are in a non-communication connection state at this time, the multi-channel data selection module needs to preferentially transmit the wake-up instruction of the peer NBIO controller to establish a communication connection with the peer NBIO controller, that is, to establish a handshake mechanism. It should be noted that the wake-up instruction can be understood as one of the handshake signals. Based on the actual design, the present disclosure does not limit any other handshake signal with the function of establishing a communication connection.

[0088] For example, in one possible implementation, the arbitrator 320 further includes: a virtual interface state machine determination module configured to set the interface state of the data scheduling module to a working state in advance in response to at least one of the interface states of receiving N protocol layer data being a working state.

[0089] For example, the arbitrator includes N input ports connected to the protocol layer controller and one output port (for example, the output port of the above-mentioned data scheduling module), wherein each input port is connected to a protocol layer controller. When the data in any one of the N protocol layer controllers (for example, two, namely, the NBIO controller and the SMN controller) accumulates to a certain extent and needs to be transmitted (i.e., reaches the working state), it is necessary to set the output port of the data scheduling module to the working state in advance to ensure the immediacy of data transmission and avoid excessive accumulation of data in the protocol layer controller causing excessive cache pressure. For example, as shown in 3B, the virtual interface state machine determination module (not shown in the figure) includes three virtual interface state machines, vLSMS_0, vLSMS_1 and vLSMM, vLSMS_0 and vLSMS_1 are virtual interface state machines of two ports connected to the protocol layer controller, and vLSMM is a virtual interface state machine of the output port of the sending module 3210 (i.e., the output port of the data scheduling module).

[0090] For example, in a possible implementation manner, any one of the virtual interface state machines includes any one of a silent state, a working state, and a low power consumption state.

[0091] Figure 5 A schematic diagram showing the operation of a virtual interface state machine of an arbitrator in a data transfer controller according to at least one embodiment of the present disclosure is shown.

[0092] like Figure 5As shown, for example, the virtual link state machine (vLSM) includes three interface states, namely disconnected, LS0 and LS1. Disconnected is a silent state, LS0 is a working state, and LS1 is a low power state. It should be noted that each input port and output port of the above arbitrator includes a virtual interface state machine, and each virtual interface state machine includes any of the above three interface states. For any port, the jump of its virtual interface state machine is divided into the following four situations:

[0093] (1) Jump from the disconnected state to the LS0 state;

[0094] (2) Jump from LS0 state to disconnect state;

[0095] (3) Jump from LS0 state to LS1 state; and

[0096] (4) Jump from LS1 state to disconnect state.

[0097] It should be noted that the interface state of any of the above ports cannot jump from LS1 state (i.e. low power consumption state) to LS0 state (i.e. working state) or from disconnected state (i.e. silent state) to LS1 state (i.e. low power consumption state). LS1 state is an intermediate state. It is possible to jump from LS0 state to LS1 state only when the data to be transmitted in the protocol layer gradually decreases and the transmission rate decreases.

[0098] Figure 6 A schematic diagram showing the matching between virtual interface state machines of each port of an arbitrator in a data transfer controller according to at least one embodiment of the present disclosure is shown.

[0099] like Figure 6 As shown, for example, the arbitrator includes two input ports and one output port, the virtual interface state machines of the two input ports are vLSMS_0 and vLSMS_1 as shown, and the virtual interface state machine of the output port is vLSMM as shown. For example, the matching of the virtual interface state machines between the three ports includes the following 8 situations:

[0100] (1) vLSMS_0 is in the disconnected state, vLSMS_1 is in the disconnected state, and then vLSMM is in the disconnected state;

[0101] (2) vLSMS_0 is in a disconnected state, vLSMS_1 is in a disconnected state, and then vLSMM is in a disconnected state;

[0102] (3) vLSMS_0 is in LS0 state (i.e., working state), vLSMS_1 is in disconnected state, and vLSMM is in LS0 state (i.e., working state);

[0103] (4) vLSMS_0 is in the LS0 state (i.e., working state), vLSMS_1 is in the LS0 state (i.e., working state), and then vLSMM is in the LS0 state (i.e., working state);

[0104] (5) vLSMS_0 is in LS0 state (i.e., working state), vLSMS_1 is in LS1 state (i.e., low power state), and then vLSMM is in LS0 state (i.e., working state);

[0105] (6) vLSMS_0 is in LS1 state (i.e., low power consumption state), vLSMS_1 is in LS1 state (i.e., low power consumption state), and then vLSMM is in LS1 state (i.e., low power consumption state);

[0106] (7) vLSMS_0 is in LS0 state (i.e. working state), vLSMS_1 is in disconnected state, and vLSMM is in LS0 state (i.e. working state);

[0107] (8) vLSMS_0 is in LS1 state (i.e., low power consumption state), vLSMS_1 is in LS1 state (i.e., low power consumption state), and then vLSMM is in LS0 state (i.e., working state).

[0108] It should be noted that the input port of the arbitrator is connected to the upstream protocol layer controller. When stopping the transmission of protocol layer data, the transmission of data in the upstream protocol layer controller should be stopped first, and then the data transmission of the downstream output port should be stopped. Therefore, for the above situation (2), there is a situation when the input ports are disconnected and the output ports are working. It should be noted that the working situation of the output ports only lasts for a short time before they become disconnected. The above situation (8) is similar to the situation (2) and will not be repeated here.

[0109] It should be noted that in the embodiments of the present disclosure, the data transmission controller may include more or fewer circuits or units, and the connection relationship between the various circuits or units is not limited and can be determined according to actual needs. The specific configuration of each circuit is not limited and can be composed of analog devices according to circuit principles, or can be composed of digital chips, or can be composed in other applicable ways.

[0110] The data transmission controller provided in at least one embodiment of the present disclosure, on the one hand, arbitrates data of different protocol layers, reduces the number of data link layer controllers, transmits the data of different protocol layers through a unique data link layer controller to realize multiplexing of the data link layer, reduces the use of hardware resources, saves area and power consumption, and improves the utilization and flexibility of the data transmission link; on the other hand, through the design of data link layer encapsulation, isolation and protection of data of different protocol layers are realized, ensuring the security and reliability of data transmission.

[0111] At least one embodiment of the present disclosure also provides a data transmission method, comprising: receiving data from N protocol layers, determining data to be transmitted according to the transmission priority of the data of the above-mentioned N protocol layers, and packaging and transmitting the data of the protocol layers to be transmitted to the other end via a data transmission link, wherein N is an integer greater than or equal to 2.

[0112] Figure 7 A schematic flow chart of a data transmission method according to at least one embodiment of the present disclosure is shown. Figure 7 As shown, the data transmission method includes steps S710 to S730.

[0113] Step S710: receiving data from N protocol layer controllers;

[0114] Step S720: determining the data of the protocol layer controller to be transmitted according to the transmission priority of the data of the N protocol layer controllers;

[0115] Step S730: Pack the data of the protocol layer controller to be transmitted and transmit it to the other end via the data transmission link, where N is an integer greater than or equal to 2.

[0116] For example, the above data transmission method corresponds to the data transmission controller shown in FIG. 2 .

[0117] For example, the data of the N protocol layer controllers in the above step S710 is obtained by Figure 2A The N protocol layers 3101-310N are sent by Figure 3A The sending module 3210 receives data from N protocol layer controllers.

[0118] For example, in a possible implementation, after receiving data from N protocol layer controllers, the data transmission method further includes: converting the clock domain of the data from the N protocol layer controllers to the clock domain of the data transmission link for arbitration. For example, this step can be performed by the data clock conversion module (for example, Figure 3B The specific function of data clock conversion has been described above and will not be repeated here.

[0119] For example, in a possible implementation, the data transmission method further includes: receiving a control signal corresponding to the data of the protocol layer controller to be transmitted, converting the clock domain of the control signal to the clock domain of the data transmission link, and packaging the control signal into a control instruction, which is transmitted to the other end via the data transmission link to communicate with the protocol layer controller of the other end, wherein the transmission priority of the control instruction is higher than the transmission priority of the data of the protocol layer controller to be transmitted. For example, this step can be performed by the control signal clock conversion module and the control instruction generation module.

[0120] For example, when a signal from a NBIO controller is to be transmitted through a data transmission link, a control signal (eg, a wake-up signal OBBwake1) sent by the NBIO controller passes through a control signal clock conversion module (eg, Figure 3B The wake-up signal is then synchronized with the clock of the data transmission link after the Async in the sending module 3210 is sent. The wake-up signal is generated by the control instruction generating module (for example, Figure 3B The Meta packet generation module in the sending module 3210 is packaged into a control instruction and sent to the NBIO controller at the other end via the data transmission link so that the two NBIO controllers can establish a communication connection. It should be noted that data can only be sent and received after the two NBIO controllers establish a communication connection, that is, the transmission priority of the control instruction in the protocol layer controller is higher than the transmission priority of the data.

[0121] For example, in a possible implementation, the above-mentioned determination of the data of the protocol layer controller to be transmitted according to the transmission priority of the data of N protocol layer controllers includes: in response to selecting the nth protocol layer data from the N protocol layer data, the unselected n+1th protocol layer data is not empty and continues for a certain period of time, and the transmission priority of the n+1th protocol layer data is greater than that of the nth protocol layer data, selecting the n+1th protocol layer data as the protocol layer data to be transmitted; or

[0122] In response to the nth protocol layer data in the selected N protocol layer data being empty, and the unselected n+1th protocol layer data being full, the transmission priority of the n+1th protocol layer data is greater than the nth protocol layer data, the n+1th protocol layer data is selected as the protocol layer data to be transmitted; wherein n is an integer greater than 0 and less than or equal to N. For example, this step can be performed by the above-mentioned data arbitration module.

[0123] For example, if the data transmission link is transmitting data from the NBIO controller, the data from the SMN controller is continuously accumulated in multiple clock cycles (for example, 16 / 32 beats, one beat is one clock cycle). At this time, in order to prevent excessive accumulation of data in the SMN controller, it is determined that the transmission priority of the data in the SMN controller is greater than the data transmission priority of the NBIO controller. Therefore, the data from the SMN controller is selected through data arbitration and the data is transmitted to the opposite SMN controller for data communication. It should be noted that since part of the data in the NBIO controller has been transmitted, there is remaining space to receive the subsequent data for transmission during the transmission of the SMN controller data. At least one embodiment of the present disclosure flexibly allocates bandwidth through an internal arbitration strategy, dynamically and flexibly allocates bandwidth according to the actual bandwidth requirements of the physical interface, and implements isolation and protection of data at different protocol layers to ensure the security and reliability of data transmission.

[0124] For example, in a possible implementation, the data transmission method further includes: in response to at least one of the virtual interface state machines receiving N protocol layer data being in a working state, setting the virtual interface state machine connected to the data transmission link to a working state in advance. For example, the virtual interface state machine includes any one of a silent state, a working state, and a low power consumption state. For example, this step can be performed by the virtual interface state machine determination module.

[0125] It should be noted that the low power consumption state is an intermediate state of the working state and also belongs to a kind of working state. For example, the state of each of the above interfaces is determined by a virtual interface state machine, wherein the function and execution logic of the virtual interface state machine have been described above and will not be repeated here.

[0126] At least one embodiment of the present disclosure provides a data transmission method, which, on the one hand, arbitrates data of different protocol layers, reduces the number of data link layer controllers, and transmits the data of different protocol layers through a unique data link layer controller to realize multiplexing of the data link layer, thereby reducing the use of hardware resources and achieving the effect of saving area and power consumption; on the other hand, it flexibly allocates bandwidth through an internal arbitration strategy, dynamically and flexibly allocates the bandwidth of each protocol layer data according to the actual bandwidth requirements of the physical interface, and realizes isolation and protection of data of different protocol layers, thereby ensuring the security and reliability of data transmission.

[0127] At least one embodiment of the present disclosure further provides an electronic device, which includes the data transmission controller of any of the above embodiments. Figure 8 A schematic block diagram of an electronic device provided by at least one embodiment of the present disclosure. Figure 8As shown, the electronic device includes: a processing device 910; a storage device 980, including one or more computer program modules; wherein the one or more computer program modules are stored in the storage device 980 and are configured to be executed by the processing device 910, and the one or more computer program modules are used to execute the data transmission method provided by any embodiment of the present disclosure.

[0128] For example, the processing device 910 may be a central processing unit (CPU), a digital signal processor (DSP), a graphics processing unit (GPU), a general-purpose graphics processing unit (GPGPU), or other forms of processing units having data processing capabilities and / or instruction execution capabilities, and may be a general-purpose processor or a special-purpose processor, and may control other components in the electronic device to perform desired functions.

[0129] For example, the storage device 980 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may include, for example, a random access memory (RAM) and / or a cache memory (cache), etc. The non-volatile memory may include, for example, a read-only memory (ROM), a hard disk, a flash memory, etc. One or more computer program instructions may be stored on a computer-readable storage medium, and the processing device may run the program instructions to implement the functions (implemented by the processing device) in the embodiment of the present disclosure and / or other desired functions, such as a data transmission method, etc. Various applications and various data may also be stored in the computer-readable storage medium, such as a first release information packet, a second release information total packet, a second release information sub-packet, and various data used and / or generated by an application, etc.

[0130] For example, the electronic devices in the embodiments of the present disclosure may include, but are not limited to, mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Figure 8 The electronic device 900 shown is merely an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0131] For example, Figure 8As shown, in some examples, the processing device 910 may include a processor of any of the above-mentioned embodiments, which may perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 920 or a program loaded from a storage device 980 into a random access memory (RAM) 930. Various programs and data required for the operation of the computer system are also stored in the RAM 930. The processing device 910, the ROM 920, and the RAM 930 are connected to each other via a bus 940. An input / output (I / O) interface 950 is also connected to the bus 940.

[0132] For example, the following components may be connected to the I / O interface 950: an input device 960 including, for example, a touch screen, a touch pad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 970 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 980 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 990 which may also include, for example, a network interface card such as a LAN card, a modem, etc. The communication device 990 may allow the electronic device 900 to communicate with other devices wirelessly or by wire to exchange data, performing communication processing via a network such as the Internet. Although Figure 8 The electronic device 900 is shown to include various devices, but it should be understood that it is not required to implement or include all the devices shown. More or fewer devices may be implemented or included instead.

[0133] For example, the electronic device 900 may further include a peripheral interface (not shown in the figure), etc. The peripheral interface may be various types of interfaces, such as a USB interface, a lightning interface, etc. The communication device 990 may communicate with a network and other devices through wireless communication, such as the Internet, an intranet and / or a wireless network such as a cellular phone network, a wireless local area network (LAN) and / or a metropolitan area network (MAN). Wireless communication may use any of a variety of communication standards, protocols, and techniques, including, but not limited to, Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging, and / or Short Message Service (SMS), or any other suitable communication protocol.

[0134] For example, the electronic device 900 can be any device such as a mobile phone, a tablet computer, a laptop computer, an e-book, a game console, a television, a digital photo frame, a navigator, a server, etc., or it can be any combination of data processing devices and hardware, and the embodiments of the present disclosure are not limited to this.

[0135] At least one embodiment of the present disclosure further provides a computer storage medium for storing non-transitory computer program executable code (e.g., computer executable instructions). When the non-transitory computer program executable code is executed by a computer (e.g., including one or more processors), the data transmission method of any embodiment of the present disclosure can be implemented.

[0136] Fig. 9 FIG. 1 is a schematic diagram of a computer storage medium provided by at least one embodiment of the present disclosure. Fig. 9 As shown, the computer storage medium 1000 non-temporarily stores computer executable instructions 1010. For example, when the computer executable instructions 1010 are executed by a computer (eg, including one or more processors), the data transmission method provided according to any embodiment of the present disclosure may be executed.

[0137] For example, the storage medium may be any combination of one or more computer-readable storage media, such as one computer-readable storage medium containing a computer-readable program code for receiving data from N protocol layers, another computer-readable storage medium containing a computer-readable program code for determining the data of the protocol layer to be transmitted according to the transmission priority of the data of the N protocol layers, and another computer-readable storage medium containing a computer-readable program code for packaging the data of the protocol layer to be transmitted and transmitting it to the other end via a data transmission link. For example, when the program code is read by a computer, the computer can execute the program code stored in the computer storage medium and execute, for example, the data transmission method provided in any embodiment of the present disclosure.

[0138] For example, the storage medium may include a memory card of a smart phone, a storage component of a tablet computer, a hard disk of a personal computer, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a portable compact disk read-only memory (CD-ROM), flash memory, or any combination of the above storage media, or other applicable storage media.

[0139] For example, the computer storage medium 1000 may be applied to the above-mentioned data transmission controller. Figure 8 The read-only memory 920 in the electronic device 900 is shown. For example, the relevant description of the computer storage medium 1000 can be referred to Figure 8The corresponding description of the read-only memory 920 in the electronic device 900 is not repeated here.

[0140] Although the disclosure has been described in detail above with general descriptions and specific implementation methods, it is obvious to those skilled in the art that some modifications or improvements may be made to the embodiments of the disclosure. Therefore, these modifications or improvements made without departing from the spirit of the disclosure are within the scope of protection claimed by the disclosure.

[0141] In addition to the above exemplary description, the following points need to be explained for this disclosure:

[0142] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure. Other structures may refer to the general design.

[0143] (2) For the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the thickness of layers or regions is enlarged or reduced, that is, these drawings are not drawn according to the actual scale.

[0144] (3) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to obtain new embodiments.

[0145] The above description is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. A data transmission controller, comprising N protocol layer controllers, an arbitrator and a data link layer controller, wherein: The N protocol layer controllers are configured to transmit N protocol layer data; The arbitrator is configured to receive N protocol layer data from the N protocol layer controllers and determine the transmission priority of the N protocol layer data; The data link layer controller is configured to transmit the N protocol layer data according to the transmission priority; Wherein, N is an integer greater than or equal to 2.

2. The data transfer controller according to claim 1, wherein: The arbitrator comprises: A sending module, configured to receive N protocol layer data from the N protocol layer controllers, and after determining the transmission priority of the N protocol layer data, send the protocol layer data to be transmitted to the data link layer controller to perform data communication with the protocol layer of the opposite end; The receiving module is configured to receive the data of the protocol layer sent by the opposite end and send it to its own protocol layer to perform data communication with the protocol layer of the opposite end.

3. The data transfer controller according to claim 2, wherein: The sending module comprises: a data clock conversion module, configured to switch the first clock domain of the N protocol layer data to the second clock domain; and A control signal clock conversion module is configured to switch the first clock domain of the control signal corresponding to the N protocol layer data to the second clock domain, wherein the control signal is used to control each protocol layer to communicate with the protocol layer corresponding to the opposite end, wherein the second clock domain is the same as the clock domain of the data link layer controller.

4. The data transfer controller according to claim 3, wherein: The sending module also includes: a data arbitration module, configured to determine the transmission priority of the N protocol layer data and select the protocol layer data to be transmitted; and The data scheduling module is configured to receive the protocol layer data to be transmitted sent by the data arbitration module and transmit the data to the data link layer controller to send to the opposite end.

5. The data transfer controller according to claim 4, wherein: The sending module also includes: A control instruction generating module, configured to receive the control signal converted by the control signal clock conversion module and package it into a first control instruction to transmit to the data scheduling module; The data scheduling module is also configured to transmit the first control instruction to the data link layer controller and send it to the opposite end to establish a communication connection with the protocol layer corresponding to the opposite end.

6. The data transfer controller according to claim 4, wherein: The receiving module comprises: A multi-channel data selection module, configured to receive the protocol layer data and the first control instruction sent by the opposite end; a data clock restoration module, configured to restore the second clock domain of the protocol layer data sent by the opposite end to the first clock domain; and The control signal clock restoration module is configured to restore the second clock domain of the control signal sent by the opposite end to the first clock domain and then transmit it to the corresponding protocol layer.

7. The data transfer controller according to claim 6, wherein: The receiving module further comprises a control instruction parsing module configured to unpack the first control instruction into a control signal and then transmit the control signal to the control signal clock restoration module; The multi-channel data selection module is also configured to transmit the received protocol layer data sent by the opposite end to the data clock recovery module, and transmit the first control instruction to the control instruction parsing module, wherein the transmission priority of the first control instruction is higher than the transmission priority of the protocol layer data.

8. The data transfer controller according to claim 7, wherein: The transmission priority of the first control instruction is higher than the transmission priority of the protocol layer data, including: In response to receiving the first control instruction for the transmission of the protocol layer to be transmitted at the opposite end, the data of the protocol layer to be transmitted is transmitted.

9. The data transfer controller according to claim 4, wherein: The determining the transmission priority of the N protocol layer data and selecting the protocol layer data to be transmitted includes: In response to selecting the nth protocol layer data from N protocol layer data, if the unselected n+1th protocol layer data is not empty and continues for a certain period of time, the transmission priority of the n+1th protocol layer data is greater than that of the nth protocol layer data, the n+1th protocol layer data is selected as the protocol layer data to be transmitted; or In response to the nth protocol layer data among the selected N protocol layer data being empty, and the unselected n+1th protocol layer data being full, the transmission priority of the n+1th protocol layer data being greater than the nth protocol layer data, selecting the n+1th protocol layer data as the protocol layer data to be transmitted; Here, n is an integer greater than 0 and less than or equal to N.

10. The data transfer controller according to claim 4, wherein: The arbitrator also includes: The virtual interface state machine determination module is configured to set the virtual interface state machine of the data scheduling module to the working state in advance in response to at least one of the virtual interface state machines receiving the N protocol layer data being in the working state.

11. The data transfer controller according to claim 10, wherein: The virtual interface state machine includes any one of a silent state, a working state and a low power consumption state.

12. A data transmission method, comprising: Receive data from N protocol layer controllers; Determining the data of the protocol layer controller to be transmitted according to the transmission priority of the data of the N protocol layer controllers; Packing the data of the protocol layer controller to be transmitted and transmitting it to the other end via the data transmission link; Wherein, N is an integer greater than or equal to 2.

13. The data transmission method according to claim 12, wherein: After receiving data from the N protocol layer controllers, the method further includes: The clock domain of the data from the N protocol layer controllers is converted to the clock domain of the data transmission link controller for arbitration.

14. The data transmission method according to claim 13, further comprising: Receive a control signal corresponding to the data of the protocol layer controller to be transmitted, convert the clock domain of the control signal to the clock domain of the data transmission link, and then package it into a control instruction, which is transmitted to the other end via the data transmission link to communicate with the protocol layer controller of the other end, wherein the transmission priority of the control instruction is higher than the transmission priority of the data of the protocol layer controller to be transmitted.

15. The data transmission method according to claim 12, wherein: The determining the protocol layer data to be transmitted according to the transmission priority of the data of the N protocol layer controllers includes: In response to selecting the nth protocol layer data from N protocol layer data, if the unselected n+1th protocol layer data is not empty and continues for a certain period of time, the transmission priority of the n+1th protocol layer data is greater than that of the nth protocol layer data, the n+1th protocol layer data is selected as the protocol layer data to be transmitted; or In response to the nth protocol layer data among the selected N protocol layer data being empty, and the unselected n+1th protocol layer data being full, the transmission priority of the n+1th protocol layer data being greater than the nth protocol layer data, selecting the n+1th protocol layer data as the protocol layer data to be transmitted; Here, n is an integer greater than 0 and less than or equal to N.

16. The data transmission method according to claim 12, further comprising: In response to at least one of the virtual interface state machines receiving the N protocol layer data being in a working state, the virtual interface state machine connected to the data transmission link is set to a working state in advance.

17. The data transmission method according to claim 16, wherein: The virtual interface state machine includes any one of a silent state, a working state and a low power consumption state.

18. An electronic device, comprising: a storage device configured to non-transitorily store computer-executable instructions; as well as a processing device configured to execute the computer executable instructions, Wherein, when the computer executable instructions are executed by the processing device, the data transmission method according to any one of claims 12-17 is executed.

19. A non-transitory storage medium that non-transitorily stores computer-executable instructions, wherein: When the computer executable instructions are executed by a computer, the data transmission method according to any one of claims 12 to 17 is executed.

Images