An interconnect system

Abstract

The present application relates to the field of chip design, in particular to an interconnection system, which comprises at least one switch and K servers. Wherein each server comprises a plurality of unit groups, each unit group comprises T computing units, each computing unit comprises Q ports to be interconnected with the switch; the switch connects all ports of all computing units in the K servers, and by configuring the switch, Sum interconnection relationships are obtained, each interconnection relationship comprises one computing unit in each unit group, different computing units in the same unit group are located in different interconnection relationships, and two computing units in different unit groups can directly communicate through one hop through the switch, compared with the communication through the hardware topology formed by the computing units in each unit group, the communication delay is reduced, and the bandwidth of the system is increased.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of chip design, and in particular to an interconnection system. BACKGROUND

[0002] With the increasing demand for high-performance computing (HPC) and large-scale parallel processing, building large-scale interconnected clusters has become a key way to improve computing power. However, in large-scale interconnected clusters, the limitation of physical connection leads to the bottleneck of communication efficiency. Specifically, due to the limitation of physical distance and hardware resources, direct communication between any two computing units often cannot be achieved in one hop, but needs to go through multiple intermediate nodes for data exchange. This multi-hop communication increases the communication delay, and further reduces the overall computing efficiency. This phenomenon is particularly evident in complex interconnection topologies. In ring, mesh or tree topologies, the connection path of computing units is often long, and the direct connection between nodes is limited. For example, in a ring topology, data must be passed along the ring until it reaches the target node. This means that if two nodes are far apart in the ring, data needs to go through multiple intermediate nodes to complete transmission. Each intermediate node introduces additional delay, while increasing the burden of the node processing the packet, resulting in a decrease in overall communication efficiency.

[0003] In the traditional northbound network communication architecture, computing units are connected to PCIe switch chips within the server through PCIe interfaces, and then connected to network cards to access cluster network switches. This communication architecture to some extent alleviates the time delay problem introduced by multi-hop communication in super-large ring topology, but this architecture itself contains at least 6 intermediate nodes, for example: computing unit A to PCIe switch chip, PCIe switch chip to network card A, network card A to network switch, network switch to network card B, network card B to PCIe switch chip, PCIe switch chip to computing unit B. Obviously, the communication delay of the traditional network communication architecture cannot be ignored, and the communication delay increases with the increase of the network switch networking layer. In addition, the communication bandwidth of the computing unit under this architecture is limited by the number of PCIe switch chips within the server and the PCIe interface bandwidth of the computing unit. The delay caused by multi-hop communication not only affects the transmission speed of data, but also has a negative impact on the parallel processing capability of the GPU cluster. In high-performance computing, many tasks require frequent inter-node communication and data exchange. The increase of communication delay directly affects the overall completion time of the computing task, and reduces the throughput of the system. Therefore, when designing a large-scale interconnected cluster, how to optimize the topology to reduce the time delay of multi-hop communication and reduce the bandwidth limitation of intermediate nodes becomes a problem to be solved. SUMMARY

[0004] To address the aforementioned technical problems, the present invention adopts the following technical solution: an interconnection system comprising at least one switch and K servers. Each server comprises multiple unit groups, wherein the i-th server serves... i Includes R(i) unit groups; serv i The r-th unit group comprises T computing units, each computing unit comprising Q ports to be interconnected with the switch, where i ranges from 1 to K, r ranges from 1 to R(i), and t ranges from 1 to T. The switch connects the Q ports of all computing units in the K servers, and Sum interconnections are obtained by configuring the switch. Each interconnection includes one computing unit from each unit group, and different computing units within the same unit group reside in different interconnections.

[0005] The present invention has at least the following beneficial effects:

[0006] Direct connection between the Q ports of the computing unit and the switch enables communication between two computing units in different unit groups via a single hop. Compared to communication through hardware topologies formed by computing units within unit groups or traditional northbound networks, this reduces communication latency, increases system bandwidth, and lowers the bandwidth limitations imposed by intermediate nodes. Furthermore, the switch distinguishes between the Sum interconnections between different computing units within a unit group. Communication between the T computing units within a unit group is achieved through a fixed topology within the unit group. With the same interconnection scale and bandwidth, compared to traditional northbound networks, this reduces the number of ports interconnected via switches, further saving on the interconnection costs of large clusters. Attached Figure Description

[0007] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0008] Figure 1 This is a schematic diagram of an interconnection system provided in Embodiment 1 of the present invention;

[0009] Figure 2 This is a schematic diagram of the logical topology formed after configuration via a switch, as provided in Embodiment 2 of the present invention.

[0010] Figure 3 To be Figure 2 A schematic diagram of a loop topology switching in the topology;

[0011] Figure 4 forFigure 3 A structural diagram of a degraded topology when a computing unit fails;

[0012] Figure 5 For Figure 3 A structural diagram of a redundant topology switched to when a logical topology fails. DETAILED DESCRIPTION

[0013] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0014] Unless otherwise defined, all the technical and scientific terms used in the embodiments of the present application have the same meanings as commonly understood by a person of ordinary skill in the art.

[0015] Embodiment one

[0016] Please refer to Figure 1 , which shows a schematic diagram of an interconnected system, the system including at least one switch and K servers.

[0017] Among them, the server is a physical computer, which is usually configured with one or more central processing units, a certain number of computing units and sufficient memory and other hardware resources.

[0018] Among them, the switch is a network device, which can connect the computing units in multiple servers to enable cross-server communication between the computing units.

[0019] In an embodiment, the switch is a PCIe (Peripheral Component Interconnect Express) switch or an optical circuit switch (OCS). Other switches capable of directly connecting computing units across servers also fall within the protection scope of the present application.

[0020] Further, each server includes a plurality of unit groups, wherein the i-th server serv i includes R(i) unit groups Gp i ={Gp i,1 ,Gp i,2 ,…,Gp i,r ,…,Gp i,R(i)}, Gp i,r is the r-th unit group in the i-th server, r ranges from 1 to R(i), and i ranges from 1 to K; please refer toFigure 1 , Figure 1 In the example of serv i The rth unit group Gp i,r is taken as a representative example of the composition of all unit groups, where Gp i,r includes T computing units {PRC i,r,1 , PRC i,r,2 , …, PRC i,r,t , …, PRC i,r,T}, PRC i,r,t is the tth computing unit in Gp i,r , and t ranges from 1 to T. Each computing unit includes Q ports to be interconnected with the switch.

[0021] where R(i) is the number of unit groups. Different servers can include the same number of unit groups or different numbers of unit groups. For example, one server includes two unit groups, and another server includes four unit groups.

[0022] In an embodiment, the computing unit is a graphics processing unit (GPU), a general-purpose computing on graphics processing units (GPGPU), or a neural processing unit (NPU), and other computing units for processing data fall within the protection scope of the present application.

[0023] In an embodiment, T x R(i) ≤ th0, and th0 is a preset optimal number threshold of computing units in a server. When T x R(i) is less than th0, the system is more reliable and the replacement cost is low, and when T x R(i) is greater than or equal to th0, the system reliability risk increases and the replacement cost increases. Since the server replacement frequency is high, th0 is preset, which not only reduces the replacement cost, but also ensures that the system can still provide sufficient computing resources in the case of frequent server replacement, and guarantees the continuous and reliable operation of the system. For example, th0 is equal to 16, when the number of T x R(i) is less than 16, the system is more reliable and the replacement cost is low, and when the number of T x R(i) is greater than or equal to 16, the system reliability risk increases and the replacement cost increases.

[0024] In an embodiment, each server includes one unit group, and the unit group includes 4 computing units.

[0025] In an embodiment, each server includes two unit groups, and each unit group includes 4 computing units.

[0026] Other combinations of the number of unit groups included in each server and the number of computing units in each unit group also fall within the scope of the present application.

[0027] In one embodiment, the computing units are modules conforming to the OAM standard. Computing units that are modules conforming to other standards also fall within the scope of the present application.

[0028] Further, the switches are directly connected to Q ports of all computing units in the K servers, and by configuring the switches, Sum interconnection relationships are obtained, each of which includes one computing unit in each unit group, and different computing units in the same unit group are located in different interconnection relationships, where T ≤ Sum ≤ Q × T. In this way, the switches enable any two computing units in different unit groups to directly communicate through one hop, and compared with the hardware topology formed by the computing units in each unit group, the communication between the computing units is performed through a shorter path, reducing the communication delay and increasing the bandwidth of the system. Meanwhile, since all computing units in each unit group are respectively connected to different switches, the pressure of cross-group communication is dispersed, and the load is more balanced; the traffic between different switches can be more evenly distributed, reducing the load bottleneck of a single switch and optimizing the use of network bandwidth.

[0029] In one embodiment, when Sum = T, the system includes T interconnection relationships with the same bandwidth, and each interconnection relationship is obtained by configuring the SW to configure the Q ports of each computing unit to be interconnected with the switch into the same interconnection relationship. That is, the Q ports of each computing unit to be interconnected with the switch are connected to the same switch and configured to communicate with the same computing unit in the same interconnection relationship.

[0030] Optionally, when Q = 1, the system includes T switches, and a single switch is connected to one computing unit in each unit group, and different switches are connected to different computing units in the same group; by configuring each switch to configure all computing units connected to the current switch into an interconnection relationship, the number of interconnected computing units can be maximized.

[0031] As an example, please refer again to Figure 1 , which shows that the system includes T switches SW = {SW1, SW2, …, SW f ,…,SW T}, SW f is the fth switch, and f ranges from 1 to T. Each switch is connected to one computing unit in all unit groups. Among them, SW f is connected to PRC i,r in Gp i,r,t , and SW fnot connected with Gp i,r the qth computing unit in the group PRC i,r,q connected, PRC i,r,t not connected with the hth switch in the group SW h connected, q and f are both in the range of 1 to T, and t≠q, f≠h. Wherein PRC i,r,q and SW h are not shown in the figure.

[0032] In an embodiment, when the interconnection ports of the switches themselves are sufficient, the number of switches can be less than T. For example, each switch is connected with two computing units in each unit group respectively, and after configuring the switches, the two computing units connected with the same switch in each unit group are located in two interconnection relationships. For another example, when the interconnection ports of the switches themselves are completely sufficient, sufficient to support all computing units, the number of switches can be 1, all computing units are connected through one switch, but the computing units in each interconnection relationship formed still belong to different unit groups.

[0033] In an embodiment, when Sum=Q×T, the system includes Q×T interconnection relationships with the same bandwidth, each interconnection relationship is that through configuring the SW, Q ports of each computing unit to be interconnected with the switch are configured into Q different interconnection relationships. That is, the Q ports of the same computing unit are located in different interconnection relationships, in other words, the Q ports of the same unit are interconnected with different computing units, so that each computing unit can communicate with other computing units through Q different interconnection relationships at the same time, reducing the inter-group communication hop count.

[0034] In an embodiment, when T

[0035] Wherein, different computing units in the same group are connected to different switches, which can limit the influence range to the part of computing units connected with the switch when the switch fails, without affecting all computing units of the whole group, providing better fault isolation capability.

[0036] In one embodiment, when each unit group is numbered independently, the numbering of all the computing units connected to the same switch is the same or different. Taking the example of each unit group including 4 computing units, the numbering of the computing units in each group is 1-4, in the first connection mode, the same numbering is connected: taking SW f as an example, SW f connects the computing unit numbered 1 in each group. In the second connection mode, the different numbering is connected: taking SW f as an example, SW f connects the computing unit numbered 1 in the first group, the computing unit numbered 2 in the second group, the computing unit numbered 3 in the third group, and the computing unit numbered 4 in the fourth group, respectively. Or the numbering in two of the connected groups is the same and the numbering in the other two groups is different.

[0037] In one embodiment, when each x unit group is numbered independently, the numbering of all the computing units connected to the same switch includes preset x kinds of numbering. Taking x = 2 as an example, when the computing unit is a module conforming to the OAM standard, the maximum numbering of the computing unit is 8, and every two unit groups form a numbering cycle, so the two computing units connected to the same switch in the two unit groups have different numbering. For example: including 4 unit groups, every 2 unit groups form a numbering cycle, and taking SW f as an example, the computing unit numbered 2 in the first unit group in the first numbering cycle and the computing unit numbered 4 in the second unit group are connected to SW f . The computing unit numbered 2 in the third unit group in the second numbering cycle and the computing unit numbered 4 in the fourth unit group are also connected to SW f .

[0038] In one embodiment, the connection between the switch and the computing unit is an optical cable or an electrical cable, and other types of connection lines for data communication also fall within the protection scope of the present application.

[0039] In one embodiment, the connection between the computing units is an optical cable or an electrical cable, and other types of connection lines for data communication also fall within the protection scope of the present application.

[0040] In one embodiment, the interconnection between the computing units in the unit group is a ring topology or a mesh topology, and other types of topologies also fall within the protection scope of the present application.

[0041] In one embodiment, K servers form a server group including G servers in each group, and for each server in each server group, the interconnection between the computing units in the E unit groups inside the server is a hardware interconnection topology, and G and E are both greater than or equal to 1.

[0042] In an embodiment, the hardware interconnection topology is a ring topology, a Dragonfly topology or a mesh topology, and other types of topologies also fall within the protection scope of the present application.

[0043] In an embodiment, by configuring the current switch, the target computing unit connected to the current switch directly accesses other computing units whose numbers are different from that of the target computing unit. The logical topology formed by the configuration rule is suitable for the MOE scenario.

[0044] In an embodiment, when the numbers of all computing units connected to the same switch include preset x numbers, by configuring the switch f , the PRC i,r,t directly accesses all other computing units connected to the switch f and having numbers different from that of the PRC i,r,t . Or by configuring the switch f , the PRC i,r,t directly accesses all other computing units connected to the switch f . Similarly, the configuration rule of other switches is the same as that of the switch f . The logical topology formed by the configuration rule is suitable for the MOE scenario.

[0045] The scheme provided by the embodiment one of the present application can enable any two computing units in different unit groups to directly communicate through one hop by the switch, compared with the hardware topology formed by the computing units in each unit group, the communication between the computing units is performed through a shorter path, the communication delay is reduced, the bandwidth of the system is increased, and the limitation of the bandwidth by the intermediate nodes is reduced. Meanwhile, the switch distinguishes Sum interconnection relationships between different computing units in the unit group, and the communication between T computing units in the unit group is completed through the fixed topology in the unit group. Under the same interconnection scale and bandwidth, compared with the traditional northbound network, the number of interconnection ports of the switch is reduced, and the interconnection cost of the large cluster is further saved.

[0046] In order to obtain an interconnection system which can expand the interconnection topology and improve the fault redundancy of the system, the embodiment two of the present application is provided.

[0047] The embodiment two

[0048] The embodiment two of the present application provides an interconnection system based on a double-layer topology structure, the system includes at least one switch and at least one interconnection topology, each interconnection topology includes N physical topologies and a plurality of logical topologies.

[0049] The physical topology is a point-to-point direct connection through actual physical wiring.

[0050] In an embodiment, the links of the physical topology are cables or optical cables.

[0051] In the embodiment one of the present application, the switch is also applicable to the embodiment two of the present application, and will not be described again.

[0052] Further, each physical topology comprises: L groups of units, intra-group physical links and inter-group physical links. Each group of units comprises T computing units. Each intra-group physical link is used to connect the computing units in each group of units. Each inter-group physical link is used to connect the computing units belonging to different groups of units, and the two computing units connected by each inter-group physical link are different.

[0053] In an embodiment, each group of units comprises an intra-group topology, the intra-group topology is formed by the T computing units in the group of units through the intra-group physical links, and the topology is a ring topology, a mesh topology or a star topology, and other types of topologies also fall within the protection scope of the present application.

[0054] In an embodiment, each group of units comprises an inter-group topology, the inter-group topology is formed by the T computing units in the group of units and the T computing units in the adjacent group through the inter-group physical links, and other types of topologies also fall within the protection scope of the present application. The adjacent group is a group of units that is physically adjacent. When the physical topologies are distributed in the same direction, the adjacent groups are the groups of units that are physically adjacent, and the first group of units and the last group of units are regarded as adjacent groups.

[0055] Further, the switch is used to connect all the computing units in the interconnection topology.

[0056] In the embodiment one of the present application, the switch enables any two computing units in different groups of units to directly communicate through one hop, without the need to pass through the physical topology formed by the computing units in each group of units. At the same time, since all the computing units in each group of units are connected to different switches respectively, the pressure of cross-group communication is dispersed.

[0057] It should be noted that the connection relationship between the switch and each group of units in the embodiment one of the present application is also applicable to the embodiment two of the present application, and will not be described again.

[0058] Further, the plurality of logical topologies are logical topologies obtained by configuring the connection relationship between the computing units in the N physical topologies by the switch. Each logical topology comprises two groups of units and a logical path therebetween, wherein the i-th logical topology comprises T logical paths, and each logical path is used to connect two computing units belonging to two groups of units, and the computing units connected by different logical paths are different.

[0059] Each logical path includes two connections between the two computing units and the switch, and a logical path configured inside the switch.

[0060] The two unit groups are connected through logical topologies, which can expand the interconnection scale of the GPU. Through this way, the unit groups are connected through logical topologies, and the interconnection scale of the GPU is expanded. For example, when each unit group includes four computing units, the two unit groups are connected through logical topologies, and then an interconnection scale of eight GPUs is formed. If a third unit group is added to the interconnection scale of the eight GPUs, and the third unit group is connected to any one of the two unit groups, an interconnection scale of twelve GPUs is formed. If a fourth unit group is added, an interconnection scale of sixteen GPUs is formed, and so on.

[0061] In addition, the connections in the physical topology and the logical paths in the logical topology are redundant to each other. When one or more connections fail, the logical paths provide a path to replace the failed path for data exchange, reducing the risk of network interruption and improving the overall reliability of the system. When a fault in the inter-group connection in the physical topology is detected, the system can automatically switch to the logical path, simplifying the fault recovery process and reducing the need for manual intervention. The system provides effective measures for possible technical failures, ensuring the continuity and integrity of data transmission.

[0062] In an embodiment, the two unit groups in each logical topology belong to two unit groups in different physical topologies. The unit groups are connected through logical topologies in sequence to form an interconnection structure with unit groups as basic nodes and logical topologies as basic paths, and then the interconnection scale of the GPU is expanded infinitely. For example, two unit groups are included in a physical topology, and each unit group includes four GPUs. In this physical topology, one unit group is used to connect a unit group in the previous physical topology, and the other unit group in this physical topology is used to connect a unit group in the next physical topology. In an embodiment, when the number of unit groups included in the physical topology is greater than or equal to two, two logical topologies are included between two physical topologies, and the two logical topologies are connected to two unit groups belonging to the same physical topology.

[0063] In an embodiment, the two unit groups belonging to different physical topologies in each logical topology are physically adjacent. When the physical topologies are sequentially distributed in the same direction, the first and last physical topologies in the sequence are considered to be physically adjacent. Through this way, the adjacent physical topologies are connected in sequence through logical topologies to form a ring-shaped interconnection structure with unit groups as basic nodes and logical topologies as basic paths. On the basis of infinitely expanding the interconnection scale of the GPU, transmission in both clockwise and counterclockwise directions is allowed, which improves the system throughput.

[0064] In one embodiment, the two unit groups in each logical topology belong to two unit groups in different physical topologies respectively, and when one inter-group physical link fails, two target unit groups connected by the failed inter-group physical link are obtained, two sets of logical paths corresponding to the two target unit groups are obtained, all inter-group physical links of all unit groups connected by the two sets of logical paths are configured as unavailable, and switching to a new topology formed by the remaining physical topology and logical topology is performed for data exchange. That is, the system function is restored by forming a new fusion topology for exchanging data by combining the unfailed physical topology and logical topology. Other methods for replacing the failed physical link by logical path also fall within the protection scope of the present application.

[0065] In one embodiment, the two unit groups in each logical topology are two unit groups in the same physical topology.

[0066] In one embodiment, in an interconnection system, the following two configurations coexist: the two unit groups in each logical topology belong to two unit groups in different physical topologies respectively; and the two unit groups in each logical topology are two unit groups in the same physical topology.

[0067] In one embodiment, the two unit groups in each logical topology are two unit groups in the same physical topology and physically adjacent. When the unit groups are sequentially distributed in the same direction, the first unit group and the last unit group in the sequentially distributed unit groups are regarded as adjacent groups.

[0068] In one embodiment, in an interconnection system, the following two configurations coexist: the two unit groups in each logical topology belong to two unit groups in different physical topologies respectively; and the two unit groups in each logical topology are two unit groups in the same physical topology.

[0069] In one embodiment, the two unit groups in each logical topology are two unit groups in the same physical topology, and when one inter-group physical link fails, two target unit groups connected by the failed inter-group physical link are obtained, all inter-group physical links between the two target unit groups are configured as unavailable, and switching to a new topology formed by the remaining physical topology and logical topology is performed for data exchange. Other methods for replacing the failed physical link by logical path also fall within the protection scope of the present application.

[0070] For the convenience of understanding, taking an example of a system including 2 physical topologies, each physical topology including 4 unit groups, each unit group including 4 computing units, the computing units being modules conforming to the OAM standard, and each two computing units being independently numbered, a new topology structure configured when one inter-group physical link fails is described. Please refer to Figure 2 ,Figure 2 The shown interconnection system includes two physical topologies and two logical topologies. Among them, the two physical topologies are: the first physical topology and the second physical topology, each of which includes four unit groups: the first unit group, the second unit group, the third unit group, and the fourth unit group, the intra-group physical connection of each unit group, and the inter-group physical connection of point-to-point interconnection between unit groups. Among them, the first unit group and the second unit group are an indivisible basic unit group, which is independently numbered, and the third unit group and the fourth unit group are an indivisible basic unit group, which is independently numbered. As shown in Figure 2 The numbers of the computing units in the first unit group and the second unit group are S0-S7, and the numbers of the computing units in the third unit group and the fourth unit group are S0-S7. In the first physical topology and the second physical topology, the computing units numbered S1 and S0 are connected to the first switch SW1, the computing units numbered S2 and S4 are connected to the second switch SW2, the computing units numbered S3 and S5 are connected to the third switch SW3, and the computing units numbered S6 and S7 are connected to the fourth switch SW4. After configuration through SW1-SW4, two logical topologies are obtained, as shown in Figure 2 The first logical topology includes the second unit group in the first physical topology and the first unit group in the second physical topology, and the second logical topology includes the fourth unit group in the first physical topology and the third unit group in the second physical topology. The first logical topology and the second logical topology are the same, and each includes a logical path connecting S1 and S0, a logical path connecting S2 and S4, a logical path connecting S3 and S5, and a logical path connecting S6 and S7. When at least one inter-group connection between the second unit group and the fourth unit group in the first physical topology fails, for example, the inter-group physical connection between S1 in the second unit group of the first physical topology and S3 in the fourth unit group of the first physical topology fails, then all inter-group physical connections between the second unit group and the fourth unit group in the first physical topology are configured as unavailable, and at the same time, all inter-group physical connections between the first unit group and the third unit group in the second physical topology are also configured as unavailable. Please refer to Figure 3 The system is switched from the original topology to a loop topology composed of the remaining physical topology and logical topology. That is, the loop topology is formed by sequentially passing through the logical path between the second unit group of the first physical topology and the first unit group of the second physical topology, the inter-group physical connections of the first, second, fourth, and third unit groups of the second physical topology, the logical path between the third unit group of the second physical topology and the fourth unit group of the first physical topology, and the inter-group physical connections of the fourth, third, first, and second unit groups of the first physical topology, forming a loop topology with unit groups as the basic unit. Data exchange is carried out through the loop topology, the system function is restored, and the stability and reliability of the system are improved.

[0071] In one embodiment, when a computing unit fails, a degraded topology is obtained: if L1 unit groups are bound as one indivisible base unit group, when a computing unit fails, the base unit group where the failed computing unit is located and its associated inter-group physical links and logical topology are configured as unavailable, obtaining at least one original degraded topology; the switches are reconfigured according to the original degraded topology, obtaining a plurality of degraded logical topologies, and the original degraded topology and the degraded logical topologies constitute the degraded topology. Through the logical topology cooperating with the physical topology, the degraded topology is obtained by maximizing the full use of the original degraded topology, and the entire interconnection system is not unusable due to the failure of one computing unit.

[0072] Referring to Figure 3 , in another embodiment scenario, it is assumed that Figure 3 There are no inter-group physical links in the first physical topology, i.e., all the inter-group physical links between the second unit group and the fourth unit group in the first physical topology and all the inter-group physical links between the first unit group and the third unit group in the second physical topology are configured as unavailable. The ring topology with the unit group as the basic unit is configured due to design needs. Two unit groups are bound as one indivisible base unit group, wherein, in the first physical topology, one base unit group is the first and second unit groups, and the other base unit group is the third and fourth unit groups; in the second physical topology, one base unit group is the first and second unit groups, and the other base unit group is the third and fourth unit groups. When S0 of the first unit group in the second physical topology fails, the base unit where S0 is located and its associated inter-group physical links and logical topology are configured as unavailable, obtaining an original degraded topology, which includes the first physical topology and a target base unit group composed of the third and fourth unit groups in the second physical topology connected through the logical topology, as shown in Figure 4 Referring to Figure 4 , the switches are reconfigured according to the original degraded topology, the logical topology between the first physical topology and the target base unit group is configured as unavailable, and the logical topology inside the target base unit group is configured, so that S2 of the third unit group and S4 of the fourth unit group in the second physical topology are logically connected, S6 of the third unit group and S7 of the fourth unit group are logically connected, S1 of the third unit group and S0 of the fourth unit group are logically connected, S5 of the third unit group and S3 of the fourth unit group are logically connected, obtaining a degraded topology composed of the physical topology of the target base unit group and the configured internal logical topology. That is, the degraded topology includes two: one is the first physical topology, and the other is the degraded topology of the target base unit group.

[0073] In one embodiment, when the logical topology is faulty, the faulty logical topology is configured to be unavailable, obtaining at least one degraded topology. Alternatively, when the logical topology is faulty, the faulty logical topology is configured to be unavailable, and another logical path is configured to replace the function of the faulty logical path. Wherein, when one or more logical paths are faulty, the logical topology to which the faulty logical path belongs is considered to be faulty. Through the flexible configuration of the logical topology, the logical topologies are redundant to each other, the fault tolerance and the flexibility of the system are improved, and the stability and reliability of the interconnected system are ensured.

[0074] Please refer to Figure 3 In another implementation scenario, Figure 3 The ring topology in the unit group is taken as the basic unit, and in Figure 3 There is no faulty inter-group physical connection, that is, the inter-group physical connection configured to be unavailable does not fail, but is configured to be unavailable according to the design requirement. When the logical path between S1 in the second unit group of the first physical topology and S0 in the first unit group of the second physical topology fails, the logical topology between the second unit group of the first physical topology and the first unit group of the second physical topology is considered to be faulty, and the faulty logical topology is configured to be unavailable. Please refer to Figure 5 In order to restore Figure 3 the ring topology in the unit group, the logical topology between the fourth unit group of the first physical topology and the third unit group of the second physical topology is also configured to be unavailable, the inter-group physical connection between the second and fourth unit groups of the first physical topology is configured to be available, the inter-group physical connection between the first and third unit groups of the second physical topology is configured to be available, and the logical topology between the first unit group of the first physical topology and the second unit group of the second physical topology and the logical topology between the third unit group of the first physical topology and the fourth unit group of the second physical topology are configured by the switch, forming a new ring topology.

[0075] Other interconnected topologies caused by the failure of the computing unit or the connection are configured by the switch to degrade the interconnected scale to a degraded topology with a smaller interconnected scale, which falls within the protection scope of the present application.

[0076] The system provided by the second embodiment of the present application comprises a physical topology and a logical topology configured by a switch, the connection in the physical topology and the logical path in the logical topology cooperate with each other, so that two unit groups are interconnected through the logical topology, and the scale of the GPU interconnection is expanded. Meanwhile, since the logical topology has the characteristic of flexible and configurable communication path, when one or more connections fail, the path provided by the logical path replaces the failed path to exchange data, the fault tolerance is high, the risk of network interruption is reduced, and the overall reliability of the system is improved.

[0077] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the above-mentioned division of each functional unit and module is exemplified, and in actual application, the above-mentioned functions can be completed by different functional units and modules according to needs, that is, the internal structure of the device is divided into different functional units or modules to complete all or part of the functions described above.

[0078] Although some specific embodiments of the present application have been described in detail by examples, those skilled in the art should understand that the above examples are only for illustration, not for limiting the scope of the present application. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of the present application. The scope of the present application is defined by the appended claims.

Claims

1. An interconnection system, characterized in that, The system includes: At least one switch is provided for connecting computing units within multiple servers, enabling cross-server communication between the computing units. There are K servers, each a separate physical computer. Each server comprises multiple unit groups, where the i-th server serves... i Includes R(i) unit groups; serv i The r-th unit group includes T computing units, and each computing unit includes Q ports to be interconnected with the switch, where the value of i ranges from 1 to K, and the value of r ranges from 1 to R(i). The switch directly connects to Q ports of all computing units in the K servers. By configuring the switch, Sum interconnections are obtained. Each interconnection includes one computing unit in each unit group. Different computing units in the same unit group are located in different interconnections, where T≤Sum≤Q×T. The system has T switches. A single switch connects to one computing unit in each unit group, and different switches connect to different computing units in the same group. Each switch is configured to form an interconnection relationship between all computing units connected to the current switch.

2. The system according to claim 1, characterized in that, When Sum=T, the system includes T interconnections with the same bandwidth. Each interconnection is configured by configuring the switch so that Q ports of each computing unit to be interconnected with the switch are configured into the same interconnection.

3. The system according to claim 1, characterized in that, When Sum = Q×T, the system includes Q×T interconnections with the same bandwidth. Each interconnection is configured by configuring the switch so that Q ports of each computing unit to be interconnected with the switch are configured into Q different interconnections.

4. The system according to claim 1, characterized in that, When T < Sum < Q × T, the system includes at least two interconnection relationships with different bandwidths: the number of ports configured for each computing unit in the first interconnection relationship is different from the number of ports configured for each computing unit in the second interconnection relationship.

5. The system according to claim 1, characterized in that, When each unit group is numbered independently, all computing units connected to the same switch may have the same or different numbers.

6. The system according to claim 1, characterized in that, When each x unit group is numbered independently, the numbering of all computing units connected to the same switch includes x preset numbering methods.

7. The system according to claim 6, characterized in that, By configuring the current switch, the target computing unit connected to the current switch can directly access other computing units with different numbers than the target computing unit.

8. The system according to claim 1, characterized in that, The switch is a PCIe switch or an all-optical switch.

9. The system according to claim 1, characterized in that, T×R(i)≤th0, where th0 is the maximum number of computing units in the preset server.

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