Image centroid coordinate extraction circuit without divider

Abstract

The invention discloses an image centroid coordinate extraction circuit without a divider, which is realized by relying on a field programmable gate array (FPGA), and has the core that division operation in a centroid calculation formula is converted into addition, subtraction and multiplication operation so as to avoid trial division and remainder taking processes required by the division operation. In order to further optimize the area of the circuit and enhance the functionality of the circuit, an adder unit in the multiplier is expanded, so that the adder unit not only can support multiplication operation, but also can execute subtraction operation. Through the design, in combination with a time division multiplexing technology, the multiplier circuit can execute all arithmetic processes of centroid extraction iterative approximation. According to the invention, the processing speed of the centroid extraction circuit is optimized, rapid centroid extraction of a large-target-surface image is realized through a small clock period and a controllable circuit area, and the method has wide application potential in multiple fields such as image recognition, target tracking and artificial intelligence.

Description

Technical Field

[0001] The invention belongs to the technical fields of image centroid extraction, digital integrated circuit design and real-time signal processing, and in particular relates to an image centroid coordinate extraction circuit without a divider. Background Art

[0002] The centroid extraction circuit plays a very important role in the field of image processing. It can identify the center position of objects in the image, and plays a vital role in target tracking, object recognition and wavefront detection. Specifically, the digital circuit can locate the exact coordinates of the object by calculating the weighted average of each pixel in the image. It has a wide range of applications in fields such as autonomous driving, face recognition and aerospace.

[0003] In practical applications, centroid extraction is usually performed in the form of digital circuits, which is mainly caused by the separation of the acquisition system and signal processing. Therefore, building adders, multipliers, and dividers on FPGA can realize the rapid practice of centroid calculation. However, in the general centroid calculation circuit design, the division requires continuous trial division and remainder comparison, which takes a very long time. In large-surface image applications, the shift comparison loop division seems to be inadequate. Summary of the invention

[0004] In order to solve the above technical problems, the present invention provides an image centroid coordinate extraction circuit without a divider, the core of which is based on the idea of ​​numerical approximation, uses a lookup table to read the initial value of the centroid coordinate inexact solution, constructs an iterative loop circuit, and realizes the successive solution of the centroid coordinate exact value through iterative approximation. This circuit expands one of the adders on the basis of the matrix multiplier to support three operations of multiplication, addition and subtraction, thereby allowing a group of circuit modules to perform all operations required for numerical iteration, and completes the centroid coordinate extraction of large bit width images within dozens of clock cycles with less logic resources.

[0005] To achieve the above purpose, the technical solution adopted by the present invention is as follows:

[0006] An image centroid coordinate extraction circuit without a divider includes a table lookup unit based on FPGA, a multiplier composed of N adders cascaded, and a clock design unit; wherein,

[0007] The table lookup unit of the FPGA is used to find the corresponding reciprocal initial value according to the first m bits of the value of the pixel sum of the input image, and the reciprocal initial value enters the multiplier together with the first m bits of the value of the pixel sum through the first algorithm selector to perform a multiplication operation to obtain a first multiplication result; the first multiplication result is fed back to the Nth adder in the multiplier through the second algorithm selector, and a difference calculation operation is performed by inversion to obtain a first subtraction result; the first subtraction result is used as a multiplier through the first algorithm selector and is input into the multiplier again with the first m bits of the pixel sum to perform a secondary multiplication operation to obtain a second multiplication result, that is, a first iteration result;

[0008] Send the first m+1 bits of the pixel sum value and the first iteration result to the multiplier to sequentially perform the multiplication operation, the difference calculation operation, and the secondary multiplication operation, and repeat the cycle until the corresponding iteration of all the bits of the pixel sum is completed;

[0009] The clock design unit is used to control the control pins arranged on the cascade adder, the Nth adder and the shift register to realize timing control.

[0010] Furthermore, the value of the pixel sum of the input image includes M bits, M≥2; the value of the pixel sum is input into a shift register to obtain the first m bits of the value of the pixel sum, m<M.

[0011] Furthermore, the Nth adder is an enhanced adder supporting multiplication and subtraction operations.

[0012] Furthermore, the enhanced adder expands the input channel of the look-ahead adder on the FPGA, allowing the clock signal to control the source of the addend and the augend, so that the look-ahead adder circuit can dynamically switch between addition and subtraction operations.

[0013] Furthermore, the addend input of the enhanced adder is the result of the previous adder or a fixed value 2, and the augend input is the multiplier of the multiplier or the inverse of the multiplier operation result.

[0014] Furthermore, when the addend input is the result of the previous adder, the addend input is the multiplier of the multiplier; when the addend input is a fixed value of 2, the addend input is the inverse of the multiplier operation result.

[0015] Furthermore, the timing design unit performs iterative approximation according to the following formula:

[0016] ,

[0017] Where, X i+1 Represents the result after iteration, X i represents the initial value of the iteration, and b represents the iteration parameter.

[0018] On the other hand, the present invention provides a method for extracting image centroid coordinates without a divider, comprising the following steps:

[0019] The table lookup unit of the FPGA searches for the corresponding reciprocal initial value according to the first m bits of the value of the pixel sum of the input image, and the reciprocal initial value enters the multiplier together with the first m bits of the value of the pixel sum through the first algorithm selector to perform a multiplication operation to obtain a first multiplication result; the first multiplication result is fed back to the Nth adder in the multiplier through the second algorithm selector, and a difference calculation operation is performed by inversion to obtain a first subtraction result; the first subtraction result is used as a multiplier through the first algorithm selector and is input into the multiplier again with the first m bits of the pixel sum to perform a secondary multiplication operation to obtain a second multiplication result, that is, a first iteration result;

[0020] Send the first m+1 bits of the pixel sum value and the first iteration result to the multiplier to sequentially perform the multiplication operation, the difference calculation operation, and the secondary multiplication operation, and repeat the cycle until the corresponding iteration of all the bits of the pixel sum is completed;

[0021] The clock design unit controls the control pins arranged on the cascade adder, the Nth adder and the shift register to realize timing control.

[0022] In a third aspect, the present invention provides an electronic device, comprising: one or more processors; a memory for storing one or more programs; wherein, when the one or more programs are executed by the one or more processors, the one or more processors implement the aforementioned image centroid coordinate extraction method without a divider.

[0023] In a fourth aspect, the present invention provides a computer-readable storage medium having executable instructions stored thereon, which, when executed by a processor, enables the processor to implement the aforementioned method for extracting image centroid coordinates without a divider.

[0024] The beneficial effects of the present invention are:

[0025] The present invention adopts initial value table lookup and numerical approximation, does not involve division operation, and improves the operation speed of the centroid extraction circuit in principle;

[0026] The present invention expands the first-level adder in the matrix multiplier to enable it to perform addition and subtraction operations. By applying time-division multiplexing technology, complete numerical iteration arithmetic operations are implemented on a single multiplier circuit, thereby significantly reducing the overall area of ​​the centroid extraction circuit.

[0027] The present invention utilizes time domain segmentation and timing matching technology and realizes automatic function switching and iterative calculation of an arithmetic unit through a circuit circulation mechanism without the need for an additional control unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 This is a schematic diagram of the principle of an image centroid coordinate extraction circuit without a divider according to the present invention;

[0029] Figure 2 This is a schematic diagram of the structure of an image centroid coordinate extraction circuit without a divider according to the present invention;

[0030] Figure 3 This is the circuit synthesis diagram of 8-bit carry-lookahead adder on FPGA;

[0031] Figure 4 The figure is the device implementation diagram of 8-bit carry-lookahead adder on FPGA;

[0032] Figure 5 Functional diagram of an enhanced adder supporting multiplication and fixed-value subtraction operations;

[0033] Figure 6 A schematic diagram of clock distribution of an image centroid coordinate extraction circuit without a divider according to the present invention;

[0034] Figure 7 It is the timing design for the entire circuit, including the timing relationship between the arithmetic unit, shift register, selector and each trigger. DETAILED DESCRIPTION

[0035] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0036] like Figure 1 As shown, the present invention shows a schematic diagram of the design of an image centroid coordinate extraction circuit without a divider. The design uses a lookup table device in a programmable logic unit to read the inexact solution of the reciprocal value corresponding to the high bit of the pixel value. By enhancing the matrix cascade multiplier circuit and applying the time-sharing multiplexing principle, the inexact solution of the reciprocal value can perform Newton iterative approximation operation on the enhanced multiplier, thereby realizing the successive approximation solution of the exact solution.

[0037] like Figure 2 As shown, the overall architecture of the image centroid coordinate extraction circuit without a divider of the present invention includes three main parts, a table lookup unit of an FPGA, a multiplier composed of N cascaded adders, and a clock design unit including multiple associated clock domains.

[0038] The sum of all pixel values ​​of the input image is obtained as the input of the centroid coordinate extraction circuit of the present invention, which is recorded as pixel sum. It is assumed that the value of the pixel sum includes M bits, M≥2; specifically:

[0039] The value of the pixel sum is input into the shift register to obtain the first m bits of the pixel sum, where m < M;

[0040] The table lookup unit of the FPGA is used to find the corresponding reciprocal initial value according to the first m bits of the pixel sum, and the reciprocal initial value enters the multiplier together with the first m bits of the pixel sum through the first algorithm selector to perform a multiplication operation to obtain a first multiplication result, which is stored in the trigger FF2; the first multiplication result is fed back to the Nth adder in the multiplier through the second algorithm selector, and a difference calculation operation is performed by inversion to obtain a first subtraction result, which is stored in the trigger FF3; the first subtraction result is used as a multiplier through the first algorithm selector and the first m bits of the pixel sum are input into the multiplier again to perform a secondary multiplication operation to obtain a second multiplication result, that is, a first iteration result, which is stored in the trigger FF1;

[0041] Input the value of the pixel sum into the shift register again, obtain the first m+1 bits of the pixel sum, and send the first m+1 bits of the pixel sum and the result of the first iteration into the multiplier to perform a multiplication operation, a difference calculation operation, and a second multiplication operation in sequence, and iterate in a loop until the M-bit iteration of the pixel sum is completed;

[0042] The clock design unit is used to control the control pins and clocks arranged on the cascade adder, the inverter and the shift register to realize automatic timing control.

[0043] like Figure 3 As shown, the cascade adder includes N stages of look-ahead adders, each stage of which is constructed by a look-up table LUT and a carry chain component in a CLB (programmable logic unit). By inputting the addend and the augend into the XOR gate (XOR) synthesized by the look-up table LUT, and using the XOR gate result to control the carry chain selector S, the arithmetic and signal and the carry signal are quickly generated, see Figure 4 .

[0044] like Figure 5 As shown, the Nth-stage adder in the extended multiplier is an enhanced adder. A selector can be added to each pin of the adder input, allowing the selector to dynamically control the source of the addend, the source of the augend, and whether to reverse. Specifically, when the selector control signal is at a high level, the addend and the augend are set to the previous level input and the multiplier input to perform the multiplication operation. Conversely, when the control signal is at a low level, the adder input will be set to the fixed value '2' and the inverse of the result of the previous multiplication operation to complete the difference operation of 2 and the product. Through this setting, using a time-sharing multiplexing strategy, this circuit can be allowed to perform multiplication or fixed number subtraction at different time points to achieve the arithmetic functions required for centroid iteration.

[0045] In the time domain, Figure 6, by designing five clock domains and accurately controlling the timing between them, seamless integration of multiplication operation, difference calculation operation, and secondary multiplication operation can be achieved. Specifically, when the CLK_02 signal is pulled high, the multiplexer (MUX) will be placed in the multiplication calculation mode, and the CLK_03 signal will activate the trigger FF2 to capture and hold the intermediate result of the multiplication operation, that is, the first multiplication result mentioned above. Next, the CLK_02 signal is pulled low, switching the MUX to the subtraction operation mode, so that the previous operation result stored in FF2 can be used to perform the subtraction operation. After the operation is completed, the CLK_04 signal will trigger FF3 to latch the subtraction operation result, that is, the first subtraction result mentioned above. Subsequently, the rising edge of CLK_02 switches the multiplexer (MUX) back to the multiplier mode again. In this stage, the rising edge of CLK_05 first switches the multiplier input of the multiplier to FF3, and the falling edge switches the multiplier input of the multiplier back to FF1 and triggers FF1 for acquisition, that is, the second multiplication result mentioned above.

[0046] The above steps can be summarized as the iterative process shown in Table 1, which is represented by formula (1), and it is preferred that the pixel value is moved to 2k-bit precision in each iteration.

[0047] Table 1

[0048] (1)

[0049] Here, X i+1 Represents the result after iteration, X i represents the initial value of the iteration, b represents the iteration parameter (this parameter is shifted to 2k bits of precision by the shift register in each iteration, and k represents the number of iterations to match the iteration precision increment). In this way, the circuit can accurately perform the calculation iteration process required for the Newton-Raphson rational number approximation.

[0050] Figure 7 The relevant timing is fully displayed in the form of a tiled diagram. It can be seen that the operation mode, shift register and MUX_2 of this circuit are switched at the same frequency, while FF1, FF2 and FF3 are driven by different clocks to capture the operation results generated in different operation modes.

[0051] In summary, the present invention successfully constructs an arithmetic circuit capable of performing multiplication and subtraction operations on the FPGA platform by using existing circuit components and time-division multiplexing technology. Subsequently, by decomposing the centroid calculation process into two stages: initial value table lookup and successive approximation circuit, the clock domain decomposition technology is used to realize the single circuit modularization of numerical iterative calculation.

[0052] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. An image centroid coordinate extraction circuit without a divider, characterized in that: It includes a table lookup unit based on FPGA, a multiplier composed of N adders cascaded, and a clock design unit; wherein, The table lookup unit of the FPGA is used to find the corresponding reciprocal initial value according to the first m bits of the value of the pixel sum of the input image, and the reciprocal initial value enters the multiplier together with the first m bits of the value of the pixel sum through the first algorithm selector to perform a multiplication operation to obtain a first multiplication result; the first multiplication result is fed back to the Nth adder in the multiplier through the second algorithm selector, and a difference calculation operation is performed by inversion to obtain a first subtraction result; the first subtraction result is used as a multiplier through the first algorithm selector and is input into the multiplier again with the first m bits of the pixel sum to perform a secondary multiplication operation to obtain a second multiplication result, that is, a first iteration result; Send the first m+1 bits of the pixel sum value and the first iteration result to the multiplier to sequentially perform the multiplication operation, the difference calculation operation, and the secondary multiplication operation, and iterate in a loop until the corresponding iteration of all the bits of the pixel sum is completed; The clock design unit is used to control the control pins arranged on the cascade adder, the Nth adder and the shift register to realize timing control.

2. The image centroid coordinate extraction circuit without a divider according to claim 1, characterized in that: The pixel sum value of the input image includes M bits, M≥2; the pixel sum value is input into the shift register to obtain the first m bits of the pixel sum value, m<M.

3. The image centroid coordinate extraction circuit without a divider according to claim 1, characterized in that: The Nth adder is an enhanced adder supporting multiplication and subtraction operations.

4. The image centroid coordinate extraction circuit without a divider according to claim 3, characterized in that: The enhanced adder is an expansion of the input channel of the look-ahead adder on the FPGA, allowing the clock signal to control the sources of addends and augends, so that the look-ahead adder circuit can dynamically switch between addition and subtraction operations.

5. The image centroid coordinate extraction circuit without a divider according to claim 4, characterized in that: The addend input of the enhanced adder is the result of the previous adder or a fixed value 2, and the augend input is the multiplier of the multiplier or the inverse of the multiplier operation result.

6. The image centroid coordinate extraction circuit without a divider according to claim 5, characterized in that: When the addend input is the result of the previous adder, the augend input is the multiplier of the multiplier; when the addend input is a fixed value of 2, the augend input is the inverse of the multiplier operation result.

7. The image centroid coordinate extraction circuit without a divider according to claim 6, characterized in that: The timing design unit performs iterative approximation according to the following formula: （1） Where, X i+1 Represents the result after iteration, X i represents the iteration initial value, and b represents the iteration parameter.

8. A method for extracting image centroid coordinates without a divider, characterized in that: The steps include: The table lookup unit of the FPGA searches for the corresponding reciprocal initial value according to the first m bits of the value of the pixel sum of the input image, and the reciprocal initial value enters the multiplier together with the first m bits of the value of the pixel sum through the first algorithm selector to perform a multiplication operation to obtain a first multiplication result; the first multiplication result is fed back to the Nth adder in the multiplier through the second algorithm selector, and a difference calculation operation is performed by inversion to obtain a first subtraction result; the first subtraction result is used as a multiplier through the first algorithm selector and is input into the multiplier again with the first m bits of the pixel sum to perform a secondary multiplication operation to obtain a second multiplication result, that is, a first iteration result; Send the first m+1 bits of the pixel sum value and the first iteration result to the multiplier to sequentially perform the multiplication operation, the difference calculation operation, and the secondary multiplication operation, and iterate in a loop until the corresponding iteration of all the bits of the pixel sum is completed; The clock design unit controls the control pins arranged on the cascade adder, the Nth adder and the shift register to realize timing control.

9. An electronic device, characterized in that: include: one or more processors; A memory for storing one or more programs; When one or more programs are executed by the one or more processors, the one or more processors implement the method for extracting image centroid coordinates without a divider as described in claim 8.

10. A computer-readable storage medium, characterized in that: Executable instructions are stored thereon, and when the instructions are executed by the processor, the processor can implement the image centroid coordinate extraction method without a divider as described in claim 8.

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