High-speed low-noise pixel A / D conversion circuit

Abstract

The invention relates to the technical field of semiconductor image sensing, in particular to a high-speed low-noise pixel A / D (analog / digital) conversion circuit, which optimally designs a pixel signal sampling readout circuit capable of obtaining a low-noise pixel voltage signal through a single-slope pixel signal sampling readout mode based on a traditional active reset pixel structure. Two input end circuits of a comparator of the pixel signal sampling readout circuit are connected in parallel to design a change-over switch, deviation voltage generated by the comparator is stored to a coupling capacitor connected with the comparator in series through switching on and switching off of the change-over switch, and the influence of noise on a readout signal is restrained. The problem that a traditional double-slope type pixel voltage signal sampling readout scheme needs two-time slope signals to eliminate the deviation voltage of the comparator is solved, and compared with a traditional scheme, under the condition that the noise reduction effect is the same, the signal sampling readout time is greatly shortened, and the overall readout speed of the circuit can be improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor image sensing, and in particular relates to a high-speed and low-noise pixel A / D conversion circuit. Background Art

[0002] CMOS image sensors are currently widely used in scientific and civilian fields due to their low power consumption, low cost and high integration capabilities. In the pixel signal readout circuit structure of the CMOS image sensor, there are two parts of circuits that work together to realize the pixel signal readout function. The first part is the pixel signal output circuit, and the second part is the circuit for sampling and reading the pixel signal.

[0003] For CMOS image sensors, the active reset pixel signal output circuit is a commonly used circuit, which achieves effective control of pixel signals and noise reduction by precisely controlling the reset transistor and signal amplifier, thereby improving the performance of the image sensor. Figure 1 As shown, for the active reset pixel signal output circuit, its working process is as follows: before the exposure starts, the photodiode PD is reset by the global reset switch GRST, and the pixel signal exposure starts. Then the row selection switch SEL is closed, the reset switch RST and the negative feedback switch VFB are closed, so that the source follower SF, the row selection switch SEL, the amplifier, the reset switch RST and the negative feedback switch VFB form a negative feedback loop, and the negative feedback loop is used to reset the capacitor C1. Then the reset switch RST and the negative feedback switch VFB are disconnected in sequence, so that the reset noise is gradually reduced under the action of the negative feedback loop, and the reset voltage at C1 is sampled and read out at the same time; the transfer control gate switch TX is closed, and all the charges accumulated after the photodiode is exposed are transferred and stored in C1 at one time. Finally, the row selection switch SEL and the negative feedback switch VFB are closed, and the pixel signal voltage stored in the capacitor C1 is sampled and read out after passing through the source follower SF and the row selection switch SEL.

[0004] Based on the active reset pixel structure, the design is further optimized as follows Figure 2 Compared with the active reset pixel signal output circuit, the dual slope pixel signal readout circuit structure shown in the figure adds a comparator initialization switch Tinit, a pixel signal bus control switch Tbus and a coupling capacitor C2. The circuit structure has a complete pixel signal readout function. Figure 3As shown, the dual-slope pixel signal readout circuit structure has the following working process: the pixel signal is transmitted to the sampling readout circuit; the comparator initialization switch Tinit is closed, and is disconnected after the initialization operation is completed; the first ramp signal is input to the sampling input end of the comparator, and the input pixel voltage signal is sampled and read out; the control pixel signal bus switch Tbus is closed, and the output voltage signal is transmitted to the feedback circuit; the reset switch RST is closed to perform the reset operation, and the negative feedback switch VFB is closed; after the reset operation is completed, the reset switch RST and the negative feedback switch VFB are disconnected, and the reset voltage signal is transmitted to the sampling readout circuit; the control pixel signal bus switch Tbus is disconnected, and the second ramp signal is input to the comparator sampling end, and the input reset voltage signal is output; the row selection switch SEL is disconnected to complete the single sampling and reading operation of the pixel signal. Figure 3 Tramp is the ramp signal, and the two ramps are Sample signal and Sample reset, which represent the rising and falling process of the signal.

[0005] Although the above-mentioned dual-slope pixel signal readout circuit can effectively eliminate the offset voltage generated by the comparator by using two ramp signals and reduce the frequency limitation, the use of two ramp signals for sampling and reading will increase the overall circuit readout noise level and increase the single pixel voltage signal sampling and reading time, which is not conducive to improving the overall circuit readout speed. Summary of the invention

[0006] In view of this, the present invention aims to provide a high-speed, low-noise pixel A / D conversion circuit, which optimizes and improves the traditional active reset pixel structure, and samples and reads the pixel signal through a single slope voltage signal, thereby eliminating the offset voltage in the circuit, and also reducing the noise level of the pixel voltage signal readout circuit, and shortening the single pixel voltage signal readout time, thereby improving the overall circuit readout speed.

[0007] To achieve the above object, the technical solution created by the present invention is implemented as follows: The invention provides a high-speed low-noise pixel A / D conversion circuit, including: an active reset pixel structure and a pixel signal sampling and reading circuit, the pixel signal sampling and reading circuit including: a comparator, a pixel signal transmission switch, a switching switch, a pixel signal bus control switch and a first coupling capacitor; Among them, the first pole of the pixel signal transmission switch is coupled to the active reset pixel structure, the second pole of the pixel signal transmission switch is coupled to one end of the first coupling capacitor, the other end of the first coupling capacitor is coupled to the first input end of the comparator, the first pole of the switching switch is coupled to the second input end of the comparator, and the second pole of the switching switch is connected between the pixel signal transmission switch and the first coupling capacitor; the first pole of the control pixel signal bus switch is coupled to the output end of the comparator, and the second pole of the control pixel signal bus switch is coupled to the active reset pixel structure.

[0008] Preferably, the pixel signal sampling and reading circuit further includes: a comparator initialization switch, a first pole of the comparator initialization switch is coupled to the first input terminal of the comparator, and a second pole of the comparator initialization switch is coupled to the output terminal of the comparator.

[0009] Preferably, the pixel signal sampling and reading circuit further includes: a bias voltage control switch, a first pole of the bias voltage control switch is grounded, and a second pole of the bias voltage control switch is coupled to the pixel signal transmission switch.

[0010] Preferably, the pixel signal sampling and reading circuit further includes: an analog-to-digital converter coupled between the comparator and the control pixel signal bus switch.

[0011] Preferably, the active reset pixel structure includes: a global reset switch, a reset switch, a transfer control gate, a photodiode, a source follower, a row selection switch, a negative feedback switch, a storage transfer photocharge capacitor, a second coupling capacitor and a sampling capacitor, wherein the first electrode of the global reset switch is coupled to the power supply, the second electrode of the global reset switch is coupled to the first electrode of the transfer control gate, the photodiode is coupled between the global reset switch and the transfer control gate, the second electrode of the transfer control gate is coupled to the gate of the source follower, the drain of the source follower is coupled to the source follower power supply terminal, the source of the source follower is coupled to the first electrode of the row selection switch, and the second electrode of the row selection switch is coupled to the first electrode of the pixel signal transmission switch; the storage transfer photocharge capacitor is coupled between the transfer control gate and the source follower; the first electrode of the reset switch is coupled between the transfer control gate and the source follower, the second electrode of the reset switch is coupled to the first electrode of the negative feedback switch, the second electrode of the negative feedback switch is coupled to the second electrode of the control pixel signal bus switch, the second coupling capacitor is connected in parallel to both ends of the reset switch, one end of the sampling capacitor is coupled between the reset switch and the negative feedback switch, and the other end of the sampling capacitor is grounded.

[0012] Preferably, the deviation voltage generated by the comparator is stored in the first coupling capacitor by closing the switching switch, and the switching switch is opened after the deviation voltage on the comparator is eliminated.

[0013] Preferably, the working state of the switching switch is opposite to the working state of the switch for transmitting the pixel signal.

[0014] Preferably, a single slope pixel signal sampling and reading method is used to collect pixel voltage signals.

[0015] Compared with the prior art, the invention can achieve the following beneficial effects:

[0016] The present invention designs a switching switch at the two input ends of the comparator, controls the closing and opening of the comparator, and stores the offset voltage generated by the comparator on the coupling capacitor C2. The single slope signal sampling and reading method can achieve the same effect of eliminating the comparator offset voltage as the dual slope pixel signal sampling and reading circuit, effectively reducing the noise level in the sampling and reading process, as well as the low-frequency noise level of the source follower SF in the active reset pixel circuit structure. In addition, the single slope sampling shortens the time used for pixel signal reading and improves the pixel signal reading speed.

[0017] The present invention is not only applicable to single-slope sampling and reading, but also compatible with two working modes of dual-slope sampling and reading, and has high flexibility and applicability.

[0018] The comparator in the present invention serves as an amplifier of the feedback loop in the active reset pixel structure and also as a pixel signal sampling and reading circuit, thereby simplifying the circuit structure while ensuring the integrity of the circuit function.

[0019] The present invention can complete the double reset operation of the active reset pixel structure and the comparator within a single pixel signal sampling and reading cycle by controlling the reset switch RST and the comparator initialization switch Tinit timing, thereby effectively improving the circuit working speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The drawings constituting part of the present invention are used to provide a further understanding of the present invention. The exemplary embodiments and descriptions of the present invention are used to explain the present invention and do not constitute an improper limitation on the present invention. In the drawings: Figure 1 It is a structural diagram of an active reset pixel circuit in the background technology; Figure 2 It is a structural diagram of a dual slope pixel signal readout circuit in the background technology; Figure 3 It is a working timing diagram of a dual slope pixel signal readout circuit in the background technology; Figure 4 is a structural diagram of a high-speed and low-noise pixel A / D conversion circuit provided according to an embodiment of the present invention; Figure 5 1 is a working timing diagram of a single slope pixel signal sampling and reading circuit provided according to an embodiment of the present invention. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical scheme and advantages of the invention clearer, the invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the invention and do not constitute a limitation to the invention. Similar components in different embodiments use associated similar component numbers. In the following embodiments, many detailed descriptions are to enable the invention to be better understood. However, those skilled in the art can easily recognize that some of the features can be omitted in different situations, or can be replaced by other components, materials, and methods. In some cases, some operations related to the invention are not shown or described in the specification, in order to avoid the core part of the invention being overwhelmed by too much description, and for those skilled in the art, it is not necessary to describe these related operations in detail, and they can fully understand the related operations according to the description in the specification and the general technical knowledge in the art.

[0022] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other to form various implementation methods. At the same time, the steps or actions in the method description can also be interchanged or adjusted in a manner that is obvious to those skilled in the art. Therefore, the various sequences in the specification and the drawings are only for the purpose of clearly describing a certain embodiment and are not meant to be a necessary sequence, unless otherwise specified that a certain sequence must be followed.

[0023] In the description of the invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the invention. In addition, the terms "first", "second", etc. are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first", "second", etc. may explicitly or implicitly include one or more of the features. In the description of the invention, unless otherwise specified, the meaning of "multiple" is two or more.

[0024] In the description of the invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the invention can be understood according to specific circumstances.

[0025] The present invention will be described in detail below with reference to the accompanying drawings and in combination with embodiments.

[0026] In order to solve the problem that the conventional CMOS image sensor pixel signal readout circuit structure requires a dual slope pixel voltage signal sampling and reading method to effectively suppress noise. In one embodiment of the present invention, refer to Figure 4 A high-speed low-noise pixel A / D conversion circuit is proposed, by coupling a transistor switch Tvtb, i.e., a switching switch, to the two input ends of the comparator. By controlling the closing and opening of the transistor switch Tvtb, the offset voltage generated by the comparator is transferred to eliminate the sampling readout noise. Specifically, the high-speed low-noise pixel A / D conversion circuit includes two circuit parts, i.e., an active reset pixel structure and a pixel signal sampling readout circuit.

[0027] The active reset pixel structure is an existing pixel structure, including a global reset switch GRST, a reset switch RST, a transfer control gate TX, a photodiode PD, a source follower SF, a row selection switch SEL, a negative feedback switch VFB, a storage transfer photocharge capacitor C1, a coupling capacitor Cc (i.e., a second coupling capacitor) and a sampling capacitor Cs. Among them, the global reset switch GRST is a key control switch, which is used to synchronously reset the photodiodes PD of all pixels before the exposure starts. The photodiode PD is an exposure function device, which is used to convert the light signal into charge. The first electrode of the global reset switch GRST is coupled to the power supply VDD. The second electrode of the global reset switch GRST is coupled to the first electrode of the transfer control gate TX. The transfer control gate TX is used to control the transfer of charge from the photodiode PD to the storage transfer photocharge capacitor C1. The storage transfer photocharge capacitor C1 is coupled between the transfer control gate TX and the source follower SF. When the transfer control gate TX is activated, it allows the charge on the photodiode PD to be transferred to the storage transfer photocharge capacitor C1. The photodiode PD is coupled between the global reset switch GRST and the transfer control gate TX, and is responsible for converting the light signal into charge. The second electrode of the transfer control gate TX is coupled to the gate of the source follower SF, the drain of the source follower SF is coupled to the source follower power supply terminal VDDPIX, and the source of the source follower SF is coupled to the first electrode of the row selection switch SEL. The function of the source follower SF is to transfer the voltage signal stored on the storage transfer photocharge capacitor C1 to the output while maintaining a low output impedance. The second electrode of the row selection switch SEL is coupled to the first electrode of the transfer pixel signal switch Tvtb_n in the pixel signal sampling readout circuit. The reset switch RST is used to reset the storage transfer photocharge capacitor C1 after the exposure is completed. The first electrode of the reset switch RST is coupled between the transfer control gate TX and the source follower SF, and the second electrode of the reset switch RST is coupled to the first electrode of the negative feedback switch VFB. The second pole of the negative feedback switch VFB is coupled to the second pole of the control pixel signal bus switch Tbus in the pixel signal sampling readout circuit. The negative feedback switch VFB is used to control the formation of a negative feedback loop, which is formed by connecting the source follower SF, the row selection switch SEL, the comparator in the pixel signal sampling readout circuit, the reset switch RST and the negative feedback switch VFB to form a negative feedback loop to improve the stability and accuracy of the circuit. It should be noted that the role of the comparator in the negative feedback loop is an amplifier. The two ends of the reset switch RST are also connected in parallel with a coupling capacitor Cc, which is used to keep the voltage on the storage transfer photocharge capacitor C1 stable after the reset switch RST is disconnected to prevent charge leakage. One end of the sampling capacitor Cs is coupled between the reset switch RST and the negative feedback switch VFB, and the other end of the sampling capacitor Cs is grounded. The sampling capacitor Cs is used to sample and process the signal. The working principle and process of the active reset pixel structure are consistent with the description in the background technology, and will not be repeated here.

[0028] The pixel signal sampling and reading circuit includes a comparator, a pixel signal transmission switch Tvtb_n, a switching switch Tvtb, a comparator initialization switch Tinit, a pixel signal bus control switch Tbus, a bias voltage control switch VBIASN and a coupling capacitor C2 (i.e., a first coupling capacitor). The pixel signal transmission switch Tvtb_n is used to control the pixel voltage signal to be input into the pixel signal sampling and reading circuit by the active reset pixel structure, thereby realizing signal reading. The first pole of the pixel signal transmission switch Tvtb_n is coupled to the second pole of the row selection switch SEL in the active reset pixel structure, and the second pole of the pixel signal transmission switch Tvtb_n is coupled to one end of the coupling capacitor C2. The coupling capacitor C2 is used to store and transmit voltage signals. In the initialization stage, the coupling capacitor C2 stores the bias voltage of the comparator; in the sampling stage, the coupling capacitor C2 transmits the pixel voltage signal to the comparator and isolates the DC bias voltage at the same time to ensure that the comparator is only sensitive to changes in the pixel voltage signal. The other end of the coupling capacitor C2 is coupled to the first input end of the comparator. The comparator is a core component in the circuit and is used to compare the size of two voltage signals. During the A / D conversion process, it compares the input pixel voltage signal with the ramp voltage signal. When the ramp voltage signal reaches or exceeds the pixel voltage signal, the comparator changes its output state to trigger the ADC conversion process. The second input terminal of the comparator is coupled to the ramp test voltage Vramp. In an embodiment of the present invention, a single-slope pixel signal sampling and reading method is used to collect the pixel voltage signal, that is, only a single-slope Sample signal is generated to read the signal. In the traditional CMOS signal sampling and reading circuit, the single-slope pixel signal sampling and reading method cannot effectively eliminate the offset voltage generated by the comparator, which will cause the final read signal to have a large noise. Therefore, only a double-slope pixel signal reading method can be used. Although this can effectively eliminate the offset voltage generated by the comparator by using two ramp signals, the use of two ramp signals for sampling and reading will increase the overall circuit readout noise size and reduce the overall circuit readout speed. Therefore, in an embodiment of the present invention, a switching switch Tvtb is designed at the two input terminals of the comparator. The design of the switching switch Tvtb is convenient for storing and eliminating the offset voltage of the comparator. The first pole of the switching switch Tvtb is coupled to the second input terminal of the comparator, and the second pole of the switching switch Tvtb is connected between the pixel signal transmission switch Tvtb_n and the coupling capacitor C2. In the initialization stage, by closing the switching switch Tvtb, the deviation voltage of the comparator can be stored on the coupling capacitor C2 to eliminate the deviation; in the sampling stage, the switching switch Tvtb is opened to allow the pixel signal to pass. The output end of the comparator is coupled to the first pole of the control pixel signal bus switch Tbus, and the second pole of the control pixel signal bus switch Tbus is coupled to the negative feedback switch VFB in the active reset pixel structure to form a feedback circuit.The pixel signal bus switch Tbus is used to control the signal transmission on the pixel signal bus. When the pixel signal bus switch Tbus is closed, the pixel signal is allowed to be transmitted through the bus; when the pixel signal bus switch Tbus is disconnected, the signal transmission is cut off. In addition, the input and output ends of the comparator are coupled with an initialization switch Tinit, the first pole of the comparator initialization switch Tinit is coupled to the first input end of the comparator, the second pole of the comparator initialization switch Tinit is coupled to the output end of the comparator, and the comparator initialization switch Tinit is coupled. Used to initialize the comparator to ensure that the comparator starts working from a known state. When the circuit starts or the comparator state needs to be reset, close the comparator initialization switch Tinit to short-circuit the input of the comparator, and disconnect it after initialization is completed.

[0029] The first electrode of the pixel signal transmission switch Tvtb_n is also coupled to the second electrode of the bias voltage control switch VBIASN, and the first electrode of the bias voltage control switch VBIASN is grounded. The bias voltage control switch VBIASN is used to control the bias voltage and provide a stable operating voltage for the circuit. When VBIASN is closed, the bias voltage is provided for the circuit; when it is open, the bias voltage is cut off.

[0030] An analog-to-digital converter (ADC) is also provided between the comparator and the pixel signal bus switch Tbus. The analog-to-digital converter is used to perform digital-to-analog conversion and determine the digital value of the pixel signal through the output signal of the comparator.

[0031] The working process of the pixel signal sampling and reading circuit and the specific working timing of each transistor switch can be found in Figure 5 Specifically, first, the switch Tvtb connected to the two input ends of the comparator is closed, and the offset voltage generated by the comparator is stored in the coupling capacitor C2. After the offset voltage of the comparator is eliminated, the switch Tvtb is disconnected. In this process, the pixel signal transfer switch Tvtb_n and the switch Tvtb are controlled to always maintain opposite working states. When the switch Tvtb is in a closed state, the pixel signal transfer switch Tvtb_n is in an open state. When the pixel signal transfer switch Tvtb_n is closed, the pixel voltage signal output by the active reset pixel structure can be input into the pixel signal sampling and reading circuit.

[0032] The comparator initialization switch Tinit is closed to perform the initialization operation, and the comparator initialization switch Tinit is opened after the initialization operation is completed.

[0033] A single ramp voltage signal Sample signal is input to the sampling input terminal of the comparator, and the input pixel voltage signal is sampled, read out, and then outputted. The output voltage signal is transmitted to the analog-to-digital converter for further reading operation.

[0034] The pixel signal bus switch Tbus is closed to transmit the output pixel voltage signal to the feedback loop, that is, the negative feedback loop formed by the source follower SF, the row selection switch SEL, the comparator (acting as an amplifier), the reset switch RST and the negative feedback switch VFB.

[0035] Close the reset switch RST to perform the reset operation and close the negative feedback switch VFB; after the reset operation is completed, disconnect the reset switch RST and the negative feedback switch VFB to transmit the reset voltage signal value to the sampling readout circuit. Disconnect the control pixel signal bus switch Tbus and the row selection switch SEL to complete the single sampling readout operation of the pixel voltage signal.

[0036] As a feasible embodiment, the high-speed low-noise pixel A / D conversion circuit of the embodiment of the present invention is also suitable for collecting pixel voltage signals in a dual-slope pixel signal sampling and reading manner. In short, the above are only preferred embodiments of this specification and are not intended to limit the protection scope of this specification. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of this specification should be included in the protection scope of this specification.

[0037] The systems, devices, modules or units described in one or more of the above embodiments may be implemented by a computer chip or entity, or by a product having a certain function. A typical implementation device is a computer. Specifically, the computer may be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

[0038] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0039] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0040] The above is a description of a specific embodiment of the specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the embodiments and still achieve the desired results. In addition, the processes depicted in the drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

Claims

1. A high-speed low-noise pixel A / D conversion circuit, comprising: An active reset pixel structure and a pixel signal sampling and reading circuit, characterized in that the pixel signal sampling and reading circuit comprises: a comparator, a pixel signal transmission switch, a switching switch, a pixel signal bus control switch and a first coupling capacitor; Among them, the first pole of the pixel signal transmission switch is coupled to the active reset pixel structure, the second pole of the pixel signal transmission switch is coupled to one end of the first coupling capacitor, the other end of the first coupling capacitor is coupled to the first input end of the comparator, the first pole of the switching switch is coupled to the second input end of the comparator, and the second pole of the switching switch is connected between the pixel signal transmission switch and the first coupling capacitor; the first pole of the control pixel signal bus switch is coupled to the output end of the comparator, and the second pole of the control pixel signal bus switch is coupled to the active reset pixel structure.

2. The high-speed low-noise pixel A / D conversion circuit according to claim 1, characterized in that: The pixel signal sampling and reading circuit further includes: a comparator initialization switch, a first electrode of the comparator initialization switch is coupled to the first input terminal of the comparator, and a second electrode of the comparator initialization switch is coupled to the output terminal of the comparator.

3. The high-speed low-noise pixel A / D conversion circuit according to claim 1, characterized in that: The pixel signal sampling and reading circuit further includes: a bias voltage control switch, a first electrode of the bias voltage control switch is grounded, and a second electrode of the bias voltage control switch is coupled to the pixel signal transmission switch.

4. The high-speed low-noise pixel A / D conversion circuit according to claim 1, characterized in that: The pixel signal sampling and reading circuit further includes: an analog-to-digital converter coupled between the comparator and the control pixel signal bus switch.

5. The high-speed low-noise pixel A / D conversion circuit according to claim 1, characterized in that: The active reset pixel structure includes: a global reset switch, a reset switch, a transfer control gate, a photodiode, a source follower, a row selection switch, a negative feedback switch, a storage transfer photocharge capacitor, a second coupling capacitor and a sampling capacitor, wherein a first electrode of the global reset switch is coupled to a power supply, a second electrode of the global reset switch is coupled to a first electrode of the transfer control gate, the photodiode is coupled between the global reset switch and the transfer control gate, a second electrode of the transfer control gate is coupled to a gate of the source follower, a drain of the source follower is coupled to a power supply terminal of the source follower, a source of the source follower is coupled to a first electrode of the row selection switch, and a second electrode of the row selection switch is coupled to a first electrode of a switch for transmitting pixel signals; the storage transfer photocharge capacitor is coupled between the transfer control gate and the source follower; a first electrode of the reset switch is coupled between the transfer control gate and the source follower, a second electrode of the reset switch is coupled to a first electrode of the negative feedback switch, a second electrode of the negative feedback switch is coupled to a second electrode of a switch for controlling a pixel signal bus, a second coupling capacitor is connected in parallel to two ends of the reset switch, one end of the sampling capacitor is coupled between the reset switch and the negative feedback switch, and the other end of the sampling capacitor is grounded.

6. The high-speed low-noise pixel A / D conversion circuit according to claim 1, characterized in that: The deviation voltage generated by the comparator is stored in the first coupling capacitor by closing the switching switch, and the switching switch is opened after the deviation voltage on the comparator is eliminated.

7. The high-speed low-noise pixel A / D conversion circuit according to claim 6, characterized in that: The working state of the switching switch is opposite to the working state of the switch transmitting the pixel signal.

8. The high-speed low-noise pixel A / D conversion circuit according to claim 7, characterized in that: The pixel voltage signal is collected by adopting a single slope pixel signal sampling and reading method.

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