SRAM layout with small area and efficient aspect ratio

Abstract

Embodiments disclose SRAM layouts with small area and high efficiency aspect ratios. A memory cell includes a set of active regions that overlap a set of gate regions to form pairs of cross-coupled inverters. The first active region extends along a first axis. The first gate region extends transversely to and overlaps the first active region to form a first transistor of the pair of cross-coupled inverters. The second gate region extends transversely to and overlaps the first active region to form a second transistor of the pair of cross-coupled inverters. The second active region extends along a second axis and overlaps the first gate region to form a third transistor of the pair of cross-coupled inverters. The fourth active region extends along the third axis and overlaps the gate region to form a transistor of the read port.

Description

[0001] Divisional Application Instructions

[0002] This application is a divisional application of the Chinese patent application filed on December 18, 2020, with application number 202011501881.7 and invention name “SRAM layout with small area and efficient aspect ratio”. Technical Field

[0003] The present disclosure relates to the field of computer memory, and more particularly to static random access memory (SRAM) cell architecture. Background Art

[0004] Traditional static random access memory (SRAM) is implemented in many computing environments due to its performance, ease of interfacing, simplicity, relatively low standby power consumption, and robustness. However, a significant drawback is the area occupied by traditional SRAM layout topologies. The size of this traditional SRAM layout can be a significant inhibitor for applications where space is a concern. Summary of the Invention

[0005] Briefly, the present disclosure includes embodiments relating to a memory cell architecture and memory cell array having reduced area and improved performance characteristics. A memory cell according to the present disclosure includes a plurality of gate regions arranged at a spacing extending transversely to a first axis of the memory cell. A first active region extends along the first axis and overlaps the first gate region at a first spacing, and a second gate region extends along a second spacing to form a first transistor and a second transistor of a pair of cross-coupled inverters of the memory cell. A second active region extends along a second axis parallel to the first axis and is spaced apart from the first active region. The second active region overlaps the first gate region to form a third transistor of the cross-coupled inverter pair.

[0006] The memory cell may include a third active region extending along a third axis parallel to the first axis and spaced apart from the first active region on a side of the first active region opposite the second active region. The third active region covers the second gate region to form a fourth transistor of the pair of cross-coupled inverters. Thus, three active regions are used instead of four (see Figure 1 ) forms a cross-coupled inverter pair, thereby reducing the area occupied by the memory cell.

[0007] In some embodiments, the second active region may overlap with the second gate region to form a fourth transistor of the cross-coupled inverter pair. In such an embodiment, two active regions are thus used instead of four (see FIG. Figure 1 ) cross-coupled inverters, thereby reducing the area occupied by the memory cell.

[0008] The first active region may extend through the upper and lower edges of the memory cell and extend into the adjacent memory cell. The continuously extended first active region may reduce the performance impact caused by the shallow trench isolation characteristic.

[0009] A memory cell array can be formed according to the memory cell architecture discussed herein, wherein an active region—a first active region—extends through memory cells arranged along a first axis. Adjacent memory cells along the first axis can be mirror images of each other with respect to edges between adjacent memory cells. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a layout diagram of memory cells of a memory cell array;

[0011] Figure 2 is a diagram of a static random access memory (SRAM) cell according to one or more embodiments;

[0012] Figure 3 is a first layout diagram of a first SRAM cell according to one or more embodiments;

[0013] Figure 4 yes Figure 3 a second layout diagram of the first SRAM cell;

[0014] Figure 5 yes Figure 3 A schematic circuit diagram of a first SRAM cell;

[0015] Figure 6 is a first layout of a second SRAM cell according to one or more embodiments;

[0016] Figure 7 yes Figure 6 a second layout of a second SRAM cell;

[0017] Figure 8 is a schematic diagram of the second SRAM cell;

[0018] Figure 9 is a layout diagram of a third SRAM cell according to one or more embodiments; and

[0019] Figure 10 is a layout diagram of a fourth SRAM cell according to one or more embodiments. DETAILED DESCRIPTION

[0020] The technology disclosed herein relates to the layout of SRAM cells and SRAM cell arrays and their interconnections, with reduced size and improved shallow trench isolation characteristics relative to alternative layouts. The following description, together with the accompanying drawings, sets forth certain specific details in order to provide a thorough understanding of the various disclosed embodiments. However, those skilled in the relevant art will recognize that the disclosed embodiments can be practiced in various combinations without requiring one or more of these specific details, or using other methods, components, devices, materials, etc. In other instances, well-known structures or components associated with the environment of the present disclosure are not shown or described to avoid unnecessarily obscuring the description of the embodiments.

[0021] Throughout the specification, claims, and drawings, the following terms have the meanings explicitly associated herein unless the context clearly dictates otherwise. The term "herein" refers to the specification, claims, and drawings associated with the present application. The phrases "in one embodiment," "in another embodiment," "in various embodiments," "in some embodiments," "in other embodiments," and other variations thereof refer to one or more features, structures, functions, limitations, or characteristics of the present disclosure, and are not limited to the same or different embodiments, unless the context clearly dictates otherwise. As used herein, the term "or" is an inclusive "or" operator and is equivalent to the phrases "A or B, or both" or "A or B or C, or any combination thereof," and lists with additional elements are treated similarly. The term "based on" is not exclusive and allows for being based on additional features, functions, aspects, or limitations that are not described, unless the context clearly dictates otherwise. In addition, throughout the specification, the meanings of "a," "an," and "the" include both singular and plural references.

[0022] Unless otherwise indicated or contradicted by context, references to the term "set" (eg, "a set of items") used herein are to be interpreted as comprising a non-empty set of one or more members or instances.

[0023] As used herein, the term "overlay" refers to an arrangement of at least a first member and a second member in which an axis intersects a portion of the first member and a portion of the second member. The overlapping portion of the first member and the portion of the second member can be spaced apart from each other along the axis. For example, the first member and the second member can be considered overlapping without being in contact.

[0024] As used herein, the term "active region" refers to a continuous region formed of p-type and n-type semiconductor materials having a structure that depends on the desired operation of the memory cell. The active region may form one or more PN junctions, such as an N-type channel formed on a P-type substrate or a P-type channel formed on an N-type substrate. Non-limiting examples of semiconductor materials used in the active region include gallium arsenide (GaAs), gallium nitride (GaN), gallium aluminum nitride (AlGaN), and indium phosphide (InP).

[0025] The term "gate region" as used herein refers to a continuous region formed of silicon material or polysilicon material, which may include a combination of polysilicon and other silicon materials, such as silicide (eg, cobalt silicide, tantalum silicide, tungsten silicide).

[0026] As used herein, the term "pitch" refers to a row or line along which multiple regions (e.g., gate regions) are arranged. The multiple regions can initially be formed as a single region extending along the pitch. The single region can then be divided into multiple regions spaced apart from each other along the pitch by removing portions of the single region.

[0027] Figure 1 A diagram of a layout 100 for at least a portion of an SRAM cell is shown. Layout 100 includes a six-transistor (6T) write port implemented across two polysilicon pitches. The 6T write port is formed in SRAM cell 101 and includes a first pair of laterally extended gate regions 102 and 104. Gate region 102 is formed on a first pitch 103, while gate region 104 is formed on a second pitch 105 spaced apart from first pitch 103. Layout 100 also includes a first active region 106 extending laterally from the extended portion of gate region 102, and a second active region 108 extending laterally from the extended portion of the second gate region and separated from and spaced apart from first active region 106. First active region 106 overlaps gate region 102 to form a first transistor 110, and second active region 108 overlaps gate region 104 to form a second transistor 112. As shown in layout 100, first transistor 110 and second transistor 112 are formed across two silicon pitches and spaced apart from each other.

[0028] Layout 100 also includes a third active region 114 that extends laterally relative to the extended portion of gate region 102 and is laterally and outwardly spaced apart from first active region 106. Third active region 114 overlaps gate region 102 at first spacing 103 to form a third transistor 116. Gate region 118 overlaps third active region 114 at second spacing 105 to form a fourth transistor 120. Third transistor 116 and fourth transistor 120 are located laterally outside first active region 106 and spaced apart from first transistor 110 in layout 100.

[0029] Layout 100 also includes a fourth active region 122 that extends laterally relative to an extension of gate region 104 and is laterally and outwardly spaced apart from second active region 108. Fourth active region 122 overlaps gate region 104 at second spacing 105 to form fifth transistor 124. Gate region 126 at first spacing 103 overlaps fourth active region 122 to form sixth transistor 128. Fifth transistor 124 and sixth transistor 128 are located laterally outside second active region 108 and spaced apart from second transistor 112 in layout 100.

[0030] First transistor 110, second transistor 112, third transistor 116, fourth transistor 120, fifth transistor 124, and sixth transistor 128 collectively form a six-transistor (6T) write port of the SRAM cell in layout 100. As shown, the six transistors are formed on two pitches 103 and 105.

[0031] Layout 100 includes a plurality of active contacts 129 for coupling electrical signals to active regions 106, 108, 114, and 122, and a poly or gate contact 130 for coupling electrical signals to gate regions (e.g., gate regions 102, 104, 118, and 126). Layout 100 includes a region arranged along a third pitch 132 and a region arranged along a fourth pitch 134. Third pitch 132 is positioned adjacent to and extends parallel to first pitch 103, and fourth pitch 134 is positioned adjacent to and extends parallel to second pitch 105. Second memory cell 136 and third memory cell 138 may be located on the upper and lower sides, respectively, of SRAM cell 101. The active region of SRAM cell 101 may extend into second memory cell 136 and / or third memory cell 138.

[0032] The SRAM cell 101 includes a plurality of read ports located laterally to the 6T write port along the width of the SRAM cell 101. Specifically, the SRAM cell 101 includes a fifth active region 140 extending laterally to the extended portion of the gate region 102. The fifth active region 140 is located laterally outward from the third active region 114 relative to the first active region 106. The SRAM cell 101 also includes a sixth active region 142 extending laterally to the extended portion of the gate region 104. The sixth active region 142 is located laterally outward from the fourth active region 122 relative to the second active region 108. The fifth active region 140 and the sixth active region 142 each extend continuously across the first spacing 103, the second spacing 105, the third spacing 132, and the fourth spacing 134.

[0033] The multiple read ports of the SRAM cell 101 may include a read port 144 and a read port 146 formed at least partially along the fifth active region 140. The gate region of the second pitch 105 and / or the gate region of the fourth pitch 134 may overlap with the fifth active region 140 to form one or more transistors of the read port 144. The gate region of the first pitch 103 (e.g., gate region 102) and / or the gate region of the third pitch 132 may overlap with the fifth active region 140 to form one or more transistors of the read port 146.

[0034] The multiple read ports of the SRAM cell 101 may further include a read port 148 and a read port 150 formed at least partially along the sixth active region 142. The gate region of the second pitch 105 (e.g., gate region 104) and / or the gate region of the fourth pitch 134 may overlap the sixth active region 142 to form one or more transistors of the read port 148. The gate region of the first pitch 103 and / or the gate region of the third pitch 132 may overlap the sixth active region 142 to form one or more transistors of the read port 150.

[0035] Read port 144 , read port 146 , read port 148 and / or read port 150 may include one or more active contacts 129 coupled to the active region and / or one or more gate contacts 130 coupled to the gate region to apply electrical signals and control operation of the multiple read ports.

[0036] The SRAM cell 101 has a width W1, which depends on Figure 1 The structure of the SRAM cell 101 is shown. An array of SRAM memory cells can be created, each SRAM memory cell having the structure shown relative to the SRAM cell 101. Therefore, the overall area occupied by the array of SRAM memory cells depends on the structure of the constituent memory cells.

[0037] Figure 2An SRAM cell diagram 200 is shown in accordance with one or more embodiments. Diagram 200 has a five-port topology including a single write port 202 and four read ports designated RPA, RPB, RPC, and RPD in diagram 200. Write port 202 includes six transistors (6T) and is located between four read port pairs. A first pair of read ports 204 and 206 is located on a first side of write port 202, while a second pair of read ports 208 and 210 is located on a second side of write port 202, opposite the first side. A set of read word lines 212, 214, 216, and 218 are provided for controlling read operations from read ports 204, 206, 208, and 210. A write word line 220 is provided for controlling write operations to write port 202. Read bit lines 222, 228, 230, and 232 are connected to read ports 204, 206, 208, and 210, respectively, for reading data from the SRAM cells. A set of write bit lines 224 is connected to write port 202 for writing data to the SRAM cells.

[0038] The SRAM cell in Figure 200 has a four-pitch structure, in which the read ports 204, 206, 208, 210 and the write port 202 are formed across the four-pitch gate region. Internal connections can be set in a first layer of the SRAM cell, such as a first layer of the metal region. The read bit lines 222, 228, 230 and 232 and the write bit line 224 can be set in a second layer of the SRAM cell, such as a second layer of the metal region. The read bit lines 222, 228, 230 and 232 provide signals for selectively enabling read operations of bits of data stored in the SRAM cell. The group of write bit lines 224 provides signals for selectively enabling write operations to store bits of data in the SRAM cell. Power lines and ground lines can also be set in the second layer. The read word lines and write word lines 212, 214, 216, 218 and 220 can be set in a third layer of the SRAM cell, such as a third layer of the metal region. It should be noted that Figure 200 is a non-limiting representation of the overall layout of the SRAM cell, and the SRAM cell may include more than about Figure 2 The lines depicted and described have a greater number of lines.

[0039] Figure 3A layout of an SRAM cell 300 according to one or more embodiments is shown. The SRAM cell 300 includes an active area disposed on an active area layer, and a gate area disposed on a gate area layer different from the active area layer. The SRAM cell 300 includes other layers and interconnections between layers, some of which may be omitted from this disclosure for clarity, and some of which are discussed elsewhere herein. For example, the SRAM cell 300 may include word lines, bit lines, power lines, ground lines, etc. for providing signals to and between various parts of the SRAM component. The SRAM cell 300 includes edges 320, 332, 350, 352. Outside these edges are adjacent cells of the SRAM cell array.

[0040] The SRAM cell 300 includes a first active region 302 formed on a semiconductor substrate, such as silicon or another suitable material. The first active region 302 has an elongated shape extending in a direction along a first axis a1 (e.g., parallel to the illustrated y-axis). The SRAM cell 300 includes a first gate region 304 having an elongated shape extending in a direction transverse to the first axis a1 (e.g., parallel to the illustrated x-axis), and a second gate region 306 extending in a direction transverse to the first axis a1. The first gate region 304 is positioned along a first spacing 308 of a set of gate regions in the SRAM cell 300, while the second gate region 306 is positioned along a second spacing 310 of a set of gate regions in the SRAM cell 300. The first spacing 308 and the second spacing 310 extend in a direction parallel to the illustrated x-axis. The gate regions at the first spacing 308 are spaced apart from the gate regions at the second spacing 310 in a direction transverse to the first axis a1.

[0041] The first active area 302 covers the first gate area 304 to form a first transistor 312, and the first active area 302 covers the second gate area 306 to form a second transistor 314. The first gate area and the second gate area can form the source region and the drain region of each transistor. For example, these can be doped regions formed in the wafer before the gate area is formed. The first gate area 304 and the second gate area 306 are separated and spaced apart from each other in the direction along the first axis a1, that is, they are spaced apart from each other along the dimension of the first active area 302 along the first axis a1. The first transistor 312 is positioned along the first spacing 308 of the SRAM cell 300, and the second transistor 314 is positioned along the second spacing 310 of the SRAM cell 300. The first transistor 312 and the second transistor 314 are positioned relative to each other along a direction parallel to the first axis a1.

[0042] The SRAM cell 300 also includes a second active region 316 having an elongated shape extending in a direction along the second axis a2 (e.g., in a direction parallel to the y-axis). The second active region 316 is spaced apart from the first active region 302 in a substantially lateral direction transverse to the first axis a1. The second active region 316 overlaps with the first gate region 304 to form a third transistor 318 positioned along the first spacing 308 of the SRAM cell 300. The third transistor 318 is also located between the first axis a1 and the first side 320 of the SRAM cell 300 along the second axis a2.

[0043] The SRAM cell 300 also includes a third gate region 322 having an elongated shape extending in a direction transverse to the second axis a2. The third gate region 322 is positioned along a third spacing 324 of a set of gate regions of the SRAM cell 300. The third spacing 324 extends in a direction parallel to the first spacing 308 and / or the second spacing 310. The third spacing 324 is spaced apart from the first spacing 308 in a direction along the first axis a1 (e.g., in a +y direction parallel to the +y axis). The third gate region 322 overlaps with the second active region 316 to form a fourth transistor 326 positioned along the third spacing 324. The fourth transistor 326 is positioned along the second axis a2 between the first axis a1 and the first side 320 of the SRAM cell 300. The SRAM cell 300 may include a gate region 327 positioned at a first end of the first active region 302 along the third spacing 324.

[0044] The SRAM cell 300 includes a third active region 328 having an elongated shape extending in a direction along a third axis a3 (e.g., in a direction parallel to the y-axis). The third active region 328 is spaced apart from the first active region 302 in a substantially lateral direction transverse to the first axis a1. The third active region 328 overlaps with the second gate region 306 to form a fifth transistor 330 positioned along the second spacing 310 of the SRAM cell 300. The fifth transistor 330 is also positioned along the third axis a3 and the second side 332 of the SRAM cell 300.

[0045] The SRAM cell 300 also includes a fourth gate region 334 having an elongated shape extending in a direction transverse to the third axis a3. The fourth gate region 334 is positioned along a fourth spacing 336 of a set of gate regions of the SRAM cell 300. The fourth spacing 336 extends in a direction parallel to the first spacing 308 and / or the second spacing 310. The fourth spacing 336 is spaced apart from the second spacing 310 along the first axis a1 (e.g., parallel to the y-axis). The fourth gate region 334 overlaps with the third active region 328 to form a sixth transistor 338 positioned along the fourth spacing 336. The sixth transistor 338 is positioned along the third axis a3 between the first axis a1 and the second side 332 of the SRAM cell 300. The SRAM cell 300 may include a gate region 337 positioned at a second end of the first active region 302, opposite the first end, along the fourth spacing 336.

[0046] The first active area 302 extends between the four pitches. Specifically, the first active area 302 extends between the third pitch 324 and the first pitch 308. Although the first active area 302 may not overlap with the gate region in the third pitch 324 to form a transistor, the first active area 302 may partially overlap with the third pitch 324. The first active area 302 also extends between the fourth pitch 336 and the second pitch 310. Although the first active area 302 may not overlap with the gate region in the fourth pitch 336 to form a transistor, the first active area 302 may partially overlap with the fourth pitch 336. The first active area 302 also extends between the first pitch 308 and the second pitch 310.

[0047] The fourth transistor 326 and the sixth transistor 338 partially comprise the write port of the SRAM cell 300. The first transistor 312, the second transistor 314, the third transistor 318, and the fifth transistor 330 form a cross-coupled inverter pair that stores the data state of the SRAM cell 300. The cross-coupled inverter pair and the write port are located in a central portion between the active regions comprising the read ports (e.g., read ports 204, 206, 208, and 210) of the SRAM cell 300, as described herein. As a non-limiting example of a complementary metal oxide semiconductor (CMOS) configuration of the SRAM cell 300, the first transistor 312 and the second transistor 314 can be pull-up transistors (i.e., PMOS transistors), the third transistor 318 and the fifth transistor 330 can be pull-down transistors (i.e., NMOS transistors), and the fourth transistor 326 and the sixth transistor 338 can be passgate transistors (e.g., NMOS transistors). However, this relative configuration of transistor types can be adjusted based on the signal connections to the SRAM cell 101.

[0048] The SRAM cell 300 includes a set of read ports for reading electrical characteristics representing memory bits in the SRAM cell 300. Specifically, the SRAM cell 300 includes a first read port 340, a second read port 342, a third read port 344, and a fourth read port 346. The schematic layout and operation of the read ports are described elsewhere herein. In some embodiments, the first read port 340 may include a seventh transistor 354 of the SRAM cell 300. The first read port 340 is located outside the center portion between the second active area 316 and the first side 320. The fourth active area 348 extends between the upper side 350 of the SRAM cell 300 and the lower side 352 of the SRAM cell 300 and along a fourth axis a4. The fourth active area 348 is spaced apart from the second active area 316 toward the first side 320. The fourth active region 348 overlaps the first gate region 304 to form a seventh transistor 354 , which is positioned along the first pitch 308 of the SRAM cell 300 and also along the fourth axis a4 .

[0049] The SRAM cell 300 includes a fifth gate region 356 having an elongated shape extending in a direction transverse to the fourth axis a4. The fifth gate region 356 is positioned along the third spacing 324 of the set of gate regions of the SRAM cell 300. The fifth gate region 356 overlaps with the fourth active region 348 to form an eighth transistor 358 positioned along the third spacing 324. The eighth transistor 358 is positioned along the fourth axis a4 between the seventh transistor 354 and the upper side 350. The eighth transistor 358 is considered to be part of the first read port 340.

[0050] The fourth read port 346 is located outside the central portion between the second active region 316 and the first side 320 and is located adjacent to the first read port 340 along the fourth axis a4. The SRAM cell 300 may include a sixth gate region 360 positioned along the second spacing 310 of the set of gate regions of the SRAM cell 300. The sixth gate region 360 has an elongated shape extending in a direction transverse to the fourth axis a4. The fourth active region 348 overlaps with the sixth gate region 360 to form a ninth transistor 362, which is part of the fourth read port 346. The ninth transistor 362 is positioned along the second spacing 310 of the SRAM cell 300 and along the fourth axis a4.

[0051] The SRAM cell 300 may also include a seventh gate region 364 positioned along the third spacing 336 of the set of gate regions of the SRAM cell 300. The seventh gate region 364 has an elongated shape extending in a direction transverse to the fourth axis a4. The fourth active region 348 overlaps with the seventh gate region 364 to form a tenth transistor 366, which is part of the fourth read port 346. The tenth transistor 366 is positioned along the third spacing 336 of the SRAM cell 300 and along the fourth axis a4.

[0052] A second read port 342, including one or more transistors, is located outside the write port between the third active region 328 and the second side 332. The SRAM cell 300 may include a fifth active region 368 extending along the fifth axis a5 between the upper side 350 and the lower side 352 of the SRAM cell 300. The fifth active region 368 is spaced apart from the third active region 328 toward the second side 332. The second read port 342 may include an eighth gate region 370 having an elongated shape extending in a direction transverse to the fifth axis a5. The eighth gate region 370 is positioned along the first spacing 308 of the SRAM cell 300. The fifth active region 368 overlaps with the eighth gate region 370 to form an eleventh transistor 372 positioned along the first spacing 308 of the SRAM cell 300. The eleventh transistor 372 is also positioned along the fifth axis a5 and is considered part of the second read port 342.

[0053] In some embodiments, the second read port 342 of the SRAM cell 300 may include a twelfth transistor 376 of the SRAM cell 300. The second read port 342 may include a ninth gate region 374 having an elongated shape extending in a direction transverse to the fifth axis a5. The ninth gate region 374 is positioned along the third spacing 324 of the SRAM cell 300. The fifth active region 368 overlaps the ninth gate region 374 to form a twelfth transistor 376, which is positioned along the third spacing 324 of the SRAM cell 300.

[0054] A third read port 344, including one or more transistors, is located outside the central portion of the SRAM cell 300 between the third active region 328 and the second side 332. The third read port 344 may include a thirteenth transistor 378 of the SRAM cell 300. The fifth active region 368 may overlap the second gate region 306 along the fifth axis a5 to form the thirteenth transistor 378, which is positioned along the second pitch 310 of the SRAM cell 300.

[0055] In some embodiments, the third read port 344 may include a fourteenth transistor 380 of the SRAM cell 300. The third read port 344 may include a tenth gate region 382 having an elongated shape extending in a direction transverse to the fifth axis a5. The tenth gate region 382 is positioned along the fourth spacing 336 of the SRAM cell 300. The fifth active region 368 overlaps the tenth gate region 382 to form a fourteenth transistor 380, which is positioned along the fourth spacing 336 of the SRAM cell 300.

[0056] Figure 4 The layout 400 of the SRAM cell 300 including additional regions according to one or more embodiments is shown, and the connections between different regions of the SRAM cell 300 are shown. Specifically, the layout 400 includes the following: Figure 3 The regions outside of the active and gate regions discussed, and including interconnections between different regions. The layout 400 of the SRAM cell 300 includes a set of metal regions disposed in a layer separate from the active and gate region layers.

[0057] First metal region 402 is connected to third active region 328 via first active contact 404. First metal region 402 is connected to first gate region 304 via first gate contact 408. First metal region 402 connects third active region 328 to first active region 302 via second active contact 406. Second metal region 410 is connected to second active region 316 via third active contact 412. Second metal region 410 is connected to second gate region 306 via second gate contact 414 and to first active region 302 via fourth active contact 416. First metal region 402 and second metal region 410 can be considered to have an L-shape; however, in some embodiments, first metal region 402 and second metal region 410 can each include multiple segments forming the L-shape. First metal region 402 and second metal region 410 cross-couple a pair of inverters formed by first transistor 312, second transistor 314, third transistor 318, and fifth transistor 330, as described elsewhere herein.

[0058] Signals can be provided to the transistors of the SRAM cell 300 through various contacts coupled to the regions. A fifth active contact 418 is coupled to the first active region 302 between the first spacing 308 and the second spacing 310. Lines providing power signals or ground can be coupled to the first active region 302 via the fifth active contact 418. A sixth active contact 420 is coupled to the second active region 316, and a seventh active contact 422 is coupled to the third active region 328 between the first spacing 308 and the second spacing 310. Lines providing power signals or ground can be coupled to the second active region 316 and the third active region 328 via the sixth active contact 420 and the seventh active contact 422. For example, a power line providing a power signal (e.g., +5 VDC) can be provided to the SRAM cell 300 via the fifth active contact 418, and a ground line providing a ground reference (e.g., a 0 VDC reference) can be coupled to the sixth active contact 420 and the seventh active contact 422. This configuration may be modified based on the desired operation of the SRAM cell 300 .

[0059] The contacts of the SRAM cell 300 can be coupled to various circuits thereof to operable to store electrical signals representing data bits in the SRAM cell 300. In some embodiments, a third gate contact 424 is coupled to the third gate region 322 along a third spacing 324, and a fourth gate contact 426 is coupled to the fourth gate region 334 along a fourth spacing 336. Circuits can be coupled to the third gate contact 424 and the fourth gate contact 426 to provide signals that control the operation of the gate of the fourth transistor 326 and the gate of the sixth transistor 338. For example, a write word line (WWL) for selectively enabling data to be written to the SRAM cell 300 can be coupled to the third gate contact 424 and the fourth gate contact 426. A ninth active contact 428 is coupled to the second active region 316 above the third spacing 324, and a tenth active contact 430 is coupled to the third active region 328 below the fourth spacing 336. Lines may be coupled to the ninth active contact 428 and the tenth active contact 430 for providing signals corresponding to data to be written to the SRAM cell 300. For example, a bit line (BL) for providing data to be written to the SRAM cell 300 may be coupled to the ninth active contact 428 and the tenth active contact 430.

[0060] Data can be read from the SRAM cell 300 via one or more read ports. Lines are provided in the SRAM cell 300 and connected to the read ports for enabling read operations from the respective read ports. The ninth gate contact 431 is coupled to the fifth gate region 356 (e.g., along the third spacing 324) to enable a read operation from the first read port 340. The tenth gate contact 432 is coupled to the ninth gate region 374 (e.g., along the third spacing 324) to enable a read operation from the second read port 342. The eleventh gate contact 434 is coupled to the tenth gate region 382 (e.g., along the fourth spacing 336) to enable a read operation from the third read port 344. The twelfth gate contact 436 is coupled to the seventh gate region 364 (e.g., along the fourth spacing 336) to enable a read operation from the fourth read port 346.

[0061] The thirteenth gate contact 438 electrically couples the eighth gate region 370 to the second metal region 410, thereby connecting the cross-coupled inverters of the SRAM cell 300 to the second read port 342. The thirteenth gate contact 438 can be positioned along the first spacing 308. The fourteenth gate contact 440 electrically couples the sixth gate region 360 to the first metal region 402, thereby connecting the cross-coupled inverters of the SRAM cell 300 to the fourth read port 346. The fourteenth gate contact 440 can be positioned along the second spacing 310. A read word line (not shown) can be coupled to the ninth gate contact 431, the tenth gate contact 432, the eleventh gate contact 434, and the twelfth gate contact 436 to perform read operations on the first read port 340, the second read port 342, the third read port 344, and the fourth read port 346, respectively.

[0062] The lines are also connected to a read port for reading data stored in the SRAM cell 300. An eleventh active contact 442 is coupled to the fourth active region 348 for reading data stored in the SRAM cell 300 from the first read port 340. A twelfth active contact 444 is coupled to the fifth active region 368 for reading data stored in the SRAM cell 300 from the second read port 342. The eleventh active contact 442 and the twelfth active contact 444 are located above the third spacing 324 toward the upper edge 350. A thirteenth active contact 446 is coupled to the fifth active region 368 for reading data stored in the SRAM cell 300 from the third read port 344. A fourteenth active contact 448 is coupled to the fourth active region 348 for reading data stored in the SRAM cell 300 from the fourth read port 346. The thirteenth active contact 446 and the fourteenth active contact 448 are located below the fourth spacing 336 toward the lower edge 352. A read bit line (not shown) may be coupled to the eleventh active contact 442 , the twelfth active contact 444 , the thirteenth active contact 446 , and the fourteenth active contact 448 for reading the state of the SRAM cell 300 .

[0063] The SRAM cell 300 may include a fifteenth active contact 450 coupled to the fourth active region 348 and a sixteenth active contact 452 coupled to the fifth active region 368. The fifteenth active contact 450 and the sixteenth active contact 452 may be configured to couple a power line or a ground line to the read port. For example, a ground line providing a ground reference (0 VDC) may be coupled to the fifteenth active contact 450 and the sixteenth active contact 452.

[0064] The configuration and layout of the SRAM cell 300 provides many advantages over other SRAM designs. For example, the six transistor regions comprising the central portion of the SRAM cell 300 have a relatively high Figure 1 The width of the SRAM cell 101 discussed is shorter (i.e., in the direction along the x-axis). This design can achieve a 26.3% area reduction compared to previously implemented designs. For example, the occupied area of ​​the SRAM cell 300 can be smaller than the area of ​​the SRAM cell 101. This is because the first transistor 312 and the second transistor 314 are stacked on each other in the same active area (i.e., the first active area 302) rather than being formed on separate laterally spaced active areas as the first transistor 110 and the second transistor 112 are.

[0065] Figure 5 Shows the corresponding Figure 3 and Figure 4Schematic diagram of a circuit 500 of the described SRAM cell 300 and layout 400. The circuit 500 includes a cross-coupled inverter pair, which includes a first inverter 502 and a second inverter 504. The first inverter 502 includes a first transistor 506 and a second transistor 508 in series with the first transistor 506. The second inverter 504 includes a third transistor 510 and a fourth transistor 512 in series with the third transistor 510. In some embodiments, the first transistor 506 and the third transistor 510 are pull-up transistors, while the second transistor 508 and the fourth transistor 512 are pull-down transistors. However, the type of transistors can be adjusted according to the desired configuration of the circuit 500. Reference Figure 3 , the first transistor 506 may correspond to the first transistor 312, the second transistor 508 may correspond to the third transistor 318, the third transistor 510 may correspond to the second transistor 314, and the fourth transistor 512 may correspond to the fifth transistor 330. A pair of cross-coupled inverters 502 and 504 together form a storage element for storing a data bit of the SRAM cell 300.

[0066] The circuit 500 includes a fifth transistor 514 coupled to the first inverter 502 and having a first terminal (e.g., one of a source terminal and a drain terminal) coupled to a node 516 at which the terminals of the first transistor 506 and the second transistor 508 are commonly connected. The gate terminal of the fifth transistor 514 is coupled to a line for controlling a write operation of the SRAM cell 300, such as WWL. A second terminal (e.g., the other of the source terminal and the drain terminal) of the fifth transistor 514 is coupled to a line for providing a bit to be written to the SRAM cell 300 during a write operation, such as a write bit line. The fifth transistor 514 may correspond to a first terminal (e.g., a source terminal and a drain terminal) of the fifth transistor 514. Figure 3 3. The fourth transistor 326 is depicted. In at least some embodiments, the fifth transistor 514 is a pass gate transistor.

[0067] The circuit 500 also includes a sixth transistor 518 connected to the second inverter 504 and having a first terminal (e.g., one of a source terminal and a drain terminal) coupled to a node 520 where the terminals of the third transistor 510 and the fourth transistor 512 are commonly connected. The gate terminal of the sixth transistor 518 is coupled to a line for controlling a write operation of the SRAM cell 300, such as WWL. The second terminal (e.g., the other of the source terminal and the drain terminal) of the sixth transistor 518 is coupled to a line for providing a bit to be written to the SRAM cell 300 during a write operation, such as a write bit line. The sixth transistor 518 may correspond to a first terminal (e.g., one of a source terminal and a drain terminal) coupled to a node 520 where the terminals of the third transistor 510 and the fourth transistor 512 are commonly connected. Figure 3 3. The sixth transistor 338 is depicted. In at least some embodiments, the sixth transistor 518 is a pass-gate transistor.

[0068] The circuit 500 further includes a set of read ports for reading stored bit values ​​from the SRAM cell 300. The set of read ports includes one or more ports selected from a first read port 522, a second read port 524, a third read port 526, and a fourth read port 528. The set of read ports has a substantially similar layout to one another. Having multiple read ports can provide many advantages for the SRAM circuit, such as enabling many read operations to be performed in a single cycle without requiring a precharge operation for each read. In some embodiments, the circuit 500 can include fewer than four read ports, such as a pair of read ports, each coupled to read from one of the first inverter 502 and the second inverter 504.

[0069] The first read port 522 includes a seventh transistor 530 and an eighth transistor 532 coupled in series with the seventh transistor 530. The gate terminal of the seventh transistor 530 is coupled to the node 516 for reading a bit value from the first inverter 502 during a read operation. The gate terminal of the eighth transistor 532 is coupled to a line for selectively enabling the first read port 522 to perform a read operation, such as a read word line coupled to the ninth gate contact 431. The first terminal of the eighth transistor 532 is coupled to a line for outputting a bit read from the first inverter 502 during a read operation (e.g., at a gate terminal 516). Figure 4 The second terminal of the eighth transistor 532 is coupled to the first terminal of the seventh transistor 530, and the second terminal of the seventh transistor 530 is coupled to a line providing a ground reference (e.g., at the fifteenth active contact 450). Figure 3 , the seventh transistor 530 corresponds to the seventh transistor 354 , and the eighth transistor 532 corresponds to the eighth transistor 358 .

[0070] The second read port 524 includes a ninth transistor 534 and a tenth transistor 536 coupled in series with the ninth transistor 534. The gate terminal of the ninth transistor 534 is coupled to the node 520 for reading a bit value from the second inverter 504 during a read operation. The gate terminal of the tenth transistor 536 is coupled to a line for selectively enabling the second read port 524 to perform a read operation, such as a read word line coupled to the tenth gate contact 432. A first terminal of the tenth transistor 536 is coupled to a line for outputting a bit read from the second inverter 504 during a read operation (e.g., at a gate terminal 520). Figure 4 The second terminal of the tenth transistor 536 is coupled to the first terminal of the ninth transistor 534, and the second terminal of the ninth transistor 534 is coupled to a line providing a ground reference (e.g., at the twelfth active contact 444 of FIG. 1 ). Figure 4 16th active contact 452). Figure 3 , the ninth transistor 534 corresponds to the eleventh transistor 372 , and the tenth transistor 536 corresponds to the twelfth transistor 376 .

[0071] The third read port 526 includes an eleventh transistor 538 and a twelfth transistor 540 coupled in series with the eleventh transistor 538. The gate terminal of the eleventh transistor 538 is coupled to the node 520 for reading a bit value from the second inverter 504 during a read operation. The gate terminal of the twelfth transistor 540 is coupled to a line for selectively enabling the third read port 526 to perform a read operation, such as a read word line coupled to the eleventh gate contact 434. A first terminal of the twelfth transistor 540 is coupled to a line for outputting a bit read from the second inverter 504 during a read operation (e.g., at a gate terminal). Figure 4 The second terminal of the twelfth transistor 540 is coupled to the first terminal of the eleventh transistor 538, and the second terminal of the eleventh transistor 538 is coupled to a line providing a ground reference (e.g., at the thirteenth active contact 446 of FIG. 1 ). Figure 4 16th active contact 452). Figure 3 , the eleventh transistor 538 corresponds to the thirteenth transistor 378 , and the twelfth transistor 540 corresponds to the fourteenth transistor 380 .

[0072] The fourth read port 528 includes a thirteenth transistor 542 and a fourteenth transistor 544 coupled in series with the thirteenth transistor 542. The gate terminal of the thirteenth transistor 542 is coupled to the node 516 for reading a bit value from the first inverter 502 during a read operation. The gate terminal of the fourteenth transistor 544 is coupled to a line for selectively enabling the fourth read port 528 to perform a read operation, such as a read word line coupled to the twelfth gate contact 436. The first terminal of the fourteenth transistor 544 is coupled to a line for outputting a bit read from the first inverter 502 during a read operation (e.g., at a 12th gate contact 436). Figure 4 The second terminal of the fourteenth transistor 544 is coupled to the first terminal of the thirteenth transistor 542, and the second terminal of the thirteenth transistor 542 is coupled to a line providing a ground reference (e.g., at the Figure 4 The fifteenth active contact 450 of FIG. Figure 3 , the thirteenth transistor 542 corresponds to the ninth transistor 362 , and the fourteenth transistor 544 corresponds to the tenth transistor 366 .

[0073] The read operation may include causing a read operation to be performed via two read ports. For example, the read operation may include causing the first read port 522 to read the state of the first inverter 502 via node 516, and causing the second read port 524 to read the state of the second inverter 504 via node 520. The read operation may exclude execution from the other two read ports (the third read port 526 and the fourth read port 528). A subsequent read operation may include (e.g., by a controller not shown) causing the third read port 526 to read the state of the second inverter 504 via node 520, and causing the fourth read port 528 to read the state of the first inverter 502 via node 516.

[0074] As a result of the present SRAM cell structure, the central active region can extend into adjacent SRAM cells. Figure 6 An SRAM cell 600 according to one or more embodiments is shown. The SRAM cell 600 includes a first active region 602 extending along an axis a6 parallel to the y-axis. The first active region 602 extends from the SRAM cell 600 along the axis a6 in a first direction (i.e., in a −y direction parallel to the y-axis) to a second SRAM cell 604 adjacent to the SRAM cell 600. The first active region 602 also extends from the SRAM cell 600 along the axis a6 in a second direction opposite to the first direction (i.e., in a +y direction parallel to the y-axis) to a third SRAM cell 606 adjacent to the SRAM cell 600.

[0075] The SRAM cell 600 includes a first gate region 608 extending in a direction transverse to the axis a6 along a first spacing 610. The first gate region 608 overlaps the first active region 602 to form a first transistor 612 positioned along the axis a6. The first transistor 612 corresponds to Figure 3 The SRAM cell 600 further includes a second gate region 614 extending along a second spacing 616 in a direction transverse to the axis a6. The second gate region 614 overlaps the first active region 602 to form a second transistor 618 positioned along the first axis a6. The second transistor 618 corresponds to Figure 3 A second transistor 314 is depicted.

[0076] The SRAM cell 600 includes a third gate region 620 extending along a third spacing 622 in a direction transverse to the axis a6. The third gate region 620 is located between the second spacing 616 and the second SRAM cell 604 along the axis a6. The third gate region 620 overlaps with the first active area 602 to form a third transistor 624 positioned along the axis a6. The SRAM cell 600 includes a fourth gate region 626 extending along a fourth spacing 628 in a direction transverse to the axis a6. The fourth gate region 626 is located between the first spacing 610 and the third SRAM cell 606 along the axis a6. The fourth gate region 626 overlaps with the first active area 602 to form a fourth transistor 630 positioned along the axis a6.

[0077] A first active contact 632 can be coupled to the first active region 602 at a location between the second gate region 614 and the third gate region 620. A second active contact 634 can be coupled to the first active region 602 at a location between the first gate region 608 and the fourth gate region 626. One or more lines can be connected to the first active contact 632 and the second active contact 634 to provide a signal or ground reference to a portion of the first active region 602. For example, a line providing a ground reference (e.g., VDC) can be connected to the first active contact 632 and the second active contact 634.

[0078] Extending the first active area 602 through a plurality of SRAM cells positioned along axis a6 provides a source of improved shallow trench isolation. Specifically, the trenches extending on the sides of the first active area 602 provide a continuous source of shallow trench isolation along the entire length of the SRAM cell array. Shallow trench isolation prevents or reduces current leakage between a portion of the SRAM cell on a first side of axis a6 and a portion of the SRAM cell on a second side of axis a6 opposite the first side. In other words, the continuous length of the first active area 602 of the SRAM cell 600 helps prevent or reduce current leakage between the left and right sides of the SRAM cell. The SRAM cell architecture disclosed herein can also be associated with improvements in performance characteristics, such as power efficiency and write speed for writing data to the SRAM cell.

[0079] Each adjacent SRAM cell is substantially identical to the SRAM cell 600. The second SRAM cell 604 is a mirror image of the SRAM cell 600 as reflected about the lower side 636 of the SRAM cell 600, and the third SRAM cell 606 is a mirror image of the SRAM cell 600 as reflected about the upper side 638 of the SRAM cell 600. Specifically, Figure 3 The active area 640 of the second active area 316 extends from the SRAM cell 600 and into the third SRAM cell 606 through the upper side 638. Figure 3 The active area 642 of the third active area 328 extends from the SRAM cell 600 and into the second SRAM cell 604 through the lower side 636. The fourth SRAM cell (not shown) located below the second SRAM cell 604 can be a mirror image of the second SRAM cell 604 with respect to its lower side. The fifth SRAM cell (not shown) located above the third SRAM cell 606 can be a mirror image of the third SRAM cell 606 with respect to its upper side. This pattern can be repeated along the length of the axis a6 to the edge of the SRAM cell array.

[0080] The second SRAM cell 604 may include a gate region 644 extending along a spacing 646 in a direction transverse to the axis a6, the spacing 646 being a spacing adjacent to the third spacing 622. The gate region 644 overlaps the first active area 602 to form a transistor 648 of the second SRAM cell 604. A third active contact 650 is coupled to the first active area 602 between the third gate region 620 of the SRAM cell 600 and the gate region 644 of the second SRAM cell 604. A line may be connected to the third active contact 650 to provide a signal to a portion of the first active area 602. For example, a line providing a power signal (e.g., +5 VDC) may be connected to the third active contact 650.

[0081] The third SRAM cell 606 may include a gate region 652 extending along a spacing 654 in a direction transverse to the axis a6, the spacing 654 being a spacing adjacent to the fourth spacing 628. The gate region 652 overlaps the first active area 602 to form a transistor 656 of the third SRAM cell 606. A fourth active contact 658 is coupled to the first active area 602 between the fourth gate region 626 of the SRAM cell 600 and the gate region 652 of the third SRAM cell 606. A line may be connected to the fourth active contact 658 to provide a signal to a portion of the first active area 602. For example, a line providing a power signal (e.g., +5 VDC) may be connected to the fourth active contact 658.

[0082] The SRAM cell 600 may include a fourth active region 660 extending parallel to the axis a6 and located laterally outside the active region 640. The SRAM cell 600 may include a fifth active region 662 extending parallel to the axis a6 and located laterally outside the active region 642. The fourth active region 660 and / or the fifth active region 662 may overlap with the gate region along the first spacing 610, the second spacing 616, the third spacing 622, and / or the fourth spacing 628 to form one or more read port transistors, as described with respect to FIG. Figure 3 and Figure 4 The fourth active region 660 can be spaced apart from the active region 640 toward a first side 664 of the SRAM cell 600. The fifth active region 662 can be spaced apart from the active region 642 toward a second side 666 of the SRAM cell 600 opposite the first side 664.

[0083] Figure 7 Layout 700 of SRAM cell 600 and partial layouts of SRAM cells 604 and 606 are shown according to one or more embodiments. Layout 700 includes Figure 3 and Figure 6 The regions outside of the active and gate regions discussed, and including interconnections between different regions. Layout 700 includes a set of metal regions disposed in a layer separate from the active and gate region layers.

[0084] Layout 700 includes a first metal region 702 coupled to a third active contact 650. A gate contact 704 is coupled to the third gate region 620 of the SRAM cell 600, and a gate contact 706 is coupled to the gate region 644 of the second SRAM cell 604. The first metal region 702 is coupled to the gate contact 704 and the gate contact 706. The first metal region 702 connects the signal provided at the third active contact 650 to the gate terminal of the transistor 648 and to the gate terminal of the third transistor 624.

[0085] The layout includes a second metal region 708 coupled to the fourth active contact 658. A gate contact 710 is coupled to the fourth gate region 626 of the SRAM cell 600, and a gate contact 712 is coupled to the gate region 652 of the third SRAM cell 606. The second metal region 708 is coupled to the gate contact 710 and the gate contact 712. The second metal region 708 connects the signal provided at the fourth active contact 658 to the gate terminal of the transistor 656 and the gate terminal of the fourth transistor 630.

[0086] The SRAM cell 600 and the layout 700 are otherwise substantially similar to the SRAM cell 300 and the layout 400 , and thus further description thereof is omitted for the sake of brevity.

[0087] Figure 8 Shows the corresponding Figure 6 6. Circuit 800 of SRAM cell 600 is depicted. Circuit 800 includes a fifteenth transistor 802 and a sixteenth transistor 804. Fifteenth transistor 802 is coupled between a power supply 806 and node 516 of circuit 800. Power supply 806 can be coupled to, for example, third active contact 650. A first terminal (e.g., a source terminal) of fifteenth transistor 802 is coupled to the gate of fifteenth transistor 802 and to power supply 806. A second terminal (e.g., a drain terminal) of fifteenth transistor 802 is coupled to node 516. Sixteenth transistor 804 is coupled between power supply 806 and node 520. A first terminal (e.g., a source terminal) of sixteenth transistor 804 is coupled to the gate of sixteenth transistor 804 and to power supply 806. A second terminal (e.g., a drain terminal) of sixteenth transistor 804 is coupled to node 520.

[0088] In at least some embodiments, the fifteenth transistor 802 and the sixteenth transistor 804 are P-channel MOSFETs. The fifteenth transistor 802 corresponds to the fourth transistor 630, and the sixteenth transistor 804 corresponds to the third transistor 624. In operation, the fifteenth transistor 802 and the sixteenth transistor 804 are dummy transistors that are biased off (i.e., open circuit between their first and second terminals) when power is applied via the power supply 806. Therefore, the dummy transistors do not affect the operation of the SRAM cell. Advantageously, due to the SRAM cell 600 and the layout 700, the area occupied by the SRAM cell layout is reduced while improving its shallow trench isolation characteristics.

[0089] In some embodiments, the area of ​​the SRAM cell can be further reduced. For example, the write port of the SRAM cell can be implemented using two active regions instead of three active regions, thereby further reducing the area occupied by the SRAM cell. Figure 9An SRAM cell 900 according to one or more embodiments is shown. The SRAM cell 900 includes a first active region 902 extending along an axis a7 parallel to the y-axis. The first active region 902 extends to overlap all four pitches of the SRAM cell 300. The first active region 902 extends from the SRAM cell 900 along the axis a7 in a first direction (i.e., in a −y direction parallel to the y-axis) to a second SRAM cell 904 adjacent to the SRAM cell 900. The first active region 902 also extends from the SRAM cell 900 along the axis a7 in a second direction opposite to the first direction (i.e., in a +y direction parallel to the y-axis) to a third SRAM cell 906 adjacent to the SRAM cell 900.

[0090] The SRAM cell 900 includes a first gate region 908 extending in a direction transverse to the axis a7 along a first spacing 910. The SRAM cell 900 also includes a second gate region 912 extending in a direction transverse to the axis a7 along a second spacing 914. The first gate region 908 overlaps with the first active region 902 to form a first transistor 916 of the SRAM cell 900. The second gate region 912 overlaps with the first active region 902 to form a second transistor 918 of the SRAM cell 900.

[0091] The first transistor 916 and the second transistor 918 located along the first active region 902 correspond to the Figure 5 500 and the transistors of the first inverter 502 and the second inverter 504 in the circuit 500 described elsewhere. The first transistor 916 may correspond to the transistor 508 of the first inverter 502, and the second transistor 918 may correspond to the transistor 512 of the second inverter 504. In at least some embodiments, the first transistor 916 and the second transistor 918 are the same type of transistors. For example, the first transistor 916 and the second transistor 918 may be N-type MOSFETs or pull-down transistors.

[0092] The SRAM cell 900 includes a third gate region 920 extending in a direction transverse to the axis a7 along a third spacing 922. The third gate region 920 overlaps the first active region 902 to form a third transistor 924 of the SRAM cell 900. The third transistor 924 corresponds to a pass-gate transistor for controlling a write operation of the SRAM cell 900. For example, the third transistor 924 may correspond to the fifth transistor 514 or the sixth transistor 518 of the circuit 500.

[0093] The SRAM cell 900 includes a fourth gate region 926 extending in a direction transverse to the axis a7 along a fourth spacing 928. The fourth gate region 926 overlaps the first active area 902 to form a fourth transistor 930 of the SRAM cell 900. The fourth transistor 930 corresponds to another pass-gate transistor of the circuit 500 for controlling a write operation of the SRAM cell 900. For example, the fourth transistor 930 may correspond to the fifth transistor 514 or the sixth transistor 518 of the circuit 500.

[0094] The SRAM cell 900 also includes a second active area 932 that extends laterally along axis a8 and is separated and laterally spaced apart from the first active area 902. The second active area 932 extends to overlap an appropriate subset of the four pitches of the SRAM cell 900. The second active area 932 overlaps the first gate area 908 to form a fifth transistor 934 of the SRAM cell 900 and overlaps the second gate area 912 to form a sixth transistor 936 of the SRAM cell 900.

[0095] The fifth transistor 934 and the sixth transistor 936, positioned along the second active region 932, correspond to the transistor of the first inverter 502 and the transistor of the second inverter 504, respectively, in the circuit 500. The fifth transistor 934 may correspond to the transistor 506 of the first inverter 502, and the sixth transistor 936 may correspond to the transistor 510 of the second inverter 504. In at least some embodiments, the fifth transistor 934 and the sixth transistor 936 are transistors of the same type. The fifth transistor 934 and the sixth transistor 936 may be transistors of a different type than the first transistor 916 and the second transistor 918. In addition to the examples provided above with respect to the first transistor 916 and the second transistor 918, the fifth transistor 934 of the sixth transistor may be a P-type MOSFET or a pull-up transistor that is complementary to the N-type MOSFETs or pull-down transistors of the first transistor 916 and the second transistor 918.

[0096] The first transistor 916 and the fifth transistor 934 together form an inverter of the circuit 500, such as the first inverter 502. The second transistor 918 and the sixth transistor 936 together form another inverter of the circuit 500, such as the second inverter 504.

[0097] The first transistor 916, the second transistor 918, the fifth transistor 934, and the sixth transistor 936 collectively form a pair of cross-coupled inverters for storing bit data, as described herein. The third transistor 924 and the fourth transistor 930 correspond to pass gates for controlling write operations of the SRAM cell 900.

[0098] The SRAM cell 900 includes a first active contact 938 between the fifth transistor 934 and the sixth transistor 936 coupled to the second active region 932. The first active contact 938 can be coupled to a line for providing power or ground to the terminals of the fifth transistor 934 and the sixth transistor 936. For example, the first active contact 938 can be coupled to a line that provides a power signal (e.g., +5 VDC) to the source terminals of the fifth transistor 934 and the sixth transistor 936. The SRAM cell 900 also includes a second active contact 940 between the first transistor 916 and the second transistor 918 coupled to the first active region 902. The second active contact 940 can be coupled to a signal line for providing power or ground to the terminals of the first transistor 916 and the second transistor 918—for example, the second active contact 940 can be connected to a line that provides power ground (0 VDC) to the drain terminals of the first transistor 916 and the second transistor 918.

[0099] In an embodiment where the first active contact 938 is coupled to a line providing a power signal and the second active contact 940 is coupled to a signal line providing a power ground, the first transistor 916 and the second transistor 918 are pull-down transistors, while the fifth transistor 934 and the sixth transistor 936 are pull-up transistors. However, these transistor types may differ depending on the signal on the line coupled to the first active contact 938 and the signal on the line coupled to the second active contact 940.

[0100] The SRAM cell 900 includes a first metal region 942 for cross-coupling the gate terminals of the fifth transistor 934 and the first transistor 916 with the terminals of the sixth transistor 936 and the second transistor 918. The first metal region 942 is coupled to a first gate contact 944, which is located outside the fifth transistor 934 along the first spacing 910. The first metal region 942 is coupled to the second active region 932 via a third active contact 946 located between the second spacing 914 and the third spacing 922 along the axis a8. The first metal region 942 is also coupled to the first active region 902 via a fourth active contact 948 located between the second spacing 914 and the third spacing 922 along the axis a7.

[0101] SRAM cell 900 includes a second metal region 950 for cross-coupling the gate terminals of second transistor 918 and sixth transistor 936 with the terminals of fifth transistor 934 and first transistor 916. Second metal region 950 is coupled to a second gate contact 952, which is located outside of second transistor 918 along second spacing 914. Second metal region 950 is also coupled to first active region 902 via a fifth active contact 954 located between first spacing 910 and fourth spacing 928 along axis a7. Second metal region 950 is also coupled to second active region 932 via a sixth active contact 956 located between first spacing 910 and fourth spacing 928 along axis a8.

[0102] The SRAM cell 900 also includes a third gate contact 958 coupled to the third gate region 920 along a third spacing 922 and located outside the axis a7. The SRAM cell 900 includes a fourth gate contact 960 coupled to the fourth gate region 926 along a fourth spacing 928 and located outside the axis a7. One or more lines can be coupled to the third gate contact 958 and the fourth gate contact 960 for providing signals that control write operations of the SRAM cell 900, such as signals provided by the WWL.

[0103] The seventh active contact 962 is coupled to the first active area 902 outside the third transistor 924 below the third spacing 922 along the axis a7. The eighth active contact 964 is coupled to the first active area 902 outside the fourth transistor 930 above the fourth spacing 928 along the axis a7. One or more lines, such as a write bit line and a complementary write bit line, can be coupled to the seventh active contact 962 and the eighth active contact 964 for writing data bits to the SRAM cell 900.

[0104] The SRAM cell 900 may include a third active region 966 extending parallel to the axis a7 and may include a fourth active region 968 extending parallel to the axis a7. The third active region 966 and / or the fourth active region 968 may overlap with the gate region along the first spacing 910, the second spacing 914, the third spacing 922, and / or the fourth spacing 928 to form one or more transistors of a read port, as described elsewhere herein. The third active region 966 may be spaced apart from the second active region 932 on a first side of the SRAM cell 900 and located outside the second active region 932. The fourth active region 968 may be spaced apart from the first active region 902 on a second side of the SRAM cell opposite the first side and located outside the first active region 902.

[0105] The area occupied by SRAM cell 900 is approximately 20% (19.5%) less than the area occupied by a memory cell implementing layout 100. Otherwise, SRAM cell 900 is substantially similar to other SRAM cells described herein, and thus further description thereof is omitted for the sake of brevity.

[0106] Figure 10 An SRAM cell 1000 is shown in which two active regions are continuous between adjacent SRAM cells. Specifically, the first active region 1002 extends from the SRAM cell 1000 along the axis a7 (see above). Figure 9 The second active region 1008 extends from the SRAM cell 1000 along the axis a8 (described above with reference to FIG. 1 ) to the first SRAM cell 1004 adjacent to the SRAM cell 1000 and to the second SRAM cell 1006 adjacent to the SRAM cell 1000. Figure 9 1004 and the second SRAM cell 1006. As shown, the first active region 1002 is separated and spaced apart from the second active region 1008 in a direction transverse to the axes a7 and a8.

[0107] The SRAM cell 1000 includes a fifth gate region 1010 that overlaps the second active region 1008 located along the fourth spacing 928 to form a seventh transistor 1012. The SRAM cell 1000 also includes a sixth gate region 1014 that overlaps the second active region 1008 located along the third spacing 922 to form an eighth transistor 1016. The seventh transistor 1012 and the eighth transistor 1016 are dummy transistors that do not affect the operation of the circuit 500. However, as described with respect to the SRAM cell 600, the continuous second active region 1008 contributes to improved shallow trench isolation characteristics, which, for example, reduces or prevents current leakage in the SRAM cell 1000.

[0108] Otherwise, SRAM cell 1000 is substantially similar to other SRAM cells described herein and operates as described herein with respect to circuits 500 and 700 , and thus further description thereof is omitted for the sake of brevity.

[0109] Advantageously, the layout disclosed herein substantially reduces the area occupied by an SRAM cell or SRAM cell array. In previous implementations, shallow trench isolation characteristics have been shown to adversely affect performance, such as write speed and power consumption. The SRAM cell layout described herein improves the performance of the SRAM cell by mitigating the effects of shallow trench isolation. According to at least some models, the SRAM cell described herein improves the write time for writing data to the SRAM cell and also reduces the power consumption associated with the write operation.

[0110] The various embodiments described above can be combined to provide further embodiments.

[0111] These and other changes can be made to the embodiments in light of the above detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and claims, but should be construed to include all possible embodiments and the full scope of equivalents to which such claims are entitled. Therefore, the claims are not limited by this disclosure.

Claims

1. A memory cell array, comprising: A first memory cell having a first pair of cross-coupled inverters, wherein the first pair of cross-coupled inverters comprises: a first transistor including a first active region extending along a first axis and including a first gate region extending transversely to the first axis and overlapping the first active region; a second transistor including a second gate region extending transversely to the first axis and overlapping the first active region, the second gate region being spaced apart from the first gate region along the first axis; and A second memory cell having a second pair of cross-coupled inverters, wherein the second pair of cross-coupled inverters comprises: the first active region extending from the first memory cell into the second memory cell along the first axis; a third transistor including a third gate region extending transversely to the first axis and overlapping the first active region; and The fourth transistor includes a fourth gate region extending transversely to the first direction and overlapping the first active region, wherein the fourth gate region is spaced apart from the third gate region along the first axis.

2. The memory cell array of claim 1, wherein the second memory cell is adjacent to the first memory cell along the first axis; and a third memory cell is adjacent to the first memory cell along the first axis.

3. The memory cell array according to claim 1, comprising: The fifth transistor includes a fifth gate region extending in a direction transverse to the first axis and overlapping the first active region, wherein the fifth gate region is positioned between the second gate region and the third gate region along the first axis.

4. The memory cell array according to claim 3, wherein the fifth gate region is included in the first memory cell, and the second memory cell comprises: A sixth transistor includes a sixth gate region extending along a second direction transverse to the first axis and overlapping the first active region, wherein the sixth gate region is positioned between the fifth gate region and the third gate region along the first axis.

5. The memory cell array of claim 1 , wherein the first pair of cross-coupled inverters comprises: a fifth transistor comprising a second active region extending along a second axis spaced apart from the first side of the first active region; as well as The first memory cell includes a sixth transistor including a third active region extending along a third axis spaced apart from a second side of the first active region, the third active region overlapping the second gate region.

6. The memory cell array of claim 5, wherein the first pair of cross-coupled inverters comprises: a fifth transistor comprising a second active region extending along a second axis spaced apart from the first side of the first active region; as well as A sixth transistor includes the second active region and the second gate region overlapping the second active region.

7. The memory cell array of claim 5, wherein the second active region extends from the first memory cell into the second memory cell.

8. An integrated circuit comprising: A first memory unit, comprising a first pair of cross-coupled inverters, wherein the first pair of cross-coupled inverters comprises: a first transistor including a first active region extending along a first axis and a first gate region extending transversely to the first axis and overlapping the first active region; a second transistor including a second gate region extending transversely to the first axis and overlapping the first active region, the second gate region being spaced apart from the first gate region along the first axis; and a third transistor including a first gate region extending transversely to the first axis and overlapping a second active region extending along a second axis substantially parallel to the first axis, and A fourth transistor includes a second gate region extending transversely to the first axis and overlapping the second active region.

9. The integrated circuit of claim 8, wherein the first memory cell comprises a first read port, the first read port comprising a third active region extending along a second axis, the first gate region overlapping the third active region.

10. The integrated circuit of claim 8, comprising a second memory cell, wherein the first active area and the second active area extend into the second memory cell.

11. The integrated circuit of claim 10, comprising a third memory cell, wherein the first active area and the second active area extend into the third memory cell.

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