Semiconductor device and manufacturing method thereof, electronic device

Abstract

A semiconductor device and its manufacturing method, and an electronic device thereof, are disclosed. The semiconductor device includes: multiple rows of transistors distributed along a first direction parallel to a substrate; each transistor includes semiconductor pillars extending along a direction perpendicular to the substrate; the semiconductor pillars of all odd-numbered rows of transistors form an array distributed along the first direction and a second direction parallel to the substrate; the semiconductor pillars of all even-numbered rows of transistors form an array distributed along the first direction and the second direction; and the semiconductor pillars of odd-numbered rows of transistors are staggered from those of even-numbered rows of transistors in the second direction, wherein the first direction and the second direction are perpendicular; and multiple bit lines extending along the second direction, with transistors in the same column connected to the same bit line. The solution provided in this embodiment, by setting transistors with staggered column directions, can avoid misaligned etching or reduce the degree of misalignment when forming node contact electrodes, thereby reducing process difficulty and improving yield.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, device design and manufacturing in the field of semiconductor technology, and particularly to a semiconductor device and its manufacturing method, and electronic equipment. Background Technology

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing, which means that any slight difference in the manufacturing process can affect the performance of the devices.

[0003] To minimize product costs, the goal is to fabricate as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] This application provides a semiconductor device and its manufacturing method, as well as an electronic device, which simplifies the process and improves the yield.

[0006] This application provides a semiconductor device, including:

[0007] A plurality of rows of transistors are distributed along a first direction parallel to a substrate, the transistors including semiconductor pillars extending along a direction perpendicular to the substrate, the semiconductor pillars of all odd-numbered rows of transistors forming an array distributed along the first direction and along a second direction parallel to the substrate, the semiconductor pillars of all even-numbered rows of transistors forming an array distributed along the first direction and the second direction, and the semiconductor pillars of the odd-numbered rows of transistors are offset from the semiconductor pillars of the even-numbered rows of transistors in the second direction, the first direction and the second direction being perpendicular;

[0008] Multiple bit lines extending along the second direction, with transistors in the same column connected to the same bit line.

[0009] In some embodiments, every two adjacent columns of transistors share a single bit line.

[0010] In some embodiments, each bit line is disposed between semiconductor pillars of two columns of transistors sharing the bit line.

[0011] In some embodiments, along the extension direction of the semiconductor pillar, the sidewall of the semiconductor pillar includes a first region, a channel region, and a second region distributed sequentially, and the first region is disposed on the side of the channel region facing the substrate, and the bit line is connected to the first region of the semiconductor pillar of two columns of transistors sharing the bit line.

[0012] In some embodiments, in two columns of semiconductor pillars connected to the same bit line, the sidewall of the first region of any column of semiconductor pillars facing the other column of semiconductor pillars includes a first sub-region extending in a direction perpendicular to the substrate, a second sub-region extending from the first sub-region in a direction away from the other column of semiconductor pillars, and a third sub-region extending from the second sub-region in a direction perpendicular to the substrate, the third sub-region being disposed on the side of the first sub-region away from the substrate, the bit line being connected to the regions of the second sub-region and the third sub-region adjacent to the second sub-region, but not connected to the first sub-region.

[0013] In some embodiments, the semiconductor device further includes: a plurality of first trenches extending along a second direction, each first trench having a bit line disposed therein, two columns of transistors disposed between adjacent first trenches being respectively connected to the bit lines in adjacent first trenches, and the depth of the first trench being less than the height of the semiconductor pillars, and the sidewalls of the two columns of semiconductor pillars adjacent to the first trenches forming the bottom wall and sidewall of the first trench.

[0014] In some embodiments, the size of the bit line along the first direction is smaller than the size of the bit line along the direction perpendicular to the substrate.

[0015] In some embodiments, the orthographic projection of the channel region and the second region onto the substrate falls within the orthographic projection of the first region onto the substrate.

[0016] In some embodiments, the transistor further includes a gate electrode surrounding the channel region, wherein the gate electrodes of transistors in the same row are connected to form word lines extending along a first direction.

[0017] In some embodiments, the semiconductor device further includes a plurality of node contact electrodes disposed on the surface of the plurality of semiconductor pillars on the side away from the substrate and respectively connected to the plurality of semiconductor pillars, wherein the arrangement of the plurality of node contact electrodes is consistent with the arrangement of the plurality of transistors.

[0018] In some embodiments, the semiconductor device further includes a plurality of capacitors disposed on the side of the plurality of node contact electrodes away from the transistor, each capacitor being connected to a surface of the node contact electrode opposite to the transistor, and the arrangement of the plurality of capacitors being consistent with the arrangement of the plurality of transistors.

[0019] This disclosure provides a method for manufacturing a semiconductor device, including:

[0020] A substrate is provided, on which a plurality of first trenches extending in a second direction are formed, and in each of the first trenches a bit line extending in the second direction is formed;

[0021] Multiple rows of semiconductor pillars extending perpendicular to the substrate are formed along a first direction, and all odd-numbered rows of semiconductor pillars form an array distributed along the first direction and a second direction, and all even-numbered rows of semiconductor pillars form an array distributed along the first direction and the second direction, with the odd-numbered rows of semiconductor pillars offset from the even-numbered rows of semiconductor pillars in the second direction; the first trench is disposed between two adjacent rows of semiconductor pillars, and the depth of the first trench is less than the height of the semiconductor pillars.

[0022] In some embodiments, the semiconductor pillar is formed by forming a mask layer on the substrate comprising a plurality of first strips extending along a third direction and a plurality of second strips extending along a fourth direction, and etching the substrate covered by the mask layer to form the semiconductor pillar, wherein the third direction intersects the first direction and the second direction, the fourth direction intersects the first direction and the second direction, and the third direction intersects the fourth direction.

[0023] In some embodiments, the method further includes: forming a second trench extending along the first direction between adjacent semiconductor pillars, the bottom wall of the second trench exposing the bit line;

[0024] The exposed semiconductor pillars are disposed in the channel region on the side of the bit line away from the substrate, forming a gate electrode surrounding the channel region, and the gate electrodes of the semiconductor pillars in the same row are connected to form a word line extending along a first direction.

[0025] This disclosure provides an electronic device, including the semiconductor device described in any of the above embodiments, or a semiconductor device formed by the manufacturing method of the semiconductor device described in any of the above embodiments.

[0026] This application includes a semiconductor device and a method for manufacturing the same, as well as an electronic device. The semiconductor device includes: multiple rows of transistors distributed along a first direction parallel to a substrate; each transistor includes semiconductor pillars extending along a direction perpendicular to the substrate; the semiconductor pillars of all odd-numbered rows of transistors form an array distributed along the first direction and a second direction parallel to the substrate; the semiconductor pillars of all even-numbered rows of transistors form an array distributed along the first direction and the second direction; and the semiconductor pillars of odd-numbered rows of transistors are staggered from those of even-numbered rows of transistors in the second direction, wherein the first direction and the second direction are perpendicular; and multiple bit lines extending along the second direction, with transistors in the same column connected to the same bit line. The solution provided in this embodiment, by setting transistors with staggered column directions, can avoid misaligned etching during the formation of node contact electrodes, reducing process difficulty and improving yield. Other features and advantages of this application will be set forth in the following description and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the methods described in the description and drawings.

[0027] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0028] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0029] Figure 1A A top view of a semiconductor device provided as an exemplary embodiment. Figure 1B For along Figure 1A A schematic diagram of the direction aa' in the middle; Figure 1C For along Figure 1A A schematic diagram of the direction of bb' in the middle; Figure 1D For along Figure 1A A schematic diagram in the cc' direction; Figure 1E For along Figure 1A A schematic diagram of the dd' direction;

[0030] Figure 2A A three-dimensional schematic diagram of a semiconductor device is provided as an exemplary embodiment;

[0031] Figure 2B A three-dimensional schematic diagram of a semiconductor device is provided for another exemplary embodiment;

[0032] Figure 3A A cross-sectional view in the aa' direction after the formation of the first trench, provided as an exemplary embodiment. Figure 3B To form a cross-sectional view in the bb' direction after the first trench is formed, Figure 3CTo form a cross-sectional view in the cc' direction after the first trench is formed, Figure 3D A cross-sectional view in the dd' direction after the first trench is formed;

[0033] Figure 4A A cross-sectional view in the aa' direction after forming a bit line, provided as an exemplary embodiment. Figure 4B To form a cross-sectional view in the bb' direction after the bit line. Figure 4C To form a cross-sectional view in the cc' direction after the bit line, Figure 4D To form a cross-sectional view in the dd' direction after the bit line is formed;

[0034] Figure 5A A top view provided as an exemplary embodiment after the formation of the first sub-pattern. Figure 5B To form the cross-sectional view in the aa' direction after the first sub-pattern is formed. Figure 5C To form the cross-sectional view in the bb' direction after the first sub-pattern is formed. Figure 5D To form the cross-sectional view in the cc' direction after the first sub-pattern is formed. Figure 5E To form the first sub-pattern dd', a cross-sectional view is shown in the direction.

[0035] Figure 6A A top view of the patterned part provided as an exemplary embodiment. Figure 6B This is a cross-sectional view along the aa' direction after the pattern has been formed. Figure 6C This is a cross-sectional view in the bb' direction after the pattern has been formed. Figure 6D This is a cross-sectional view in the cc' direction after the pattern has been formed. Figure 6E This is a cross-sectional view in the dd' direction after the pattern has been formed;

[0036] Figure 7A A cross-sectional view in the aa' direction after forming a semiconductor pillar is provided as an exemplary embodiment. Figure 7B To form a cross-sectional view of the semiconductor pillar in the bb' direction. Figure 7C To form a cross-sectional view of the semiconductor pillar in the cc' direction, Figure 7D To form a cross-sectional view of the semiconductor pillar in the dd' direction;

[0037] Figure 8A A cross-sectional view in the aa' direction after forming the third trench is provided as an exemplary embodiment. Figure 8B To form the cross-sectional view in the bb' direction after the third trench is formed, Figure 8C To form a cross-sectional view in the cc' direction after the third trench is formed, Figure 8D A cross-sectional view in the dd' direction after the formation of the third trench;

[0038] Figure 9A A cross-sectional view along direction aa' after forming the third and fourth insulating layers is provided as an exemplary embodiment. Figure 9B The cross-sectional view in the bb' direction after the formation of the third and fourth insulating layers is shown. Figure 9CThe cross-sectional view in the cc' direction after the formation of the third and fourth insulating layers is shown. Figure 9D Cross-sectional view in the dd' direction after the formation of the third and fourth insulating layers;

[0039] Figure 10A A cross-sectional view in the aa' direction after exposing the second region, provided as an exemplary embodiment. Figure 10B This is a cross-sectional view in the bb' direction after exposing the second region. Figure 10C This is a cross-sectional view in the cc' direction after exposing the second region. Figure 10D A cross-sectional view in the dd' direction after exposing the second region;

[0040] Figure 11A A cross-sectional view in the aa' direction after forming the gate insulating layer is provided as an exemplary embodiment. Figure 11B This is a cross-sectional view in the bb' direction after the gate insulating layer has been formed. Figure 11C This is a cross-sectional view in the cc' direction after the gate insulating layer has been formed. Figure 11D Cross-sectional view in the dd' direction after the gate insulating layer is formed;

[0041] Figure 12A A cross-sectional view in the aa' direction after forming a word line is provided as an exemplary embodiment. Figure 12B To form a cross-sectional view in the bb' direction after the word line is formed. Figure 12C To form a cross-sectional view in the cc' direction after the word line is formed, Figure 12D This is a cross-sectional view of the dd' direction after the word line is formed;

[0042] Figure 13A A cross-sectional view in the aa' direction after forming the sixth insulating layer is provided as an exemplary embodiment. Figure 13B The cross-sectional view in the bb' direction after the formation of the sixth insulating layer. Figure 13C This is a cross-sectional view in the cc' direction after the formation of the sixth insulating layer. Figure 13D This is a cross-sectional view in the dd' direction after the formation of the sixth insulating layer. Detailed Implementation

[0043] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the embodiments of this disclosure and the features thereof can be combined arbitrarily with each other.

[0044] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains.

[0045] The embodiments disclosed herein are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect actual proportions. Furthermore, the drawings schematically illustrate ideal examples, and the embodiments of this disclosure are not limited to the shapes or values ​​shown in the drawings.

[0046] The ordinal numbers “first,” “second,” “third,” etc., used in this disclosure are provided to avoid confusion among the constituent elements and do not indicate any order, quantity, or importance.

[0047] In this disclosure, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of the specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the direction in which each constituent element is described. Therefore, the disclosure is not limited to the terms used herein and may be appropriately replaced as appropriate.

[0048] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to physical or signal connections, contact or integral connections; direct connections, indirect connections via intermediate components, or internal communication between two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure according to the specific circumstances.

[0049] In this disclosure, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0050] In this disclosure, the first electrode may be the drain electrode and the second electrode may be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this disclosure, the "source electrode" and the "drain electrode" can be interchanged.

[0051] In this disclosure, "connection" includes the situation where constituent elements are connected together by a component having some electrical function. There are no particular limitations on the "component having some electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "component having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0052] In this disclosure, "parallel" means approximately parallel or nearly parallel, for example, two straight lines forming an angle of -10° or more and less than 10°, and therefore also includes angles of -5° or more and less than 5°. Similarly, "perpendicular" means approximately perpendicular, for example, two straight lines forming an angle of 80° or more and less than 100°, and therefore also includes angles of 85° or more and less than 95°.

[0053] In this embodiment of the disclosure, "A and B are an integral structure" can refer to a structure without obvious boundaries such as discontinuities or gaps in its microstructure. Generally, an integral structure is formed by patterning interconnected membrane layers on a single membrane layer. For example, A and B may be formed using the same material as a single membrane layer and simultaneously created through the same patterning process, resulting in a structure with an interconnected relationship.

[0054] In this embodiment of the disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0055] In some technical solutions, transistors are implemented using buried channels or vertical MOSFETs. From a top view, the transistors are mainly arranged in a square stack, while the capacitors connected to the transistors are arranged in a hexagonal close-packed configuration to improve capacitor space utilization. However, this also introduces the problem of designing staggered node contacts for the connections between the transistors and capacitors, which is technically challenging and affects device yield. In the embodiments of this disclosure, the transistors are arranged in a hexagonal close-packed or near-hexagonal close-packed configuration, thus eliminating the need for staggered node contacts, reducing process complexity, and improving device yield.

[0056] In this disclosure, substrate 1 has two main surfaces and a side surface between the main surfaces. The two main surfaces are an upper surface and a lower surface disposed opposite to each other. The upper surface is the surface on which the transistor is disposed. Parallel to substrate 1 means parallel to the lower surface of substrate 1, and perpendicular to substrate 1 means perpendicular to the lower surface of substrate 1. Before the semiconductor pillar 10 is formed, substrate 1 refers to the entire substrate (including the semiconductor region used to manufacture the semiconductor pillar 10). After the semiconductor pillar 10 is formed, substrate 1 refers to the region in the entire substrate located below the transistor.

[0057] Figure 1A A top view of a semiconductor device provided as an exemplary embodiment. Figure 1B For along Figure 1A A schematic diagram of the direction aa' in the middle. Figure 1C For along Figure 1A A schematic diagram of the bb' direction. Figure 1D For along Figure 1A A schematic diagram in the cc' direction. Figure 1E For along Figure 1A A schematic diagram of the dd' direction. The cc' and dd' directions are parallel to the first direction X, and the aa' and bb' directions are parallel to the second direction Y. (See diagram below.) Figures 1A to 1E As shown, this disclosure provides a semiconductor device, including:

[0058] A plurality of rows of transistors are distributed along a first direction X parallel to the substrate 1. Each transistor includes a semiconductor pillar 10 extending along a direction perpendicular to the substrate 1. The semiconductor pillar 10 has a main surface, which is a side surface or sidewall, and also includes an end, which is the top end of the semiconductor pillar 10. The semiconductor pillar 10 can be formed by epitaxy on the substrate 1 or by etching trenches on the substrate 1, so that the other end of the semiconductor pillar 10 can be connected to the substrate 1 as an integral structure.

[0059] The semiconductor pillars 10 of all odd-numbered rows of transistors are arranged in an array along the first direction X and along the second direction Y parallel to the substrate 1, and the semiconductor pillars 10 of all even-numbered rows of transistors are arranged in an array along the first direction X and the second direction Y, and the semiconductor pillars 10 of the odd-numbered rows of transistors are offset from the semiconductor pillars 10 of the even-numbered rows of transistors in the second direction Y, and the first direction X and the second direction Y are perpendicular.

[0060] Multiple bit lines 30 extending along the second direction Y, with transistors in the same column connected to the same bit line 30; the multiple bit lines 30 may be distributed at intervals along the first direction X;

[0061] Multiple word lines 40 extending along the first direction X, with transistors in the same row connected to the same word line 40; the multiple word lines 40 may be spaced apart along the second direction Y.

[0062] The solution provided in this embodiment staggers transistors in different rows in the direction of bit line extension. When connected to a capacitor, it can improve the utilization of capacitor space without designing misaligned node contacts or reducing the degree of misalignment, thereby reducing process difficulty and improving yield.

[0063] In some embodiments, every two adjacent columns of transistors may share a single bit line 30. For example... Figure 1A As shown, adjacent transistors on both sides of the same bit line 30 are connected to the bit line 30. The solution provided in this embodiment can reduce the number of bit lines, and the transistors in adjacent columns share the same bit line, resulting in a more compact structure and improved space utilization.

[0064] In some embodiments, each bit line 30 is disposed between semiconductor pillars 10 of two columns of transistors sharing the bit line 30. Compared to a scheme where the bit line 30 is disposed at the bottom of the semiconductor pillars 10, the bit line 30 does not need to cover the area where the two columns of semiconductor pillars 10 are located, which can reduce the width of the bit line 30 along the first direction X, and makes it less likely to form voids when forming the bit line 30.

[0065] In some embodiments, along the extending direction of the semiconductor pillar 10, the sidewalls of the semiconductor pillar 10 may include a first region 12, a channel region 11, and a second region 13 sequentially distributed, with the first region 12 disposed on the side of the channel region 11 facing the substrate 1. The bit line 30 is connected to the first region 12 of the semiconductor pillar 10, which shares the bit line 30 with two rows of transistors. It can be understood that the sidewalls near both ends of the semiconductor pillar 10 are the first region 12 and the second region 13, and the region between the first region 12 and the second region 13 is the channel region 11. The channel region 11 can be roughly distinguished from the first region 12 and the second region 13 by the position of the gate electrode, or by the difference in conductivity between the first region 12 and the second region 13 and the channel region 11.

[0066] In this embodiment, the bit line is disposed on the sidewall of the semiconductor pillar. In one technical solution, isotropic etching is used to form a bit line trench at the bottom of the silicon pillar, and metal is filled in the trench to form the bit line. However, this trench has a large aspect ratio, which is difficult to process and may form voids, resulting in high resistance. Furthermore, it is difficult to form the metal silicide for ohmic contacts. In this embodiment, the bit line can be formed on the sidewall of the semiconductor pillar. Compared with the solution of placing the bit line at the bottom of the semiconductor pillar, this reduces the aspect ratio of the bit line trench, reduces the difficulty of bit line filling, and can reduce bit line resistance. In addition, it is easier to form metal silicide to achieve ohmic contacts and reduce contact resistance.

[0067] In some embodiments, the semiconductor pillar 10 extending in a direction perpendicular to the substrate 1 can be understood as extending only in a direction perpendicular to the substrate 1, and the sidewalls of the semiconductor pillar 10 may have regions extending in a direction parallel to the substrate 1.

[0068] In some embodiments, the dimensions and shapes of the cross-section of the channel region 11 in the direction parallel to the substrate 1 may be approximately the same at different locations. It can be understood that the channel region 11 of the semiconductor pillar 10 is a continuously smooth curved surface, and the cross-sectional shapes of the curved surface at different locations are similar, but their sizes may differ.

[0069] In some embodiments, the dimensions and shapes of the cross-section of the second region 12 in the direction parallel to the substrate 1 may be approximately the same at different locations. It can be understood that the second region 12 of the semiconductor pillar 10 is a continuously smooth curved surface, and the cross-sectional shapes at different locations of the curved surface are similar, but their sizes may differ.

[0070] In some embodiments, in two columns of semiconductor pillars 10 connected to the same bit line 30, the sidewall of the first region 12 of any column of semiconductor pillars 10 facing the other column of semiconductor pillars 10 includes a first sub-region 121 extending in a direction perpendicular to the substrate 1, a second sub-region 122 extending from the first sub-region 121 in a direction away from the other column of semiconductor pillars 10, and a third sub-region 123 extending from the second sub-region 122 in a direction perpendicular to the substrate. The third sub-region 123 is disposed on the side of the first sub-region 121 away from the substrate 1. The bit line 30 is connected to the regions of the second sub-region 122 and the third sub-region 123 adjacent to the second sub-region 122, but not connected to the first sub-region 121. Figure 1D As shown, the semiconductor pillar 10 forms a platform on the side facing another column of semiconductor pillars 10 (another column of semiconductor pillars 10 sharing the same bit line), and the bit line 30 is disposed on this platform. The bit line 30 does not cover the area of ​​the third sub-region 123 away from the second sub-region 122, so as to prevent the bit line 30 and the word line 40 from connecting.

[0071] In some embodiments, two rows of semiconductor pillars 10 sharing the same bit line 30 are connected, and a pillar extending along the second direction Y is formed between the two rows of semiconductor pillars 10, with the bit line 30 disposed on the pillar. That is, the aforementioned platforms are connected to each other to form a pillar, and the bit line 30 is disposed on the pillar.

[0072] In some embodiments, the semiconductor device further includes: a plurality of first trenches T1 extending along a second direction Y, each first trench T1 having a bit line 30 disposed therein, two columns of transistors disposed between adjacent first trenches T1 being respectively connected to the bit lines 30 in the adjacent first trenches T1, and the depth h1 of the first trench T1 being less than the height h2 of the semiconductor pillars 10, the sidewalls of the two columns of semiconductor pillars 10 adjacent to the first trench T1 forming the bottom wall and sidewall of the first trench T1. That is, a first trench T1 is disposed between two columns of semiconductor pillars connecting the same bit line 30, and the bit line 30 is formed in the first trench T1, and the depth of the first trench T1 is less than the height of the semiconductor pillars 10, which can avoid a large aspect ratio and reduce the difficulty of bit line filling.

[0073] In some embodiments, the dimension of the bit line 30 along the first direction X is smaller than the dimension of the bit line 30 along the direction perpendicular to the substrate 1. Compared to the scheme of forming the bit line at the bottom of the semiconductor pillar, which has a limited bit line height due to the difficulty of filling, the scheme provided in this embodiment has a lower process difficulty because the bit line is formed on the sidewall of the semiconductor pillar. Therefore, the height of the bit line can be increased and the width of the bit line can be reduced, thereby reducing the area occupied by the transistor without increasing the resistance of the bit line.

[0074] In some embodiments, the orthographic projections of the channel region 11 and the second region 13 onto the substrate 1 may fall within the orthographic projection of the first region 12 onto the substrate 1. That is, the cross-sectional area of ​​the channel region 11 and the second region 13 of the semiconductor pillar may be smaller than the cross-sectional area of ​​the first region 11.

[0075] In some embodiments, the transistor may further include a gate electrode surrounding the channel region 11, wherein the gate electrodes of transistors in the same row are connected to form a word line 40 extending along a first direction. A gate insulating layer 24 is disposed between the word line 40 and the channel region 11, surrounding the channel region 11. The gate insulating layer 24 is located between the word line 40 and the semiconductor pillar 10, insulating the word line 40 from the semiconductor pillar 10.

[0076] In one exemplary embodiment, the semiconductor device may further include an isolation structure filled between transistors, the isolation structure including at least one of silicon oxide, silicon nitride, silicon oxynitride, etc.

[0077] Figure 2A A three-dimensional schematic diagram of a semiconductor device provided for another exemplary embodiment. (e.g.) Figure 2A As shown, the semiconductor device includes multiple rows and columns of transistors. The arrangement of the transistors is the same as in the previous embodiment. Each transistor includes a semiconductor pillar 10 extending perpendicular to the substrate 1. The semiconductor device may further include multiple node contact electrodes 50 disposed on the surface of the multiple semiconductor pillars 10 away from the substrate 1 and respectively connected to the multiple semiconductor pillars 10. The arrangement of the multiple node contact electrodes 50 is consistent with the arrangement of the multiple transistors. That is, in this embodiment, the node contact electrodes 50 do not need to be etched at different positions and can be directly formed on the upper surface of the semiconductor pillars 10, reducing the process difficulty. In this embodiment, the morphology of the semiconductor pillars 10 differs from that in the previous embodiment and is only for illustration. Please refer to the previous embodiment for the actual structure.

[0078] Figure 2B A three-dimensional schematic diagram of a semiconductor device provided for another exemplary embodiment. (e.g.) Figure 2BAs shown, the semiconductor device includes multiple memory cells. Each memory cell includes a transistor and a capacitor 60 disposed on the side of the transistor away from the substrate 1. The transistor and capacitor 60 are connected via node contact electrodes 50. The transistor arrangement is the same as in the previous embodiment. The capacitor 60 is disposed on the side of the node contact electrode 50 away from the transistor. One capacitor 60 is connected to the surface of one node contact electrode 50 opposite to the transistor, and the arrangement of the multiple capacitors 60 is consistent with the arrangement of the multiple transistors. In this embodiment, the transistor arrangement can be adapted to the capacitor arrangement. While ensuring the largest possible capacitor area, there is no need for misalignment etching or to reduce the degree of misalignment, thus reducing the process difficulty.

[0079] The technical solution of this embodiment is further illustrated below through the manufacturing process of the semiconductor device in this embodiment. The "patterning process" mentioned in this embodiment includes deposition of a film layer, coating with photoresist, mask exposure, development, etching, and photoresist stripping, which are mature manufacturing processes in related technologies. The "photolithography process" mentioned in this embodiment includes coating of a film layer, mask exposure, and development, which are mature manufacturing processes in related technologies. Deposition can employ known processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; and etching can employ known methods, without specific limitations. In the description of this embodiment, it should be understood that a "thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process or photolithography process during the entire manufacturing process, it can also be called a "layer." If the "thin film" requires a patterning process or photolithography process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process or photolithography process contains at least one "pattern."

[0080] In one exemplary embodiment, the manufacturing process of the semiconductor device may include:

[0081] 1) Formation of the first trench T1;

[0082] A substrate 1 is provided, and the substrate 1 is etched to form a plurality of first trenches T1 extending along the second direction Y, such as Figure 3A , Figure 3B , Figure 3C and Figure 3D As shown, where, Figure 3A To form a cross-sectional view in the aa' direction after the first trench T1, Figure 3B To form a cross-sectional view in the bb' direction after the first trench T1, Figure 3C To form a cross-sectional view in the cc' direction after the first trench T1, Figure 3DThis is a cross-sectional view along the dd' direction after the formation of the first trench T1. The plurality of first trenches T1 are spaced apart along the first direction X. Subsequently, bit lines 30 can be formed in the first trenches T1.

[0083] In some embodiments, the substrate 1 may be a semiconductor substrate; for example, it may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), at least one III-V compound semiconductor material (e.g., a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, etc.), at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art.

[0084] 2) Form bit line 30;

[0085] The formation of the bit line 30 may include: sequentially depositing a first interconnect layer film and a first conductive film within the first trench T1, and etching the first interconnect layer film and the first conductive film to a preset height to form the bit line 30. Figure 4A , Figure 4B , Figure 4C and Figure 4D As shown, where, Figure 4A To form a cross-sectional view in the direction of aa' after bit line 30. Figure 4B To form a cross-sectional view in the bb' direction after bit line 30. Figure 4C To form a cross-sectional view in the cc' direction after bit line 30, Figure 4D A cross-sectional view in the dd' direction is shown after bit line 30 is formed. Bit line 30 may include an adhesive sublayer 31 formed by a connecting layer thin film and a conductive sublayer 32 formed by a first conductive thin film.

[0086] In some embodiments, the first bonding layer film may be, for example, TiN, which can enhance the adhesion between the bit line 30 and the subsequently formed semiconductor pillar.

[0087] In some embodiments, the first conductive thin film may be one or more of the following different types of materials:

[0088] For example, it contains metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; it can also be a metal alloy containing these metals.

[0089] Alternatively, it can be conductive metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as conductive metal oxide materials like indium tin oxide (ITO), indium zinc oxide (IZO), and indium oxide (InO); or conductive metal nitride materials like titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), and titanium aluminum nitride (TiAlN).

[0090] Alternatively, it could be polycrystalline silicon, silicon, germanium, silicon-germanium, etc., which become conductive after doping.

[0091] The second conductive film is similar to the first conductive film and will not be described in detail.

[0092] In some embodiments, chemical vapor deposition (CVD) or ALD processes can be used to deposit the interconnect layer thin film and the first conductive thin film.

[0093] In some embodiments, a metal silicide can also be formed by an annealing process to reduce the contact resistance between bit line 30 and semiconductor pillar 10.

[0094] 3) Form the first sub-pattern 41;

[0095] A first insulating film is spin-coated onto the substrate 1 on which the aforementioned structure is formed to form a first insulating layer 2; the first insulating layer 2 fills the first trench T1 and covers the substrate 1.

[0096] A first hard mask film is deposited to form a first hard mask layer 3, and the first hard mask layer 3 covers the first insulating layer 2;

[0097] A second hard mask film is deposited, and the first sub-pattern 41 is formed, as shown. Figure 5A , Figure 5B , Figure 5C , Figure 5D and Figure 5E As shown, where, Figure 5A To form a top view after the first sub-pattern 41 is created, Figure 5B To form the cross-sectional view in the aa' direction after the first sub-pattern 41 is formed, Figure 5C To form the cross-sectional view in the bb' direction after the first sub-pattern 41 is formed, Figure 5D To form the first sub-pattern 41, a cross-sectional view in the cc' direction is generated. Figure 5E A cross-sectional view in the dd' direction after forming the first sub-pattern 41. The material of the second hard mask film is different from that of the first hard mask film. Figure 5A Only bit line 30 and the first sub-pattern 41 are shown. (See image.) Figure 5A As shown, the first sub-pattern 41 includes a plurality of first strip-shaped portions extending along a third direction, wherein the third direction forms an angle greater than 0 and less than 90 degrees with the second direction Y.

[0098] In some embodiments, the first insulating film may be a low-k material, such as silicon dioxide (SiO2).

[0099] In some embodiments, the first hard mask film is, for example, polycrystalline silicon, and the second hard mask film can be a low-k material, such as silicon dioxide (SiO2).

[0100] 4) Form the second sub-pattern 42;

[0101] A third hard mask thin film is spin-coated onto the substrate 1 on which the aforementioned structure is formed, thereby patterning and forming the third hard mask layer 5.

[0102] Backfill with the second hard mask film to form the second sub-pattern 42; the second sub-pattern 42 and the first sub-pattern 41 constitute pattern 4, as shown in the figure. Figure 6A , Figure 6B , Figure 6C , Figure 6D and Figure 6E As shown, where, Figure 6A To form a top view of pattern 4, Figure 6B To form a cross-sectional view in the aa' direction after pattern 4 is formed. Figure 6C To form a cross-sectional view in the bb' direction after pattern 4 is formed. Figure 6D To form a cross-sectional view in the cc' direction after pattern 4 is formed. Figure 6E This is a cross-sectional view along the dd' direction after pattern 4 is formed. Among them, Figure 6A Only bit line 30, first sub-pattern 41 and second sub-pattern 42 are shown.

[0103] like Figure 6A As shown, the second sub-pattern 42 includes multiple second strip-shaped portions extending along a fourth direction. The fourth direction forms an angle greater than 0 and less than 90 degrees with the third direction, for example, an angle of 30 to 60 degrees. Subsequent etching of the substrate 1 covered by the first and second strip-shaped portions forms multiple rows of semiconductor pillars 10 arranged along the first direction X, with adjacent rows of semiconductor pillars 10 staggered in the second direction Y. The orthographic projection of the first trench T1 may overlap with the orthographic projection of the intersection of the first and second strip-shaped portions. The first and second strip-shaped portions divide the substrate 1 into multiple rhomboid regions, and the same rhomboid region is located on the same side of the first trench T1; that is, the rhomboid region is not divided into two parts by the first trench T1. The position of the first trench T1 can be referenced to the position of the bit line 30, and the rhomboid region is not divided into two parts by the bit line 30.

[0104] In some embodiments, the third hard mask film may be, for example, a spin-coated hard mask (SOH).

[0105] 5) Form semiconductor pillar 10;

[0106] Using pattern 4 as a mask, the area of ​​substrate 1 not covered by pattern 4 is etched to form multiple second trenches T2 extending perpendicular to the direction of substrate 1. These multiple second trenches T2 divide the substrate 1 to form multiple semiconductor pillars 10. The multiple semiconductor pillars 10 are arranged in a hexagonal close-packed configuration; the shape of the multiple second trenches T2 is referenced to... Figure 6A The shape of pattern 4. The depth of the second trench T2 along the direction perpendicular to the substrate 1 is greater than the depth of the first trench T1 along the direction perpendicular to the substrate 1.

[0107] A second insulating film is deposited or coated, and then ground smooth to form a second insulating layer 6. The second insulating layer 6 fills the second trench T2, such as... Figure 7A , Figure 7B , Figure 7C and Figure 7D As shown, where, Figure 7A To form a cross-sectional view in the aa' direction after semiconductor pillar 10, Figure 7B To form a cross-sectional view of semiconductor pillar 10 in the bb' direction, Figure 7C To form a cross-sectional view in the cc' direction after semiconductor pillar 10, Figure 7D A cross-sectional view of the dd' direction after forming semiconductor pillar 10.

[0108] In some embodiments, the second insulating film may be a low-k material, such as silicon dioxide (SiO2).

[0109] In the solution provided in this embodiment, the second trench T2 is filled with low-k material. Compared with the solution where the bit line 30 is located at the bottom of the semiconductor pillar 10, the low-k material spacing between the bit line 30 and the word line can reduce the parasitic capacitance between the bit line 30 and the word line 40.

[0110] 6) Formation of the third trench T3;

[0111] The formation of the third trench T3 may include: forming a plurality of third trenches T3 extending along a first direction X on the substrate 1 on which the aforementioned structure is formed, the plurality of third trenches T3 being spaced apart along a second direction Y, and a row of semiconductor pillars 10 between adjacent third trenches T3, such as... Figure 8A , Figure 8B , Figure 8C and Figure 8D As shown, where, Figure 8A To form the cross-sectional view in the aa' direction after the third trench T3, Figure 8B To form the cross-sectional view in the bb' direction after the third trench T3, Figure 8C To form the cross-sectional view in the cc' direction after the third trench T3, Figure 8DThis is a cross-sectional view in the dd' direction after the third trench T3 is formed. The bottom wall of the third trench T3 exposes the bit line 30, meaning that when etching to form the third trench T3, the etching stops at the upper surface of the bit line 30 (the surface away from the substrate 1). The third trench T3 can isolate different word lines 40 in the same layer. Figure 8A As shown, there are two third trenches T3 between adjacent semiconductor pillars 10 in the same column. This is because there is another row of semiconductor pillars 10 between adjacent semiconductor pillars 10 in the same column, so two third trenches T3 are needed for spacing. When forming the third trenches T3, in addition to etching the second insulating layer 6, the semiconductor pillars 10 formed in step 5 are also etched, so that the width of the semiconductor pillars 10 along the second direction Y is thinned.

[0112] In some embodiments, the semiconductor pillar 10 may be thinned to the same width on both sides along the second direction Y.

[0113] 7) Form the third insulating layer 7 and the fourth insulating layer 8;

[0114] A third insulating film is deposited in the third trench T3 to form a third insulating layer 7, which covers the inner wall (bottom wall and side wall) of the third trench T3;

[0115] A fourth insulating film is deposited in the third trench T3 where the third insulating layer 7 is formed, to form a fourth insulating layer 8 that fills the third trench T3, such as... Figure 9A , Figure 9B , Figure 9C and Figure 9D As shown, where, Figure 9A The cross-sectional view in the aa' direction after the formation of the third insulating layer 7 and the fourth insulating layer 8 is shown. Figure 9B A cross-sectional view in the bb' direction after the formation of the third insulating layer 7 and the fourth insulating layer 8. Figure 9C A cross-sectional view in the cc' direction after the formation of the third insulating layer 7 and the fourth insulating layer 8. Figure 9D Cross-sectional view in the dd' direction after the formation of the third insulating layer 7 and the fourth insulating layer 8.

[0116] In some embodiments, the third insulating film may be a low-k material, such as silicon dioxide (SiO2).

[0117] In some embodiments, the fourth insulating film may be a material with an etching selectivity ratio to the third insulating film, such as SiN. When the channel region 11 is exposed to form word lines 40, the fourth insulating layer 8 located in the third trench T3 will not be etched away, thereby isolating word lines 40 in different rows.

[0118] 8) Expose the second area 13;

[0119] The second insulating layer 6 and the third insulating layer 7 are etched to expose the second region 13 of the semiconductor pillar 10;

[0120] A fifth insulating film is deposited on the substrate 1 on which the aforementioned structure is formed, and the fifth insulating film is etched to form a fifth insulating layer 9, as shown below. Figure 10A , Figure 10B , Figure 10C and Figure 10D As shown, where, Figure 10A To expose the cross-sectional view in the direction of aa' after the second region 13 is exposed. Figure 10B To expose the cross-sectional view of the second region 13 in the bb' direction, Figure 10C To expose the cross-sectional view in the cc' direction after region 13 of the second region, Figure 10D This is a cross-sectional view in the dd' direction after exposing the second region 13. The fifth insulating layer 9 covers the second region 13 of the semiconductor pillar 10 to protect it. The fifth insulating layer 9 has a via K1, which exposes the surface of the first insulating layer 2 away from the substrate 1 and the surface of the second insulating layer 6 away from the substrate 1. This allows for subsequent etching of the first insulating layer 2 and the second insulating layer 6 through the via K1, thereby exposing the channel region 11 of the semiconductor pillar 10.

[0121] In some embodiments, the fifth insulating film may be an insulating material with an etching selectivity ratio to the second insulating film, such as SiN, to facilitate the protection of the semiconductor 10 in the second region 13 when the semiconductor pillar 10 is subsequently exposed on the sidewall of the channel region 11.

[0122] In some embodiments, the second insulating layer 6 and the third insulating layer 7 can be etched by wet etching.

[0123] 9) Forming a gate insulating layer 24;

[0124] The first insulating layer 2 and the second insulating layer 6 are etched through the via K1 to expose the channel region 11 of the semiconductor pillar 10;

[0125] A gate insulating film is deposited to form a gate insulating layer 24; the gate insulating layer 24 surrounds the sidewall of the semiconductor pillar 10, covers the channel region 11 of the semiconductor pillar 10, and covers the surface of the semiconductor pillar 10 away from the substrate 1, such as... Figure 11A , Figure 11B , Figure 11C and Figure 11D As shown, where, Figure 11A This is a cross-sectional view in the aa' direction after the gate insulating layer 24 is formed. Figure 11B A cross-sectional view in the bb' direction after the gate insulating layer 24 is formed. Figure 11C A cross-sectional view in the cc' direction after the gate insulating layer 24 is formed. Figure 11D Cross-sectional view in the dd' direction after the gate insulating layer 24 is formed.

[0126] In some embodiments, the gate insulating layer 24 may be formed by atomic layer deposition (ALD) and in-situ steam generation (ISSG) methods.

[0127] In some embodiments, the gate insulating layer 24 may comprise one or more high-K dielectric materials, such as dielectric materials with a dielectric constant K ≥ 3.9. In some embodiments, it may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplarily, for example, it may include, but is not limited to, at least one of the following high-K materials: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), etc.

[0128] 10) Forming a character line 40;

[0129] A second interconnect layer film and a second conductive film are sequentially deposited, and the second interconnect layer film and the second conductive film are etched to the bottom of the second region 13 to form a word line 40 extending along the first direction X, that is, so that the word line 40 only surrounds the channel region 11 of the semiconductor pillar 10, such as... Figure 12A , Figure 12B , Figure 12C and Figure 12D As shown, where, Figure 12A To form a cross-sectional view in the direction of aa' after word line 40, Figure 12B To form a cross-sectional view in the bb' direction after word line 40. Figure 12C To form a cross-sectional view in the cc' direction after the word line 40, Figure 12D This is a cross-sectional view in the dd' direction after word line 40 is formed. Word line 40 may include a second adhesive sublayer formed by a second interconnecting layer thin film and a second conductive sublayer formed by a second conductive thin film. A portion of word line 40 may serve as the gate electrode of a transistor, and the gate electrodes of transistors in the same row are connected to form one word line 40.

[0130] In some embodiments, the second bonding layer film may be, for example, TiN, which can enhance the adhesion between the word line 40 and the gate insulating layer 24.

[0131] 11) Form the sixth insulating layer 14;

[0132] A sixth insulating film is deposited on the substrate 1 on which the aforementioned structure is formed, forming a sixth insulating layer 14; the sixth insulating layer 14 fills the via K1, such as... Figure 13A , Figure 13B , Figure 13C and Figure 13DAs shown, where, Figure 13A A cross-sectional view in the aa' direction after the formation of the sixth insulating layer 14. Figure 13B To form the cross-sectional view in the bb' direction after the sixth insulating layer 14 is formed, Figure 13C To form the cc' direction cross-sectional view after the sixth insulating layer 14 is formed, Figure 13D Cross-sectional view in the dd' direction after the formation of the sixth insulating layer 14.

[0133] In some embodiments, the sixth insulating film may be a low-k material, such as SiN.

[0134] This disclosure also provides an electronic device, including the semiconductor device described in the foregoing embodiments. The electronic device may be a storage device, smartphone, computer, tablet computer, artificial intelligence device, wearable device, or power bank, etc. The storage device may include memory in a computer, etc., and is not limited thereto.

[0135] While the embodiments disclosed in this invention are as described above, the content is merely for the purpose of facilitating understanding of the invention and is not intended to limit the invention. Any person skilled in the art to which this invention pertains may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this invention shall still be determined by the scope defined in the appended claims.

Claims

1. A semiconductor device, characterized in that, include: A plurality of rows of transistors are distributed along a first direction parallel to a substrate, the transistors including semiconductor pillars extending along a direction perpendicular to the substrate, the semiconductor pillars of all odd-numbered rows of transistors forming an array distributed along the first direction and along a second direction parallel to the substrate, the semiconductor pillars of all even-numbered rows of transistors forming an array distributed along the first direction and the second direction, and the semiconductor pillars of the odd-numbered rows of transistors are offset from the semiconductor pillars of the even-numbered rows of transistors in the second direction, the first direction and the second direction being perpendicular; Multiple bit lines extending along the second direction, with transistors in the same column connected to the same bit line; every two adjacent columns of transistors share one bit line; Along the extension direction of the semiconductor pillar, the sidewall of the semiconductor pillar includes a first region, a channel region, and a second region distributed sequentially, and the first region is disposed on the side of the channel region facing the substrate, and the bit line is connected to the first region of the semiconductor pillar of two columns of transistors sharing the bit line.

2. The semiconductor device according to claim 1, characterized in that, Each bit line is disposed between the semiconductor pillars of two columns of transistors sharing the bit line.

3. The semiconductor device according to claim 1, characterized in that, In two columns of semiconductor pillars connected to the same bit line, the sidewall of the first region of any column of semiconductor pillars facing the other column of semiconductor pillars includes a first sub-region extending in a direction perpendicular to the substrate, a second sub-region extending from the first sub-region in a direction away from the other column of semiconductor pillars, and a third sub-region extending from the second sub-region in a direction perpendicular to the substrate. The third sub-region is disposed on the side of the first sub-region away from the substrate. The bit line is connected to the regions of the second sub-region and the third sub-region adjacent to the second sub-region, but not connected to the first sub-region.

4. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes: a plurality of first trenches extending along a second direction, each first trench having a bit line disposed therein, two columns of transistors disposed between adjacent first trenches being respectively connected to the bit lines in the adjacent first trenches, and the depth of the first trench being less than the height of the semiconductor pillars, and the sidewalls of the two columns of semiconductor pillars adjacent to the first trenches forming the bottom wall and sidewall of the first trench.

5. The semiconductor device according to claim 1, characterized in that, The dimension of the bit line along the first direction is smaller than the dimension of the bit line along the direction perpendicular to the substrate.

6. The semiconductor device according to claim 1, characterized in that, The orthographic projection of the channel region and the second region onto the substrate falls within the orthographic projection of the first region onto the substrate.

7. The semiconductor device according to claim 1, characterized in that, The transistor further includes a gate electrode surrounding the channel region, wherein the gate electrodes of transistors in the same row are connected to form word lines extending along a first direction.

8. The semiconductor device according to any one of claims 1 to 7, characterized in that, The semiconductor device further includes a plurality of node contact electrodes disposed on the surface of the plurality of semiconductor pillars on the side away from the substrate and respectively connected to the plurality of semiconductor pillars, wherein the arrangement of the plurality of node contact electrodes is consistent with the arrangement of the plurality of transistors.

9. The semiconductor device according to claim 8, characterized in that, The semiconductor device further includes a plurality of capacitors disposed on the side of the plurality of node contact electrodes away from the transistor, each capacitor being connected to a surface of the node contact electrode opposite to the transistor, and the arrangement of the plurality of capacitors being consistent with the arrangement of the plurality of transistors.

10. A method for manufacturing a semiconductor device, characterized in that, include: A substrate is provided, on which a plurality of first trenches extending in a second direction are formed, and in each of the first trenches a bit line extending in the second direction is formed; Multiple rows of semiconductor pillars extending perpendicular to the substrate are formed along a first direction, and all odd-numbered rows of semiconductor pillars form an array distributed along the first direction and a second direction, and all even-numbered rows of semiconductor pillars form an array distributed along the first direction and the second direction, with the odd-numbered rows of semiconductor pillars offset from the even-numbered rows of semiconductor pillars in the second direction; the first trench is disposed between two adjacent rows of semiconductor pillars, and the depth of the first trench is less than the height of the semiconductor pillars.

11. The method for manufacturing a semiconductor device according to claim 10, characterized in that, The semiconductor pillar is formed by forming a mask layer on the substrate, comprising a plurality of first strips extending along a third direction and a plurality of second strips extending along a fourth direction, and etching the substrate covered by the mask layer to form the semiconductor pillar, wherein the third direction intersects the first direction and the second direction, the fourth direction intersects the first direction and the second direction, and the third direction intersects the fourth direction.

12. The method for manufacturing a semiconductor device according to claim 10, characterized in that, The method further includes: forming a second trench extending along the first direction between adjacent semiconductor pillars, the bottom wall of the second trench exposing the bit line; The exposed semiconductor pillars are disposed in the channel region on the side of the bit line away from the substrate, forming a gate electrode surrounding the channel region, and the gate electrodes of the semiconductor pillars in the same row are connected to form a word line extending along a first direction.

13. An electronic device, characterized in that, It includes the semiconductor device as described in any one of claims 1 to 9, or the semiconductor device formed by the manufacturing method of the semiconductor device as described in any one of claims 10 to 12.

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