Semiconductor device

Abstract

A semiconductor device is provided. The semiconductor device includes: a first structure having a memory block region and an extension region; and a second structure having a peripheral circuit region. The first structure includes memory cells and word lines. The second structure includes: a semiconductor body; a through insulating pattern in the semiconductor body; and a peripheral transistor. The first structure and the second structure include a word line signal path electrically connecting the word line to the peripheral transistor. The word line signal path includes: a word line contact with the word line in the extension region; a word line wiring lower structure electrically connected to the word line contact and extending from the extension region into the memory block region; and a word line wiring connection structure electrically connecting the word line wiring lower structure to the word line wiring peripheral structure.

Description

Technical Field

[0001] Example embodiments of the present disclosure relate to a semiconductor device including a signal path having a through via and a method of manufacturing the same. Background Art

[0002] Research has been conducted to reduce the size of elements included in semiconductor devices and improve performance. For example, in dynamic random access memory (DRAM), research has been conducted to reliably and stably form elements with reduced size, but as the size of the elements is reduced, the performance of the semiconductor device may deteriorate. Summary of the invention

[0003] Example embodiments of the present disclosure are to provide a semiconductor device that can increase integration density and can improve performance.

[0004] According to example embodiments, a semiconductor device includes: a first structure, the first structure having a memory block region and an extension region adjacent to the memory block region in a first direction; and a second structure, the second structure vertically overlapping the first structure and having a peripheral circuit region vertically overlapping the memory block region, wherein the first structure includes memory cells and word lines, the memory cells are located in the memory block region and each of the memory cells includes a vertical channel transistor and a data storage structure, the word lines are electrically connected to the memory cells, intersect the memory block region and extend into the extension region, wherein the second structure includes a semiconductor body, a back side insulating layer, an isolation region, a through insulating pattern and a peripheral transistor, the back side insulating layer is located below the semiconductor body, the isolation region defines a peripheral active region on the semiconductor body, the through insulating pattern is located in the semiconductor body, and the peripheral transistor includes a first peripheral source / drain, a second peripheral source / drain, and a first peripheral source / drain located between the first peripheral source / drain and the second peripheral source / drain. / drain and a peripheral channel region between the first peripheral source / drain and the second peripheral source / drain and the peripheral channel region are located in a first peripheral active region among the peripheral active regions, wherein the first structure and the second structure include a word line signal path that electrically connects the word line to the peripheral transistor, wherein the word line signal path includes a word line routing peripheral structure, a word line contact, a word line routing lower structure and a word line routing connection structure, the word line routing peripheral structure is electrically connected to the peripheral transistor on the semiconductor body, the word line contact contacts the word line in the extension region, the word line routing lower structure is electrically connected to the word line contact and extends from the extension region to the storage block region, the word line routing connection structure electrically connects the word line routing lower structure to the word line routing peripheral structure, and wherein the word line routing connection structure includes a word line routing through-path that vertically overlaps the storage block region and penetrates the semiconductor body.

[0005] According to example embodiments, a semiconductor device includes: a first structure, the first structure having a memory block region and an extension region adjacent to the memory block region in a first direction; and a second structure, the second structure vertically overlapping the first structure and having a peripheral circuit region vertically overlapping the memory block region, wherein the first structure includes memory cells, word lines, and bit lines, the memory cells being located in the memory block region and each of the memory cells including a vertical channel transistor and a data storage structure, the word lines being electrically connected to the memory cells, crossing the memory block region and extending into the extension region, the bit lines being electrically connected to the memory cells and crossing the memory block region, wherein the second structure includes a semiconductor body, a first peripheral transistor, a second peripheral transistor, and a through-insulating pattern located in the semiconductor body, wherein the first structure and the second structure include a first word line signal path electrically connecting the word line to the first peripheral transistor and a bit line signal path electrically connecting the bit line to the second peripheral transistor, wherein the first structure A word line signal path includes a word line wiring through-path, a word line contact, and a word line wiring lower structure, wherein the word line wiring through-path penetrates a first through-insulating pattern among the through-insulating patterns and vertically overlaps the memory block region, the word line contact contacts the word line in the extension region, and the word line wiring lower structure electrically connects the word line contact to the word line wiring through-path, wherein the bit line signal path includes a bit line wiring through-path, a bit line contact, and a bit line wiring lower structure, wherein the bit line wiring through-path penetrates the through-insulating pattern A second through-insulating pattern among the edge patterns and vertically overlaps the storage block area, the bit line contact is in contact with the bit line, and the bit line wiring lower structure electrically connects the bit line contact to the bit line wiring through-path, wherein the lower surface of the word line wiring through-path and the lower surface of the bit line wiring through-path are located at a height lower than the height of the lower surface of the through-insulating pattern, and wherein the upper surface of the word line wiring through-path and the upper surface of the bit line wiring through-path are located at a height higher than the height of the upper surface of the through-insulating pattern.

[0006] According to an example embodiment, a semiconductor device includes: a first structure, the first structure having a first storage block area and a second storage block area adjacent to each other in a first direction, and an extension area located between the first storage block area and the second storage block area; and a second structure, the second structure vertically overlaps with the first structure and includes a first peripheral circuit area vertically overlapping with the first storage block area and a second peripheral circuit area vertically overlapping with the second storage block area, wherein the first structure includes storage cells and word lines, the storage cells are respectively located in the first storage block area and the second storage block area, and each of the storage cells includes a vertical channel transistor and a data storage structure, the word line passes through the first storage block area and the second storage block area and the extension area and is electrically connected to the storage cells located in the first storage block area and the storage cells located in the second storage block area. The memory cell, wherein the second structure comprises a semiconductor body, a peripheral transistor and a through-insulating pattern located in the semiconductor body, wherein the first structure and the second structure comprise a first word line signal path electrically connecting the word line to a first peripheral transistor among the peripheral transistors, wherein the first word line signal path comprises a word line wiring through-path, a word line contact and a word line wiring lower structure, the word line wiring through-path penetrates a first through-insulating pattern among the through-insulating patterns and vertically overlaps the first memory block region, the word line contact contacts the word line in the extension region, the word line wiring lower structure electrically connects the word line contact to the word line wiring through-path, wherein a lower surface of the word line wiring through-path is located at a lower height than a lower surface of the through-insulating pattern, and wherein an upper surface of the word line wiring through-path is located at a higher height than an upper surface of the through-insulating pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The above and other aspects, features and advantages of example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1A , Figure 1B , Figure 2A-2C , Figure 3A-3C , Figure 4A-4D , Figure 5 and Figure 6 is a diagram illustrating a semiconductor device according to an example embodiment of the present disclosure; Figure 7 is an enlarged cross-sectional view illustrating a portion of a semiconductor device according to an example embodiment of the present disclosure; Fig. 8A is an enlarged cross-sectional view illustrating a portion of a semiconductor device according to an example embodiment of the present disclosure; Figure 8B is an enlarged cross-sectional view illustrating a portion of a semiconductor device according to an example embodiment of the present disclosure; Figure 8C is an enlarged cross-sectional view illustrating a portion of a semiconductor device according to an example embodiment of the present disclosure; Fig. 9 is an enlarged cross-sectional view illustrating a semiconductor device according to an example embodiment of the present disclosure; Fig. 10A , Fig. 10B and Fig.11 is a diagram illustrating a semiconductor device according to an example embodiment of the present disclosure; Fig.12 is a cross-sectional view illustrating a semiconductor device according to an example embodiment of the present disclosure; Fig.13 is a cross-sectional view illustrating a semiconductor device according to an example embodiment of the present disclosure; Fig.14 is a cross-sectional view illustrating a semiconductor device according to an example embodiment of the present disclosure; Fig.15 is a cross-sectional view illustrating a semiconductor device according to an example embodiment of the present disclosure; Fig.16A and Fig. 16B is a cross-sectional view illustrating a semiconductor device according to an example embodiment of the present disclosure; and Figures 17A-17D , Fig.18A , Fig.18B , Fig.19A and Fig.19B is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an example embodiment of the present disclosure. DETAILED DESCRIPTION

[0008] Hereinafter, example embodiments will be described with reference to the accompanying drawings as follows.

[0009] Reference Figure 1A , Figure 1B , Figure 2A , Figure 2B and Figure 2C Examples of semiconductor devices according to example embodiments are described. Figure 1A is a perspective view illustrating an example of a semiconductor device according to example embodiments. Figure 1B It's a picture. Figure 1A A stereoscopic view of a portion of a storage body BA in FIG. Figure 2A is a circuit diagram illustrating an example of a memory block in a memory block region of a semiconductor device according to example embodiments. Figure 2B is a circuit diagram illustrating an example of a sub word line driver in a peripheral circuit region of a semiconductor device according to example embodiments. Figure 2Cis a circuit diagram illustrating an example of a sense amplifier in a peripheral circuit region of a semiconductor device according to example embodiments.

[0010] refer to Figure 1A , Figure 1B , Figure 2A , Figure 2B and Figure 2C , a semiconductor device 1 according to example embodiments may include a first structure ST1 and a second structure ST2 vertically overlapping the first structure ST1. The second structure ST2 may be disposed on the first structure ST1.

[0011] In an example embodiment, the first structure ST1 may be configured as a first chip structure including a memory cell, and the second structure ST2 may be configured as a second chip structure including a peripheral circuit for operating the memory cell MC. The first structure ST1 and the second structure ST2 may be formed by bonding via a bonding process such as a wafer bonding process. Therefore, the first structure ST1 may contact and bond to the second structure ST2.

[0012] The semiconductor device 1 may include a plurality of banks BA and an outer peripheral region PERI.

[0013] The outer peripheral region PERI may include a first peripheral region PERI1 in the first structure ST1 and a second peripheral region PERI2 in the second structure ST2. The outer peripheral region PERI may be configured as a peripheral circuit region in which peripheral circuits for data or command input / output or power / ground input are disposed.

[0014] Each of the plurality of memory banks BA may include a first memory bank region BA1 located in a first structure ST1 and a second memory bank region BA2 located in a second structure ST2 .

[0015] The first bank region BA1 located in the first structure ST1 may include a block region CA and extension regions ER1 and ER2. The extension regions ER1 and ER2 may also be referred to as connection regions.

[0016] The memory block areas CA may be arranged along a first direction X and a second direction Y. The first direction X and the second direction Y may be perpendicular to each other.

[0017] The storage block area CA may include first to fourth storage block areas CA1, CA2, CA3 and CA4 adjacent to each other. For example, the first storage block area CA1 and the second storage block area CA2 may be adjacent to each other in the second direction Y, the third storage block area CA3 and the fourth storage block area CA4 may be adjacent to each other in the second direction Y, the first storage block area CA1 and the third storage block area CA3 may be adjacent to each other in the first direction X, and the second storage block area CA2 and the fourth storage block area CA4 may be adjacent to each other in the first direction X.

[0018] The extension regions ER1 and ER2 may include a first extension region ER1 and a second extension region ER2. The first extension region ER1 may be disposed between the first storage block region CA1 and the third storage block region CA3, and may be disposed between the second storage block region CA2 and the fourth storage block region CA4. The second extension region ER2 may be disposed between the first storage block region CA1 and the second storage block region CA2, and between the third storage block region CA3 and the fourth storage block region CA4.

[0019] The second memory bank region BA2 located in the second structure ST2 may include a peripheral circuit region PC. The peripheral circuit region PC may be arranged along the first direction X and the second direction Y. The peripheral circuit region PC may overlap the memory block region CA in the vertical direction Z.

[0020] The peripheral circuit region PC may include a first peripheral circuit region PC1 vertically overlapping the first storage block region CA1, a second peripheral circuit region PC2 vertically overlapping the second storage block region CA2, a third peripheral circuit region PC3 vertically overlapping the third storage block region CA3, and a fourth peripheral circuit region PC4 vertically overlapping the fourth storage block region CA4.

[0021] Each peripheral circuit region PC may include sense amplifier regions SAR1 and SAR2, a sub word line driver region SWDR, and an internal peripheral region CONR. In each peripheral circuit region PC, the sense amplifier regions SAR1 and SAR2 may include a first sense amplifier region SAR1 and a second sense amplifier region SAR2 spaced apart from each other in the second direction Y. In each peripheral circuit region PC, the sub word line driver region SWDR and the peripheral region CONR may be disposed between the first sense amplifier region SAR1 and the second sense amplifier region SAR2. In each peripheral circuit region PC, the internal peripheral region CONR may include a control circuit for controlling the sense amplifier SA of the sense amplifier regions SAR1 and SAR2 and the sub word line driver SWD of the sub word line driver region SWDR.

[0022] Each memory block region CA may include memory cells MC arranged in first and second directions X and Y, word lines WL connected to the memory cells MC and extending in the first direction X, and bit lines BL connected to the memory cells MC and extending in the second direction Y.

[0023] The word line WL may cross the memory block region CA and may extend into the first extension region ER1 . The bit line BL may cross the memory block region CA and may extend into the second extension region ER2 .

[0024] Each memory cell MC may include a cell transistor cTR and a data storage structure DS that may function as a data storage device. In a memory such as a DRAM, the data storage structure DS may be configured as a cell capacitor that may store data.

[0025] Each memory block region CA may further include a back gate line BG. Each back gate line BG may be disposed between pairs of word lines WL adjacent to each other in the second direction Y among the word lines WL. Each back gate line BG may be disposed between channel regions of the cell transistors cTR. The back gate line BG may pass through the memory block region CA and may extend into the first extension region ER1.

[0026] Each sub word line driver region SWDR may include a sub word line driver SWD. The sub word line driver SWD may be electrically connected to the word line WL.

[0027] Each sub-word line driver SWD may include a PMOS transistor PT, a first NMOS transistor NT1, and a second NMOS transistor NT2. The drive signal PXID may be connected to the source terminal of the PMOS transistor PT, the word line WL may be electrically connected to the drain terminal of the PMOS transistor PT, and the word line enable signal NWEIB may be connected to the gate terminal of the PMOS transistor PT. The PMOS transistor PT may be configured as a pull-up transistor. A precharge voltage corresponding to the reverse bias voltage VBB2 may be connected to the source terminal of the first NMOS transistor NT1, the word line WL may be electrically connected to the drain terminal of the first NMOS transistor NT1, and the word line enable signal NWEIB may be connected to the gate terminal of the first NMOS transistor NT1. The first NMOS transistor NT1 may be configured as a pull-down transistor. The complementary drive signal PXIB may be connected to the gate terminal of the second NMOS transistor NT2, the precharge voltage corresponding to the reverse bias voltage VBB2 may be connected to the source terminal of the second NMOS transistor NT2, and the word line WL may be electrically connected to the drain terminal of the second NMOS transistor NT2. The second NMOS transistor NT2 may be configured as a holding transistor for maintaining the word line WL at a ground voltage level when the word line WL is not selected. The second NMOS transistor NT2 may be connected in parallel to the first NMOS transistor NT1. The sub-word line driver SWD may drive the word line WL in response to the word line enable signal NWEIB and the drive signal PXID. The PMOS transistor PT may pull up the word line WL to the level of the drive signal PXID in response to the word line enable signal NWEIB. The first NMOS transistor NT1 may pull down the word line WL to the level of the negative voltage VBB2 in response to the word line enable signal NWEIB. The second NMOS transistor NT2, which may be used as a holding transistor, may maintain the word line WL at the level of the negative voltage VBB2 at the time point when the word line WL is deactivated. To this end, the second NMOS transistor NT2 may switch between a source providing a negative voltage VBB2 and a drain electrically connected to the word line WL in response to a drive signal PXIB complementary to the drive signal PXID. The circuit of the sub word line driver SWD described above may be merely an example, and the circuit of the sub word line driver SWD may be implemented with various circuit elements.

[0028] The sense amplifier regions SAR1 and SAR2 may each include a sense amplifier SA. Each sense amplifier SA may include a plurality of transistors P1_a, P1_b, N1_a, and N1_b. The transistors P1_a, P1_b, N1_a, and N1_b may include transistors P1_a and P1_b as PMOS transistors and transistors N1_a and N1_b as NMOS transistors. The transistors P1_a and P1_b may be referred to as a PMOS transistor pair, and the transistors N1_a and N1_b may be referred to as an NMOS transistor pair. The source of the transistor P1_a and the source of the transistor P1_b may be connected to the first control line LA through a first node ND1_a. The source of the transistor N1_a and the source of the transistor N1_b may be connected to the second control line LAB through a second node ND1_b. The first node ND1_a and the second node ND1_b may be referred to as a first source node and a second source node, respectively. The drain of transistor P1_a and the drain of transistor N1_a can be connected to the first bit line BL1 among the bit lines BL through the first drain node ND1_c. The drain of transistor P1_b and the drain of transistor N1_b can be connected to the complementary bit line BL2 among the bit lines BL through the second drain node ND1_d. The sense amplifier SA can sense the voltage change of the first bit line BL1 and amplify it. When the sense amplifier SA performs the sensing and amplification operations, the internal power supply voltage can be applied to the first node ND1_a through the first control line LA, and the second node ND1_b can be connected to the ground terminal through the second control line LAB. The sense amplifier SA may include a PMOS transistor pair and an NMOS transistor pair, and may be implemented as a circuit element in which transistors are cross-coupled, but this is merely an example embodiment, and therefore the present disclosure is not limited thereto. For example, the circuit of the sense amplifier SA may be implemented with various circuit elements.

[0029] In the following description, reference will be made to Figure 3A , Figure 3B , Figure 3C , Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 5 and Figure 6 An example of a cross-sectional structure of the above-described semiconductor device 1 is described. Figure 3A It is a diagram showing the Figure 1B A cross-sectional view of the area cut along line II' in FIG. Figure 3B It's a picture. Figure 3A Magnified view of area "A" in FIG. Figure 3C is a cross-sectional view illustrating a word line signal path WSP. Figure 4A It is a diagram showing the Figure 1BA cross-sectional view of the area cut along line II-II' in FIG. Figure 4B It's a picture. Figure 4A Magnified view of area "B". Figure 4C is a cross-sectional view illustrating a first bit line signal path BL1SP according to example embodiments. Figure 4D is a cross-sectional view illustrating a second bit line signal path BL2SP according to example embodiments. Figure 5 is a perspective view illustrating a bit line BL and a conductive shielding structure SL according to example embodiments. Figure 6 is a cross-sectional view illustrating a signal path CPSP of a second electrode of a data storage structure DS according to example embodiments.

[0030] refer to Figures 3A to 6 as well as Figures 1A to 2C In the first stacked structure ST1, the word line WL may pass through the memory block region CA and the first extension region ER1. For example, the word line WL may pass through the first memory block region CA1, the third memory block region CA3, and the first extension region ER1 between the first memory block region CA1 and the third memory block region CA3 without being disconnected.

[0031] In the first stacked structure ST1 , the data storage structure DS may be disposed at a height lower than that of the word lines WL.

[0032] Each of the data storage structures DS may include a first electrode 127 extending in the vertical direction Z, a second electrode 131 covering a side surface and a lower surface of each first electrode 127 , and a dielectric layer 129 between the first electrode 127 and the second electrode 131 .

[0033] The data storage structure DS may be a cell capacitor that can store data in a memory such as a DRAM, but example embodiments thereof are not limited thereto. For example, the data storage structure DS may be configured as a data storage structure of a magnetoresistive RAM (MRAM) or a data storage structure of a ferroelectric RAM (FeRAM).

[0034] The first stacked structure ST1 may further include a cell active pattern cACT.

[0035] Each cell active pattern cACT may include a first source / drain region cSD1, a second source / drain region cSD2 disposed at a height different from that of the first source / drain region cSD1, and a vertical channel region cCH between the first source / drain region cSD1 and the second source / drain region cSD2. The first source / drain region cSD1 may be disposed at a height higher than that of the second source / drain region cSD2. The cell active pattern cACT may also be referred to as a cell semiconductor layer or a vertical channel layer.

[0036] Each cell transistor cTR may include a first source / drain region cSD1, a second source / drain region cSD2, a vertical channel region cCH, a word line WL opposite to the side surface of the vertical channel region cCH, and a gate dielectric layer cGO located between the cell active pattern cACT and the word line WL. The cell transistor cTR may therefore be a vertical channel transistor. In the word line WL, a portion opposite to the vertical channel region cCH may be configured as a gate electrode. The gate dielectric layer cGO may be in contact with the side surface of the vertical channel region cCH of the cell active pattern cACT, and a gate electrode portion of the word line WL may be in contact with the gate dielectric layer cGO.

[0037] The back gate line BG may face the side surface of the vertical channel region cCH. The back gate dielectric layer cBO may be disposed between the back gate line BG and the vertical channel region cCH. The vertical channel region cCH may be disposed between the back gate line BG and the word line WL. Pairs of cell active patterns cACT adjacent to each other may be disposed between pairs of word lines WL adjacent to each other, and the back gate line BG may be disposed between pairs of cell active patterns cACT adjacent to each other. The back gate line BG may be configured as a back gate electrode.

[0038] The back gate line BG may control the charge accumulated in the vertical channel region cCH. The vertical channel region cCH may be configured as a floating body disposed between the first source / drain region cSD1 and the second source / drain region cSD2, and the back gate line BG may suppress or prevent the performance degradation of the cell transistor cTR due to the floating body effect, and may improve the performance of the cell transistor cTR. For example, the back gate line BG may reduce or prevent the change in the threshold voltage of the cell transistor cTR by accumulating charge (e.g., holes) in the floating body of the vertical channel region cCH during the operation of the cell transistor cTR.

[0039] The word line WL may be formed of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, or a combination thereof, but example embodiments thereof are not limited thereto. Each word line WL may include a single layer or multiple layers of the above-mentioned conductive materials. The back gate line BG may include at least one conductive material. For example, each back gate line BG may be formed of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, or a combination thereof, but example embodiments thereof are not limited thereto. Each back gate line BG may include a single layer or multiple layers of the above-mentioned materials.

[0040] The first structure ST1 may further include a contact structure 121 electrically connecting the second source / drain region cSD2 to the first electrode 127 .

[0041] Each of the contact structures 121 may include a plug portion 112 contacting the cell active pattern cACT and a pad portion 118 located under the plug portion 112. A data storage structure DS may be disposed under the pad portion 118.

[0042] The bit line BL may be connected to the cell active pattern cACT on the cell active pattern cACT. For example, the bit line BL may be electrically connected to the first source / drain region cSD1 of the cell active pattern cACT. Therefore, the bit line BL may be electrically connected to the cell transistor cTR.

[0043] Each bit line BL may be formed of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, or a combination thereof, but example embodiments thereof are not limited thereto. Each bit line BL may include a single layer or a plurality of layers of the above-mentioned conductive materials. For example, each bit line BL may include a first conductive layer 150 and a second conductive layer 152 located on the first conductive layer 150. The first conductive layer 150 may include doped silicon, and the second conductive layer 152 may include a conductive material having a resistivity lower than that of the doped silicon among the aforementioned conductive materials.

[0044] The first structure ST1 may further include a conductive shielding structure SL including line portions LP alternately arranged with the bit lines BL and connection portions PP extending from the line portions LP and covering the upper surfaces of the bit lines BL. The connection portions PP may be in a plate shape. The conductive shielding structure SL may be spaced apart from the bit lines BL. The conductive shielding structure SL may shield the capacitive coupling between the bit lines BL. For example, the conductive shielding structure SL may reduce or block the parasitic capacitance between the bit lines BL, thereby reducing the resistance-capacitance delay (RC delay) of the bit lines BL.

[0045] The first structure ST1 may further include an under-wiring structure RT1. The under-wiring structure RT1 may include a first horizontal portion 160, a vertical via 165 located on the first horizontal portion 160, and a second horizontal portion 170 located on the vertical via 165. The first horizontal portion 160 and the second horizontal portion 170 may be configured as a redistribution line for wiring, and the vertical via 165 may be configured as a conductive via.

[0046] The first structure ST1 may further include first and second bit line contacts BL1C and BL2C electrically connecting the lower wiring structure RT1 to the bit line BL, and a word line contact WLC electrically connecting the lower wiring structure RT1 to the word line WL.

[0047] The first structure ST1 may also include a capacitor via 136 located below the second electrode 131, a capacitor interconnect 139 disposed below the capacitor via 136 and extending outside the data storage structure DS, an intermediate pad 118c disposed at the same vertical height as the pad portion 118, a first contact plug 136c located between the intermediate pad 118c and the capacitor interconnect 139, and a second contact plug CPC disposed on the intermediate pad 118c and connected to the wiring lower structure RT1.

[0048] The first structure ST1 may further include a first insulating structure 142 , a second insulating layer 124 on the first insulating structure 142 , a third insulating layer 115 on the second insulating layer 124 , a fourth insulating structure 109 on the third insulating layer 115 , and a fifth insulating structure 180 on the fourth insulating structure 109 .

[0049] The data storage structure DS may be disposed in the first insulating structure 142. The second insulating layer 124 may be disposed on the side surface of the pad portion 118. The third insulating layer 115 may be disposed on the side surface of the plug portion 112. The cell transistor cTR and the back gate line BG may be disposed in the fourth insulating structure 109. The bit line BL, the conductive shielding structure SL, the first and second bit line contacts BL1C and BL2C, the word line contact WLC, and the under-wiring structure RT1 may be disposed in the fifth insulating structure 180.

[0050] The second structure ST2 may include a semiconductor body 3 having a peripheral active region pACT, an isolation region 6 defining the peripheral active region pACT on the semiconductor body 3, and a through-insulating pattern 9 penetrating the semiconductor body 3. The isolation region 6 may define a side surface of the peripheral active region pACT. The isolation region 6 may be formed of an insulating material. The through-insulating pattern 9 may have a lower surface coplanar with the lower surface of the semiconductor body 3 and an upper surface coplanar with the upper surface of the isolation region 6. The through-insulating pattern 9 may include at least one of a low-k dielectric, silicon oxide, silicon nitride, SiBN, SiCN, SiON, SiOCN, silicon oxide doped with impurities, or silicon nitride doped with impurities.

[0051] The semiconductor body 3 may include a semiconductor material such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, the group IV semiconductor may include silicon, germanium, or silicon germanium. The semiconductor body 3 may include single crystal silicon. The thickness of the semiconductor body 3 may be in the range of about 0.5 micrometers (μm) to about 2 μm.

[0052] The second structure ST2 may further include a peripheral transistor pTR, a first peripheral interconnect structure RT2, and a second peripheral interconnect structure RT3 disposed on the semiconductor body 3.

[0053] Each peripheral transistor pTR may include a peripheral source / drain region pSD disposed in a peripheral active region pACT, a peripheral channel region pCH located between the peripheral source / drain regions pSD, and a peripheral gate pGO and pGE located on the peripheral channel region pCH. The peripheral gates pGO and pGE may include a peripheral gate dielectric layer pGO and a peripheral gate electrode pGE located on the peripheral gate dielectric layer pGO. The peripheral transistor pTR may include an NMOS transistor and a PMOS transistor. When the peripheral transistor pTR is configured as an NMOS transistor, the peripheral source / drain region pSD may have an N-type conductivity, and when the peripheral transistor pTR is configured as a PMOS transistor, the peripheral source / drain region pSD may have a P-type conductivity.

[0054] The peripheral transistor pTR may include a sub-word line driver ( Figure 2B The transistors PT, NT1 and NT2 and the sense amplifier ( Figure 2C Transistors P1_a, P1_b, N1_a and N1_b of SA).

[0055] In an example embodiment, the sub-word line driver ( Figure 2BThe transistors PT, NT1 and NT2 of the sub word line driver region SWDR can be arranged in the sub word line driver region SWDR, and the sense amplifier ( Figure 2C The transistors P1_a, P1_b, N1_a and N1_b of the sense amplifier region SA) may be provided in the sense amplifier region SAR.

[0056] As an example, in the drawings, the peripheral transistor pTR may be configured as: a sub-word line driver ( Figure 2B The first peripheral transistor pTRw of one of the transistors PT, NT1 and NT2 in the SWD) and the sense amplifier ( Figure 2C The second peripheral transistor pTRb1 and the third peripheral transistor pTRb2 of the transistors P1_a, P1_b, N1_a and N1_b of SA in FIG.

[0057] The first peripheral interconnect structure RT2 may include a vertical plug 15, a first horizontal portion 18 disposed at a height higher than that of the vertical plug 15, a first vertical via 34 located on the first horizontal portion 18, a second horizontal portion 45 disposed at a height higher than that of the first vertical via 34, a second vertical via 48 located on the second horizontal portion 45, a third horizontal portion 51 disposed at a height higher than that of the second vertical via 48, and a third vertical via 54 located on the third horizontal portion 51.

[0058] The upper surface of the through via 37 may be disposed at a height higher than that of the first horizontal portion 18. The upper surface of the through via 37 may be disposed at a height lower than that of the second horizontal portion 45. The through via 37 and the second horizontal portion 45 may include the through via 37 and the second horizontal portion 45 contacting each other.

[0059] The second peripheral interconnect structure RT3 may include a first horizontal portion 60, a first vertical via 69 located on the first horizontal portion 60, a second horizontal portion 72 located on the first vertical via 69, a third vertical via 81 located on the second horizontal portion 72, and a fourth horizontal portion 84 located on the third vertical via 81. The horizontal portions 60, 72, and 84 may be configured as peripheral interconnect lines for routing.

[0060] The second structure ST2 may further include an upper via 93 located on the second horizontal portion 84 and an upper interconnector 96 located on the upper via 93 .

[0061] The second structure ST2 may include a lower insulating structure 23, and a first interlayer insulating layer 57, a first blocking insulating layer 63, a second interlayer insulating layer 66, a second blocking insulating layer 75, a third interlayer insulating layer 78, a third blocking insulating layer 86, a fourth interlayer insulating layer 88, and a fourth blocking insulating layer 90 sequentially stacked on the lower insulating structure 23. The first to fourth blocking insulating layers 63, 75, 86, and 90 may include a material different from that of the first to fourth interlayer insulating layers 57, 66, 78, and 88 located between the first to fourth blocking insulating layers 63, 75, 86, and 90. The first peripheral interconnection structure RT2 may be disposed in the lower insulating structure 23. The second peripheral interconnection structure RT3 may be disposed in the first interlayer insulating layer 57, the first blocking insulating layer 63, the second interlayer insulating layer 66, the second blocking insulating layer 75, and the third interlayer insulating layer 78. The upper via 93 may penetrate the third blocking insulating layer 86, the fourth interlayer insulating layer 88, and the fourth blocking insulating layer 90. Upper interconnections 96 may be disposed on the fourth blocking insulating layer 90 .

[0062] Each of the wiring lower structure RT1, the first peripheral interconnect structure RT2, the second peripheral interconnect structure RT3, the upper via 93, and the upper interconnect 96 may be formed of Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, or a combination thereof, but example embodiments thereof are not limited thereto. Each of the wiring lower structure RT1, the first peripheral interconnect structure RT2, the second peripheral interconnect structure RT3, the upper via 93, and the upper interconnect 96 may include a single layer or a plurality of layers formed of the above-mentioned materials.

[0063] The second peripheral interconnect structure RT3 may include a conductive material different from at least one of the wiring lower structure RT1, the first peripheral interconnect structure RT2, the upper via 93, and the upper interconnect 96. At least a portion of the wiring lower structure RT1 may include a first conductive material, at least a portion of the first peripheral interconnect structure RT2 may include a second conductive material, at least a portion of the second peripheral interconnect structure RT3 may include a third conductive material, the upper via 93 may include a fourth conductive material, and the upper interconnect 96 may include a fifth conductive material. The third conductive material may include copper, and at least one of the wiring lower structure RT1, the first peripheral interconnect structure RT2, the upper via 93, and the upper interconnect 96 may not include copper. The fifth conductive material may include a material different from the first conductive material, the second conductive material, the third conductive material, and the fourth conductive material, such as aluminum, and at least one of the first conductive material, the second conductive material, and the fourth conductive material may include tungsten or molybdenum.

[0064] The second structure ST2 may further include a back-side insulating layer 31 covering a lower surface of the semiconductor body 3 and a lower surface of the through-insulating pattern 9 .

[0065] The lower surface of the back insulating layer 31 may be bonded to the upper surface of the fifth insulating structure 180. Thus, the upper surface of the first structure ST1 and the lower surface of the second structure ST2 may be bonded to each other, thereby forming a bonding surface JC.

[0066] The first structure ST1 and the second structure ST2 may further include a through via 37 located in (e.g., penetrating) the through insulating pattern 9. The through via 37 may penetrate the through insulating pattern 9, may extend upward, may be connected to the first peripheral interconnection structure RT2, may penetrate the through insulating pattern 9, may extend downward, and may be connected to the under-wiring structure RT1.

[0067] Each through via 37 may be formed of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, or a combination thereof, but example embodiments thereof are not limited thereto. Each through via 37 may include a single layer or a plurality of layers formed of the above-mentioned conductive materials. For example, each through via 37 may include a conductive pillar 37b and a conductive barrier layer 37a covering the side surface and the lower surface of the conductive pillar 37b.

[0068] The word line WL may be electrically connected to the first peripheral transistor pTRw through a word line signal path WSP. Among the bit lines BL, the first bit line ( Figure 2C The second bit line (BL1 in the bit line) can be electrically connected to the second peripheral transistor pTRb1 through the first bit line signal path BL1SP. Figure 2C The second electrode 131 of the data storage structure DS may be electrically connected to a fourth peripheral transistor pTRc included in a voltage supply circuit among the peripheral transistors pTR through a capacitor electrode signal path CPSP.

[0069] The wiring substructure RT1 may include a word line wiring substructure RT1w included in a word line signal path WSP, a first bit line wiring substructure RT1b1 included in a first bit line signal path BL1SP, a second bit line wiring substructure RT1b2 included in a second bit line signal path BL2SP, and a capacitor electrode wiring substructure RT1c included in a capacitor electrode signal path CPSP.

[0070] The through-path 37 may include a word line wiring through-path 37w included in a word line signal path WSP, a first bit line wiring through-path 37b1 included in a first bit line signal path BL1SP, a second bit line wiring through-path 37b2 included in a second bit line signal path BL2SP, and a capacitor electrode wiring through-path 37c included in a capacitor electrode signal path CPSP.

[0071] The first peripheral interconnect structure RT2 may include a word line wiring peripheral structure RT2w included in a word line signal path WSP, a first bit line wiring peripheral structure RT2b1 included in a first bit line signal path BL1SP, a second bit line wiring peripheral structure RT2b2 included in a second bit line signal path BL2SP, and a capacitor electrode wiring peripheral structure RT2c included in a capacitor electrode signal path CPSP.

[0072] Word line signal path ( Figure 3C The WSP in the semiconductor body 3 may include a word line contact WLC connected to (e.g., in contact with) the word line WL, a word line wiring lower structure RT1w connected to the word line contact WLC, a word line wiring connection structure electrically connecting the word line wiring lower structure RT1w to the word line wiring peripheral structure RT2w, and a word line wiring peripheral structure RT2w connecting the word line wiring through-via 37w to the first peripheral transistor PTRw. The word line wiring connection structure may include a word line wiring through-via 37w vertically overlapping the memory block area CA and extending in the semiconductor body 3 (e.g., penetrating the semiconductor body 3).

[0073] The word line contact WLC may be disposed in the first extension region ER1 , and may electrically connect the word line WL to the word line wiring under structure RT1 w in the first extension region ER1 .

[0074] Word line wiring structure ( Figure 3C The word line wiring lower structure RT1w may extend from the first extension region ER1 into the memory block region CA. The word line wiring lower structure RT1w may include a word line wiring lower redistribution line 160w connected to the word line contact WLC in the first horizontal portion 160, a word line wiring upper redistribution line 170w connected to the word line wiring through-path 37w in the second horizontal portion 170, and a word line wiring lower path 165w electrically connecting the word line wiring lower redistribution line 160w to the word line wiring upper redistribution line 170w between the word line wiring lower redistribution line 160w and the word line wiring upper redistribution line 170w in the vertical path 165. Therefore, the word line wiring lower structure RT1w may include at least two redistribution lines 160w and 170w arranged at different vertical heights from each other (i.e., different positions in the direction Z). The redistribution lines 160w and 170w may be configured as word line redistribution lines.

[0075] The word line wiring through-path 37w may overlap vertically with the memory block area CA. The word line wiring through-path 37w may overlap vertically with the data storage structure DS. The lower surface of the word line wiring through-path 37w may be connected to the second horizontal portion 170w of the word line wiring lower structure RT1w, and the upper surface of the word line wiring through-path 37w may be connected to (e.g., contact) the word line wiring peripheral structure RT2w. The word line wiring through-path 37w may penetrate (e.g., extend through) the first through-insulating pattern 9_1 among the through-insulating patterns 9, and may be spaced apart from the semiconductor body 3 by the first through-insulating pattern 9_1.

[0076] Word line wiring peripheral structure ( Figure 3C The word line wiring peripheral structure RT2w may include a first peripheral wiring contact plug 15w connected to the first peripheral transistor pTRw among the vertical plugs 15, a first peripheral wiring lower interconnection line 18w connected to the first peripheral wiring contact plug 15w among the first horizontal portion 18, a first peripheral wiring via 34w connected to the first peripheral wiring lower interconnection line 18w among the first vertical vias 34, and a first peripheral wiring upper interconnection line 45w electrically connecting the first peripheral wiring via 34w to the word line wiring through-via 37w among the second horizontal portion 45. The upper surface of the word line wiring through-via 37w may be connected to the lower surface of the first peripheral wiring upper interconnection line 45w. The word line wiring peripheral structure RT2w may include at least two interconnections (the first peripheral wiring lower interconnection line 18w and the first peripheral wiring upper interconnection line 45w) arranged at different vertical heights from each other. The upper surface of the word line wiring through-via 37w may be connected in contact with the lower surface of the second peripheral wiring upper interconnection line 45w.

[0077] First bit line signal path ( Figure 4C The first peripheral transistor pTRb1 may include a first bit line contact BL1C electrically connected to (e.g., contacting) the first bit line BL1, a first bit line wiring lower structure RT1b1 electrically connected to the first bit line contact BL1C, a first bit line wiring connection structure electrically connecting the first bit line wiring lower structure RT1b1 to the first bit line wiring peripheral structure RT2b1, and a first bit line wiring peripheral structure RT2b1 electrically connecting the first bit line wiring connection structure to the second peripheral transistor pTRb1. The first bit line BL1 may pass through the first storage block region CA1 and may extend into the second extension region ER2. The first bit line wiring connection structure may include a first bit line wiring through-path 37b1.

[0078] The first bit line contact BL1C may be disposed in the second extension region ER2 , and the first bit line BL1 and the first bit line wiring lower structure RT1 b 1 may be electrically connected to (eg, contact) each other in the second extension region ER2 .

[0079] First line wiring structure ( Figure 4C The first bit line wiring lower structure RT1b1 may extend from the second extension region ER2 into the first memory block region CA1. The first bit line wiring lower structure RT1b1 may include a first bit line wiring lower redistribution line 160b1 connected to the first bit line contact BL1C among the first horizontal portion 160, a first bit line wiring upper redistribution line 170b1 connected to the first bit line wiring through-via 37b1 among the second horizontal portion 170, and a first bit line wiring lower via 165b1 electrically connecting the first bit line wiring lower redistribution line 160b1 to the first bit line wiring upper redistribution line 170b1 between the first bit line wiring lower redistribution line 160b1 and the first bit line wiring upper redistribution line 170b1 among the vertical via 165. Therefore, the first bit line wiring lower structure RT1b1 may include at least two redistribution lines (the first bit line wiring lower redistribution line 160b1 and the first bit line wiring upper redistribution line 170b1) disposed at different vertical heights from each other.

[0080] The first bit line wiring through-path 37b1 may overlap vertically with the first storage block region CA1. The first bit line wiring through-path 37b1 may overlap vertically with the data storage structure DS. The lower surface of the first bit line wiring through-path 37b1 may be connected to the first bit line wiring upper redistribution line 170b1 of the first bit line wiring lower structure RT1b1 in the first storage block region CA1, and the upper surface of the first bit line wiring through-path 37b1 may be connected to the first bit line wiring peripheral structure RT2b1. The first bit line wiring through-path 37b1 may penetrate (e.g., extend through) the second through-insulation pattern 9_2 among the through-insulation pattern 9, and may be spaced apart from the semiconductor body 3 by the second through-insulation pattern 9_2.

[0081] The first bit line wiring peripheral structure RT2b1 may include a vertical plug 15b1 connected to the second peripheral transistor pTRb1, a first horizontal portion 18b1 located on the vertical plug 15b1, a first vertical via 34b1 located on the first horizontal portion 18b1, and a second horizontal portion 45b1 electrically connecting the first vertical via 34b1 to the first bit line wiring through via 37b1. The upper surface of the first bit line wiring through via 37b1 may be connected to the lower surface of the second horizontal portion 45b1. The first bit line wiring peripheral structure RT2b1 may include at least two horizontal portions (a first horizontal portion 18b1 and a second horizontal portion 45b1) disposed at different vertical heights from each other.

[0082] Second bit line signal path ( Figure 4DThe second bit line BL2 may include a second bit line contact BL2C connected to the second bit line BL2, a second bit line wiring lower structure RT1b2 connected to the second bit line contact BL2C, a second bit line wiring through-path 37b2 connected to the second bit line wiring lower structure RT1b2, and a second bit line wiring peripheral structure RT2b2 connecting the second bit line wiring through-path 37b2 to the third peripheral transistor pTRb2. The second bit line BL2 may cross the first and second memory block regions CA1 and CA2 adjacent to each other in the second direction Y and may extend into the second extension region ER2.

[0083] The second bit line contact BL2C may be disposed in the second extension region ER2 , and the second bit line BL2 and the second bit line wiring lower structure RT1 b 2 may be electrically connected to each other in the second extension region ER2 .

[0084] The second bit line wiring structure ( Figure 4D The second bit line wiring lower structure RT1b2 may include a second bit line wiring lower redistribution line 160b2 connected to the second bit line contact BL2C, a second bit line wiring upper redistribution line 170b2 connected to the second bit line wiring through-via 37b2, and a second bit line wiring lower via 165b2 electrically connecting the second bit line wiring lower redistribution line 160b2 and the second bit line wiring upper redistribution line 170b2 to each other between the second bit line wiring lower redistribution line 160b2 and the second bit line wiring upper redistribution line 170b2. Therefore, the second bit line wiring lower structure RT1b2 may include at least two redistribution lines (the second bit line wiring lower redistribution line 160b2 and the second bit line wiring upper redistribution line 170b2) disposed at different vertical heights from each other.

[0085] The second bit line wiring through-path 37b2 may overlap vertically with the second extension region ER2. The lower surface of the second bit line wiring through-path 37b2 may be connected to the second bit line wiring upper redistribution line 170b2 of the second bit line wiring lower structure RT1b2 in the second extension region ER2, and the upper surface of the second bit line wiring through-path 37b2 may be connected to the second bit line wiring peripheral structure RT2b2. The second bit line wiring through-path 37b2 may penetrate the third through-insulation pattern 9_3 among the through-insulation pattern 9, and may be spaced apart from the semiconductor body 3 by the third through-insulation pattern 9_3. The second bit line wiring through-path 37b2 may be electrically connected to the third peripheral transistor pTRb2 vertically overlapping with the first storage block region CA1, and the second bit line wiring through-path 37b2 may not overlap vertically with the first storage block region CA1. The first peripheral transistor pTRw, the second peripheral transistor pTRb1, and the third peripheral transistor pTRb2 may overlap vertically with the first storage block region CA1.

[0086] The second bit line wiring peripheral structure RT2b2 may include a vertical plug 15b2 connected to the third peripheral transistor pTRb2, a first horizontal portion 18b2 located on the vertical plug 15b2, a first vertical via 34b2 located on the first horizontal portion 18b2, a 2-1 horizontal portion 45b2b located on the first vertical via 34b2, a 3-1 vertical via 48b2b located on the 2-1 horizontal portion 45b2b, a 2-2 horizontal portion 45b2a located on the second bit line wiring through via 37b2, a 3-2 vertical via 48b2a located on the 2-2 horizontal portion 45b2a, and a third horizontal portion 51b2 connecting the 3-2 vertical via 48b2a to the 3-1 vertical via 48b2b. The upper surface of the second bit line wiring through via 37b2 may be connected to the lower surface of the 2-2 horizontal portion 45b2a. The second bit line wiring peripheral structure RT2b2 may include at least three horizontal portions (a first horizontal portion 18b2, a 2-1 horizontal portion 45b2b, and a third horizontal portion 51b2) disposed at different vertical heights from each other.

[0087] In the following description, various modified examples of the elements of the above-described example embodiments will be described. Various modified examples of the elements of the above-described example embodiments described below will be described with respect to the modified or replaced elements. Here, the above-described elements may be directly referenced without detailed description, or description may not be provided. Similarly, elements that may be modified or replaced will be described with reference to the accompanying drawings, but the elements that may be modified or replaced may be combined with each other or with the above-described elements, and may be included in the semiconductor device according to the example embodiments.

[0088] Figure 7 It's a picture. Figure 3A FIG. 1 is a diagram illustrating an example of a semiconductor device according to example embodiments, with an enlarged example of a region 'C' in FIG.

[0089] refer to Figure 7 , the insulating spacer 39 may be disposed on the side surface of the through via 37. The insulating spacer 39 may be disposed between the fifth insulating structure 180 and the through via 37, between the back insulating layer 31 and the through via 37, between the through insulating pattern 9 and the through via 37, and between the lower insulating structure 23 and the through via 37. The lower end of the insulating spacer 39 may be disposed at a height lower than the height of the lower surface of the through insulating pattern 9, and the upper end of the insulating spacer 39 may be disposed at a height higher than the height of the upper surface of the through insulating pattern 9.

[0090] Fig. 8A It's a picture. Figure 3A FIG. 1 is a diagram illustrating an example of a semiconductor device according to example embodiments, with an enlarged example of a region 'C' in FIG.

[0091] refer to Fig. 8A The through-insulating pattern 9 may be replaced with a through-insulating pattern 9a, and the lower surface of the through-insulating pattern 9a may have a lower surface 9_L in an upwardly curved shape. The lower surface 9_L of the through-insulating pattern 9a may be further recessed than the lower surface 3_L of the semiconductor body 3. The lower surface 9_L of the through-insulating pattern 9a and the lower surface 3_L of the semiconductor body 3 may be in contact with the back insulating layer 31.

[0092] Figure 8B It's a picture. Figure 3A FIG. 1 is a diagram illustrating an example of a semiconductor device according to example embodiments, with an enlarged example of a region 'C' in FIG.

[0093] refer to Figure 8B , the through-insulating pattern 9 may be replaced with a through-insulating pattern 9b including at least two insulating layers. For example, the through-insulating pattern 9b may include an insulating column 9b1 and an insulating pad 9b2 covering the side surface and the lower surface of the insulating column 9b1. The insulating column 9b1 and the insulating pad 9b2 may be formed of different materials. The insulating pad 9b2 may be in contact with the back insulating layer 31, and the insulating column 9b1 may be spaced apart from the back insulating layer 31.

[0094] Figure 8C It's a picture. Figure 3A FIG. 1 is a diagram illustrating an example of a semiconductor device according to example embodiments, with an enlarged example of a region 'C' in FIG.

[0095] refer to Figure 8C , the through-insulating pattern 9 may be replaced by a through-insulating pattern 9c including at least two insulating layers and having a lower surface 9c_L in an upwardly curved shape. The lower surface 9c_L of the through-insulating pattern 9c may be more recessed upward than the lower surface 3_L of the semiconductor body 3. The through-insulating pattern 9c may include an insulating column 9c1 and an insulating pad 9c2 located between the side surface of the insulating column 9c1 and the semiconductor body 3. The insulating column 9c1 and the insulating pad 9c2 may be formed of different materials. The lower surface of the insulating column 9c1 may be in contact with the back insulating layer 31.

[0096] Fig. 9 is a cross-sectional view illustrating an example of a semiconductor device according to an example embodiment, thereby illustrating Figure 3A Part of the cross-section view modification.

[0097] refer to Fig. 9 , FIG. 3A to FIG. 8CThe through passage 37 disposed at a height higher than the height of the first horizontal portion 18 may be replaced with a through passage 237 disposed at a height lower than the height of the first horizontal portion 18. The through passage 237 and the first horizontal portion 18 may include the through passage 237 and the first horizontal portion 18 contacting each other.

[0098] The through-via 237 may include a word line wiring through-via 237w included in the word line signal path WSP. The first peripheral interconnection structure RT2 may include a word line wiring peripheral structure RT2wa included in the word line signal path WSP.

[0099] A lower surface of the word line wiring through-via 237w may be connected to the second horizontal portion 170w of the word line wiring lower structure RT1w, and an upper surface of the word line wiring through-via 237w may be connected to the word line wiring peripheral structure RT2wa.

[0100] The word line wiring peripheral structure RT2wa may include a vertical plug 15w connected to the first peripheral transistor pTRw, a 1-1 horizontal portion 18wa located on the vertical plug 15w, a 2-1 vertical path 34wa located on the 1-1 horizontal portion 18wa, a 1-2 horizontal portion 18wb connected to the upper surface of the word line wiring through-path 237w, a 2-2 vertical path 34wb located on the 1-2 horizontal portion 18wb, and a second horizontal portion 45w electrically connecting the 2-1 vertical path 34wa to the 2-2 vertical path 34wb. The upper surface of the word line wiring through-path 237w may be connected to the lower surface of the 1-2 horizontal portion 18wb. The word line wiring through-path 237w may be connected to the 1-2 horizontal portion 18wb set at a height lower than that of the word line wiring peripheral structure RT2wa.

[0101] According to example embodiments, in the word line wiring peripheral structure RT2wa, the 1-1 horizontal portion 18wa and the 1-2 horizontal portion 18wb may be integrated with each other and may form a word line wiring interconnect, and the 2-1 vertical via 34wa, the 2-2 vertical via 34wb, and the second horizontal portion 45w may not be provided. Therefore, the word line wiring peripheral structure RT2wa may include a word line wiring interconnect (1-1 horizontal portion 18wa and 1-2 horizontal portion 18wb) contacting and connected to the upper surface of the word line wiring through-via 237w.

[0102] Reference Fig. 10A , Fig. 10B and Fig.11 Examples of semiconductor devices according to example embodiments are described. Fig. 10A It is a diagram showing the Figure 1B A cross-sectional view of the area cut along line II-II' in FIG. Fig. 10B It's a picture. Fig. 10A Magnified view of area "D" in FIG. Fig.11 is a perspective view illustrating a first bit line signal path BL1SP, a first bit line BL, and a portion of a conductive shielding structure SL in a semiconductor device according to example embodiments.

[0103] refer to Fig. 10A , Fig. 10B and Fig.11 , Figures 3A to 9 A first bit line contact ( Figure 4A The first bit line contact BL1C in the first extension region ER2 may be replaced with a first bit line contact BL1Ca that penetrates the conductive shielding structure SL and is connected to (e.g., contacts) the first bit line BL1 in the first memory cell block region CA1. Since the length of the first bit line BL1 extending into the second extension region ER2 may be reduced, the width of the second extension region ER2 may be reduced. Therefore, the integration density of the semiconductor device may be improved.

[0104] The conductive shielding structure SL may have an opening SL_O penetrating the connection portion PP of the conductive shielding structure SL. The first bit line contact BL1Ca may pass through the opening SL_O and may contact and be connected to the first bit line BL1.

[0105] The first bit line wiring structure ( Figure 4C The RT1b1 in FIG. 1 may be replaced by a first bit line wiring lower structure RT1b1′ connected to the first bit line contact BL1Ca.

[0106] The first bit line signal path BL1SP may include a first bit line contact BL1Ca, a first bit line wiring lower structure RT1b1', a first bit line wiring through via 37b1, and a first bit line wiring peripheral structure RT2b1.

[0107] Reference Fig.12 Examples of semiconductor devices according to example embodiments are described. Fig.12 It is a diagram showing the Figure 1B A cross-sectional view of the area cut along line II-II' in FIG.

[0108] refer to Fig.12 , Figures 3A to 11 A second bit line contact ( Figure 4AThe second bit line contact BL2C in the second extension region ER2 may be replaced with a second bit line contact BL2Ca that penetrates the conductive shielding structure SL and is connected to the second bit line BL2 in the second memory cell block region CA2. Since the length of the second bit line BL2 extending into the second extension region ER2 may be reduced, the width of the second extension region ER2 may be reduced. Therefore, the integration density of the semiconductor device may be improved.

[0109] Reference Fig.13 Examples of semiconductor devices according to example embodiments are described. Fig.13 It is a diagram showing the Figure 1B A cross-sectional view of the area cut along line II' in FIG.

[0110] refer to Fig.13 , Figures 3A to 12 The second structure ST2 in the semiconductor body 3 may further include a device isolation insulating pattern 209 penetrating the semiconductor body 3. The device isolation insulating pattern 209 and the through insulating pattern 9 may be formed by the same semiconductor process. Therefore, the device isolation insulating pattern 209 may have the same shape as the through insulating pattern 9.

[0111] In an example, the device isolation insulating pattern 209 may penetrate the isolation region 6 , may extend downward, and may penetrate the semiconductor body 3 .

[0112] In an example, the through-insulating pattern 9 may penetrate the isolation region 6 , may extend downward, and may penetrate the semiconductor body 3 .

[0113] In an example, the peripheral transistor pTR may include a fourth peripheral transistor pTRc1, a fifth peripheral transistor pTRc2, and a sixth peripheral transistor pTRc3, the fourth peripheral transistor pTRc1 and the fifth peripheral transistor pTRc2 may be spaced apart from each other by the isolation region 6, and the fifth peripheral transistor pTRc2 and the sixth peripheral transistor pTRc3 may be spaced apart from each other by the device isolation insulating pattern 209. One of the fifth peripheral transistor pTRc2 and the sixth peripheral transistor pTRc3 may be configured as an NMOS transistor, and the other may be configured as a PMOS transistor. In another example, one of the fifth peripheral transistor pTRc2 and the sixth peripheral transistor pTRc3 may be a transistor included in a first circuit, and the other may be a transistor included in a second circuit different from the first circuit. Therefore, the device isolation insulating pattern 209 may also isolate different circuits from each other.

[0114] Reference Fig.14 Examples of semiconductor devices according to example embodiments are described. Fig.14 It is a diagram showing the Figure 1B A cross-sectional view of the area cut along line II' in FIG.

[0115] refer to Fig.14 , you may not provide FIG. 3A to FIG. 13 The through insulating pattern 9 in the FIG. 3A to FIG. 13 The through via 37 in the semiconductor body 3 may penetrate the semiconductor body 3. The second structure ST2 may include Figure 7 The insulating spacer 39 a may be provided on a side surface of the through via 37 and may isolate the through via 37 from the semiconductor body 3 .

[0116] Reference Fig.15 Examples of semiconductor devices according to example embodiments are described. Fig.15 It is a diagram showing the Figure 1B A cross-sectional view of the area cut along line II' in FIG.

[0117] refer to Fig.15 , Figures 3A to 14 The first structure ST1 in FIG. 1 may further include a first bonding pad 175 having an upper surface coplanar with an upper surface of the fifth insulating structure 180 . Figures 3A to 14 The wiring lower structure RT1 in FIG. 1 may be replaced with a lower wiring structure RT1 a further including a first connection via 172 connecting the first bonding pad 175 to the second horizontal portion 170 .

[0118] Figures 3A to 14 The second structure ST2 in the embodiment may have a lower surface coplanar with the lower surface of the back insulating layer 31, and may further include a second bonding pad 320 contacting and bonding to the first bonding pad 175, and redistribution line structures 310 and 315 connecting the second bonding pad 320 to the through via 37. The redistribution line structures 310 and 315 may include a redistribution line 310 connected to the through via 37 and a second connection via 315 connecting the redistribution line 310 to the second bonding pad 320. The first bonding pad 175 and the second bonding pad 320 may include the same metal material, such as copper. The word line wiring connection structure may include a word line wiring through via ( Figure 3C In addition to the 37w in the example, it may also include a structure electrically connected to the word line wiring ( Figure 3C The first bonding pad 175 of RT1w in FIG. 1 is electrically connected to the word line wiring through-path ( Figure 3C 37w in FIG. 37a ) and a redistribution line structure 310 and 315 and a second bonding pad 320 .

[0119] Reference Fig.16A and Fig. 16B Examples of semiconductor devices according to example embodiments are described. Fig.16A It is a diagram showing the Figure 1B A cross-sectional view of the region taken along line II' in FIG. Fig. 16B It is a diagram showing the Figure 1B A cross-sectional view of the area cut along line II-II' in FIG.

[0120] refer to Fig.16A and Fig. 16B ,include Figures 3A to 15 The structures of the data storage structure DS and the conductive shielding structure SL (and the layers / elements therebetween) in the embodiment may be modified to be inverted. The bit line BL may be modified to be set at a height lower than that of the word line WL and the cell transistor cTR, and Figures 3A to 15 The data storage structure DS in the embodiment may be modified to be a data storage structure DS set at a height higher than that of the word line WL and the cell transistor cTR. The data storage structure DS may include a first electrode 127, a second electrode 131 covering the side surface and the upper surface of the first electrode 127, and a dielectric layer 129 located between the first electrode 127 and the second electrode 131.

[0121] In the above-described contact structure 121 , the plug portion 112 may be connected to the cell transistor cTR, and the pad portion 118 may electrically connect the plug portion 112 to the first electrode 127 between the plug portion 112 and the first electrode 127 .

[0122] In each bit line BL, the second conductive layer 152 may be modified to be disposed under the first conductive layer 150. Therefore, the first conductive layer 150 may be disposed on the second conductive layer 152.

[0123] Figures 3A to 15 The word line contact WLC in the first extension region ER1 may be replaced with a lower word line contact WLC_L connected to the word line WL in the first extension region ER1, an intermediate word line contact WLC_M on the lower word line contact WLC_L, and an upper word line contact WLC_U connected to the wiring lower structure RT1 on the intermediate word line contact WLC_M. The intermediate word line contact WLC_M may be disposed at the same height as that of the pad portion 118.

[0124] Figures 3A to 15 Each of the bit line contacts BL1C and BL2C in the second extension region ER2 may be replaced with a lower bit line contact BLC_L connected to the bit line BL in the second extension region ER2, an intermediate bit line contact BLC_M located on the lower bit line contact BLC_L, and an upper bit line contact BLC_U connected to the wiring lower structure RT1 on the intermediate bit line contact BLC_M. The intermediate bit line contact BLC_M may be disposed at the same height as that of the pad portion 118.

[0125] The lower bit line contact BLC_L may contact the first conductive layer 150 and the second conductive layer 152 of the bit line BL. The lower bit line contact BLC_L may have a lower surface disposed at a height lower than that of the first conductive layer 150 and may contact the second conductive layer 152.

[0126] In the following description, reference will be made to 17A to 17D , Fig.18A , Fig.18B and FIG. 19A to FIG. 19B An example of a method of manufacturing a semiconductor device according to example embodiments is described. 17A to 17D , Fig.18A , Fig.18B and FIG. 19A to FIG. 19B It is a diagram showing the Figure 1B 8 is a cross-sectional view of a region taken along line II-II′ in FIG. 1 , thereby illustrating an example of a method of manufacturing a semiconductor device according to example embodiments.

[0127] refer to Figure 1B and Fig.17A , an isolation region 6 defining a peripheral active region pACT may be formed on the substrate 2. A through insulating pattern 9 may be formed on the substrate 2. A lower surface of the through insulating pattern 9 may be formed at a height lower than that of the lower surface of the isolation region 6.

[0128] The peripheral transistor pTR may be formed on the substrate 2. Each peripheral transistor pTR may include a peripheral source / drain region pSD formed in the peripheral active region pACT, a peripheral channel region pCH located between the peripheral source / drain regions pSD, and peripheral gates pGO and pGE located on the peripheral channel region pCH. The peripheral gates pGO and pGE may include a peripheral gate dielectric layer pGO and a peripheral gate electrode pGE located on the peripheral gate dielectric layer pGO.

[0129] By performing the first interconnection process on the substrate 2 , a vertical plug 15 connected to the peripheral transistor pTR, a first horizontal portion 18 on the vertical plug 15 , and an insulating structure 21 covering the vertical plug 15 and the first horizontal portion 18 on the substrate 2 may be formed.

[0130] refer to Figure 1B and Fig. 17B , a first support substrate 28 including a first adhesive layer 26 bonded to an upper surface of the insulating structure 21 and a first wafer 27 located on the first adhesive layer 26 may be formed.

[0131] refer to Figure 1B and Fig. 17C , can be achieved by reducing the substrate ( Fig. 17B2) in thickness until the through insulating pattern 9 is exposed to form the semiconductor body 3. For example, by grinding the substrate ( Fig. 17B 2), can form a thickness less than the substrate ( Fig. 17B 2) of the thickness of the semiconductor body 3. The semiconductor body 3 may be formed, and the through insulating pattern 9 may be exposed. For example, in order to reduce the substrate ( Fig. 17B In the grinding process of increasing the thickness of the electrode 2), the through insulating pattern 9 may serve as a stopper.

[0132] In the example, in order to form Fig. 8A or Figure 8C The illustrated through insulating patterns 9 a and 9 c may clean the exposed surface of the semiconductor body 3 and the exposed surface of the through insulating pattern 9 , and the surface of the through insulating pattern 9 may also be recessed.

[0133] refer to Figure 1B and Fig.17D A back side insulating layer 31 may be formed on the exposed surface of the semiconductor body 3 and the exposed surface of the through insulating pattern 9 . The exposed surface of the semiconductor body 3 and the exposed surface of the through insulating pattern 9 may be in contact with the back side insulating layer 31 .

[0134] refer to Fig.18A , a silicon-on-insulator substrate (SOI substrate) may be used to form a cell transistor cTR and a back gate line BG using a word line WL as a gate electrode. The cell transistor cTR and the back gate line BG may be buried in an insulating structure 142. Cell source / drain regions cSD1 and cSD2 and a vertical channel region cCH of each cell transistor cTR may be formed in a cell active pattern cACT. The cell active pattern cACT may be formed of silicon in an SOI substrate. A contact structure 121 and insulating layers 124 and 115 may be formed on the cell transistor cTR, a data storage structure DS may be formed on the contact structure 121, a capacitor path 136 and a capacitor interconnect 139 may be formed on the data storage structure DS, and an insulating structure 142 covering the data storage structure DS, the capacitor path 136, and the capacitor interconnect 139 may be formed. A second supporting substrate 147 including a second adhesive layer 145 bonded to the insulating structure 142 and a second wafer 146 located on the second adhesive layer 145 may be formed. By removing the insulating layer and the substrate in the SOI substrate, the cell active pattern cACT may be exposed.

[0135] refer to Fig.18B , a bit line BL connected to the first source / drain region cSD1 of the cell active pattern cACT and a conductive shielding structure SL located on the bit line BL may be formed. As described above, the conductive shielding structure SL may include a line portion ( Figure 5 LP in the bit line) and a connecting portion ( Figure 5 The conductive shielding structure SL may be separated from the bit line BL by an insulating material.

[0136] Bit line contacts BL1C and BL2C connected to the bit line BL and word line contacts (BL1C and BL2C) connected to the word line WL may be formed. Figure 3A in the WLC).

[0137] The bit line contacts BL1C and BL2C and the word line contacts ( Figure 3A The wiring structure RT1 may be formed on the bit line contacts BL1C and BL2C and the word line contacts ( Figure 3A A first horizontal portion 160 is formed on the WLC in the embodiment of the present invention, a vertical path 165 is formed on the first horizontal portion 160, and a second horizontal portion 170 is formed on the vertical path 165.

[0138] Bit line contacts BL1C and BL2C, word line contacts ( Figure 3A The WLC in the first horizontal portion 160, the vertical path 165 and the second horizontal portion 170 may be covered by the insulating structure 180.

[0139] refer to Fig.19A By performing the wafer bonding process, the insulating structure 180 supported by the second support substrate 147 and the back insulating layer 31 supported by the first support substrate 28 may contact and bond with each other. A bonding surface JC may be formed as the insulating structure 180 and the back insulating layer 31 are bonded to each other.

[0140] refer to Fig.19B , the first supporting substrate ( Fig.19A 28 in FIG. 28). A first vertical via 34 may be formed on the first horizontal portion 18. A through via 37 penetrating the through insulating pattern 9 and connected to the second horizontal portion 170 of the under-wiring structure RT1 may be formed.

[0141] In example embodiments, the first vertical via 34 and the through via 37 may be formed simultaneously or may be formed in separate processes.

[0142] A second horizontal portion 45 located on the first vertical via 34 and the through via 37, a second vertical via 48 located on the second horizontal portion 45, a third horizontal portion 51 located on the second vertical via 48, and a third vertical via 54 located on the third horizontal portion 51 may be formed. The vertical plug 15, the first horizontal portion 18, the first vertical via 34, the second horizontal portion 45, the second vertical via 48, the third horizontal portion 51, and the third vertical via 54 may be included in the first peripheral interconnect structure RT2. The first peripheral interconnect structure RT2 may be buried in the insulating structure 23.

[0143] A second peripheral interconnection structure RT3 and insulating layers 57 , 63 , 66 , 75 , and 78 covering side surfaces of the second peripheral interconnection structure RT3 may be formed on the first peripheral interconnection structure RT2 .

[0144] The second peripheral interconnect structure RT3 may include a first horizontal portion 60 , a first vertical via 69 on the first horizontal portion 60 , a second horizontal portion 72 on the first vertical via 69 , a third vertical via 81 on the second horizontal portion 72 , and a fourth horizontal portion 84 on the third vertical via 81 .

[0145] Insulation layers 86 , 88 , and 90 sequentially stacked on the second peripheral interconnection structure RT3 may be formed, an upper via 93 penetrating the insulation layers 86 , 88 , and 90 may be formed, and an upper interconnection 96 may be formed on the upper via 93 .

[0146] Afterwards, the second support substrate 147 may be removed to form Figures 1A to 6 The semiconductor device 1 described in FIG.

[0147] According to the foregoing example embodiments, a semiconductor device including a memory block region and a peripheral circuit region vertically overlapping each other can be provided. Therefore, the integration density of the semiconductor device can be improved.

[0148] Likewise, the word line may pass through the first memory block region and the second memory block region adjacent to each other and an extension region between the first memory block region and the second memory block region.

[0149] Similarly, a word line signal path for electrically connecting a word line to a first peripheral transistor in a peripheral circuit region may be provided. The word line signal path may include a word line contact connected to the word line in an extension region, a word line wiring lower structure extending from the extension region to the first storage block region, and a word line wiring through-path that penetrates an insulating pattern that penetrates a semiconductor body in the peripheral circuit region. The word line wiring through-path and the first peripheral transistor may overlap vertically with the first storage block region. Such an arrangement of the word line signal path and the first peripheral transistor as above may improve the integration density of the semiconductor device, and may improve the signal transmission speed, thereby improving the performance of the semiconductor device.

[0150] While example embodiments have been illustrated and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope defined by the appended claims.

Claims

1. A semiconductor device, comprising: a first structure having a storage block region and an extension region adjacent to the storage block region in a first direction; as well as a second structure vertically overlapping the first structure and having a peripheral circuit region vertically overlapping the memory block region, The first structure includes a memory cell and a word line, the memory cell is located in the memory block area and each of the memory cells includes a vertical channel transistor and a data storage structure, the word line is electrically connected to the memory cell, intersects the memory block area and extends into the extension area, The second structure includes a semiconductor body, a back insulating layer, an isolation region, a through insulating pattern, and a peripheral transistor, wherein the back insulating layer is located below the semiconductor body, the isolation region defines a peripheral active region on the semiconductor body, the through insulating pattern is located in the semiconductor body, and the peripheral transistor includes a first peripheral source / drain, a second peripheral source / drain, a peripheral channel region between the first peripheral source / drain and the second peripheral source / drain, and a peripheral gate located on the peripheral channel region. wherein the first peripheral source / drain, the second peripheral source / drain and the peripheral channel region are located in a first peripheral active region among the peripheral active regions, wherein the first structure and the second structure include a word line signal path electrically connecting the word line to the peripheral transistor, wherein the word line signal path comprises a word line wiring peripheral structure, a word line contact, a word line wiring lower structure and a word line wiring connection structure, wherein the word line wiring peripheral structure is electrically connected to the peripheral transistor and is located on the semiconductor body, the word line contact contacts the word line in the extension region, the word line wiring lower structure is electrically connected to the word line contact and extends from the extension region to the storage block region, and the word line wiring connection structure electrically connects the word line wiring lower structure to the word line wiring peripheral structure, and The word line wiring connection structure includes a word line wiring through-path vertically overlapping the storage block region and penetrating the semiconductor body.

2. The semiconductor device according to claim 1, in, The word line wiring through-path penetrates the through-insulating pattern, The upper surface of the word line wiring through-via is located at a height higher than the upper surface of the semiconductor body and the upper surface of the through-insulating pattern. wherein the height of the lower surface of the word line wiring through-path is lower than the height of the lower surface of the semiconductor body and the height of the lower surface of the through-insulating pattern, and The word line wiring through-via is separated from the semiconductor body by the through-insulating pattern.

3. The semiconductor device according to claim 2, in, The second structure further includes an insulating spacer located on a side surface of the word line wiring through via, The height of the lower end of the insulating spacer is lower than the height of the lower surface of the through insulating pattern, and The height of the upper end of the insulating spacer is higher than the height of the upper surface of the through insulating pattern.

4. The semiconductor device according to claim 1, wherein: The word line wiring lower structure comprises: a redistribution line under the wordline wiring, the redistribution line under the wordline wiring electrically connected to the wordline contact; a word line wiring lower via, the word line wiring lower via being located on a redistribution line under the word line wiring; and A word line wiring upper redistribution line electrically connects the word line wiring lower via to the word line wiring through via.

5. The semiconductor device according to claim 1, wherein The vertical channel transistor comprises: A first unit source / drain region, a second unit source / drain region at a height different from that of the first unit source / drain region, and a vertical channel region between the first unit source / drain region and the second unit source / drain region, wherein the vertical channel region and the first unit source / drain region and the second unit source / drain region are located in a unit active pattern; a gate dielectric layer, the gate dielectric layer contacting the vertical channel region; and the word line, the word line being in contact with the gate dielectric layer, and The data storage structure includes a first electrode electrically connected to the second unit source / drain region, a dielectric layer located on the first electrode, and a second electrode located on the dielectric layer.

6. The semiconductor device according to claim 5, wherein: The vertical channel transistor is located between the data storage structure and the second structure.

7. The semiconductor device according to claim 5, wherein: The data storage structure is located between the vertical channel transistor and the second structure.

8. The semiconductor device according to claim 5, in, The first structure also includes a bit line electrically connected to the memory cell and crossing the memory block region in a second direction intersecting the word line and perpendicular to the first direction, wherein the through-insulating pattern is a first through-insulating pattern, the peripheral transistor is a first peripheral transistor, the peripheral channel region is a first peripheral channel region, and the peripheral gate is a first peripheral gate, The second structure further includes a second through-insulating pattern and a second peripheral transistor, the second through-insulating pattern is located in the semiconductor body, the second peripheral transistor includes a third peripheral source / drain, a fourth peripheral source / drain, a second peripheral channel region located between the third peripheral source / drain and the fourth peripheral source / drain, and a second peripheral gate located on the second peripheral channel region. The third peripheral source / drain, the fourth peripheral source / drain and the second peripheral channel region are located in a second peripheral active region among the peripheral active regions. The first structure and the second structure further include a first bit line signal path electrically connecting a first bit line among the bit lines to the second peripheral transistor, wherein the first bit line signal path further comprises a first bit line wiring peripheral structure, a first bit line contact, a first bit line wiring lower structure and a first bit line wiring connection structure, wherein the first bit line wiring peripheral structure is electrically connected to the second peripheral transistor and is located on the semiconductor body, the first bit line contact is in contact with the first bit line, the first bit line wiring lower structure is electrically connected to the first bit line contact, and the first bit line wiring connection structure electrically connects the first bit line wiring lower structure to the first bit line wiring peripheral structure, and The first bit line wiring connection structure includes a first bit line wiring through-path vertically overlapping the memory block region and penetrating the semiconductor body.

9. The semiconductor device according to claim 8, wherein: The first structure also includes a conductive shield structure including a line portion located between the bit lines and a connecting portion extending from the line portion and located on the bit lines.

10. The semiconductor device according to claim 8, in, The extended region is a first extended region, The second structure further has a second extension region adjacent to the storage block region in the second direction. The first bit line passes through the storage block area and extends into the second extension area. wherein the first bit line contact contacts the first bit line in the second extension region, wherein the first bit line wiring lower structure extends from the second extension region into the storage block region, and The first bit line wiring lower structure is in contact with the first bit line contact in the second extension region and is in contact with the first bit line wiring through-via in the memory block region.

11. The semiconductor device according to claim 8, in, The first bit line contact contacts the first bit line in the memory block region, and The first bit line wiring lower structure electrically connects the first bit line contact to the first bit line wiring through-via in the memory block region.

12. The semiconductor device according to claim 1, in, The second structure includes a first peripheral interconnect structure located on the semiconductor body and a second peripheral interconnect structure located on the first peripheral interconnect structure, Wherein, the first peripheral interconnection structure comprises: vertical plug; a first horizontal portion, the first horizontal portion being located at a height higher than the height of the vertical plug; a first vertical passage, the first vertical passage being located on the first horizontal portion; a second horizontal portion, the second horizontal portion being located at a height higher than that of the first vertical passage; a second vertical passage, the second vertical passage being located at a height higher than that of the second horizontal portion; and A third horizontal portion, wherein the third horizontal portion is located at a height higher than that of the second vertical passage.

13. The semiconductor device according to claim 12, in, The word line wiring peripheral structure includes: a first peripheral wiring contact plug electrically connected to the first peripheral source / drain among the vertical plugs, a first peripheral wiring lower interconnection line electrically connected to the first peripheral wiring contact plug among the first horizontal portion, a first peripheral wiring via electrically connected to the first peripheral wiring lower interconnection line among the first vertical via, and a first peripheral wiring upper interconnection line electrically connected to the first peripheral wiring via among the second horizontal portion, and The upper surface of the word line wiring through-via contacts the lower surface of the interconnection line on the first peripheral wiring.

14. The semiconductor device according to claim 12, in, The word line wiring peripheral structure includes: a first peripheral wiring contact plug electrically connected to the first peripheral source / drain among the vertical plugs, and a peripheral wiring lower interconnection line contacting an upper surface of the word line wiring through via among the first horizontal portion.

15. The semiconductor device according to claim 12, in, The second peripheral interconnect structure includes a first via at a different vertical height, and a peripheral interconnect line electrically connected to the first via and at a different vertical height, wherein the first peripheral interconnect structure comprises a first conductive material, and The second peripheral interconnect structure includes a second conductive material different from the first conductive material.

16. The semiconductor device according to claim 1, wherein: The word line wiring connection structure further includes: a first bonding pad electrically connected to the structure under the word line wiring; and A second bonding pad is electrically connected to the word line wiring through-via and is in contact with the first bonding pad.

17. A semiconductor device, comprising: a first structure having a storage block region and an extension region adjacent to the storage block region in a first direction; as well as a second structure vertically overlapping the first structure and having a peripheral circuit region vertically overlapping the memory block region, The first structure includes a memory cell, a word line and a bit line, wherein the memory cell is located in the memory block region and each of the memory cells includes a vertical channel transistor and a data storage structure, the word line is electrically connected to the memory cell, crosses the memory block region and extends to the extension region, and the bit line is electrically connected to the memory cell and crosses the memory block region. The second structure includes a semiconductor body, a first peripheral transistor, a second peripheral transistor, and a through-insulating pattern located in the semiconductor body. wherein the first structure and the second structure include a first word line signal path electrically connecting the word line to the first peripheral transistor and a bit line signal path electrically connecting the bit line to the second peripheral transistor, wherein the first word line signal path comprises a word line wiring through-path, a word line contact and a word line wiring lower structure, the word line wiring through-path penetrates a first through-insulating pattern among the through-insulating patterns and vertically overlaps the memory block region, the word line contact contacts the word line in the extension region, and the word line wiring lower structure electrically connects the word line contact to the word line wiring through-path, The bit line signal path includes a bit line wiring through-path, a bit line contact and a bit line wiring lower structure, wherein the bit line wiring through-path penetrates a second through-insulating pattern among the through-insulating patterns and vertically overlaps the memory block region, the bit line contact contacts the bit line, and the bit line wiring lower structure electrically connects the bit line contact to the bit line wiring through-path, The lower surface of the word line wiring through-via and the lower surface of the bit line wiring through-via are located at a height lower than the lower surface of the through-insulating pattern, and The upper surface of the word line wiring through via and the upper surface of the bit line wiring through via are located at a height higher than the upper surface of the through insulating pattern.

18. The semiconductor device according to claim 17, in, The second structure also includes: a back side insulating layer, the back side insulating layer being located below the semiconductor body and the through insulating pattern; and an isolation region defining a peripheral active region on the semiconductor body, wherein the lower surface of the semiconductor body and the lower surface of the through-insulation pattern are in contact with the back-side insulation layer, and The word line wiring through-via and the bit line wiring through-via penetrate at least a portion of the back insulating layer.

19. A semiconductor device, comprising: a first structure having a first storage block region and a second storage block region adjacent to each other in a first direction, and an extension region located between the first storage block region and the second storage block region; as well as a second structure vertically overlapping the first structure and including a first peripheral circuit region vertically overlapping the first memory block region and a second peripheral circuit region vertically overlapping the second memory block region, The first structure includes storage cells and word lines, the storage cells are located in the first storage block area and the second storage block area respectively, and each of the storage cells includes a vertical channel transistor and a data storage structure, the word line passes through the first storage block area, the second storage block area and the extension area and is electrically connected to the storage cells located in the first storage block area and the storage cells located in the second storage block area, The second structure includes a semiconductor body, a peripheral transistor, and a through-insulation pattern located in the semiconductor body. wherein the first structure and the second structure include a first word line signal path electrically connecting the word line to a first peripheral transistor among the peripheral transistors, wherein the first word line signal path comprises a word line wiring through-path, a word line contact and a word line wiring lower structure, the word line wiring through-path penetrates a first through-insulating pattern among the through-insulating patterns and vertically overlaps the first memory block region, the word line contact contacts the word line in the extension region, and the word line wiring lower structure electrically connects the word line contact to the word line wiring through-path, The lower surface of the word line wiring through-path is located at a height lower than the lower surface of the through-insulating pattern, and The upper surface of the word line wiring through-via is located at a height higher than the upper surface of the through-insulating pattern.

20. The semiconductor device according to claim 19, in, The extended region is a first extended region, The first structure further comprises a third storage block region adjacent to the first storage block region in a second direction perpendicular to the first direction, and a second extension region between the first storage block region and the third storage block region. Wherein, the first structure includes: a first bit line, the first bit line crossing the first memory block region in the second direction and electrically connected to the memory cells of the first memory block region; and a second bit line, the second bit line crossing the third memory block region in the second direction and being electrically connected to the memory cell of the third memory block region, Wherein, the first structure and the second structure further include: a first bit line signal path electrically connecting the first bit line to a second peripheral transistor among the peripheral transistors; and a second bit line signal path electrically connecting the second bit line to a third peripheral transistor among the peripheral transistors, wherein the second peripheral transistor and the third peripheral transistor vertically overlap with the first storage block region, wherein the first bit line signal path penetrates a second through-insulation pattern among the through-insulation patterns and includes a first bit line wiring through-path vertically overlapping the first memory block region, and The second bit line signal path penetrates a third through-insulation pattern among the through-insulation patterns and includes a second bit line wiring through-via that does not vertically overlap the first memory block region.

Images