Methods of forming microelectronic devices and related microelectronic devices and electronic systems

Abstract

The invention relates to a method of forming a microelectronic device and a related microelectronic device and an electronic system. A method of forming a microelectronic device includes forming a microelectronic device structure including: a substrate structure; the doped semi-conductive structure comprises a first part overlying the substrate structure and a second part vertically extending into the substrate structure from the first part; a stack structure overlying the doped semiconductive structure; a cell pillar structure extending vertically through the stack structure to the doped semiconductive structure; and a digital line structure vertically overlying the stacked structure. Additional microelectronic device structures including control logic devices are formed. The microelectronic device structure is attached to an additional microelectronic device structure to form a microelectronic device structure assembly. The carrier structure and the second portion of the doped semiconductive structure are removed. The first portion of the doped semiconductive structure is then patterned to form at least one source structure coupled to the cell pillar structure. Apparatus and systems are also described.

Description

[0001] Information about divisional applications

[0002] This application is a divisional application of the Chinese invention patent application with application number 202110670320.8, application date June 17, 2021, and invention name “Method of forming a microelectronic device and related microelectronic devices and electronic systems”.

[0003] CROSS REFERENCE TO RELATED APPLICATIONS

[0004] This application claims the benefit of the filing date of U.S. patent application serial number 16 / 905,747, filed on June 18, 2020, entitled “METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES AND ELECTRONIC SYSTEMS,” which is related to U.S. patent application serial number 16 / 905,385, filed on June 18, 2020, entitled “MICROELECTRONIC DEVICES, AND RELATED METHODS, MEMORY DEVICES, AND ELECTRONIC SYSTEMS,” which lists Kunal R. Parekh as the inventor. This application is also related to U.S. patent application Ser. No. 16 / 905,452, filed on June 18, 2020, entitled “METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES, MEMORY DEVICES, ELECTRONIC SYSTEMS, AND ADDITIONAL METHODS”, which lists Kunal R. Parekh as the inventor. This application is also related to U.S. patent application Ser. No. 16 / 905,698, filed on June 18, 2020, entitled “METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES AND ELECTRONIC SYSTEMS”, which lists Kunal R. Parekh as the inventor. This application is also related to U.S. patent application serial number 16 / 905,763, filed on June 18, 2020, entitled “METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES AND ELECTRONIC SYSTEMS,” which lists Kunal R. Parekh as the inventor.This application is also related to U.S. Patent Application Serial No. 16 / 905,734, filed on June 18, 2020, entitled “METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED BASE STRUCTURES FOR MICROELECTRONIC DEVICES”, listing Kunal R. Parekh as the inventor. The disclosures of each of the above filings are hereby incorporated herein by reference in their entirety. Technical Field

[0005] In various embodiments, the present disclosure relates generally to the field of microelectronic device design and fabrication. More particularly, the present disclosure relates to methods of forming microelectronic devices and related microelectronic devices and electronic systems. Background Art

[0006] Microelectronic device designers generally wish to increase the integration or density of features within a microelectronic device by reducing the size of individual features and by reducing the separation distance between adjacent features. In addition, microelectronic device designers generally wish to design an architecture that is not only small but also provides performance advantages and manufacturing design simplification, ease, and inexpensiveness.

[0007] One example of a microelectronic device is a memory device. Memory devices are typically provided as internal integrated circuits in computers or other electronic devices. There are many types of memory devices, including, but not limited to, non-volatile memory devices (e.g., NAND flash memory devices). One way to increase the memory density of non-volatile memory devices is to utilize a vertical memory array (also referred to as a "three-dimensional (3D) memory array") architecture. Conventional vertical memory arrays include vertical memory strings extending through openings in one or more vertical layers (e.g., stacked structures) of a hierarchy including conductive structures and dielectric materials. Each vertical memory string may include at least one selection device coupled in series to a series combination of vertically stacked memory cells. Compared to structures with conventional planar (e.g., two-dimensional) transistor arrangements, this configuration permits more switching devices (e.g., transistors) to be positioned in a unit die area (i.e., the length and width of the effective surface consumed) by building the array upward (e.g., vertically) on the die.

[0008] Control logic devices within a substrate control logic structure underlying a memory array of a memory device (e.g., a non-volatile memory device) have been used to control operations (e.g., access operations, read operations, write operations) on memory cells of the memory device. Assemblies of control logic devices may be provided to be electrically connected to memory cells of the memory array through wiring and interconnect structures. However, processing conditions (e.g., temperature, pressure, materials) used to form the memory array on top of the substrate control logic structure may limit the configuration and performance of the control logic devices within the substrate control logic structure. In addition, the number, size, and arrangement of different control logic devices employed within the substrate control logic structure may also undesirably hinder the reduction in size (e.g., horizontal footprint) of the memory device and / or the improvement in performance (e.g., faster memory cell on / off speeds, lower threshold switching voltage requirements, faster data transfer rates, lower power consumption) of the memory device. Summary of the invention

[0009] In some embodiments, a method of forming a microelectronic device includes forming a microelectronic device structure. The microelectronic device structure includes: a base structure; a doped semiconductive structure including a first portion overlying the base structure and a second portion extending vertically from the first portion into the base structure; a stacked structure overlying the doped semiconductive structure and including a vertical alternating sequence of conductive structures and insulating structures; a cell pillar structure extending vertically through the stacked structure to the first portion of the doped semiconductive structure; and a digit line structure vertically overlying the stacked structure. An additional microelectronic device structure including a control logic device is formed. The microelectronic device structure is attached to the additional microelectronic device structure to form a microelectronic device structure assembly. The digit line structure is vertically interposed between the stacked structure and the control logic device within the microelectronic device structure assembly. The base structure and the second portion of the doped semiconductive structure are removed to expose the first portion of the doped semiconductive structure. The first portion of the doped semiconductive structure is patterned after removing the base structure and the second portion of the doped semiconductive structure to form at least one source structure coupled to the cell pillar structure on the stacked structure.

[0010] In an additional embodiment, a microelectronic device includes a memory array region, a control logic region, a first interconnect region, and a second interconnect region. The memory array region includes: a stacked structure including a vertically alternating sequence of conductive structures and insulating structures; a source structure vertically overlying the stacked structure and including a doped semiconductive material; a cell pillar structure vertically extending completely through the stacked structure to the source structure; a source contact structure vertically extending completely through the stacked structure into the source structure; and a digit line structure vertically underlying the stacked structure and electrically communicating with the cell pillar structure. The control logic region vertically underlies the memory array region and includes a control logic device. The first interconnect region is vertically interposed between the memory array region and the control logic region and includes additional conductive structures coupling the digit line structures of the memory array region to the control logic devices of the control logic region. The second interconnect region vertically overlies the memory array region and includes additional conductive structures electrically communicating with the source structure.

[0011] In another embodiment, an electronic system includes: an input device; an output device; a processor device operably coupled to the input device and the output device; and a memory device operably coupled to the processor device. The memory device includes a stacked structure, a source structure, a digit line structure, a cell pillar structure, a deep contact structure, a conductive wiring structure, a control logic device, and an additional conductive wiring structure. The stacked structure includes levels each including a conductive structure and an insulating structure vertically adjacent to the conductive structure. The source structure overlies the stacked structure. The digit line structure underlies the stacked structure. The cell pillar structure is coupled to the digit line structure and extends vertically completely through the stacked structure to the source structure. The deep contact structure extends vertically completely through the stacked structure into the source structure. The conductive wiring structure vertically underlies and is coupled to the digit line structure. The control logic device is coupled to and at least partially vertically underlies the conductive wiring structure. The additional conductive wiring structure is coupled to and vertically overlies the source structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figures 1A to 1G is a simplified partial cross-sectional view illustrating a method of forming a microelectronic device structure according to an embodiment of the present disclosure.

[0013] Figures 2A to 2H The invention is to illustrate the use of the embodiments according to the present disclosure by referring to Figures 1A to 1F A simplified partial cross-sectional view of a method of forming a microelectronic device structure formed by the described method.

[0014] Figure 3is a schematic block diagram of an electronic system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0015] The following description provides specific details such as material composition, shape and size to provide a detailed description of the embodiments of the present disclosure. However, it should be understood by a person skilled in the art that the embodiments of the present disclosure can be practiced without adopting these specific details. In fact, the embodiments of the present disclosure can be practiced in combination with conventional microelectronic device manufacturing techniques used in industry. In addition, the description provided below does not form a complete process flow for manufacturing microelectronic devices (e.g., memory devices, such as 3D NAND flash memory devices). The structure described below does not form a complete microelectronic device. Only those process actions and structures required to understand the embodiments of the present disclosure are described in detail below. Additional actions to form a complete microelectronic device from the structure can be performed by conventional manufacturing techniques.

[0016] The drawings presented herein are for illustration only and do not imply actual drawings of any particular material, component, structure, device, or system. Changes in the shapes depicted in the drawings due to, for example, manufacturing techniques and / or tolerances may be expected. Therefore, the embodiments described herein should not be interpreted as being limited to the specific shapes or regions described, but rather include shape deviations due to, for example, manufacturing. For example, an area described or described as a frame may have rough and / or nonlinear features, and an area described or described as a circle may include some rough and / or linear features. In addition, the sharp angles described may be rounded, and vice versa. Therefore, the areas described in the figures are schematic, and their shapes do not wish to illustrate the precise shape of the areas and do not limit the scope of the claims of the present invention. The drawings are not necessarily drawn to scale. In addition, common elements between the figures may retain the same element symbol designation.

[0017] As used herein, "memory device" means and includes a microelectronic device that exhibits memory functionality, but is not necessarily limited to memory functionality. In other words, and by way of non-limiting example only, the term "memory device" includes not only conventional memory (e.g., conventional volatile memory, such as conventional dynamic random access memory (DRAM); conventional non-volatile memory, such as conventional NAND memory), but also application specific integrated circuits (ASICs) (e.g., single chip systems (SoCs)), microelectronic devices that combine logic and memory, and graphics processing units (GPUs) that incorporate memory.

[0018] As used herein, the term "configured" refers to the size, shape, material composition, orientation, and arrangement of one or more of at least one structure and at least one apparatus that facilitates operation of the structure and one or more of the apparatus in a predetermined manner.

[0019] As used herein, the terms "vertical," "longitudinal," "horizontal," and "lateral" are referenced to a principal plane of a structure and are not necessarily defined by the earth's gravitational field. A "horizontal" or "lateral" direction is a direction substantially parallel to a principal plane of a structure, while a "vertical" or "longitudinal" direction is a direction substantially perpendicular to a principal plane of a structure. A principal plane of a structure is defined by a surface of the structure having a relatively larger area than other surfaces of the structure. With reference to the figures, a "horizontal" or "lateral" direction may be perpendicular to the indicated "Z" axis, and may be parallel to the indicated "X" axis and / or parallel to the indicated "Y" axis; and a "vertical" or "longitudinal" direction may be parallel to the indicated "Z" axis, may be perpendicular to the indicated "X" axis, and may be perpendicular to the indicated "Y" axis.

[0020] As used herein, features (e.g., regions, structures, devices) described as being "adjacent" to each other mean and include features of one (or several) disclosed individuals that are positioned closest to each other (e.g., closest). Additional features (e.g., additional regions, additional structures, additional devices) of one (or several) disclosed individuals that do not match "adjacent" features may be disposed between "adjacent" features. In other words, "adjacent" features may be positioned directly adjacent to each other so that no other features intervene between the "adjacent" features; or "adjacent" features may be positioned indirectly adjacent to each other so that at least one feature of an individual other than an individual associated with at least one "adjacent" feature is positioned between the "adjacent" features. Therefore, features described as being "vertically adjacent" to each other mean and include features of one (or several) disclosed individuals that are positioned closest to each other vertically (e.g., closest vertically). In addition, features described as being "horizontally adjacent" to each other mean and include features of one (or several) disclosed individuals that are positioned closest to each other horizontally (e.g., closest horizontally).

[0021] As used herein, for ease of description, spatially relative terms (e.g., "below," "beneath," "bottom," "above," "up," "top," "front," "rear," "left," "right," and the like) may be used to describe the relationship of one element or feature to another element or feature, as illustrated in the figures. Unless otherwise specified, spatially relative terms are intended to encompass different orientations of material in addition to the orientation depicted in the figures. For example, if the material in the figure is reversed, an element described as being "below" or "beneath" or "under" or "on the bottom" of other elements or features would be oriented "above" or "on the top" of the other elements or features. Thus, one of ordinary skill in the art will appreciate that the term "below" may encompass both above and below orientations, depending on the context in which the term is used. The material may be oriented in other ways (e.g., rotated 90 degrees, reversed, flipped) and the spatially relative descriptors used herein interpreted accordingly.

[0022] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0023] As used herein, "and / or" includes any and all combinations of one or more of the associated listed items.

[0024] As used herein, the phrase "coupled to" means that structures are operatively connected to each other, such as by a direct ohmic connection or electrically connected through an indirect connection (such as through another structure).

[0025] As used herein, the term "substantially" with respect to a given parameter, property, or condition means and encompasses the degree to which a given parameter, property, or condition is satisfied within a certain degree of variation (e.g., within an acceptable tolerance) as understood by those of ordinary skill in the art. By way of example, depending on the particular parameter, property, or condition that is substantially satisfied, the parameter, property, or condition may be satisfied by at least 90.0%, satisfied by at least 95.0%, satisfied by at least 99.0%, satisfied by at least 99.9%, or even satisfied by 100%.

[0026] As used herein, "about" or "substantially" with respect to a numerical value of a particular parameter includes the numerical value and the degree of variation of the numerical value within an acceptable tolerance for the particular parameter as understood by one of ordinary skill in the art. For example, "about" or "substantially" with respect to a numerical value may include additional numerical values ​​within a range from 90.0% to 110.0% of the numerical value, such as within a range from 95.0% to 105.0% of the numerical value, within a range from 97.5% to 102.5% of the numerical value, within a range from 99.0% to 101.0% of the numerical value, within a range from 99.5% to 100.5% of the numerical value, or within a range from 99.9% to 100.1% of the numerical value.

[0027] As used herein, "conductive material" means and includes conductive materials such as one or more of the following: metals (e.g., tungsten (W), titanium (T), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pa), platinum (Pt), copper (Cu), silver (Ag), gold (Au), aluminum (Al)), alloys (e.g., Co-based The invention also includes conductive materials such as conductive materials (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides) and conductive doped semiconductor materials (e.g., conductive doped polysilicon, conductive doped germanium (Ge), conductive doped silicon germanium (SiGe)). In addition, the term "conductive structure" means and includes a structure formed of a conductive material and including a conductive material.

[0028] As used herein, "insulating material" means and includes electrically insulating materials, such as one or more of the following: at least one dielectric oxide material (such as one or more of the following: silicon oxide (SiO x ), phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, aluminum oxide (AlO x ), hafnium oxide (HfO x ), niobium oxide (NbO x ), titanium oxide (TiO x )、ZrO x ), tantalum oxide (TaO x ) and magnesium oxide (MgO x )), at least one dielectric nitride material (e.g. silicon nitride (SiN y )), at least one dielectric oxynitride material (e.g., silicon oxynitride (SiO x N y )), at least one dielectric carbide material (e.g., silicon oxycarbide (SiO x C y )), at least one hydrogenated dielectric oxycarbide material (e.g., hydrogenated silicon oxycarbide (SiC x O y H z )) and at least one dielectric carbon oxynitride material (e.g., silicon carbon oxynitride (SiO x C z N y)). A chemical formula (e.g., SiO x 、AlO x , HfO x 、NbO x 、TiO x 、SiN y 、SiO x N y 、SiO x C y 、SiC x O y H z 、SiO x C z N y ) represents a material containing an average ratio of "x" atoms of one element, "y" atoms of another element, and "z" atoms of an additional element (if present) for each atom of the other element (e.g., Si, Al, Hf, Nb, Ti). Since the chemical formula represents relative atomic ratios rather than absolute chemical structures, the insulating material may include one or more stoichiometric compounds and / or one or more non-stoichiometric compounds, and the values ​​of "x", "y", and "z" (if present) may be integers or may be non-integers. As used herein, the term "non-stoichiometric compound" means and includes chemical compounds with elemental compositions that cannot be represented by well-defined natural number ratios and violate the law of definite proportions. In addition, an "insulating structure" means and includes a structure formed by and including an insulating material.

[0029] Unless the context indicates otherwise, the materials described herein may be formed by any suitable technique including, but not limited to, spin coating, blanket coating, chemical vapor deposition ("CVD"), atomic layer deposition ("ALD"), plasma enhanced ALD, physical vapor deposition ("PVD") (e.g., sputtering), or epitaxial growth. Depending on the specific material to be formed, the technique for depositing or growing the material may be selected by one of ordinary skill in the art. Additionally, unless the context indicates otherwise, removal of the materials described herein may be accomplished by any suitable technique including, but not limited to, etching (e.g., dry etching, wet etching, vapor etching), ion milling, grinding planarization, or other known methods.

[0030] Figures 1A to 1G 1 is a simplified partial cross-sectional diagram illustrating an embodiment of a method of forming a microelectronic device structure (e.g., a memory device structure) of a microelectronic device (e.g., a memory device, such as a 3D NAND flash memory device). With respect to the description provided below, one of ordinary skill in the art will readily appreciate that the methods described herein can be used in a variety of applications. In other words, the methods of the present disclosure can be used any time it is desired to form a microelectronic device.

[0031] refer to Figure 1A , the microelectronic device structure 100 may be formed to include a base structure 102 and a doped semiconductive material 104 in, on, or above the base structure 102. Figure 1A , in some embodiments, the doped semiconductive material 104 is formed on the upper surface of the base structure 102. In additional embodiments, at least one material (e.g., at least one insulating material) is formed between the base structure 102 and the doped semiconductive material 104. As a non-limiting example, a dielectric oxide material (e.g., SiO x , such as silicon dioxide (SiO2)) may be formed between (e.g., formed vertically on) the base structure 102 and the doped semiconductive material 104. In further embodiments, the doped semiconductive material 104 is also formed on or over one or more additional surfaces of the base structure 102. As a non-limiting example, a first portion of the doped semiconductive material 104 may be formed on or over an upper surface of the base structure 102, and a second portion of the doped semiconductive material 104 may be formed below (e.g., below and in physical contact with) a lower surface of the base structure 102.

[0032] The base structure 102 of the microelectronic device structure 100 includes a base material or construction upon which additional features (eg, materials, structures, devices) of the microelectronic device structure 100 may be formed. The base structure 102 may be formed, for example, from and include one or more of a semiconductive material (e.g., one or more of a silicon material, such as single crystal silicon or polycrystalline silicon (polycrystalline silicon) (also referred to herein as “polysilicon”); silicon germanium; germanium; gallium arsenide; gallium nitride; gallium phosphide; indium phosphide; indium gallium nitride; and aluminum gallium nitride), a base semiconductive material on a support structure, a glass material (e.g., one or more of borosilicate glass (BSP), phosphosilicate glass (PSG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), aluminosilicate glass, alkaline earth boroaluminosilicate glass, quartz, titanosilicate glass, and soda-lime glass), and a ceramic material (e.g., one or more of polyaluminum nitride (p-AlN), silicon on polyaluminum nitride (SOPAN), aluminum nitride (AlN), aluminum oxide (e.g., sapphire; α-Al2O3), and silicon carbide). The base structure 102 can be configured to facilitate safe handling of the microelectronic device structure 100 for subsequent attachment to at least one additional microelectronic device structure, as described in more detail below.

[0033] The doped semiconductive material 104 may be formed of and include at least one semiconductive material doped with at least one conductive dopant (e.g., at least one n-type dopant, such as one or more of phosphorus (P), arsenic (Ar), antimony (Sb), and bismuth (Bi); at least one p-type dopant, such as one or more of boron (B), aluminum (Al), and gallium (Ga)). In some embodiments, the doped semiconductive material 104 is formed of and includes one or more of: a silicon material, such as single crystal silicon or polycrystalline silicon; a silicon germanium material; a germanium material; a gallium arsenide material; a gallium nitride material; and an indium phosphide material. As a non-limiting example, the doped semiconductive material 104 may be formed of and include epitaxial silicon (e.g., single crystal silicon formed by epitaxial growth) doped with at least one conductive dopant (e.g., at least one n-type dopant, at least one p-type dopant). As another non-limiting example, the doped semiconductive material 104 may be formed of and include polysilicon doped with at least one conductive dopant (eg, at least one n-type dopant, at least one p-type dopant).

[0034] Next reference Figure 1B , the preliminary stack structure 106 may be formed on or above the doped semiconductive material 104. Figure 1B , the preliminary stacked structure 106 includes a vertically alternating (e.g., in the Z direction) sequence of insulating structures 108 and sacrificial structures 110 arranged into levels 112. Each of the levels 112 of the preliminary stacked structure 106 may include at least one of the sacrificial structures 110 vertically adjacent to at least one of the insulating structures 108. The preliminary stacked structure 106 may be formed to include any desired number of levels 112, such as greater than or equal to sixteen (16) levels 112, greater than or equal to thirty-two (32) levels 112, greater than or equal to sixty-four (64) levels 112, greater than or equal to one hundred twenty-eight (128) levels 112, or greater than or equal to two hundred fifty-six (256) levels 112.

[0035] The insulating material 108 of the level 112 of the preliminary stacked structure 106 may be formed of and include at least one insulating material such as one or more of the following: at least one dielectric oxide material (such as one or more of the following: SiO x , phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, AlO x , HfO x 、NbO x 、TiO x 、ZrO x 、TaO x and MgO x ), at least one dielectric nitride material (e.g. SiNy ), at least one dielectric oxynitride material (e.g. SiO x N y ) and at least one dielectric carbon oxynitride material (e.g. SiO x C z N y ). Each of the insulating structures 108 may be individually substantially homogenous, or may be substantially heterogeneous. As used herein, the term "homogeneous" means that the amount of material does not change in all different parts of the structure (e.g., different horizontal parts, different vertical parts). Conversely, as used herein, the term "heterogeneous" means that the amount of material changes in all different parts of the structure. In some embodiments, each of the insulating structures 108 is substantially homogenous. In further embodiments, at least one of the insulating structures 108 is substantially heterogeneous. One or more of the insulating structures 108 may, for example, be formed by and include a stack (e.g., a laminated material) of at least two different insulating materials (e.g., at least two different dielectric materials). In some embodiments, each of the insulating structures 108 is made of a dielectric oxide material (e.g., SiO x The insulating structures 108 may be formed of a dielectric material (e.g., SiO2) and include the dielectric oxide material. The insulating structures 108 may each be substantially planar, and may each individually exhibit a desired thickness (e.g., a vertical height in the Z direction). In addition, each of the insulating structures 108 may be substantially identical to one another (e.g., having substantially the same material composition, material distribution, size, and shape), or at least one of the insulating structures 108 may be different from at least another of the insulating structures 108 (e.g., having one or more of a different material composition, a different material distribution, a different size, and a different shape). In some embodiments, each of the insulating structures 108 is substantially identical to each other of the insulating structures 108.

[0036] The sacrificial structure 110 of the level 112 of the preliminary stacked structure 106 may be formed of and include at least one material (e.g., at least one insulating material) that is selectively removable relative to the insulating material of the insulating structure 108. The material composition of the sacrificial structure 110 is different from the material composition of the insulating material 108. The sacrificial structure 110 may be selectively etched relative to the insulating structure 108 during common (e.g., collective, mutual) exposure to a first etchant, and the insulating structure 108 may be selectively etched relative to the sacrificial structure 110 during common exposure to a second, different etchant. As used herein, a material is "selectively etchable" relative to another material if it exhibits an etch rate that is at least about five times (5x) greater than the etch rate of the other material, such as about ten times (10x), about twenty times (20x), or about forty times (40x). As a non-limiting example, the sacrificial structure 110 may be formed of and include an additional insulating material such as one or more of the following: at least one dielectric oxide material (e.g., one or more of the following: SiO x , phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, AlO x , HfO x 、NbO x 、TiO x 、ZrO x 、TaO x and MgO x ), at least one dielectric nitride material (e.g. SiN y ), at least one dielectric oxynitride material (e.g. SiO x N y ) and at least one dielectric carbon oxynitride material (e.g. SiO x C z N y In some embodiments, each of the sacrificial structures 110 is made of a dielectric nitride material (eg, SiN yThe sacrificial structures 110 may be formed of a dielectric nitride material (e.g., Si3N4) and include the dielectric nitride material. Each of the sacrificial structures 110 may be individually substantially homogeneous or substantially heterogeneous. In some embodiments, each of the sacrificial structures 110 of the preliminary stacked structure 106 is substantially homogeneous. In additional embodiments, at least one of the sacrificial structures 110 of the preliminary stacked structure 106 is substantially heterogeneous. The sacrificial structures 110 may each be substantially planar and may each individually exhibit a desired thickness (e.g., a vertical height in the Z direction). In addition, each of the sacrificial structures 110 may be substantially identical to one another (e.g., exhibiting substantially identical material compositions, material distributions, sizes, and shapes), or at least one of the sacrificial structures 110 may be different from at least another of the sacrificial structures 110 (e.g., exhibiting one or more of different material compositions, different material distributions, different sizes, and different shapes). In some embodiments, each of the sacrificial structures 110 is substantially identical to each other of the sacrificial structures 110.

[0037] Next reference Figure 1C , an opening 114 (e.g., a pore, a through-hole) may be formed to extend vertically (e.g., in the Z direction) through each of the preliminary stacked structure 106 and the doped semiconductive material 104 into the base structure 102; and then, at least one semiconductive material 115 may be formed (e.g., epitaxially grown) within the opening 114 and may partially fill the opening 114. Figure 1C As shown, the openings 114 can each individually extend vertically from the uppermost surface of the preliminary stack structure 106 to a vertical position between the uppermost surface of the base structure 102 and the lowermost surface of the base structure 102. The semiconductive material 115 can fill the lower portion of each opening 114, as described in more detail below. The remaining (e.g., unfilled) upper portion of the openings 114 can be used to form a cell pillar structure for forming a vertically extending string of memory cells, as described in more detail below.

[0038] The openings 114 may each be individually formed to exhibit a geometric configuration (e.g., size, shape) and spacing. The geometric configuration and spacing of the openings 114 may be selected based at least in part on the configuration and location of other features of the microelectronic device structure 100. For example, the openings 114 may be sized, shaped, and spaced to facilitate the desired geometric configuration and spacing of additional features (e.g., additional structures, additional materials) subsequently formed therein. In some embodiments, each opening 114 is formed to have a substantially circular horizontal cross-sectional shape. In additional embodiments, one or more (e.g., each) of the openings 114 is formed to have a different (e.g., non-circular) horizontal cross-sectional shape, such as one or more of the following: a quadrangular horizontal cross-sectional shape (e.g., a square horizontal cross-sectional shape), an oval horizontal cross-sectional shape, an elliptical horizontal cross-sectional shape, a triangular horizontal cross-sectional shape, or other horizontal cross-sectional shapes. Each of the openings 114 may be formed to exhibit a geometric configuration (e.g., the same size and the same shape) and horizontal spacing (e.g., in the X direction, in the Y direction) that is substantially the same as every other of the openings 114, or at least some of the openings 114 may be formed to exhibit a geometric configuration (e.g., one or more different sizes, different shapes) and / or horizontal spacing that is different from at least some other of the openings 114.

[0039] Still refer to Figure 1C In each opening 114, the semiconductive material 115 may be formed (e.g., epitaxially grown) to vertically extend from a lower vertical boundary of the opening 114 within the base structure 102 (e.g., between an uppermost surface of the base structure 102 and a lowermost surface of the base structure 102) to a position vertically within or beyond the doped semiconductive material 104. In some embodiments, within each opening 114, an upper boundary (e.g., an upper surface) of the semiconductive material 115 is formed to be substantially coplanar with an upper boundary (e.g., an upper surface) of the doped semiconductive material 104. In additional embodiments, within each opening 114, an upper boundary (e.g., an upper surface) of the semiconductive material 115 is formed to be vertically offset from an upper boundary (e.g., an upper surface) of the doped semiconductive material 104. As a non-limiting example, an upper boundary of the semiconductive material 115 may vertically overlie an upper boundary of the doped semiconductive material 104 such that the semiconductive material 115 vertically extends upward beyond the doped semiconductive material 104. As another non-limiting example, an upper boundary of the semiconductive material 115 may vertically underlie an upper boundary of the doped semiconductive material 104 such that the semiconductive material 115 does not extend vertically upward beyond the doped semiconductive material 104 .

[0040] Semiconductive material 115 may be formed of and include epitaxial semiconductive material (eg, semiconductive material formed by epitaxial growth). In some embodiments, semiconductive material 115 is formed of and includes epitaxial silicon (eg, single crystal silicon formed by epitaxial growth).

[0041] Next reference Figure 1D , doped semiconductive material 104 ( Figure 1C ) and semiconductive material 115( Figure 1C ) may be annealed (eg, thermal annealing, laser annealing) to form a doped semiconductive structure 105. The doped semiconductive material 104 ( Figure 1C ) and semiconductive material 115( Figure 1C ) annealing can remove the dopant from the doped semiconductive material 104 ( Figure 1C ) diffuses into the semiconductive material 115 ( Figure 1C ) and may also promote or enhance dopant activation. The doped semiconductive structure 105 may be formed to be substantially homogeneous or may be formed to be heterogeneous. In some embodiments, the doped semiconductive structure 105 is formed to be substantially homogeneous. In additional embodiments, the doped semiconductive structure 105 is formed to be heterogeneous.

[0042] The doped semiconductive structure 105 may have a structure corresponding to the doped semiconductive material 104 ( Figure 1C ) and semiconductive material 115( Figure 1C ) is the geometric configuration (e.g., shape, size) of the combined geometric configuration of Figure 1D As shown in FIG. 1 , the doped semiconductive structure 105 may include a first portion 105A and a second portion 105B vertically underlying the first portion 105A and protruding (eg, extending vertically) into the base structure 102 .

[0043] Next reference Figure 1E , the unit pillar structure 116 can be formed in the opening 114 ( Figure 1D ). The unit pillar structure 116 may at least partially (eg, substantially) fill the opening 114 ( Figure 1D ). The unit pillar structure 116 may extend vertically (eg, in the Z direction) through the preliminary stacked structure 106 to the doped semiconductive structure 105 or into the doped semiconductive structure 105. Figure 1EAs shown, the cell pillar structures 116 may each individually extend vertically from the uppermost surface of the preliminary stacked structure 106 to a vertical position at or near the uppermost surface of the doped semiconductive structure 105. The uppermost surfaces of the cell pillar structures 116 may be substantially coplanar with the uppermost surface of the preliminary stacked structure 106, and the lowermost surfaces of the cell pillar structures 116 may be positioned at or below the uppermost surface of the doped semiconductive structure 105. If the cell pillar structures 116 extend vertically into the doped semiconductive structure 105, the cell pillar structures 116 may terminate vertically (e.g., end) within the first portion 105A of the doped semiconductive structure 105.

[0044] The cell pillar structures 116 may each be individually formed of and include a material stack to facilitate forming a vertically extending string of memory cells using the cell pillar structures 116 after subsequent processing actions, as described in more detail below. By way of non-limiting example, each of the cell pillar structures 116 may be formed to include a first dielectric oxide material 118 (e.g., SiO x , such as SiO2; AlO x , such as Al2O3), dielectric nitride material 120 (such as SiN y , such as Si3N4), a second oxide dielectric material 122 (such as SiO x , such as SiO2), a semiconductive material 124 (such as Si, such as polycrystalline Si) and a dielectric filling material 125 (such as dielectric oxide, dielectric nitride, air). The first dielectric oxide material 118 can be formed in the opening 114 ( Figure 1D ) on or above the surface of the microelectronic device structure 100 (e.g., the surface of the preliminary stacked structure 106 and the doped semiconductive structure 105) at the boundary (e.g., horizontal boundary, lower vertical boundary) of the remaining portion of the microelectronic device structure 100. The dielectric nitride material 120 may be formed in the opening 114 ( Figure 1D ) on the surface of the first dielectric oxide material 118 in the opening 114 ( Figure 1D ) on or above the surface of the dielectric nitride material 120 within the opening 114 ( Figure 1D ) on or above the surface of the second oxide dielectric material 122 within the cell pillar structure 116. The dielectric fill material 125 may occupy (e.g., fill) the opening 114 (not occupied by other features of the cell pillar structure 116, such as the first dielectric oxide material 118, the dielectric nitride material 120, the second oxide dielectric material 122, the semiconductive material 124). Figure 1D )’s central part.

[0045] The unit pillar structure 116 can be formed by sequentially depositing a first dielectric oxide material 118, a dielectric nitride material 120, a second oxide dielectric material 122, and a semiconductive material 124 in the opening 114 ( Figure 1D ) is formed within the remaining portion of the opening 114. Thereafter, the opening 114 ( Figure 1D ) to expose (e.g., reveal) a region of the doped semiconductive structure 105. In some embodiments, the first dielectric oxide material 118, the dielectric nitride material 120, the second oxide dielectric material 122, and the semiconductive material 124 are subjected to a through-etch to expose a region of the doped semiconductive structure 105. The through-etch may also partially etch into the doped semiconductive structure 105. Due to the opening 114 ( Figure 1D ) can taper horizontally inwardly as it vertically advances deeper into the microelectronic device structure 100, so that the formation of the doped semiconductive structure 105 can be achieved by relative to the opening 114 ( Figure 1D ) (eg, the lower boundary of the second portion 105B of the doped semiconductive structure 105) effectively increases the critical dimension of the opening 114 ( Figure 1D ) to facilitate the punch-through etching. After the punch-through etching, a dielectric filling material 125 may be provided on or above the semiconductive material 124, and a material removal process (e.g., a planarization process, such as a CMP process) may be used to expose the upper surface of the preliminary stack structure 106 and form the cell pillar structure 116.

[0046] Next reference Figure 1F The microelectronic device structure 100 may be subjected to a so-called "replacement gate" or "gate last" processing action to at least partially replace the preliminary stacked structure 106 ( Figure 1E ) of the sacrificial structure 110( Figure 1E ) and form a stacked structure 126. Figure 1F , the stacked structure 126 includes a vertically alternating (e.g., in the Z direction) sequence of additional insulating structures 128 and conductive structures 130 arranged in levels 132. The additional insulating structures 128 may correspond to the preliminary stacked structure 106 ( Figure 1E ) of the insulating structure 108 ( Figure 1E ) of the remaining (e.g., remaining portion, unremoved portion). Each of the levels 132 of the stacked structure 126 includes at least one of the conductive structures 130 vertically adjacent to at least one of the additional insulating structures 128. In addition, as Figure 1F, the deep contact structure 134 may be formed to extend vertically through the stack structure 126 to or into the doped semiconductive structure 105. The deep contact structure 134 may be electrically isolated from the conductive structure 130 of the level 132 of the stack structure 126 by an insulating liner structure 136 formed to horizontally interpose between the deep contact structure 134 and the stack structure 126.

[0047] The conductive structures 130 of the level 132 of the stacked structure 126 may be formed of and include a conductive material. By way of non-limiting example, the conductive structures 130 may each be individually formed of and include a metallic material including one or more of the following: at least one metal, at least one alloy, and at least one conductive metal-containing material (e.g., a conductive metal nitride, a conductive metal silicide, a conductive metal carbide, a conductive metal oxide). In some embodiments, the conductive structures 130 are formed of and include W. Each of the conductive structures 130 may be individually substantially homogeneous, or one or more of the conductive structures 130 may be individually substantially heterogeneous. In some embodiments, each of the conductive structures 130 is formed to be substantially homogeneous. In additional embodiments, each of the conductive structures 130 is formed to be heterogeneous. Each conductive structure 130 may, for example, be formed of and include a stack of at least two different conductive materials.

[0048] Still refer to Figure 1F , one or more liner materials (e.g., insulating liner materials, conductive liner materials) may be formed around the conductive structure 130. The liner material may, for example, be formed of and include one or more of the following: a metal (e.g., titanium, tantalum), an alloy, a metal nitride (e.g., tungsten nitride, titanium nitride, tantalum nitride), and a metal oxide (e.g., aluminum oxide). In some embodiments, the liner material includes at least one conductive material used as a seed material for forming the conductive structure 130. In some such embodiments, the liner material includes titanium nitride. In additional embodiments, the liner material further includes aluminum oxide. As a non-limiting example, aluminum oxide may be formed directly adjacent to the additional insulating structure 128, titanium nitride may be formed directly adjacent to the aluminum oxide, and tungsten may be formed directly adjacent to the titanium nitride. For clarity and to facilitate understanding of the description, one or more liner materials are not described in detail herein. Figure 1F Although not illustrated in FIG. 1 , it should be understood that the liner material may be disposed around the conductive structure 130 .

[0049] In order to form the stack structure 126 by the “replacement gate” process action, a slot (eg, a slit, a trench) may be formed to vertically extend through the preliminary stack structure 106 ( Figure 1D ) to form discrete blocks. Thereafter, the preliminary stacking structure 106 ( Figure 1D ) of the sacrificial structure 110( Figure 1D) can be selectively removed (e.g., selectively etched and dug) through the slots and replaced with a conductive material to form conductive structures 130. Some conductive structures 130 can be used as access line structures (e.g., word line structures) of a microelectronic device (e.g., a memory device, such as a 3D NAND flash memory device) subsequently formed using the microelectronic device structure 100, and other conductive structures 130 can be used as select gate structures of a subsequently formed microelectronic device. After the conductive structures 130 are formed, the slots can be filled with at least one dielectric material.

[0050] Continue to refer Figure 1E , the intersection of the cell pillar structure 116 and the conductive structure 130 of the level 132 of the stacked structure 126 can define a vertically extending string of memory cells 138 coupled in series with each other within the stacked structure 126. In some embodiments, the memory cells 138 formed at the intersection of the conductive structure 130 and the cell pillar structure 116 within the level 132 of the stacked structure 126 include so-called "MONOS" (metal-oxide-nitride-oxide-semiconductor) memory cells. In additional embodiments, the memory cells 138 include so-called "TANOS" (tantalum nitride-aluminum oxide-nitride-oxide-semiconductor) memory cells or so-called "BETANOS" (band / barrier engineered TANOS) memory cells, each of which is a subset of MONOS memory cells. In further embodiments, the memory cells 138 include so-called "floating gate" memory cells that include a floating gate (e.g., a metal floating gate) as a charge storage structure. The floating gate may be horizontally interposed between the central structure of the cell pillar structure 116 and the conductive structure 130 of different levels 132 of the stacked structure 126.

[0051] The deep contact structure 134 may be configured and positioned to electrically connect one or more features subsequently formed above the stacked structure 126 with one or more other features underlying the stacked structure 126 (e.g., the doped semiconductive structure 105, additional features subsequently formed and coupled to the doped semiconductive structure 105). The deep contact structure 134 may be formed of and include a conductive material. In some embodiments, the deep contact structure 134 is formed of and includes W. In additional embodiments, the deep contact structure 134 is formed of and includes conductive doped polysilicon.

[0052] The insulating liner structure 136 extends continuously over the side surface of the deep contact structure 134 and substantially covers the side surface. The insulating liner structure 136 may be formed of and include at least one insulating material such as one or more of the following: at least one dielectric oxide material (such as one or more of the following: SiO x, phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, AlO x , HfO x 、NbO x 、TiO x 、ZrO x 、TaO x and MgO x ), at least one dielectric nitride material (e.g. SiN y ), at least one dielectric oxynitride material (e.g. SiO x N y ) and at least one dielectric carbon oxynitride material (e.g. SiO x C z N y In some embodiments, each of the insulating liner structures 136 is made of at least one dielectric oxide material (eg, SiO x , such as SiO2) and includes the at least one dielectric oxide material.

[0053] Next reference Figure 1G , digit line structures 139 (e.g., data line structures, bit line structures), insulating line structures 140, digit line contact structures 142, bonding pads 144, and isolation materials 146 may be formed on or over stacked structures 126. Digit line structures 139 may be vertically formed over and electrically communicate with the vertically extending strings of memory cells 138 and deep contact structures 134. Insulating line structures 140 may be formed on or over digit line structures 139. Digit line structures 142 may vertically extend through insulating line structures 140 and may contact digit line structures 139. For each digit line contact structure 142, a first portion 142A thereof may vertically overlie one of the insulating line structures 140, and a second portion 142B thereof may vertically extend through insulating line structures 140 and contact (e.g., physically contact, electrically contact) one of the digit line structures 139. Bond pads 144 may be formed on or over digit line contact structures 142. Isolation material 146 may cover and surround portions of stack structure 126, digit line structure 139, insulated line structure 140, digit line contact structure 142, and bond pads 144.

[0054] The digit line structures 139 may exhibit horizontally elongated shapes extending in parallel in a first horizontal direction (e.g., the Y direction). As used herein, the term "parallel" means substantially parallel. The digit line structures 139 may each exhibit substantially the same size (e.g., width in the X direction, length in the Y direction, height in the Z direction), shape, and spacing (e.g., in the X direction). In additional embodiments, one or more of the digit line structures 139 may exhibit one or more of at least one size (e.g., different length, different width, different height) and shape that is different from one or more other of the digit line structures 139, and / or the spacing between at least two horizontally adjacent digit line structures 139 (e.g., in the X direction) may be different from the spacing between at least two other horizontally adjacent digit line structures 139.

[0055] The digit line structures 139 may be formed of and include a conductive material. By way of non-limiting example, the digit line structures 139 may each individually be formed of and include a metallic material including one or more of the following: at least one metal, at least one alloy, and at least one conductive metal-containing material (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide). In some embodiments, the digit line structures 139 are each individually formed of and include W. Each of the digit line structures 139 may be individually substantially homogeneous, or one or more of the digit line structures 139 may be individually substantially heterogeneous. If the digit line structures 139 are heterogeneous, the amount of one or more elements included in the conductive line structures 139 may change stepwise (e.g., abruptly) or continuously (e.g., gradually, e.g., linearly, parabolically) in all different portions of the conductive line structures 139. In some embodiments, each of the digit line structures 139 is substantially homogeneous. In additional embodiments, each of the digit line structures 139 is heterogeneous. Each digit line structure 139 may, for example, be formed of and include a stack of at least two different conductive materials.

[0056] The insulating line structure 140 may be used as an insulating cap structure (e.g., a dielectric cap structure) for the digit line structure 139. The insulating line structure 140 may have a horizontally elongated shape extending in parallel in a first horizontal direction (e.g., the Y direction). The horizontal size, horizontal path, and horizontal spacing of the insulating line structure 140 may be substantially the same as those of the digit line structure 139.

[0057] The insulated wire structures 140 may be formed of and include an insulating material. By way of non-limiting example, the insulated wire structures 140 may each be individually formed of a dielectric nitride material (e.g., SiN yThe insulating wire structures 140 may be formed of a dielectric nitride material (e.g., Si3N4) and include the dielectric nitride material. The insulating wire structures 140 may each be substantially homogeneous, or one or more of the insulating wire structures 140 may be heterogeneous. If the insulating wire structures 140 are heterogeneous, the amount of one or more elements included in the insulating wire structures 140 may be changed stepwise (e.g., abruptly) or continuously (e.g., gradually, e.g., linearly, parabolically) in all different parts of the insulating wire structures 140. In some embodiments, each of the insulating wire structures 140 is substantially homogeneous. In additional embodiments, each of the insulating wire structures 140 is heterogeneous. Each insulating wire structure 140 may be formed of and include, for example, a stack of at least two different dielectric materials.

[0058] Still refer to Figure 1G , individual digit line contact structures 142 may be at least partially (e.g., substantially) horizontally aligned with individual insulated line structures 140 in the X direction (and thus at least partially horizontally aligned with individual digit line structures 139). For example, the horizontal centerline of the digit line contact structure 142 in the X direction may be substantially aligned with the horizontal centerline of the insulated line structure 140 in the X direction. In addition, the digit line contact structure 142 may be formed at a desired position along the insulated line structure 140 (and thus along the digit line structure 139) in the Y direction. In some embodiments, at least some of the digit line contact structures 142 are provided at positions that are different from each other in the Y direction. For example, a first one of the digit line contact structures 142 may be provided at a position along the length of the first one of the insulated line structures 140 in the Y direction that is different from the position of a second one of the digit line contact structures 142 along the length of the second one of the insulated line structures 140 in the Y direction. In other words, at least some (e.g., all) of the digit line contact structures 142 may be horizontally offset from each other in the Y direction. In additional embodiments, two or more of the digit line contact structures 142 are horizontally aligned with each other in the Y direction. In some embodiments, the digit line contact structure 142 serves as a digit line contact structure (eg, a data line contact structure, a bit line contact structure) of a microelectronic device (eg, a memory device) to be formed using the microelectronic device structure 100 , as described in more detail below.

[0059] The digit line contact structure 142 may be formed to exhibit a desired geometric configuration (eg, desired size, desired shape). Figure 1G, in some embodiments, first portions 142A (e.g., upper portions) of individual digit line contact structures 142 are formed to be wider than second portions 142B (e.g., lower portions) of digit line contact structures 142. Side surfaces of isolation material 146 may define horizontal boundaries of digit line contact structures 142. Digit line contact structures 142 may extend vertically (e.g., in the Z direction) from lower vertical boundaries (e.g., lower surfaces) of bond pads 144 to upper vertical boundaries (e.g., upper surfaces) of digit line structures 139.

[0060] The digit line contact structures 142 may each be individually formed of and include a conductive material. By way of non-limiting example, the digit line contact structures 142 may be formed of and include one or more of the following: at least one metal, at least one alloy, and at least one conductive metal-containing material (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide). In some embodiments, the digit line contact structures 142 are formed of and include Cu. In additional embodiments, the digit line contact structures 142 are formed of and include W.

[0061] Bond pads 144 may be formed on or over the upper surface of digit line contact structure 142. Bond pads 144 may be formed to extend horizontally over multiple insulated line structures 140 (and therefore over multiple digit line structures 139). Individual bond pads 144 may be coupled to individual digit line contact structures 142. Bond pads 144 may be used to couple digit line contact structure 142 to additional bond pads and additional conductive contact structures, as described in more detail below.

[0062] Bond pads 144 may each individually be formed of and include a conductive material. By way of non-limiting example, bond pads 144 may be formed of and include one or more of: at least one metal, at least one alloy, and at least one conductive metal-containing material (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide). The material composition of bond pads 144 may be substantially the same as the material composition of digit line contact structure 142, or the material composition of bond pads 144 may be different from the material composition of digit line contact structure 142. In some embodiments, bond pads 144 are formed of and include Cu.

[0063] Still refer to Figure 1G , the isolation material 146 may be formed of and include at least one insulating material. By way of non-limiting example, the isolation material 146 may be formed of and include one or more of the following: at least one dielectric oxide material (e.g., one or more of the following: SiO x , phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, AlO x, HfO x 、NbO x and TiO x ), at least one dielectric nitride material (e.g. SiN y ), at least one dielectric oxynitride material (e.g. SiO x N y ), at least one dielectric carbon oxynitride material (e.g. SiO x C z N y ) and amorphous carbon. In some embodiments, the isolation material 146 is made of SiO x (e.g. SiO2) and includes SiO x (e.g., SiO2). Isolation material 146 may be substantially homogenous, or isolation material 146 may be heterogeneous. If isolation material 146 is heterogeneous, the amount of one or more elements included in isolation material 146 may change stepwise (e.g., abruptly) or continuously (e.g., gradually, e.g., linearly, parabolically) in all different portions of isolation material 146. In some embodiments, isolation material 146 is substantially homogenous. In additional embodiments, isolation material 146 is heterogeneous. Isolation material 146 may be formed of and include, for example, a stack of at least two different dielectric materials.

[0064] Previous references Figure 1G The microelectronic device structure 100 after the described process stages may be used to form a microelectronic device (e.g., a memory device, such as a 3D NAND flash memory device) of the present disclosure. By way of non-limiting example, Figures 2A to 2H is a simplified partial cross-sectional view illustrating a method of forming a microelectronic device according to an embodiment of the present disclosure. With respect to the description provided below, one of ordinary skill in the art will readily appreciate that the methods and structures described herein can be used to form a variety of devices and electronic systems.

[0065] refer to Figure 2A , which may be formed to be subsequently attached to the microelectronic device structure 100 ( Figure 1G ). The additional microelectronic device structure 200 can be formed to include a semiconductive base structure 202, a gate structure 204, a first wiring structure 206, a first contact structure 208, a second contact structure 210, an additional bonding pad 212, and an additional isolation material 214. The additional microelectronic device structure 200 can form a substrate that will be subsequently used with the additional microelectronic device structure 200 and the microelectronic device structure 100 ( Figure 1G) forms a control logic region 216 of the microelectronic device, as described in more detail below. Portions of the semiconductive substrate structure 202, the gate structure 204, the first wiring structure 206, and the first contact structure 208 of the additional microelectronic device structure 200 form respective control logic devices 218 of the control logic region 216, as also described in more detail below.

[0066] The semiconductive base structure 202 (e.g., a semiconductive wafer) of the additional microelectronic device structure 200 includes a base material or structure on which additional features (e.g., materials, structures, devices) of the additional microelectronic device structure 200 are formed. The semiconductive base structure 202 may include a base semiconductive material on a semiconductive structure (e.g., a semiconductive wafer) or a support structure. For example, the semiconductive base structure 202 may include a conventional silicon substrate (e.g., a conventional silicon wafer) or another bulk substrate including a semiconductive material. In some embodiments, the semiconductive base structure 202 includes a silicon wafer. In addition, the semiconductive base structure 202 may include one or more layers, structures, and / or regions formed therein and / or thereon. For example, the semiconductive base structure 202 may include conductive doped regions and undoped regions. The conductive doped regions may, for example, be used as source regions and drain regions of transistors of the control logic device 218 of the control logic region 216; and the undoped regions may, for example, be used as channel regions of transistors of the control logic device 218.

[0067] like Figure 2A , a gate structure 204 of a control logic region 216 of an additional microelectronic device structure 200 may vertically overlie (e.g., in the Z direction) a portion of a semiconductive base structure 202. The gate structures 204 may individually extend horizontally between and be employed by transistors of a control logic device 218 within the control logic region 216 of the additional microelectronic device structure 200. The gate structures 204 may be formed of and include a conductive material. A gate dielectric material (e.g., a dielectric oxide) may be vertically interposed (e.g., in the Z direction) between the gate structure 204 and a channel region (e.g., within the semiconductive base structure 202) of the transistor.

[0068] The first wiring structure 206 can vertically overlie (e.g., in the Z direction) the semiconductive base structure 202 and can be electrically connected to the semiconductive base structure 202 via the first contact structure 208. The first wiring structure 206 can be used as a substrate for subsequent use of additional microelectronic device structures 200 and microelectronic device structures 100 ( Figure 1G) is a local wiring structure of a microelectronic device formed by a semiconductor substrate 202. A first group 208A of first contact structures 208 may extend vertically between regions of the semiconductive substrate structure 202 (e.g., conductive doped regions, such as source regions and drain regions) and one or more of the first wiring structures 206 and couple the regions to the one or more. Additionally, a second group 208B of first contact structures 208 may extend vertically between some of the first wiring structures 206 and couple the first wiring structures to each other.

[0069] The first wiring structures 206 may each be individually formed of and include a conductive material. By way of non-limiting example, the first wiring structures 206 may be formed of and include one or more of the following: at least one metal, at least one alloy, and at least one conductive metal-containing material (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide). In some embodiments, the first wiring structures 206 are formed of and include Cu. In additional embodiments, the first wiring structures 206 are formed of and include W.

[0070] The first contact structures 208 (including the first group 208A and the second group 208B thereof) may each be individually formed of and include a conductive material. By way of non-limiting example, the first wiring structure 206 may be formed of and include one or more of the following: at least one metal, at least one alloy, and at least one conductive metal-containing material (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide). In some embodiments, the first contact structures 208 are formed of and include Cu. In additional embodiments, the first contact structures 208 are formed of and include W. In further embodiments, the first contact structures 208 of the first group 208A of the first contact structures 208 are formed of and include a first conductive material (e.g., W); and the first contact structures 208 of the second group 208B of the first contact structures 208 are formed of and include a second different conductive material (e.g., Cu).

[0071] As previously mentioned, portions of the semiconductive substrate structure 202 (e.g., conductively doped regions used as source and drain regions, undoped regions used as channel regions), the gate structure 204, the first wiring structure 206, and the first contact structure 208 form respective control logic devices 218 of the control logic region 216. In some embodiments, the control logic devices 218 include complementary metal oxide semiconductor (CMOS) circuitry. The control logic devices 218 may be configured to control the subsequent use of additional microelectronic device structures 200 and microelectronic device structures 100 ( Figure 1G) to form various operations of other components (e.g., memory cells) of a microelectronic device (e.g., a memory device). As a non-limiting example, the control logic device 218 may include one or more (e.g., each) of the following: a charge pump (e.g., V CCP Charge pump, V NEGWL Charge pump, DVC2 charge pump), delay-locked loop (DLL) circuit system (such as ring oscillator), V dd Regulators, drivers (e.g., string drivers), page buffers, decoders (e.g., local level decoders, column decoders, row decoders), sense amplifiers (e.g., equalization (EQ) amplifiers, isolation (ISO) amplifiers, NMOS sense amplifiers (NSA), PMOS sense amplifiers (PSA)), repair circuit systems (e.g., column repair circuit systems, row repair circuit systems), I / O devices (e.g., local I / O devices), memory test devices, array multiplexers (MUX), error checking and correction (ECC) devices, self-refresh / wear leveling devices, and other chip / level control circuit systems.

[0072] Continue to refer Figure 2A , the second contact structure 210 of the additional microelectronic device structure 200 may vertically overlie and couple to some of the first wiring structures 206 of the control logic region 216. In some embodiments, the second contact structure 210 includes a conductive filled via extending vertically through a portion of the additional isolation material 214 interposed between the additional bonding pads 212 and the first wiring structure 206. The second contact structure 210 may be formed of and include a conductive material. By way of non-limiting example, the second contact structure 210 may be formed of and include one or more of the following: at least one metal, at least one alloy, and at least one conductive metal-containing material (e.g., a conductive metal nitride, a conductive metal silicide, a conductive metal carbide, a conductive metal oxide). In some embodiments, each of the second contact structures 210 is formed of and includes Cu.

[0073] The additional bonding pads 212 of the additional microelectronic device structure 200 may vertically overlie and be coupled to the second contact structure 210. The second contact structure 210 may vertically extend from and between the additional bonding pads 212 and some of the first wiring structures 206. The additional bonding pads 212 may be configured and positioned to be attached to the microelectronic device structure ( Figure 1G ) of the bonding pad 144 ( Figure 1G) to form a connected bonding pad, as described in more detail below. Additional bonding pads 212 may be formed of and include a conductive material. By way of non-limiting example, additional bonding pads 212 may be formed of and include one or more of the following: at least one metal, at least one alloy, and at least one conductive metal-containing material (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide). In some embodiments, each of additional bonding pads 212 is formed of and includes Cu.

[0074] Still refer to Figure 2A , the additional isolation material 214 may cover and surround at least a portion of the first wiring structure 206, the second contact structure 210, and the additional bonding pad 212. The additional isolation material 214 may then be used in the microelectronic device structure 100 ( Figure 1G ) and additional microelectronic device structures 200 are attached to the microelectronic device structure 100 ( Figure 1G ) of the isolation material 146( Figure 1G ), as described in more detail below. The material composition of the additional isolation material 214 may be substantially the same as the isolation material 146 ( Figure 1G ) or the material composition of the additional isolation material 214 may be different from the isolation material 146 ( Figure 1G In some embodiments, the additional isolation material 214 is composed of at least one dielectric oxide material (e.g., SiO x (e.g., SiO 2 )) and includes the at least one dielectric oxide material. In additional embodiments, the additional isolation material 214 is formed of at least one low-k dielectric material (e.g., SiO 2 ) x C y 、SiO x N y 、SiC x O y H z and SiO x C z N y The additional isolation material 214 may be formed from and include the at least one low-k dielectric material. The additional isolation material 214 may be substantially homogenous, or the additional isolation material 214 may be heterogeneous. In some embodiments, the additional isolation material 214 is substantially homogenous. In additional embodiments, the additional isolation material 214 is heterogeneous. The additional isolation material 214 may be formed, for example, from and include a stack of at least two different dielectric materials.

[0075] Next reference Figure 2B, after forming the microelectronic device structure 100 and separately forming the additional microelectronic device structure 200, the microelectronic device structure 100 may be vertically inverted (e.g., flipped upside down in the Z direction) and attached (e.g., bonded) to the additional microelectronic device structure 200 to form a microelectronic device structure assembly 220. Alternatively, the additional microelectronic device structure 200 may be vertically inverted (e.g., flipped upside down in the Z direction) and attached to the microelectronic device structure 100 to form the microelectronic device structure assembly 220. The attachment of the microelectronic device structure 100 to the additional microelectronic device structure 200 may attach the bonding pads 144 of the microelectronic device structure 100 to the additional bonding pads 212 of the additional microelectronic device structure 200 to form connected bonding pads 222. In addition, the attachment of the microelectronic device structure 100 to the additional microelectronic device structure 200 may also attach the isolation material 146 of the microelectronic device structure 100 to the additional isolation material 214 of the additional microelectronic device structure 200. As Figure 2B As shown in FIG. 1 , the attachment of the microelectronic device structure 100 to the additional microelectronic device structure 200 can form a first interconnect region 224 of a microelectronic device (eg, a memory device, such as a 3D NAND flash memory device) that will subsequently be formed using the microelectronic device structure assembly 220. Figure 2B , the vertical boundary of the microelectronic device structure 100 relative to the additional microelectronic device structure 200 before the microelectronic device structure 100 is attached to the additional microelectronic device structure 200 to form the microelectronic device structure assembly 220 is depicted by dashed line AA. The microelectronic device structure 100 can be attached to the additional microelectronic device structure 200 without bonding wires.

[0076] like Figure 2B , the connected bonding pad 222 of the first interconnect region 224 can extend vertically from and vertically between the digit line contact structure 142 of the microelectronic device structure 100 and the second contact structure 210 of the additional microelectronic device structure 200. The additional bonding pad 212 of the connected bonding pad 222 can extend vertically from and vertically between the second contact structure 210 and the bonding pad 144 of the connected bonding pad 222; and the bonding pad 144 of the connected bonding pad 222 can extend vertically from and vertically between the digit line contact structure 142 and the additional bonding pad 212 of the connected bonding pad 222. When in Figure 2B, the additional bonding pad 212 and the bonding pad 144 of each connected bonding pad 222 are distinguished from each other by a dotted line, and the additional bonding pad 212 and the bonding pad 144 may be integral and continuous with each other. In other words, each connected bonding pad 222 may be a substantially unitary structure including the additional bonding pad 212 as its first area and the bonding pad 144 as its second area. For each connected bonding pad 222, its additional bonding pad 212 may be attached to its bonding pad 144 without a bonding wire.

[0077] Join reference Figure 2C , in the microelectronic device structure 100 ( Figure 2B ) after being attached to the additional microelectronic device structure 200, the base structure 102 ( Figure 2B ) and a portion of the doped semiconductive structure 105 (e.g., the second portion 105B). The material removal process may expose (e.g., reveal) the remaining portion of the doped semiconductive structure 105 (e.g., the first portion 105A). Figure 2C , the upper surface of the remaining portion (e.g., first portion 105A) of the doped semiconductive structure 105 may be substantially planar. The upper surface of the remaining portion (e.g., first portion 105A) of the doped semiconductive structure 105 may vertically overlie the upper surface of the unit pillar structure 116. In addition, optionally, an additional amount (e.g., additional volume) of doped semiconductive material (e.g., doped polysilicon) may be removed from the base structure 102 ( Figure 2B ) is formed on the remaining portion of the doped semiconductive structure 105 after forming the additional amount of doped semiconductive material. If formed, the additional amount of doped semiconductive material may have a material composition that is substantially the same as the material composition of the doped semiconductive structure 105, or may have a material composition that is different from the material composition of the doped semiconductive structure 105. Additionally, optionally, a strapping material 226 may optionally be formed on or over the doped semiconductive structure 105. The doped semiconductive structure 105 (and the additional amount of doped semiconductive material, if present) may optionally be annealed (e.g., thermally annealed) before and / or after forming the strapping material 226, if present. Annealing the remaining portion of the doped semiconductive structure 105 (and the additional amount of doped semiconductive material, if present) may, for example, promote or enhance activation of dopants within the remaining portion of the doped semiconductive structure 105 (and the additional amount of doped semiconductive material, if present).

[0078] If formed, the bonding material 226 may be formed of and include a conductive material. By way of non-limiting example, the bonding material 226, if present, may be formed of and include a metallic material including one or more of: at least one metal, at least one alloy, and at least one conductive metal-containing material (e.g., a conductive metal nitride, a conductive metal silicide, a conductive metal carbide, a conductive metal oxide). In some embodiments, the bonding material 226 is formed of tungsten silicide (WSi x ) and includes tungsten silicide (WSi x In an additional embodiment, the bonding material 226 is made of W and tungsten nitride (WN x ) (e.g., W and tungsten nitride (WN x ) is formed by and includes one or more of the above.

[0079] Next reference Figure 2D , before removing the base structure 102 ( Figure 2B ) thereafter, the remaining portion of the doped semiconductive structure 105 (eg, the first portion 105A ( Figure 2C )) (and the additional amount of doped semiconducting material (if present)) ( Figure 2C ) and lap materials 226( Figure 2C ) (if present) to be formed by doping the semiconducting structure 105 ( Figure 2C ) forms one or more source structures 228 and one or more contact pads 230 and is formed by the bonding material 226 ( Figure 2C ) (if any) to form an overlapping structure 232. Figure 2D 2, the formation of the source structure 228 and the contact pad 230 can form a memory array region 237 of a microelectronic device (e.g., a memory device) that will be subsequently formed using the microelectronic device structure assembly 220. The memory array region 237 can include: the stacked structure 126; the cell pillar structure 116; the deep contact structure 134; the digit line structure 139; the insulated line structure 140; a portion of the digit line contact structure 142 (e.g., the second portion 142B ( Figure 1G )); and a source level 235, which includes a source structure 228, a contact pad 230 and a strapping structure 232 (if present).

[0080] Within the source level 235 of the memory array region 237, the source structure 228 and the contact pad 230 can be horizontally adjacent to each other (e.g., in the X direction, in the Y direction). The source structure 228 can be electrically isolated from the contact pad 230 and can be positioned at substantially the same vertical position (e.g., in the Z direction) as the contact pad 230. The source structure 228 can be coupled to the vertically extending string of memory cells 138. The contact pad 230 can be coupled to additional conductive features within the stack structure 126, such as one or more of the deep contact structures 134.

[0081] The above article about Figures 1A to 1G and Figures 2A to 2C The described processing actions are performed after / subsequent to / following the formation of other features of the memory array region 237 and in the microelectronic device structure 100 ( Figure 2B ) is attached to the additional microelectronic device structure 200 to form the source structure 228, contact pads 230 and strapping structures 232 (if present).

[0082] Next reference Figure 2E , a third contact structure 234 may be formed over and electrically connected to the source structure 228 and the contact pad 230, and a second wiring structure 236 may be formed over and electrically connected to the third contact structure 234. The third contact structure 234 may be formed to extend between the second wiring structure 236 and the source structure 228 and the contact pad 230 of the source level 235. A lap structure 232 (if present) may be vertically interposed between the third contact structure 234 and the source structure 228 and the contact pad 230. The third contact structure 234 may be formed, for example, on an upper surface of the lap structure 232. In addition, as Figure 2E , at least one insulating material 238 may be formed to cover and surround the third contact structure 234 and the second wiring structure 236. At least one insulating material 238 may also be formed to cover and surround portions of the source structure 228 and the contact pad 230.

[0083] The third contact structure 234 and the second wiring structure 236 may each be formed of and include a conductive material. By way of non-limiting example, the third contact structure 234 and the second wiring structure 236 may each be individually formed of and include one or more of the following: at least one metal, at least one alloy, and at least one conductive metal-containing material (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide). In some embodiments, the third contact structure 234 and the second wiring structure 236 are each formed of and include Cu. In additional embodiments, the third contact structure 234 is formed of and includes W, and the second wiring structure 236 is formed of and includes Cu.

[0084] Still refer to Figure 2E In some embodiments, the insulating material 238 is composed of at least one dielectric oxide material (e.g., SiO x (e.g., SiO 2 )) and includes the at least one dielectric oxide material. In additional embodiments, the insulating material 238 is formed of at least one low-k dielectric material (e.g., SiO 2 ) x C y 、SiO x N y 、SiC x O y H z and SiO x C z N y Insulating material 238 may be formed from one or more of the above (e.g., one or more of the above) and include the at least one low-k dielectric material. Insulating material 238 may be substantially homogenous, or insulating material 238 may be heterogeneous. If insulating material 238 is heterogeneous, the amount of one or more elements included in insulating material 238 may change stepwise (e.g., abruptly) or continuously (e.g., gradually, such as linearly, parabolically) in all different parts of insulating material 238. In some embodiments, insulating material 238 is substantially homogenous. In additional embodiments, insulating material 238 is heterogeneous. Insulating material 238 is, for example, formed from and includes a stack of at least two different dielectric materials.

[0085] In additional embodiments, the above referenced Figure 2E One or more capacitors (e.g., one or more metal-insulator-metal (MIM) capacitors, one or more metal-insulator-semiconductor (MIS) capacitors) are formed during the described processing stages. By way of non-limiting example, Figure 2F and 2G is a description of the capacitor formed by the previous reference Figure 2D A simplified partial cross-sectional view of an embodiment of the present disclosure above source level 235 is depicted. Figure 2FAn embodiment of the present disclosure is shown in which one or more MIM capacitors are formed above the source level 235 . Figure 2G An embodiment of the present disclosure is shown in which one or more MIS capacitors are formed above the source level 235 .

[0086] refer to Figure 2F In some embodiments, one or more MIM capacitors 240 are formed above the source level 235. Individual MIM capacitors 240 may include a portion of an individual lap structure 232, an insulating structure 242 on or above the lap structure 232, and an individual third contact structure 234 on or above the insulating structure 242. A portion of the lap structure 232 may be used as a first metal structure for the MIM capacitor 240, the third contact structure 234 may be used as a second metal structure for the MIM capacitor 240, and the insulating structure 242 may be interposed between the lap structure 232 and the third contact structure 234. Figure 2F , for individual MIM capacitors 240, their insulating structures 242 may be positioned directly adjacent to the lower and side surfaces of the third contact structures 234. The insulating structures 242 may be interposed between the lower surface of the third contact structures 234 and the upper surface of the strapping structures 232 associated with the MIM capacitors 240, and may also be interposed between the side surfaces of the third contact structures 234 and the side surfaces of the insulating material 238 horizontally surrounding the third contact structures 234. In additional embodiments, a metallic structure (e.g., a metal structure, an alloy structure) is formed between the strapping structures 232 and the insulating structures 242, and is used as the first metal structure of the MIM capacitors 240.

[0087] The insulating structure 242 of the individual MIM capacitors 240 may be formed of and include an insulating material. For example, the insulating structure 242 may be formed of and include at least one dielectric oxide material such as one or more of the following: SiO x ; Phosphosilicate glass; Borosilicate glass; Borophosphosilicate glass; Fluorosilicate glass; AlO x ; and high-k oxides such as HfO x 、NbO x and TiO x In some embodiments, the insulating structure 242 is made of at least one high-k oxide (e.g., HfO x 、NbO x and TiO x In an additional embodiment, the insulating structure 242 is formed of SiO x (e.g. SiO2) and includes SiOx (e.g. SiO2).

[0088] The MIM capacitor 240 can be formed using conventional processes (e.g., conventional material deposition processes, conventional material removal processes, such as conventional etching processes) and conventional processing equipment that are not described in detail herein. One or more masks (e.g., one or more i-line masks) can be used to protect the insulating material (e.g., high-k oxide) of the insulating structure 242 during the patterning and etching processes used to form the MIM capacitor 240.

[0089] Next reference Figure 2G In an additional embodiment, one or more MIS capacitors 244 are formed above the source level 235. Individual MIS capacitors 244 may include a portion of an individual source structure 228, an insulating structure 246 on or above the source structure 228, and a metal structure 248 on or above the insulating structure 246. The metal structure 248 may be used as a metal structure of the MIS capacitor 244, a portion of the source structure 228 may be used as a semiconductive structure (e.g., a conductive-doped semiconductive structure) of the MIS capacitor 244, and the insulating structure 246 may be interposed between the source structure 228 and the metal structure 248. Figure 2G As shown in FIG. 2 , for individual MIS capacitors 244, their insulating structures 246 may be interposed between the lower surface of the metal structure 248 and the upper surface of the source structure 228 associated with the MIS capacitor 244. Figure 2G In the display, the overlap structure 232( Figure 2E ) may not be vertically positioned between and in contact with the source structure 228 and the insulating structure 246 of the MIS capacitor 244. In some such embodiments, the strapping structure 232 is omitted (e.g., lacks) from the upper surfaces of the source structure 228 and the contact pad 230 of the source level 235. In additional embodiments, the strapping structure 232 is formed over portions of the upper surfaces of the source structure 228 and the contact pad 230 outside the horizontal boundaries of the MIS capacitor 244, but omitted from other portions of the upper surface of the source structure 228 within the horizontal boundaries of the MIS capacitor 244.

[0090] The insulating structure 246 of the individual MIS capacitors 244 may be formed of and include an insulating material. For example, the insulating structure 246 may be formed of and include at least one dielectric oxide material such as one or more of the following: SiO x ; Phosphosilicate glass; Borosilicate glass; Borophosphosilicate glass; Fluorosilicate glass; AlO x ; and high-k oxides such as HfO x 、NbO x and TiOx In some embodiments, the insulating structure 246 is made of at least one high-k oxide (e.g., HfO x 、NbO x and TiO x In an additional embodiment, the insulating structure 246 is formed of SiO x (e.g. SiO2) and includes SiO x (e.g. SiO2).

[0091] Still refer to Figure 2G The metal structure 248 of each MIS capacitor 244 may be formed of and include a metal material including one or more of the following: at least one metal, at least one alloy, and at least one conductive metal-containing material (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide). In some embodiments, the metal structure 248 of one or more MIS capacitors 244 is formed of and includes W.

[0092] The MIS capacitor 244 can be formed using conventional processes (e.g., conventional material deposition processes, conventional material removal processes, such as conventional etching processes) and conventional processing equipment that are not described in detail herein. One or more masks (e.g., one or more i-line masks) can be used to protect the insulating material (e.g., high-k oxide) of the insulating structure 246 during the patterning and etching processes used to form the MIS capacitor 244.

[0093] Return to reference Figure 2E After forming the second wiring structure 236, the microelectronic device structure assembly 220 can undergo additional processing to couple additional features to the second wiring structure 236. For example, referring to Figure 2H , the fourth contact structure 250 may be formed on the second wiring structure 236 and electrically connected to the second wiring structure 236, and the conductive pad 252 may be formed on the fourth contact structure 250 and electrically connected to the fourth contact structure 250. The fourth contact structure 250 may be formed to extend between the second wiring structure 236 and the conductive pad 252. The fourth contact structure 250 may, for example, be formed on the upper surface of the second wiring structure 236, and the conductive pad 252 may be formed on the upper surface of the fourth contact structure 250. In addition, as Figure 2H As shown in FIG. 2 , at least one additional insulating material 254 may be formed to cover and surround the fourth contact structure 250 and the conductive pad 252 . At least one additional insulating material 254 may also be formed to cover and surround portions of the second wiring structure 236 and the insulating material 238 .

[0094] The fourth contact structure 250 and the conductive pad 252 may each be formed of and include a conductive material. By way of non-limiting example, the fourth contact structure 250 and the conductive pad 252 may each be individually formed of and include one or more of the following: at least one metal, at least one alloy, and at least one conductive metal-containing material (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide). In some embodiments, the fourth contact structure 250 is formed of and includes W, and the conductive pad 252 is formed of and includes Al.

[0095] Still refer to Figure 2H , the material composition of the additional insulating material 254 may be substantially the same as the material composition of the insulating material 238, or the material composition of the additional insulating material 254 may be different from the material composition of the insulating material 238. In some embodiments, the additional insulating material 254 is composed of at least one dielectric oxide material (e.g., SiO x (e.g., SiO 2 )) and includes the at least one dielectric oxide material. In additional embodiments, the additional insulating material 254 is formed of at least one low-k dielectric material (e.g., SiO 2 ) x C y 、SiO x N y 、SiC x O y H z and SiO x C z N y The additional insulating material 254 may be formed of one or more of the following (i.e., one or more of the following) and include the at least one low-k dielectric material. The additional insulating material 254 may be substantially homogenous, or the additional insulating material 254 may be heterogeneous. If the additional insulating material 254 is heterogeneous, the amount of one or more elements included in the additional insulating material 254 may be changed stepwise (e.g., abruptly) or continuously (e.g., gradually, such as linearly, parabolically) in all different parts of the additional insulating material 254. In some embodiments, the additional insulating material 254 is substantially homogenous. In additional embodiments, the additional insulating material 254 is heterogeneous. The additional insulating material 254 is, for example, formed of and includes a stack of at least two different dielectric materials.

[0096] like Figure 2H, the formation of the fourth contact structure 250, the conductive pad 252, and the additional insulating material 254 can form a second interconnect region 256. The second interconnect region 256 can include the third contact structure 234, the second wiring structure 236, the insulating material 238, the fourth contact structure 250, the conductive pad 252, and the additional insulating material 254. In addition, the formation of the second interconnect region 256 can enable the formation of a microelectronic device 258 (e.g., a memory device, such as a 3D NAND flash memory device). The microelectronic device 258 can include the control logic region 216, the first interconnect region 224, the memory array region 237, and the second interconnect region 256. At least the second wiring structure 236 and the conductive pad 252 of the second interconnect region 256 can be used as a global wiring structure of the microelectronic device 258. The second wiring structure 236 and the conductive pad 252 can, for example, be configured to receive a global signal from an external bus and relay the global signal to other components (e.g., structures, devices) of the microelectronic device 258.

[0097] Therefore, according to an embodiment of the present disclosure, a method for forming a microelectronic device includes forming a microelectronic device structure. The microelectronic device structure includes: a base structure; a doped semiconductive structure including a first portion overlying the base structure and a second portion extending vertically from the first portion into the base structure; a stacked structure overlying the doped semiconductive structure and including a vertical alternating sequence of conductive structures and insulating structures; a cell pillar structure extending vertically through the stacked structure to the first portion of the doped semiconductive structure; and a digit line structure vertically overlying the stacked structure. An additional microelectronic device structure including a control logic device is formed. The microelectronic device structure is attached to the additional microelectronic device structure to form a microelectronic device structure assembly. The digit line structure is vertically interposed between the stacked structure and the control logic device within the microelectronic device structure assembly. The base structure and the second portion of the doped semiconductive structure are removed to expose the first portion of the doped semiconductive structure. The first portion of the doped semiconductive structure is patterned after removing the base structure and the second portion of the doped semiconductive structure to form at least one source structure coupled to the cell pillar structure on the stacked structure.

[0098] In addition, according to an embodiment of the present disclosure, a microelectronic device includes a memory array region, a control logic region, a first interconnect region, and a second interconnect region. The memory array region includes: a stacked structure including a vertically alternating sequence of conductive structures and insulating structures; a source structure vertically overlying the stacked structure and including a doped semiconductive material; a cell pillar structure vertically extending completely through the stacked structure to the source structure; a source contact structure vertically extending completely through the stacked structure to the source structure; and a digit line structure vertically underlying the stacked structure and electrically connected to the cell pillar structure. The control logic region vertically underlies the memory array region and includes a control logic device. The first interconnect region is vertically interposed between the memory array region and the control logic region and includes an additional conductive structure that couples the digit line structure of the memory array region to the control logic device of the control logic region. The second interconnect region vertically overlies the memory array region and includes another conductive structure electrically connected to the source structure.

[0099] According to an embodiment of the present disclosure, a microelectronic device (eg, microelectronic device 258 ( Figure 2H )) can be used in the embodiments of the electronic system of the present disclosure. For example, Figure 3 is a block diagram of an illustrative electronic system 300 according to an embodiment of the present disclosure. The electronic system 300 may include, for example, a computer or computer hardware component, a server or other networking hardware component, a cellular phone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, a Wi-Fi or cellular enabled tablet computer (e.g., or Tablet computers), electronic books, navigation devices, etc. The electronic system 300 includes at least one memory device 302. The memory device 302 may include, for example, a microelectronic device (e.g., microelectronic device 258 ( Figure 2H )). The electronic system 300 may further include at least one electronic signal processor device 304 (commonly referred to as a "microprocessor"). The electronic signal processor device 304 may optionally include a microelectronic device previously described herein (e.g., microelectronic device 258 ( Figure 2H )). Although Figure 3 300 as two (2) separate devices, but in additional embodiments, a single (e.g., only one) memory / processor device having the functionality of memory device 302 and electronic signal processor device 304 is included in electronic system 300. In such embodiments, the memory / processor device may include a microelectronic device (e.g., microelectronic device 258 ( Figure 2H)). The electronic system 300 may further include one or more input devices 306 for inputting information into the electronic system 300 by a user, such as, for example, a mouse or other pointing device, a keyboard, a touch pad, buttons, or a control panel. The electronic system 300 may further include one or more output devices 308 for outputting information (e.g., visual or audio output) to the user, such as, for example, a monitor, a display, a printer, an audio output jack, a speaker, etc. In some embodiments, the input device 306 and the output device 308 may include a single touch screen device that can be used to input information into the electronic system 300 while outputting visual information to the user. The input device 306 and the output device 308 may be in electrical communication with one or more of the memory device 302 and the electronic signal processor device 304.

[0100] Therefore, according to an embodiment of the present disclosure, an electronic system includes: an input device; an output device; a processor device, which is operably coupled to the input device and the output device; and a memory device, which is operably coupled to the processor device. The memory device includes a stacked structure, a source structure, a digit line structure, a cell pillar structure, a deep contact structure, a conductive wiring structure, a control logic device, and an additional conductive wiring structure. The stacked structure includes a level that each includes a conductive structure and an insulating structure vertically adjacent to the conductive structure. The source structure overlies the stacked structure. The digit line structure is underlying the stacked structure. The cell pillar structure is coupled to the digit line structure and vertically extends completely through the stacked structure to the source structure. The deep contact structure vertically extends completely through the stacked structure into the source structure. The conductive wiring structure is vertically underlying and coupled to the digit line structure. The control logic device is coupled to and at least partially vertically underlying the conductive wiring structure. The additional conductive wiring structure is coupled to and vertically overlies the source structure.

[0101] Compared with conventional structures, conventional devices and conventional methods, the structures, devices and methods of the present disclosure advantageously promote one or more of improved performance of microelectronic devices, reduced costs (e.g., manufacturing costs, material costs), increased component miniaturization and improved packaging density. Compared with conventional structures, conventional devices and conventional methods, the structures, devices and methods of the present disclosure may also improve scalability, efficiency and simplicity.

[0102] Non-limiting example embodiments may include:

[0103] Embodiment 1: A method for forming a microelectronic device, comprising: forming a microelectronic device structure, the microelectronic device structure comprising: a base structure; a doped semiconductive structure comprising a first portion overlying the base structure and a second portion extending vertically from the first portion into the base structure; a stacked structure overlying the doped semiconductive structure and comprising a vertically alternating sequence of conductive structures and insulating structures; a cell pillar structure extending vertically through the stacked structure to the first portion of the doped semiconductive structure; and a digit line structure vertically overlying the stacked structure; forming an additional microelectronic device structure including a control logic device; attaching the microelectronic device structure to the additional microelectronic device structure to form a microelectronic device structure assembly, the digit line structure being vertically inserted between the stacked structure and the control logic device within the microelectronic device structure assembly; removing the base structure and the second portion of the doped semiconductive structure to expose the first portion of the doped semiconductive structure; and patterning the first portion of the doped semiconductive structure after removing the base structure and the second portion of the doped semiconductive structure to form at least one source structure coupled to the cell pillar structure on the stacked structure.

[0104] Embodiment 2: The method of Embodiment 1, wherein forming a microelectronic device structure comprises forming the microelectronic device structure further comprising a conductive contact structure extending vertically through the stacked structure into the doped semiconductive structure.

[0105] Embodiment 3: A method according to any one of embodiments 1 and 2, wherein forming a microelectronic device structure includes: forming a preliminary stacking structure on a doped semiconductive material overlying the base structure, the preliminary stacking structure including a vertically alternating sequence of a first insulating structure and a second insulating structure; forming an opening extending vertically through the preliminary stacking structure and the doped semiconductive material into the base structure; filling a lower portion of the opening positioned within the base structure and the doped semiconductive material with an additional semiconductive material; annealing the doped semiconductive material and the additional semiconductive material to form the doped semiconductive structure therefrom; forming the cell pillar structure within the remaining upper portion of the opening; forming a narrow groove extending through the preliminary stacking structure; using the narrow groove to at least partially replace the second insulating structure with the conductive structure to form the stacking structure, the insulating structure of the stacking structure including the remaining portion of the first insulating structure; and forming the digital line structure electrically connected to the cell pillar structure over the cell pillar structure.

[0106] Embodiment 4: A method according to any one of embodiments 1 to 3, wherein forming a microelectronic device structure includes forming the microelectronic device structure further including: an insulating line structure, which is on the digit line structure; a digit line contact structure, which extends through a portion of the insulating line structure and contacts the digit line structure; and a conductive pad structure, which is on the digit line contact structure.

[0107] Embodiment 5: The method of Embodiment 4, wherein forming an additional microelectronic device structure comprises forming the microelectronic device structure further comprising an additional conductive pad structure over the control logic device.

[0108] Embodiment 6: A method according to embodiment 5, wherein attaching the microelectronic device structure to the additional microelectronic device structure comprises: vertically inverting the microelectronic device structure and one of the additional microelectronic device structures; and joining the conductive pad structure of the microelectronic device structure to the additional conductive pad structure of the additional microelectronic device structure.

[0109] Embodiment 7: A method according to any one of embodiments 1 to 6, wherein removing the base structure and the second portion of the doped semiconductive structure to expose the first portion of the doped semiconductive structure includes forming an upper surface of the first portion of the doped semiconductive structure that is substantially planar and vertically offset from the unit pillar structure.

[0110] Embodiment 8: The method of any one of embodiments 1 to 7, further comprising forming at least one metallic strapping material over the first portion of the doped semiconducting structure before patterning the first portion of the doped semiconducting structure.

[0111] Embodiment 9: The method according to any one of embodiments 1 to 8 further comprises: forming a conductive wiring structure electrically connected to the at least one source structure on the at least one source structure; and forming a conductive pad structure electrically connected to the conductive wiring structure on the conductive wiring structure.

[0112] Embodiment 10: The method of Embodiment 9, further comprising vertically forming at least one metal-insulator-metal (MIM) capacitor above the at least one source structure and below the conductive wiring structure.

[0113] Embodiment 11: The method of Embodiment 9, further comprising vertically forming at least one metal-insulator-semiconductor (MIS) capacitor below the conductive wiring structure and at least partially above the at least one source structure.

[0114] Embodiment 12: A microelectronic device, comprising: a memory array region, comprising: a stacked structure comprising a vertically alternating sequence of conductive structures and insulating structures; a source structure vertically overlying the stacked structure and comprising a doped semiconductive material; a cell pillar structure vertically extending completely through the stacked structure to the source structure; a source contact structure vertically extending completely through the stacked structure into the source structure; and a digit line structure vertically underlying the stacked structure and electrically connected to the cell pillar structure; a control logic region vertically underlying the memory array region and comprising a control logic device; a first interconnect region vertically interposed between the memory array region and the control logic region and comprising an additional conductive structure coupling the digit line structure of the memory array region to the control logic device of the control logic region; and a second interconnect region vertically overlying the memory array region and comprising another conductive structure electrically connected to the source structure.

[0115] Embodiment 13: A microelectronic device according to embodiment 12, further comprising: a contact pad horizontally adjacent to the source structure and substantially vertically aligned with the source structure, the contact pad comprising the doped semiconductive material; and an additional contact structure coupled to the contact pad and extending vertically completely through the stacked structure.

[0116] Embodiment 14: The microelectronic device according to any one of Embodiments 12 and 13, further comprising a metal strapping structure vertically interposed between the source structure and the further conductive structure and electrically communicating with the source structure and the further conductive structure.

[0117] Embodiment 15: The microelectronic device of any one of Embodiments 12 to 14, wherein an upper boundary of the unit pillar structure is vertically underlying an upper boundary of the source structure.

[0118] Embodiment 16: The microelectronic device of any one of Embodiments 12 to 14, wherein an upper boundary of the unit pillar structure is vertically below an upper boundary of the source contact structure.

[0119] Embodiment 17: A microelectronic device according to any one of embodiments 12 to 16, wherein the additional conductive structure includes: a conductive wiring structure, which is above the source structure; a conductive contact, which extends between the conductive wiring structure and the source structure and couples the conductive wiring structure and the source structure; a conductive pad structure, which is above the conductive wiring structure; and an additional conductive contact, which extends between the conductive wiring structure and the conductive pad structure and couples the conductive wiring structure and the conductive pad structure.

[0120] Embodiment 18: The microelectronic device of any one of Embodiments 12 to 17, further comprising a metal-insulator-metal (MIM) capacitor positioned at least partially vertically between the source structure and the further conductive structure.

[0121] Embodiment 19: The microelectronic device of any one of Embodiments 12 to 18, further comprising a metal-insulator-semiconductor (MIS) capacitor positioned at least partially vertically between the source structure and the further conductive structure.

[0122] Embodiment 20: An electronic system comprising: an input device; an output device; a processor device operably coupled to the input device and the output device; and a memory device operably coupled to the processor device and comprising: a stacked structure comprising levels each comprising a conductive structure and an insulating structure vertically adjacent to the conductive structure; a source structure overlying the stacked structure; a digit line structure underlying the stacked structure; a cell pillar structure coupled to the digit line structure and extending vertically completely through the stacked structure to the source structure; a deep contact structure extending vertically completely through the stacked structure into the source structure; a conductive wiring structure vertically underlying and coupled to the digit line structure; a control logic device coupled to and at least partially vertically underlying the conductive wiring structure; and an additional conductive wiring structure coupled to and vertically overlying the source structure.

[0123] Although the present disclosure is subject to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and described in detail herein. However, the present disclosure is not limited to the specific forms disclosed. Specifically, the present disclosure encompasses all modifications, equivalents, and alternatives falling within the scope of the attached claims and their legal equivalents. For example, the elements and features disclosed in relation to one embodiment may be combined with the elements and features disclosed in relation to other embodiments of the present disclosure.

Claims

1. A memory device, comprising: A control circuit system structure, which includes a control logic circuit system; and a memory array structure vertically overlying and bonded to the control circuit system structure, the memory array structure comprising: layers, which are stacked vertically relative to each other and respectively include a conductive material and an insulating material vertically adjacent to the conductive material; pillar structures each comprising a semiconductor material extending vertically through the layer; and A source structure vertically overlies the layer and includes an annealed doped semiconductor material, the source structure being in physical contact with the semiconductor material of the pillar structure.

2. The memory device of claim 1, wherein the annealed doped semiconductor material of the source structure comprises a laser annealed doped semiconductor material.

3. The memory device of claim 1, wherein the annealed doped semiconductor material of the source structure comprises annealed doped polysilicon.

4. The memory device of claim 1, wherein the annealed doped semiconductor material of the source structure is on the semiconductor material of the pillar structure.

5. The memory device of claim 1, wherein the source structure of the memory array structure is heterogeneous.

6. The memory device of claim 1, wherein the source structures of the memory array structure are substantially homogeneous.

7. The memory device of claim 1, further comprising: a dielectric oxide material vertically covering the source structure; a conductive wiring vertically covering the dielectric oxide material; and A conductive contact extends vertically from the conductive wiring through the dielectric oxide material and to the source structure.

8. The memory device of claim 7, wherein at least some of the conductive contacts comprise tungsten contacts.

9. A method of forming a memory device, comprising: A memory array structure is formed, comprising: layers, which are stacked vertically relative to each other and respectively include a conductive material and an insulating material vertically adjacent to the conductive material; a semiconductor material vertically offset from the layer; and pillar structures extending vertically through the layer to the semiconductor material, the pillar structures each comprising additional semiconductor material; forming a control circuitry structure including control logic circuitry; bonding the memory array structure to the control circuitry structure to form an assembly including the layer vertically interposed between the semiconductor material and the control logic circuitry; partially removing the semiconductor material after bonding the memory array structure to the control circuitry structure to form the assembly; forming an annealed doped semiconductor material on the remaining portion of the semiconductor material; and The annealed doped semiconductor material is patterned to form a source structure in contact with the additional semiconductor material of the pillar structure.

10. The method of claim 9, further comprising forming the semiconductor material of the memory array structure to include single crystal silicon.

11. The method of claim 10, wherein forming an annealed doped semiconductor material on the remaining portion of the semiconductor material comprises forming annealed doped polysilicon on the remaining portion of the single crystal silicon.

12. The method of claim 9, wherein forming the annealed doped semiconductor material on the remaining portion of the semiconductor material comprises: forming n-type polysilicon on the remaining portion of the semiconductor material, the n-type polysilicon comprising polysilicon doped with phosphorus; and The n-type polysilicon is annealed.

13. The method of claim 9, further comprising forming the pillar structures of the memory array structure to respectively further comprise: a dielectric oxide material horizontally outwardly surrounding the additional semiconductor material; a dielectric nitride material horizontally outwardly surrounding the dielectric oxide material; and Additional dielectric oxide material horizontally outwardly surrounds the dielectric nitride.

14. The method of claim 9, further comprising forming the memory array structure to further include a dielectrically lined conductive contact structure extending vertically through the layer to the semiconductor material. 15 . The method of claim 9 , wherein patterning the annealed doped semiconductor material further comprises forming a contact pad comprising a portion of the annealed doped semiconductor material, the contact pad vertically overlapping and electrically isolated from the source structure. 16 . The method of claim 9 , further comprising forming a conductive wiring structure over and in contact with the source structure.

17. A 3D NAND flash memory device comprising: A control circuit system structure, which includes a control logic device; a memory array structure overlying and bonded to the control circuitry structure, the memory array structure comprising: A stacked structure comprising a conductive material and an insulating material vertically alternating with the conductive material; a digital line below the stacked structure; a source structure over the stacked structure and comprising a laser annealed doped semiconductor material; and The cell pillar structures respectively include semiconductor materials vertically extending between the digit line and the source structure, and the upper ends of the semiconductor materials are in physical contact with the laser annealed and doped semiconductor material of the source structure.

18. The 3D NAND flash memory device of claim 17, wherein the laser annealed doped semiconductor material comprises laser annealed doped polysilicon.

19. The 3D NAND flash memory device of claim 17, wherein the memory array structure is bonded to the control circuitry structure by a combination of dielectric-dielectric bonding pads and metal-metal bonding pads.

20. The 3D NAND flash memory device of claim 17, further comprising wiring structures over the source structures of the memory array structure, some of the wiring structures coupled to some of the control logic devices of the control circuitry structure.

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