Non-volatile memory device

Abstract

A non-volatile memory device includes a substrate and a memory cell. The memory cell includes a select transistor, a floating gate transistor, and a metal conductor. The select transistor includes a select gate structure over the substrate, a first source / drain region on a first side of the select gate structure, and a second source / drain region on a second side of the select gate structure opposite the first side. The floating gate transistor includes a floating gate structure over the substrate, a second source / drain region on a third side of the floating gate structure, and a third source / drain region on a fourth side of the floating gate structure opposite the third side. The metal conductor is over and electrically isolated from the floating gate structure. The floating gate transistor also includes a first low voltage lightly doped drain between the floating gate structure and the third source / drain region.

Description

Technical Field

[0001] The present invention relates to a non-volatile memory device, and in particular to a non-volatile memory device with small area and low power consumption. Background Art

[0002] A variety of non-volatile memory devices have been developed. One type of non-volatile memory device is electrically erasable programmable read-only memory (EEPROM). EEPROM can be used in digital cameras, video game consoles, personal digital assistants, telephone recording devices, and programmable IC products. The method of programming / erasing EEPROM is to drive electrons into / out of the floating gate in the EEPROM.

[0003] However, while prior art non-volatile memory devices have generally been adequate for their intended purposes, they are not satisfactory in every aspect. Summary of the invention

[0004] The present invention provides a non-volatile memory device, including a substrate and a memory cell. The memory cell includes a selection transistor, a floating gate transistor and a metal conductor. The selection transistor includes a selection gate structure above the substrate, a first source / drain region on a first side of the selection gate structure, and a second source / drain region on a second side of the selection gate structure opposite to the first side. The floating gate transistor includes a floating gate structure above the substrate, a second source / drain region on a third side of the floating gate structure, and a third source / drain region on a fourth side of the floating gate structure opposite to the third side. The metal conductor is above the floating gate structure and is electrically isolated from the floating gate structure. The floating gate transistor also includes a first low voltage lightly doped drain between the floating gate structure and the third source / drain region. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] In order to make the description of the present invention include the above examples, other advantages and features, the principles briefly described above will be described in more detail through specific examples in the accompanying drawings. It should be understood that the drawings shown here are only examples of the present invention and cannot limit the scope of the present invention. The principles of the present invention will be described and explained more clearly and in detail with the accompanying drawings.

[0006] Figure 1A A top view (or layout) of a non-volatile memory device is shown for some embodiments of the present invention;

[0007] Figure 1B Some embodiments of the present invention are shown along Figure 1AA YZ cross-sectional view of the non-volatile memory device along line segment AA';

[0008] Figure 2 Some alternative embodiments of the present invention are shown along Figure 1A A YZ cross-sectional view of the non-volatile memory device along line segment AA';

[0009] Figure 3 Some alternative embodiments of the present invention are shown along Figure 1A A YZ cross-sectional view of the non-volatile memory device along line segment AA';

[0010] Figure 4 Some alternative embodiments of the present invention are shown along Figure 1A YZ cross-sectional view of the non-volatile memory device along line segment AA'.

[0011] Explanation of symbols

[0012] 100: memory device

[0013] 101,101': memory unit

[0014] 102:Substrate

[0015] 102w: p-type well

[0016] 104: Isolation Structure

[0017] 106,106': Active area

[0018] 108-1: Gate dielectric layer

[0019] 108-2: Gate dielectric layer

[0020] 110-1: Gate electrode layer

[0021] 110-2: Gate electrode layer

[0022] 112: Gate spacer

[0023] 114-1: Source / drain region

[0024] 114-2: Source / drain region

[0025] 114-3: Source / drain region

[0026] 116-1: Low voltage lightly doped drain

[0027] 118-1: Medium Voltage Lightly Doped Drain

[0028] 118-2: Medium Voltage Lightly Doped Drain

[0029] 118-3: Medium Voltage Lightly Doped Drain

[0030] 120: Dielectric layer

[0031] 122: Silicide Characteristics

[0032] 124: Interlayer dielectric layer

[0033] 126-1,126-1':Through hole

[0034] 126-2,126-2':Through hole

[0035] 126-3,126-3':Through hole

[0036] 128-1: Metal conductor

[0037] 128-2: Metal conductor

[0038] 128-3: Metal conductor

[0039] 128-4,128-4':Metallic conductor

[0040] A-A': Line segment

[0041] ST: Select transistor

[0042] FT: Floating Gate Transistor

[0043] 200: memory device

[0044] 116-2: Low voltage lightly doped drain

[0045] 300: memory device

[0046] 116-3: Low voltage lightly doped drain

[0047] 400: Memory device

[0048] 116-4: Low voltage lightly doped drain DETAILED DESCRIPTION

[0049] The following disclosure provides many different embodiments or examples to implement the different features of the present invention. The following disclosure describes specific examples of various components and their arrangements to simplify the description. Of course, these specific examples are not intended to be limiting. For example, if the present invention describes a first feature formed on or above a second feature, it means that it may include an embodiment in which the first feature and the second feature are in direct contact, and may also include an embodiment in which an additional feature is formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. In addition, the same reference symbols and / or marks may be reused in different examples of the following disclosure. These repetitions are for the purpose of simplification and clarity, and are not intended to limit the specific relationship between the different embodiments and / or structures discussed.

[0050] For the purpose of the detailed description of the present invention, unless specifically denied, singular words include plural words and vice versa. And the word "include" means "include without limitation". In addition, approximation terms such as "about", "almost", "quite", "roughly", etc. can be used in the embodiments of the present invention, and their meanings are such as "at, close to or close to" or "within 3 to 5%" or "within an acceptable manufacturing tolerance" or any logical combination.

[0051] In addition, it is related to spatial terms. For example, "below", "lower", "above", "higher", and similar terms are used to facilitate the description of the relationship between one element or feature and another element or feature in the diagram. In addition to the orientation shown in the accompanying drawings, these spatially related terms are intended to include different orientations of the device in use or operation. For example, if the device in the schematic diagram is reversed, the elements described as "below" or "below" other elements or features will also become "above" other elements or features. In this way, the exemplary term "below" will cover both upward and downward interpretations. In addition, the device may be turned to different orientations (rotated 90 degrees or other orientations), and the spatially related terms used here may also be interpreted in the same way.

[0052] The terms used herein are for the purpose of describing specific embodiments only and do not limit the present invention. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. In addition, to the extent that the terms "encompass", "comprise", "include", "have", "have", "include" or variations thereof are used in the detailed description and / or claims, these terms are intended to be inclusive in a manner similar to "comprises".

[0053] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. In addition, terms such as those defined in common dictionaries should be interpreted as having the same meaning as in the context of the relevant art, and will not be understood as idealized or overly formal unless explicitly defined as such herein.

[0054] Now will refer to the accompanying drawings to describe the various aspects of the present invention in more detail. In order to avoid doubt, the X direction, Y direction and Z direction in the accompanying drawings are perpendicular to each other and used consistently. Throughout the present invention, unless otherwise specified, similar reference numerals represent similar features.

[0055] Figure 1A A top view (or layout) of a non-volatile memory device 100 is shown according to some embodiments of the present invention. Figure 1B According to some embodiments of the present invention, it is shown that Figure 1A The YZ cross-sectional view of the non-volatile memory device 100 along the line segment AA'. Figure 1A As shown, the non-volatile memory 100 includes two memory cells 101 and 101' arranged in the X direction. The memory cells 101 and 101' have the same functions and operations. The memory cells 101 and 101' also have the same features and components. For the sake of distinction and simplicity, the features / components in the memory cell 101' that are similar or identical to the features / components in the memory cell 101 are additionally marked with "'" and the detailed description is not repeated. Although Figure 1A The illustrated non-volatile memory device 100 includes two memory cells 101 and 101 ′, but it should be noted that the non-volatile memory device 100 may include memory cells similar to the memory cells 101 and 101 ′ arranged in a memory array in multiple columns and rows in accordance with some embodiments.

[0056] The non-volatile memory device 100 includes a substrate 102 on which or in which various features, such as gate structures and source / drain regions, are formed. Figure 1BAs shown. The substrate 102 may include a semiconductor material, such as bulk silicon (Si). Alternatively, the substrate 102 may be a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The semiconductor-on-insulator substrate may be manufactured using separation by implantation of oxygen (SIMOX), wafer bonding, and / or other suitable methods.

[0057] In some embodiments, a p-type well 102w is formed in or on the substrate 102, such as Figure 1B As shown. In the present embodiment, the p-type well 102w is a p-type doped region configured for an n-type transistor. The p-type well 102w is doped with a p-type dopant, such as boron, indium, other p-type dopant, or a combination thereof. An ion implantation process, a diffusion process, and / or other suitable doping process may be performed to form the p-type well 102w. In other embodiments, a deep n-type well doped with an n-type dopant (e.g., phosphorus, arsenic, other n-type dopant, or a combination thereof) is formed in the substrate 102, and the p-type well 102w is formed in the deep n-type well. Therefore, the various features of the memory cells 101 and 101' discussed below will be formed in / on the p-type well 102w.

[0058] The non-volatile memory 100 further includes an isolation structure 104 on / in the substrate 102 (p-type well 102w), such as Figure 1BAs shown. The isolation structure 104 can define active regions 106 and 106' for the memory cells 101 and 101', respectively, in which various features of the memory cells 101 and 101' will be formed therein / on them. More specifically, the area of ​​the substrate 102 (p-type well 102w) surrounded by the isolation structure 104 becomes the active region 106 and 106'. The isolation structure 104 can include silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation materials (for example, including silicon, oxygen, nitrogen, carbon or other suitable isolation components), or a combination thereof. The isolation structure 104 can include different structures, such as a shallow trench isolation (STI) structure, a deep trench isolation (DTI) structure and / or a local oxidation of silicon (LOCOS) structure. In some embodiments, the STI feature includes a multi-layer structure filling the trench, such as a layer including silicon nitride disposed above a liner layer including thermal oxide. In yet another example, the STI feature includes a bulk dielectric layer disposed over a liner dielectric layer, wherein the bulk dielectric layer and the liner dielectric layer include materials depending on design requirements.

[0059] The memory cell 101 further includes gate dielectric layers 108-1 and 108-2 (collectively referred to as gate dielectric layers 108) over the substrate 102, the p-type well 102w, and / or the active region 106. The memory cell 101 further includes gate electrode layers 110-1 and 110-2 (collectively referred to as gate electrode layers 110) over the gate dielectric layers 108-1 and 108-2, respectively. Figure 1A and Figure 1B As shown. Figure 1A As shown, the gate electrode layers 110-1 and 110-2 extend in the X direction to cross the active region 106. In addition, the gate electrode layer 110-1 is shared by the memory cells 101 and 101'. Figure 1A In some embodiments, the gate electrode layers 110 - 1 and 110 - 2 are arranged in the Y direction. According to some embodiments, the gate electrode layer 110 and the gate dielectric layer 108 may be referred to as a gate structure.

[0060] In the present invention, the gate dielectric layer 108-1 and the gate electrode layer 110-1 are used for the selection transistor ST. Therefore, the gate electrode layer 110-1 can be referred to as a selection gate electrode layer, and can be referred to as a selection gate or a selection gate structure together with the gate dielectric layer 108-1. In addition, the gate dielectric layer 108-2 and the gate electrode layer 110-2 are used for the floating gate transistor FT. Therefore, the gate electrode layer 110-2 can be referred to as a floating gate electrode layer, and can be referred to as a floating gate or a floating gate structure together with the gate dielectric layer 108-2.

[0061] The gate dielectric layer 108 may be silicon oxide, silicon nitride, multilayers thereof, etc., and may be deposited or thermally grown according to acceptable techniques. The gate dielectric layer may be formed by molecular-beam deposition (MBD), atomic layer deposition (ALD), plasma-enhanced chemical vapor deposition (PECVD), chemical vapor deposition (CVD), or thermal oxidation, etc. The gate electrode layer 110 may be formed of single crystal silicon or polycrystalline silicon, but may be formed using other materials. In some embodiments, the material of the gate electrode layer may include a metal-containing material, such as titanium nitride (TiN), tantalum nitride (TaN), tantalum carbide (TaC), cobalt (Co), ruthenium (Ru), aluminum (Al), combinations thereof, or multilayers thereof.

[0062] In some embodiments, the memory cell 101 further includes a gate spacer 112 on the sidewalls of the gate dielectric layer 108 and the gate electrode layer 110 (ie, the gate structure) and above the substrate 102 (the p-type well 102w). Figure 1B As shown. The gate spacer 112 may include a plurality of dielectric materials and may be selected from the group consisting of silicon nitride (Si3N4), silicon oxide (SiO2), silicon carbide (SiC), silicon oxycarbide (SiOC), silicon oxynitride (SiON), silicon oxycarbon nitride (SiOCN), carbon-doped oxide, nitrogen-doped oxide, porous oxide, air gap, or a combination thereof. In some embodiments, the gate spacer 112 may include a single layer or a multi-layer structure.

[0063] In some embodiments, the memory cell 101 further includes source / drain regions 114-1, 114-2, and 114-3 (collectively referred to as source / drain regions 114) on / in the substrate 102 (p-type well 102w), such as Figure 1B In addition, Figure 1BAs shown, the source / drain region 114 is arranged on opposite sides of the corresponding gate dielectric layer 108 and the corresponding gate electrode layer 110 (i.e., the corresponding selection gate structure and the floating gate structure) in the Y direction to form the selection transistor ST and the floating gate transistor FT. More specifically, the source / drain region 114-1 is arranged on one side of the gate electrode layer 110-1 in the Y direction, and the source / drain region 114-2 is arranged on the opposite side of the gate electrode layer 110-1 in the Y direction. In addition, the source / drain region 114-2 is also arranged on one side of the gate electrode layer 110-2 in the Y direction, and the source / drain region 114-3 is arranged on the opposite side of the gate electrode layer 110-2 in the Y direction. In some aspects, the source / drain region 114-2 is between the gate electrode layers 110-1 and 110-2 in the Y direction. In other words, the source / drain region 114-2 is shared by the selection transistor ST and the floating gate transistor FT. In addition, the source / drain region 114-1 is also between the isolation structure 104 and the gate electrode layer 110-1 (gate dielectric layer 108-1) in the Y direction, and the source / drain region 114-3 is also between another isolation structure 104 and the gate electrode layer 110-2 (gate dielectric layer 108-2) in the Y direction. The source / drain region 114 may also be referred to as a source / drain or source / drain feature. In some embodiments, the source / drain region may refer to the source or drain individually or collectively, depending on the context. The source / drain region 114 may be formed by using ion implantation. More specifically, multiple portions of the substrate 102 (p-type well 102w) are doped with dopants by ion implantation to form the source / drain region 114. In some embodiments, the source / drain region 114 may have an n-type dopant (e.g., phosphorus, arsenic, other n-type dopants, or a combination thereof). In some embodiments, the source / drain region 114 may be referred to as an n-type source / drain region.

[0064] The memory cell 101 further includes a low-voltage lightly doped drain (LVLDD) 116-1 and medium-voltage lightly doped drains (MVLDD) 118-1, 118-2, and 118-3 (which may be collectively referred to as the medium-voltage lightly doped drain 118). The LVLDD is typically used for core devices, and the MVLDD is typically used for input / output (I / O) devices. Core devices can withstand low voltage stress and require a lower operating voltage (e.g., 1.2V). I / O devices can withstand high voltage stress and require a higher operating voltage (e.g., 6V). The LVLDD 116-1 and the MVLDD 118 are disposed in the substrate 102 (p-type well 102w) and below the gate spacer 112, as shown in FIG. Figure 1B As shown. In some embodiments, the LVLDD 116-1 and the MVLDD 118 are disposed on opposite sides of the gate electrode layer 110 in the Y direction. In addition, the LVLDD 116-1 and the MVLDD 118 are disposed between the gate electrode layer 110 and the source / drain region 114. More specifically, the LVLDD 116-1 is disposed between the gate electrode layer 110-2 (floating gate structure) and the source / drain region 114-3, the MVLDD 118-1 is disposed between the gate electrode layer 110-1 (select gate structure) and the source / drain region 114-1, the MVLDD 118-2 is disposed between the gate electrode layer 110-1 (select gate structure) and the source / drain region 114-2, and the MVLDD 118-3 is disposed between the gate electrode layer 110-2 (floating gate structure) and the source / drain region 114-2.

[0065] Similar to the source / drain region 114 discussed above, the LVLDD 116-1 and the MVLDD 118 may also be formed using ion implantation. In some embodiments, the LVLDD 116-1 and the MVLDD 118 may also have the n-type dopant discussed above. The dopant concentrations of the LVLDD 116-1 and the MVLDD 118 are lower than the dopant concentration of the source / drain region 114. In addition, the dopant concentration of the MVLDD 118 is lower than the dopant concentration of the LVLDD 116-1. In some embodiments, the depth of the MVLDD 118 is greater than the depth of the LVLDD 116-1, such as Figure 1B shown.

[0066] The memory cell 101 further includes a dielectric layer 120 above the gate electrode layer 110-2. More specifically, the dielectric layer 120 is disposed above the gate electrode layer 110-2 and above the gate spacers 112 on opposite sidewalls of the gate electrode layer 110-2, such as Figure 1B As shown. In addition, the dielectric layer 120 is above the source / drain regions 114-2 and 114-3 and partially covers the source / drain regions 114-2 and 114-3. The dielectric layer 120 completely covers the top surface of the gate electrode layer 110-2 and contacts the top surface of the gate electrode layer 110-2 to protect the gate electrode layer 110-2 and the data therein (e.g., electrons (if present)). The dielectric layer 120 is formed from one or more dielectric materials selected from the group consisting of silicon nitride (Si3N4), silicon oxide (SiO2), silicon carbide (SiC), silicon oxycarbide (SiOC), silicon oxynitride (SiON), silicon oxynitride and carbon (SiOCN), or a combination thereof. In some embodiments, the dielectric layer 120 may include a single layer or a multilayer structure.

[0067] Memory cell 101 further includes a silicide feature 122 over and in contact with source / drain region 114 and gate electrode layer 110-1. In some embodiments, silicide feature 122 partially covers source / drain regions 114-2 and 114-3, such as Figure 1B As shown. In addition, the gate electrode layer 110-2 directly contacts the dielectric layer 120 without any silicide features formed therebetween. The silicide features 122 may include titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), nickel platinum silicide (NiPtSi), nickel platinum germanium silicide (NiPtGeSi), nickel germanium silicide (NiGeSi), ytterbium silicide (YbSi), platinum silicide (PtSi), iridium silicide (IrSi), erbium silicide (ErSi), cobalt silicide (CoSi), or other suitable compounds. The silicide features 122 are used to reduce the contact resistance between the vias 126 (to be discussed below) and the source / drain regions 114.

[0068] The non-volatile memory 100 further includes an inter-layer dielectric (ILD) layer 124, vias 126 (including vias 126-1, 126-2, and 126-3), and metal conductors 128 (including metal conductors 128-1, 128-2, 128-3, and 128-4). Figure 1A and Figure 1BThe ILD layer 124 is over the substrate 102 (p-type well 102 w ), the isolation structure 104 , the gate dielectric layer 108 , the gate electrode layer 110 , the gate spacer 112 , the source / drain regions 114 , the dielectric layer 120 , and the silicide feature 122 .

[0069] The ILD layer 124 includes a dielectric material, including, for example, silicon oxide, silicon nitride, silicon oxynitride, oxide formed from TEOS (tetraethylorthosilicate), PSG, BPSG, low-k dielectric materials, other suitable dielectric materials, or combinations thereof. Example low-k dielectric materials include FSG, carbon-doped silicon oxide, (Applied Materials, Santa Clara, California), Xerogel, Aerogel, amorphous fluorinated carbon, parylene, benzocyclobutene (BCB), SiLK (The Dow Chemical Company, Midland, Michigan), polyimide, other low-k dielectric materials, or combinations thereof. In some embodiments, the ILD layer 124 is a dielectric layer including a low-k dielectric material (commonly referred to as a low-k dielectric layer). The ILD layer 124 may include a multilayer structure having a plurality of dielectric materials.

[0070] The vias 126 and the metal conductors 128 are disposed in the ILD layer. The metal conductors 128-1 to 128-4 are above the corresponding gate electrode layers 110 and the corresponding source / drain regions 114. More specifically, as shown in FIG. Figure 1A and Figure 1BAs shown, metal conductor 128-1 is above and overlaps source / drain region 114-1, metal conductor 128-2 is above and overlaps gate electrode layer 110-1, metal conductor 128-3 is above and overlaps gate electrode layer 110-2, and metal conductor 128-4 is above and overlaps source / drain region 114-3. Via 126-1 is above source / drain region 114-1 and electrically connected to source / drain region 114-1 to electrically connect source / drain region 114-1 to metal conductor 128-1. Via 126-2 is above gate electrode layer 110-1 and electrically connected to gate electrode layer 110-1 to electrically connect gate electrode layer 110-1 to metal conductor 128-2. The via 126-3 is above the source / drain region 114-3 and electrically connected to the source / drain region 114-3 to electrically connect the source / drain region 114-3 to the metal conductor 128-4. It is worth noting that the metal conductor 128-3 is electrically isolated from the gate electrode layer 110-2. More specifically, the dielectric layer 120 and the ILD layer 124 are between the metal conductor 128-3 and the gate electrode layer 110-2 to electrically isolate the metal conductor 128-3 from the gate electrode layer 110-2. Therefore, the gate electrode layer 110-2 remains floating during the operation of the memory cell. The material of the through hole 126 and the metal conductor 128 is selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), titanium aluminum nitride (TiAlN), tungsten nitride (WN), tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), platinum (Pt), aluminum (Al), copper (Cu), other conductive materials or combinations thereof.

[0071] like Figure 1A As shown, the metal conductor 128 extends in the X direction and is arranged in the Y direction. Figure 1A As shown, in the top view, the metal conductors 128-2 and 128-3 are arranged to overlap (or span) the gate electrode layers 110-1, 110-2, and 110-2'. In some embodiments, the width of the metal conductor 128-3 in the Y direction is greater than the width of the metal conductor 128-2 in the Y direction. In addition, the width of the metal conductor 128-3 in the Y direction is greater than the length of the gate electrode layer 110-2 in the Y direction. Figure 1B As shown, metal conductors 128-1 to 128-4 are all located at the same metal layer level in the back-end-of-line (BEOL). This metal layer can be referred to as the first metal layer (M1). Figure 1B One metal layer is shown, but it is noted that in some embodiments, there may be more vias and metal conductors at higher metal layers and electrically connected to metal conductors 128 and vias 126 to build the BEOL interconnect structure of memory cell 101 .

[0072] In some embodiments, metal conductor 128 is connected to a power or voltage source (not shown) to provide voltage (including ground voltage) to memory cell 101. In some embodiments, metal conductor 128-1 is used as a source line (SL), metal conductor 128-2 is used as a word line (WL), metal conductor 128-3 is used as a control line (CL), and metal conductor 128-4 is used as a bit line (BL).

[0073] When programming the memory cell 101, the p-type well 102w is connected to ground, the metal conductor 128-1 (SL) is connected to ground, the metal conductor 128-2 (WL) is connected to a first positive voltage (hereinafter may be referred to as voltage V1), the metal conductor 128-3 (CL) is connected to a second positive voltage (hereinafter may be referred to as voltage V2), and the metal conductor 128-4 (BL) is connected to a third positive voltage (hereinafter may be referred to as voltage V3). In this way, the source / drain region 114-1 is connected to ground, the gate electrode layer 110-1 is connected to voltage V1, and the source / drain region 114-3 is connected to voltage V3. As described above, the gate electrode layer 110-2 is floating. In some embodiments, the voltage V1 is in a range of about voltage V3 / 8 to about voltage V3. In some embodiments, the voltage V2 is greater than or equal to (≥) about voltage V3. In some embodiments, the voltage V3 is in a range of about 6V to about 6.5V.

[0074] Under the above programming voltage condition, channel hot electron (CHE) injection is induced in the substrate 102 below the gate electrode layer 110-2 (floating gate structure), and the channel hot electron is injected into the gate electrode layer 110-2. The channel hot electron is stored in the gate electrode layer 110-2. Therefore, the threshold voltage of the floating gate transistor FT changes. This programming method may be referred to as channel hot electron programming (CHE PGM).

[0075] When erasing memory cell 101, p-type well 102w is connected to ground, metal conductor 128-1 (SL) is connected to ground, metal conductor 128-2 (WL) is connected to ground, metal conductor 128-3 (CL) is connected to a negative voltage (hereinafter may be referred to as voltage V4), and metal conductor 128-4 (BL) is connected to a positive voltage (hereinafter may be referred to as voltage V5). In this way, source / drain region 114-1 is connected to ground, gate electrode layer 110-1 is connected to ground, and source / drain region 114-3 is connected to voltage V5. As described above, gate electrode layer 110-2 is floating. In some embodiments, voltage V5 is greater than voltage V4.

[0076] Under the above erase voltage condition, band-to-band hot hole (BBHH) injection is induced in the substrate 102 (p-type well 102w) below the gate electrode layer 110-2 (floating gate structure), and the band-to-band hot holes are injected into the gate electrode layer 110-2. If the gate electrode layer 110-2 has electrons (channel hot electrons from programming), the band-to-band hot holes combine with the electrons to remove the electrons stored in the gate electrode layer 110-2. Therefore, the threshold voltage of the floating gate transistor FT is changed to the threshold voltage before programming. This erasing method can be called channel hot electron erasing (band-to-band hot holes erasing; BBHH ERS).

[0077] As described above, the threshold voltage of the floating gate transistor FT will change depending on whether electrons are stored in the gate electrode layer 110-2. This change in threshold voltage can be known by reading the memory cell 101. When reading the memory cell 101, the p-type well 102w is connected to ground, the metal conductor 128-1 (SL) is connected to ground, the metal conductor 128-2 (WL) is connected to a positive voltage (hereinafter referred to as voltage V6), the metal conductor 128-3 (CL) is connected to a positive voltage (hereinafter referred to as voltage V7), and the metal conductor 128-4 (BL) is connected to a positive voltage (hereinafter referred to as voltage V8). In some embodiments, the voltage V6 is greater than the threshold voltage of the selection transistor ST. In some embodiments, the voltage V7 is in the range of about 0V to about voltage V6. In some embodiments, the voltage V8 is approximately equal to the voltage V6. Therefore, based on the read current, it can be known whether the memory cell 101 is programmed.

[0078] As described above, the memory cell 101 is erased by injecting BBHH into the gate electrode layer 110-2 to remove the electrons stored in the gate electrode layer 110-2. Therefore, compared with the existing method, it is not necessary to extend the gate electrode layer 110-2 of the floating gate transistor FT to an additional area to drive out the electrons stored in the gate electrode layer 110-2. Figure 1A As shown, the gate electrode layer 110 - 2 is a straight line extending in the X direction without any extension branches to other regions. Therefore, compared with the existing memory cells, the memory cell 101 is smaller in size and has a small area.

[0079] In addition, since the metal conductor 128-3 (CL) is connected to the voltage V2 or the voltage V4 described above, the metal conductor 128-3 (CL) facilitates the injection of CHE or BBHH into the gate electrode layer 110-2. Figure 1A and Figure 1B As shown, when viewed from the Z direction, the metal conductor 128-3 completely covers and overlaps the gate electrode layer 110-2 to facilitate the injection of carriers (CHE and BBHH). In the Y direction, the width of the metal conductor 128-3 is greater than or equal to the width of the gate electrode layer 110-2. Therefore, when viewed from the Z direction, the metal conductor 128-3 can completely cover and overlap the MVLDD 118-3, the LVLDD 116-1 and the gate spacer 112, as shown in FIG. Figure 1B In other words, the projection of the gate electrode layers 110 - 2 and 110 - 2 ′ perpendicularly projected onto the imaginary plane along the Z direction is within the projection of the metal conductor 128 - 3 perpendicularly projected onto the imaginary plane along the Z direction.

[0080] As described above, the memory cell 101 has a LVLDD 116-1 having a lower depth and a higher dopant concentration than a conventional LDD (e.g., MVLDD). With such a LVLDD 116-1, CHE and BBHH can be more easily induced in the memory cell 101 during programming and erasing to facilitate programming and erasing. Therefore, compared with the existing memory cell, the memory cell 101 can also have a smaller operating voltage for programming, erasing, and reading. Therefore, the power consumption of the memory cell 101 and the peripheral circuit area for programming and erasing are improved.

[0081] By using such metal conductor 128-3 (CL) and LVLDD 116-1, gate electrode layer 110-2 can be designed to have a smaller length in the Y direction. In some embodiments, the length of gate electrode layer 110-2 in the Y direction is smaller than the length of gate electrode layer 110-1 in the Y direction, such as Figure 1A and Figure 1BTherefore, the memory cell 101 has the advantage of being small in area.

[0082] Figures 2 to 4 Some alternative embodiments according to the present invention show that Figure 1A The YZ cross-sectional views of the non-volatile memory devices 200 , 300 , and 400 are similar to the line segment AA′. Figure 2 The non-volatile memory device 200 is shown with Figure 1A and Figure 1B The non-volatile memory device 100 is similar to the non-volatile memory device 200, except that the memory cell 101 of the non-volatile memory device 200 has an additional LVLDD. Figure 2 As shown, the memory cell 101 includes a LVLDD 116-2, which replaces Figure 1B MVLDD 118-3 is shown in the memory cell 101 in FIG. In some embodiments, LVLDD 116-2 is disposed between gate electrode layer 110-2 (floating gate structure) and source / drain region 114-2.

[0083] Figure 3 The non-volatile memory device 300 is shown with Figure 2 The non-volatile memory device 200 is similar to the non-volatile memory device 300, except that the memory cell 101 of the non-volatile memory device 300 has an additional LVLDD. Figure 3 As shown, the memory cell 101 includes a LVLDD 116-3, which replaces Figure 2 MVLDD 118-2 is shown in the memory cell 101 in FIG. In some embodiments, LVLDD 116-3 is disposed between gate electrode layer 110-1 (floating gate structure) and source / drain region 114-2.

[0084] Figure 4 The non-volatile memory device 400 is shown with Figure 3 The non-volatile memory device 300 is similar to the non-volatile memory device 400, except that the memory cell 101 of the non-volatile memory device 400 has an additional LVLDD. Figure 4 As shown, the memory cell 101 includes a LVLDD 116-4, which replaces Figure 3 1. In some embodiments, the LVLDD 116-4 is disposed between the gate electrode layer 110-1 (floating gate structure) and the source / drain region 114-1.

[0085] Figures 2 to 4 The LVLDDs 116-2 to 116-4 shown are Figure 1B1 is similar to the LVLDD 116-1 shown. Therefore, the LVLDDs 116-2 to 116-4 also have a lower depth and a higher dopant concentration than the conventional LDD (MVLDD). It is easier to induce CHE in the memory cell 101 during programming with more LVLDDs to facilitate programming, as described above. The more LVLDDs there are, the smaller the length of the gate electrode layer in the Y direction can be designed. In other words, Figures 2 to 4 The length of the gate electrode layer 110-2 in the Y direction is less than Figure 1B The length of the gate electrode layer 110 - 2 in the Y direction is shown. Figure 3 The length of the gate electrode layer 110-1 in the Y direction is less than Figure 1B and Figure 2 The length of the gate electrode layer 110 - 1 in the Y direction is shown. Figure 4 The length of the gate electrode layer 110-1 in the Y direction is less than Figure 3 The length of the gate electrode layer 110-1 in the Y direction is shown. Figure 1B The cell pitch of the memory cell 101 in the Y direction is larger than Figure 2 The cell pitch of the memory cell 101 in the Y direction is shown. Figure 2 The cell pitch of the memory cell 101 in the Y direction is larger than Figure 3 The cell pitch of the memory cell 101 in the Y direction is shown, and Figure 3 The cell pitch of the memory cell 101 in the Y direction is larger than Figure 4 The cell pitch of the memory cell 101 in the Y direction is shown.

[0086] Embodiments of the present invention provide multiple advantages over the prior art, and it should be understood that other embodiments may provide different advantages, all of which need not be discussed here, and all embodiments have no particular advantages. For example, the embodiments discussed herein include a non-volatile memory device having a memory cell. The memory cell is programmed by a channel hot electron mechanism and erased by a band-to-band hot hole mechanism, so that there is no need to extend the gate electrode layer of the floating gate transistor to an additional area to drive out the electrons stored in the gate electrode layer, thereby obtaining a memory cell with a low footprint / area loss. In addition, the memory cell includes a metal conductor that serves as a control line above the gate electrode layer of the floating gate transistor and above the corresponding MVLDD and LVLDD. Therefore, the gate electrode layer of the floating gate transistor can be designed with a smaller length and improve the power consumption of the memory cell.

[0087] The foregoing text summarizes the features of many embodiments so that a person skilled in the art can better understand the present invention from various aspects. A person skilled in the art should understand and can easily design or modify other manufacturing processes and structures based on the present invention to achieve the same purpose and / or achieve the same advantages as the embodiments described herein. A person skilled in the art should also understand that these equivalent structures do not depart from the spirit and scope of the present invention. Various changes, substitutions or modifications may be made to the present invention without departing from the spirit and scope of the present invention.

Claims

1. A non-volatile memory device comprising: substrate; A memory unit comprising: a select transistor including a select gate structure over the substrate, a first source / drain region on a first side of the select gate structure, and a second source / drain region on a second side of the select gate structure opposite the first side; a floating gate transistor comprising a floating gate structure above the substrate, the second source / drain region on a third side of the floating gate structure, and a third source / drain region on a fourth side of the floating gate structure opposite to the third side; and a metal conductor, above the floating gate structure and electrically isolated from the floating gate structure, The floating gate transistor further includes a first low voltage lightly doped drain between the floating gate structure and the third source / drain region.

2. The non-volatile memory device of claim 1, wherein the floating gate transistor further comprises: A first medium voltage lightly doped drain is disposed between the floating gate structure and the second source / drain region. The selection transistor further comprises: a second medium voltage lightly doped drain between the select gate structure and the second source / drain region; and a third medium voltage lightly doped drain, between the select gate structure and the first source / drain region, The dopant concentrations of the first medium voltage lightly doped drain, the second medium voltage lightly doped drain and the third medium voltage lightly doped drain are lower than the dopant concentration of the first low voltage lightly doped drain.

3. The non-volatile memory device as claimed in claim 2, wherein depths of the first medium voltage lightly doped drain, the second medium voltage lightly doped drain and the third medium voltage lightly doped drain are greater than a depth of the first low voltage lightly doped drain.

4. The non-volatile memory device of claim 1 , wherein the floating gate transistor further comprises: A second low voltage lightly doped drain is disposed between the floating gate structure and the second source / drain region. The selection transistor further comprises: a first medium voltage lightly doped drain between the select gate structure and the second source / drain region; and a second medium voltage lightly doped drain, between the select gate structure and the first source / drain region, The multiple dopant concentrations of the first medium voltage lightly doped drain and the second medium voltage lightly doped drain are lower than the multiple dopant concentrations of the first low voltage lightly doped drain and the second low voltage lightly doped drain.

5. The non-volatile memory device of claim 4, wherein depths of the first medium voltage lightly doped drain and the second medium voltage lightly doped drain are greater than depths of the first low voltage lightly doped drain and the second low voltage lightly doped drain.

6. The non-volatile memory device of claim 1, wherein the floating gate transistor further comprises: A second low voltage lightly doped drain is disposed between the floating gate structure and the second source / drain region. The selection transistor further comprises: a third low voltage lightly doped drain between the select gate structure and the second source / drain region; and A medium voltage lightly doped drain is disposed between the select gate structure and the first source / drain region. The dopant concentration of the medium voltage lightly doped drain is lower than the dopant concentrations of the first low voltage lightly doped drain, the second low voltage lightly doped drain and the third low voltage lightly doped drain.

7. The non-volatile memory device of claim 6, wherein depths of the medium voltage lightly doped drain are greater than depths of the first low voltage lightly doped drain, the second low voltage lightly doped drain, and the third low voltage lightly doped drain.

8. The non-volatile memory device of claim 1, wherein the floating gate transistor further comprises: A second low voltage lightly doped drain is disposed between the floating gate structure and the second source / drain region. The selection transistor further comprises: a third low voltage lightly doped drain between the select gate structure and the second source / drain region; and A fourth low voltage lightly doped drain is between the selection gate structure and the first source / drain region.

9. The non-volatile memory device of claim 1 , further comprising: The dielectric layer completely covers and contacts the top surface of the floating gate structure.

10. The non-volatile memory device of claim 1, wherein a length of the floating gate structure in a Y direction is smaller than a length of the select gate structure in the Y direction.

11. The non-volatile memory device of claim 1, wherein the substrate has a p-type well, and the first source / drain region, the second source / drain region, and the third source / drain region have n-type dopants and are disposed in the p-type well.

12. The non-volatile memory device of claim 11, wherein the substrate further comprises a deep n-type well, and the p-type well is formed in the deep n-type well.

13. The non-volatile memory device of claim 1 , wherein when the memory cell is programmed, the p-type well is connected to ground, the select gate structure is connected to a first positive voltage, the floating gate structure is floating, the first source / drain region is connected to ground, the metal conductor is connected to a second positive voltage, and the third source / drain region is connected to a third positive voltage, wherein the second positive voltage is greater than or equal to the third positive voltage.

14. The non-volatile memory device of claim 1 , wherein when the memory cell is erased, the p-type well is connected to ground, the select gate structure is connected to ground, the floating gate structure is floating, the first source / drain region is connected to ground, the metal conductor is connected to a negative voltage, and the third source / drain region is connected to a positive voltage.

15. The non-volatile memory device of claim 1, wherein the metal conductor completely covers and overlaps the floating gate structure.

16. The non-volatile memory device of claim 1, wherein the memory cell is programmed by inducing channel hot electron injection under the floating gate structure.

17. The non-volatile memory device of claim 1, wherein the memory cell is erased by inducing band-to-band hot hole injection under the floating gate structure.

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