A memory chip, a logic chip, a chip stacking structure, and a memory.

Abstract

This disclosure provides a memory chip, a logic chip, a chip stack structure, and a memory. The center point of the active surface of the memory chip and its adjacent area are defined as a global signal region. The global signal region is penetrated by n conductive via groups, and all conductive vias in the same conductive via group are used to transmit the same global signal. The i-th first driving circuit is configured to receive the i-th global signal from the i-th conductive via group via the i-th first OR logic circuit, and send the i-th global signal to the internal circuit of the memory chip.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a memory chip, a logic chip, a chip stacking structure, and a memory. Background Technology

[0002] With the development of integrated circuit technology, the manufacturing process of semiconductor devices has made significant progress. However, in recent years, the development of two-dimensional semiconductor technology has encountered various challenges: physical limits, limitations of existing development techniques, and limits of stored electron density. Against this backdrop, to address the difficulties encountered in two-dimensional semiconductor devices and to pursue lower production costs per unit memory cell, bonding processes (e.g., hybrid bonding, bumping, wire bonding) can be used to stack multiple chips to form three-dimensional semiconductor devices. However, for three-dimensional semiconductor devices, the connection structure between different chips still suffers from problems such as large parasitic capacitance and resistance, affecting signal transmission quality. Summary of the Invention

[0003] This disclosure provides a memory chip, a logic chip, a chip stack structure, and a memory.

[0004] In a first aspect, embodiments of this disclosure provide a memory chip, wherein the center point of the active surface of the memory chip and its adjacent area are defined as a global signal region, and the center point of the global signal region coincides with the center point of the active surface; the global signal region is penetrated by n conductive via groups, and all conductive vias in the same conductive via group are used to transmit the same global signal; n is a positive integer;

[0005] The memory chip further includes n first OR logic circuits and n first driving circuits; the input terminal of the i-th first OR logic circuit is coupled to all the conductive vias in the i-th conductive via group, and the output terminal of the i-th first OR logic circuit is coupled to the i-th first driving circuit; i is a positive integer less than or equal to n;

[0006] The i-th first driving circuit is configured to receive the i-th global signal from the i-th conductive via group via the i-th first OR logic circuit, and send the i-th global signal to the internal circuit of the memory chip;

[0007] Each of the conductive via groups includes a first conductive via, a second conductive via, a third conductive via, and a fourth conductive via. The first and second conductive vias are symmetrical about a first axis, the third and fourth conductive vias are symmetrical about the first axis, and the first and fourth conductive vias are symmetrical about a second axis. The first axis and the second axis are perpendicular to each other and intersect at the center point of the active surface. The first axis is parallel to the first side of the memory chip, and the second axis is parallel to the second side of the memory chip.

[0008] In some embodiments, the first OR logic circuit includes a first OR gate, a second OR gate, and a third OR gate;

[0009] For the i-th first OR logic circuit, the first input terminal of the first OR gate is connected to the first conductive via in the i-th conductive via group, the second input terminal of the first OR gate is connected to the fourth conductive via in the i-th conductive via group, and the output terminal of the first OR gate is connected to the first input terminal of the third OR gate; the first input terminal of the second OR gate is connected to the second conductive via in the i-th conductive via group, the second input terminal of the second OR gate is connected to the third conductive via in the i-th conductive via group, and the output terminal of the second OR gate is connected to the second input terminal of the third OR gate; the output terminal of the third OR gate is used to output the global signal.

[0010] In some embodiments, each of the conductive vias is connected to a weak ground terminal; the weak ground terminal includes a resistor and a ground terminal.

[0011] If the conductive via is not transmitting a signal or is not properly connected, the ground terminal controls the voltage level of the conductive via to be low; if the conductive via is properly connected and transmitting a signal, the voltage level of the conductive via depends on the transmitted signal.

[0012] In some embodiments, the memory chip further includes n second driving circuits; the i-th second driving circuit is coupled to all the conductive vias in the i-th conductive via group;

[0013] The i-th second driving circuit is configured to send the i-th global signal generated inside the memory chip to all the conductive vias coupled thereto.

[0014] In some embodiments, the conductive vias are fabricated using any one or more of the following processes: via-first, via-middle, via-last, and back side via-last, and different conductive vias in the same memory chip are electrically isolated from each other.

[0015] Secondly, this disclosure provides a logic chip in which the center point of the active surface of the logic chip and its adjacent area are defined as a global signal region, and the center point of the global signal region coincides with the center point of the active surface; the global signal region is penetrated by n conductive via groups, and all conductive vias in the same conductive via group are used to transmit the same global signal; n is a positive integer;

[0016] Each of the aforementioned conductive via groups includes a first conductive via, a second conductive via, a third conductive via, and a fourth conductive via. The first conductive via and the second conductive via are symmetrical about a first axis, the third conductive via and the fourth conductive via are symmetrical about the first axis, and the first conductive via and the fourth conductive via are symmetrical about a second axis.

[0017] The first axis and the second axis are perpendicular to each other and intersect at the center point of the active surface. The first axis is parallel to the first side of the logic chip, and the second axis is parallel to the second side of the logic chip.

[0018] In some embodiments, the logic chip further includes n third driving circuits;

[0019] The i-th third driving circuit is coupled to all the conductive vias in the i-th conductive via group; i is a positive integer less than or equal to n;

[0020] The i-th third driving circuit is configured to send the i-th global signal generated inside the logic chip to all the conductive vias coupled thereto.

[0021] In some embodiments, the logic chip further includes n second OR logic circuits and n fourth driving circuits; the input terminal of the i-th second OR logic circuit is coupled to all the conductive vias in the i-th conductive via group, and the output terminal of the i-th second OR logic circuit is coupled to the i-th fourth driving circuit.

[0022] The i-th fourth driving circuit is configured to receive the i-th global signal from the i-th conductive via group via the i-th second OR logic circuit, and send the i-th global signal to the internal circuit of the logic chip.

[0023] In some embodiments, the second OR logic circuit includes a fourth OR gate, a fifth OR gate, and a sixth OR gate;

[0024] For the i-th second OR logic circuit, the first input terminal of the fourth OR gate is connected to the first conductive via in the i-th conductive via group, the second input terminal of the fourth OR gate is connected to the fourth conductive via in the i-th conductive via group, and the output terminal of the fourth OR gate is connected to the first input terminal of the sixth OR gate; the first input terminal of the fifth OR gate is connected to the second conductive via in the i-th conductive via group, the second input terminal of the fifth OR gate is connected to the third conductive via in the i-th conductive via group, and the output terminal of the fifth OR gate is connected to the second input terminal of the sixth OR gate; the output terminal of the sixth OR gate is used to output the global signal.

[0025] In some embodiments, each of the conductive vias is connected to a weak ground terminal; the weak ground terminal includes a resistor and a ground terminal.

[0026] If the conductive via is not transmitting a signal or is not properly connected, the ground terminal controls the voltage level of the conductive via to be low; if the conductive via is properly connected and transmitting a signal, the voltage level of the conductive via depends on the transmitted signal.

[0027] In some embodiments, the conductive vias are fabricated using any one or more of the following processes: via-first, via-middle, via-last, and back side via-last, and different conductive vias in the same logic chip are electrically isolated from each other.

[0028] Thirdly, embodiments of this disclosure provide a chip stacking structure, the chip stacking structure including a logic chip as described in any one of the second aspects and at least one stacking unit, wherein the logic chip and at least one stacking unit are stacked sequentially along a third direction; each stacking unit includes a first memory chip, a second memory chip, a third memory chip, and a fourth memory chip stacked sequentially along the third direction, the third direction being perpendicular to the top surface of each memory chip; the first memory chip, the second memory chip, the third memory chip, and the fourth memory chip are all memory chips as described in any one of the first aspects;

[0029] The first memory chip and the second memory chip are stacked face-to-face, the second memory chip and the third memory chip are stacked back-to-back, and the third memory chip and the fourth memory chip are stacked face-to-face.

[0030] The first memory chip and the logic chip in the first stacking unit are stacked back-to-back, or the first memory chip and the logic chip in the first stacking unit are stacked back-to-back; the n conductive via groups in the logic chip correspond one-to-one with the n conductive via groups in each of the first memory chip, the second memory chip, the third memory chip, and the fourth memory chip, and are aligned along the third direction, where n is a positive integer.

[0031] In some embodiments, the global signal region in each chip is penetrated by n groups of conductive vias. Each group of conductive vias includes a first conductive via, a second conductive via, a third conductive via, and a fourth conductive via. The first and second conductive vias are symmetrical about a first axis, the third and fourth conductive vias are symmetrical about the first axis, and the first and fourth conductive vias are symmetrical about a second axis. The first axis and the second axis are perpendicular to each other and intersect at the center point of the active surface. The first axis is parallel to a first side of the memory chip, and the second axis is parallel to a second side of the memory chip.

[0032] The first axis of each logic chip and each memory chip is aligned along the third direction, and the second axis of each logic chip and each memory chip is aligned along the third direction.

[0033] In some embodiments, where the logic chip and the first memory chip are stacked back-to-back,

[0034] The fourth conductive via in the i-th conductive via group of the logic chip, the first conductive via in the i-th conductive via group of each first memory chip, the second conductive via in the i-th conductive via group of each second memory chip, the third conductive via in the i-th conductive via group of each third memory chip, and the fourth conductive via in the i-th conductive via group of each fourth memory chip are aligned along the third direction and form a signal transmission channel;

[0035] The third conductive via in the i-th conductive via group of the logic chip, the second conductive via in the i-th conductive via group of each first memory chip, the first conductive via in the i-th conductive via group of each second memory chip, the fourth conductive via in the i-th conductive via group of each third memory chip, and the third conductive via in the i-th conductive via group of each fourth memory chip are aligned along the third direction and form a signal transmission channel;

[0036] The second conductive via in the i-th conductive via group of the logic chip, the third conductive via in the i-th conductive via group of each first memory chip, the fourth conductive via in the i-th conductive via group of each second memory chip, the first conductive via in the i-th conductive via group of each third memory chip, and the second conductive via in the i-th conductive via group of each fourth memory chip are aligned along the third direction and form a signal transmission channel;

[0037] The first conductive via in the i-th conductive via group of the logic chip, the fourth conductive via in the i-th conductive via group of each first memory chip, the third conductive via in the i-th conductive via group of each second memory chip, the second conductive via in the i-th conductive via group of each third memory chip, and the first conductive via in the i-th conductive via group of each fourth memory chip are aligned along the third direction and form a signal transmission channel;

[0038] Where i is a positive integer less than or equal to n.

[0039] In some embodiments, where the logic chip and the first memory chip are stacked back-to-back,

[0040] The second conductive via in the i-th conductive via group of the logic chip, the first conductive via in the i-th conductive via group of each first memory chip, the second conductive via in the i-th conductive via group of each second memory chip, the third conductive via in the i-th conductive via group of each third memory chip, and the fourth conductive via in the i-th conductive via group of each fourth memory chip are aligned along the third direction and form a signal transmission channel;

[0041] The first conductive via in the i-th conductive via group of the logic chip, the second conductive via in the i-th conductive via group of each first memory chip, the first conductive via in the i-th conductive via group of each second memory chip, the fourth conductive via in the i-th conductive via group of each third memory chip, and the third conductive via in the i-th conductive via group of each fourth memory chip are aligned along the third direction and form a signal transmission channel;

[0042] The fourth conductive via in the i-th conductive via group of the logic chip, the third conductive via in the i-th conductive via group of each first memory chip, the fourth conductive via in the i-th conductive via group of each second memory chip, the first conductive via in the i-th conductive via group of each third memory chip, and the second conductive via in the i-th conductive via group of each fourth memory chip are aligned along the third direction and form a signal transmission channel;

[0043] The third conductive via in the i-th conductive via group of the logic chip, the fourth conductive via in the i-th conductive via group of each first memory chip, the third conductive via in the i-th conductive via group of each second memory chip, the second conductive via in the i-th conductive via group of each third memory chip, and the first conductive via in the i-th conductive via group of each fourth memory chip are aligned along the third direction and form a signal transmission channel.

[0044] In some embodiments, for two chips connected face-to-face, the conductive vias aligned along the third direction are electrically connected using a hybrid bonding process; for two chips connected back-to-back or back-to-face, the conductive vias aligned along the third direction are electrically connected using a conductive bump bonding process; or...

[0045] For two chips connected face-to-face, or two chips connected back-to-back, or two chips connected back-to-face, the conductive vias aligned along the third direction are electrically connected using the hybrid bonding process; or,

[0046] For two chips connected face-to-face, or for two chips connected back-to-back, or for two chips connected back-to-face, the conductive vias aligned along the third direction are electrically connected through the conductive bump bonding process.

[0047] Fourthly, embodiments of this disclosure provide a memory comprising a chip stacking structure as described in any one of the third aspects.

[0048] This disclosure provides a memory chip, a logic chip, a chip stack structure, and a memory. Utilizing conductive vias with special symmetry, it not only reduces the number of driving circuits and data selectors, thereby reducing parasitic capacitance, but also achieves signal rotation transmission through the direct connection configuration of the conductive vias in the chip stack structure formed by the memory chip and logic chip, further reducing parasitic resistance. Furthermore, by using all conductive vias in the same conductive via group to transmit the same global signal, a repair effect is achieved. Moreover, this conductive via configuration allows for multi-point connection of global signals with a minimal number of conductive vias, reducing the occupied area of ​​the global signal region and further reducing the area of ​​the memory chip. Attached Figure Description

[0049] Figure 1 This is a schematic diagram of the structure of a chip;

[0050] Figure 2A A schematic diagram of signal transmission in a chip stacking structure. Figure 1 ;

[0051] Figure 2B Schematic diagram 2 of a chip stacking structure for signal transmission;

[0052] Figure 3 A schematic diagram of an active surface in a memory chip provided in an embodiment of this disclosure;

[0053] Figure 4 A schematic diagram of the composition structure of a memory chip provided in this embodiment of the present disclosure. Figure 1 ;

[0054] Figure 5 A schematic diagram of the composition structure of a memory chip provided in an embodiment of this disclosure is shown below;

[0055] Figure 6 A schematic diagram of the composition structure of a memory chip provided in this embodiment of the present disclosure. Figure 3 ;

[0056] Figure 7 A schematic diagram of an active surface in a logic chip provided in an embodiment of this disclosure;

[0057] Figure 8 A schematic diagram of the composition structure of a logic chip provided in this embodiment of the disclosure. Figure 1 ;

[0058] Figure 9 A schematic diagram of the composition structure of a logic chip provided in an embodiment of this disclosure is shown below;

[0059] Figure 10 A schematic diagram of the composition structure of a logic chip provided in this embodiment of the disclosure. Figure 3 ;

[0060] Figure 11 This is a schematic diagram of the composition of a chip stacking structure provided in an embodiment of the present disclosure;

[0061] Figure 12 This invention provides a schematic diagram of signal transmission in a chip stacking structure according to an embodiment of the present disclosure. Figure 1 ;

[0062] Figure 13A / Figure 13B A specific illustration of a chip stacking structure provided in this embodiment of the present disclosure. Figure 1 ;

[0063] Figure 14A / Figure 14B A second schematic diagram of a chip stacking structure provided in this embodiment of the present disclosure;

[0064] Figure 15A / Figure 15B A specific illustration of a chip stacking structure provided in this embodiment of the present disclosure. Figure 3 ;

[0065] Figure 16A / Figure 16B A specific illustration of a chip stacking structure provided in this embodiment of the present disclosure. Figure 4 ;

[0066] Figure 17 This is a schematic diagram of signal transmission for a chip stacking structure provided in an embodiment of the present disclosure;

[0067] Figure 18 This is a schematic diagram of the composition structure of a memory provided in an embodiment of this disclosure. Detailed Implementation

[0068] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only for explaining the relevant applications and are not intended to limit the scope of this disclosure. Furthermore, it should be noted that, for ease of description, only the parts relevant to the relevant applications are shown in the accompanying drawings.

[0069] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0070] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0071] It should be noted that the terms "first, second, third" used in the embodiments of this disclosure are merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0072] Before introducing the embodiments of this disclosure, we first define three directions that may be used in the plane to describe the three-dimensional structure in the following embodiments. Taking the Cartesian coordinate system as an example, the three directions may include a first direction, a second direction, and a third direction.

[0073] Please see Figure 1 A semiconductor chip (specifically, a memory chip or a logic chip) may include a top surface on the front side and a bottom surface on the back side opposite to the front side. Ignoring the flatness of the top and bottom surfaces, the direction intersecting (e.g., perpendicular to) the top and bottom surfaces of the semiconductor chip is defined as a third direction. On the top surface of the semiconductor chip, two mutually perpendicular directions are defined, namely a first direction and a second direction, where the first direction is perpendicular to one edge of the semiconductor chip, and the second direction is perpendicular to the other edge of the semiconductor chip.

[0074] Please see Figure 1 A semiconductor chip includes a substrate. One side of the substrate used to fabricate devices (such as transistors and capacitors) forms the active surface (the side of the substrate opposite to the active surface is the non-active surface, i.e., ...). Figure 1 The bottom surface has multiple metal layers distributed between its substrate and top surface, such as M1, M2, M3, etc. Figure 1 The diagram also shows two types of conductive vias (e.g., through-silicon vias), both used to enable signal connections between different stacked chips.

[0075] like Figure 1 As shown, for a type 1 conductive via, it penetrates the bottom surface and the top surface in a third direction, and the conductive via is connected to the internal circuitry of the chip through a metal layer.

[0076] like Figure 1 As shown, for type 2 conductive vias, which penetrate the substrate only along a third direction (penetrating both the active surface and the bottom surface), signal transmission is achieved in conjunction with a contact structure that penetrates the top surface along the third direction. The contact structure and the conductive via are not directly electrically connected, but rather indirectly connected through a metal layer. For example: Figure 1 The contact structure in the middle is connected to M4, and M4 is connected to M1 via M3 and M2 in sequence. M1 is then connected to the conductive via; or... Figure 1 The conductive vias in the chip are connected to the internal circuitry via M1-M4. Figure 1The input terminal of the device in the substrate, the output signal processed by the internal circuitry of the chip, is then output to the corresponding contact structure via metal layers M1-M4. Similarly, Figure 1 The contact structure in the chip can also be connected to the internal circuitry via M1-M4. Figure 1 The input terminal of the device in the substrate, after being processed by the internal circuitry of the chip, is then output to the corresponding conductive via M1-M4. Of course, in other embodiments, the contact structure and conductive via can also be designed to be directly electrically connected.

[0077] Furthermore, the types of conductive vias are not limited to the two types mentioned above; the examples are merely illustrative. In particular, the illustrations presented in this disclosure are not intended to be actual views of any particular microelectronic device or its components, but are merely idealized representations for describing illustrative embodiments, and therefore the drawings are not necessarily drawn to scale.

[0078] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0079] In one embodiment, a memory chip and a logic chip are provided. Both the memory chip and the logic chip include multiple conductive vias extending through the chip in a third direction. These conductive vias are used to enable signal transmission between different chips, and all conductive vias can be located at any position. Specifically, every four conductive vias can be functionally considered as a group of conductive vias, but the individual positions of these four conductive vias are not limited.

[0080] In one specific embodiment, eight of the aforementioned memory chips and one logic chip are stacked to form a 3D memory device. Simultaneously, the conductive vias of the eight memory chips are aligned along a third direction, and the nine aligned conductive vias along the third direction are connected to form an electrical path. See also... Figure 2A It illustrates a signal transmission diagram of a chip stacking structure. Figure 1 .like Figure 2A As shown, the chip stacking structure includes memory chips 0-7 and logic chips. Figure 2A For each memory chip, only 4 conductive vias D0 to D3 are shown, and these 4 conductive vias D0 to D3 belong to the same conductive via group. At this time, the conductive vias D0 in 8 memory chips and 1 logic chip are aligned to form a single electrical path, and the conductive vias D1 in 8 memory chips and 1 logic chip are aligned to form a single electrical path... The remaining conductive vias are similar.

[0081] At the same time, each memory chip and logic chip is also equipped with multiple driver circuits. Figure 2A Only one driving circuit is shown in the image (the rest are not shown), and each conductive via is connected to one driving circuit; each memory chip also has multiple data selectors (e.g., Figure 2A In the configuration (mux0~7), each via group corresponds to one data selector. That is, all the vias in a via group are connected to the data port of the data selector through their respective drive circuits. In other words, the data selector can choose which via transmits a signal to the memory chip or which via inputs a signal output from the memory chip.

[0082] For the overall storage device, different regions in different memory chips are managed by different channels (e.g., CH0, CH1, CH4, CH5). The signal Signal_CH0 of channel CH0 is transmitted through an electrical path consisting of "conductive via D0 in the logic chip, conductive via D0 in memory chip 0, conductive via D0 in memory chip 1, conductive via D0 in memory chip 2, conductive via D0 in memory chip 3, conductive via D0 in memory chip 4, conductive via D0 in memory chip 5, conductive via D0 in memory chip 6, and conductive via D0 in memory chip 7". The selection signals of the data selector mux0 in memory chip 0 and the data selector mux4 in memory chip 4 are both SEL_C0, that is, the signal Signal_CH0 can enter memory chip 0 and memory chip 4 through the aforementioned electrical path; the signal output process can be understood similarly.

[0083] As can be seen from the above, memory chip 0 only needs to obtain signals from conductive via D0, memory chip 1 only needs to obtain signals from conductive via D1, and so on. That is, each memory chip only needs to obtain signals from one of the conductive vias in a group of conductive vias. It is worth noting that different memory chips may need to obtain signals from different conductive vias. However, since all memory chips need to be designed with the exact same structure during manufacturing (to maximize cost and labor savings), all conductive vias in the memory chip need to be designed with corresponding drive structures and data selectors to achieve structural consistency. Furthermore, when using… Figure 2A In the chip stacking structure shown, each conductive via corresponds to a driving circuit. During the operation of this chip stacking structure, it is necessary to drive all the driving circuits of all memory chips in the same channel. This results in a large load and large parasitic capacitance, which seriously affects the performance of the chips, restricts the transmission efficiency, increases power consumption, and also limits the number of chips stacked in the three-dimensional device.

[0084] In another embodiment, please refer to Figure 2B The diagram illustrates a signal transmission schematic of a chip stacking structure. Specifically, Figure 2B Only some conductive vias (D0~D3) are marked; others are omitted. However, for... Figure 2BFor example, the markings for conductive vias aligned along a third direction are the same. Figure 2B As shown, the chip stack structure also includes eight memory chips and one logic chip aligned along a third direction. However, the conductive vias in each memory chip are rotatably connected to another conductive via at a different position in another memory chip, achieving a spiral upward connection as a whole. That is, the signal Signal_CH0 of channel CH0 is transmitted through “conductive via D0 in logic chip 0 – conductive via D1 in memory chip 0 – conductive via D2 in memory chip 1 – conductive via D3 in memory chip 2 – conductive via D0 in memory chip 3 – conductive via D1 in memory chip 4 – conductive via D2 in memory chip 5 – conductive via D3 in memory chip 6 – conductive via D0 in memory chip 7”, and the other signals are similar.

[0085] In this way, memory chip 0 can obtain the signal Signal_CH0 through the output terminal of the conductive via D0 in the logic chip, memory chip 1 can obtain the signal Signal_CH1 through the input terminal of the conductive via D0 in memory chip 0, memory chip 2 can obtain the signal Signal_CH4 through the input terminal of the conductive via D0 in memory chip 1, memory chip 3 can obtain the signal Signal_CH5 through the input terminal of the conductive via D0 in memory chip 2, and so on. For each memory chip, only one conductive via is needed to connect to the driving circuit in each group of conductive vias, and no data selector is required, which reduces the number of devices and thus reduces parasitic capacitance. However, compared to Figure 2A The conductive via direct connection configuration. Figure 2B The process of rotary connection of through-holes in medium-voltage systems is more complex, specifically... Figure 2B A horizontal interconnect structure needs to be set between adjacent conductive vias in each memory chip. Figure 2B (Only one is marked with a pentagram in the image). The signal interconnect structure can be a metal interconnect, a conductive via, etc. To achieve the rotating connection of the conductive via, the input signal signal_CH0 must first be transmitted upwards from the conductive via D0 of the logic chip to the interconnect structure below the conductive via D0 of the memory chip 0 (not directly connected to the conductive via D0 of the memory chip 0), and then horizontally transmitted from the interconnect structure below the conductive via D0 of the memory chip 0 to the conductive via D1 of the memory chip 0. That is: Figure 2B The structure shown requires the signal to pass through the interconnect structure in each memory chip during the signal transmission process, and the output signal is similar. This inevitably leads to an increase in parasitic resistance and also increases the complexity of the manufacturing process.

[0086] In particular, Figure 2A and Figure 2BIn the chip stacking structure, all chips are active-facing, meaning that different memory chips are stacked back-to-back, and memory chips and logic chips are also stacked back-to-back, that is, the bottom surface of the upper chip is in contact with the top surface of the lower chip.

[0087] In summary, on the one hand, Figure 2A The chip stacking structure requires numerous conductive vias to transmit the corresponding signals. Combined with the associated driver circuitry and data selectors, this results in a large load and parasitic capacitance. Figure 2B The chip stacking structure has a large parasitic resistance due to its rotational configuration; on the other hand... Figure 2A and Figure 2B All existing stacking structures have certain problems and cannot be directly applied to face-to-face stacking structures. Specifically, if we want to further realize face-to-face chip stacking structures, one approach is to use two sets of masks to create two different chips, one as the active-facing chip and the other as the active-facing chip. This approach has high process complexity and uncontrollable costs. Another approach is to create an additional set of conductive vias and connect both sets of conductive vias to the same driving circuit within the memory chip. However, this leads to complex internal wiring of the memory chip, increasing both process complexity and power consumption.

[0088] Therefore, embodiments of this disclosure propose a memory chip, a logic chip, a chip stacking structure, and a memory. The chip stacking structure not only has small parasitic capacitance and parasitic resistance, but also realizes a face-to-face stacking method. In particular, embodiments of this disclosure also provide a related mechanism for global signal redundancy repair under this structure.

[0089] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0090] In one embodiment of this disclosure, see [link to embodiment]. Figure 3 This illustration shows a schematic diagram of the active surface of a memory chip according to an embodiment of the present disclosure, which can be specifically understood as a cross-sectional schematic diagram of the active surface. Figure 3 As shown, the memory chip 10 includes m channels (m is a positive integer). Figure 3 (Taking m=4 as an example for illustration), m channels are arranged sequentially along the first direction. Each channel includes a first storage array region, a channel signal region, and a second storage array region distributed sequentially along the second direction. The center of each channel signal region coincides with the center of its respective channel.

[0091] It should be noted that, in order to distinguish different channels of the chip during the chip manufacturing process, a positioning structure can be made on the reference channel (e.g., the first channel) of the memory chip 10 so that the position of the reference channel can be identified through the positioning structure during subsequent packaging, and other channels can be identified in combination with the orientation of the active surface of the chip.

[0092] Figure 3 The example shown is m=4, and the following explanation will also use m=4 as an example, but m can be any positive integer.

[0093] like Figure 3 As shown, the center point of the active surface of the memory chip 10 and its adjacent area are defined as the global signal region 11, and the center point of the global signal region 11 coincides with the center point of the active surface; the m channels are symmetrical about the global signal region 11.

[0094] It should be noted that both the global signal region 11 and the channel signal region are penetrated by a plurality of conductive vias along a third direction, and the third direction is perpendicular to the active surface. Here, the conductive vias can be through-silicon vias (TSVs), specifically a vertical interconnect structure that penetrates a silicon wafer / chip, or, in other embodiments, other conductive vias with conductive functions, without specific limitation. In addition, the conductive vias can take the form of type 1 mentioned above, or take the form of type 2 mentioned above.

[0095] For the global signal region 11, each conductive via is used to transmit a global signal, which is shared by the entire region of the corresponding memory chip 10. Global signals include, but are not limited to, command signals and address signals. In some cases, the global signal region 11 may also refer to the pad region. Global signals can be design-for-test (DFT) test signals, through which the operating status of the internal circuitry and the transmission status of related signals can be determined. Furthermore, because the DFT pin pads in the memory chip 10 are generally located in the middle of the chip, the conductive vias for global signals such as DFT are preferably located in a narrower area in the middle of the chip, i.e., such as... Figure 3 The location of the global signal region 11 shown.

[0096] For the channel signal region, each conductive via is used to transmit the channel signal, and the signal transmitted in each channel signal region is only used by its respective channel. The conductive via in each channel signal region is for its own channel signal region, and only a local part of the memory chip 10 (the corresponding channel) will use the conductive via; while the conductive via in the global signal region 11 located in the middle of the memory chip 10 is used to test the entire memory chip 10, and the signal transmitted in the global signal region 11 is shared by m channels of the memory chip 10.

[0097] Please see Figure 3For the active surface of the memory chip 10, there exists a first axis AA' and a second axis BB'. The first axis AA' and the second axis BB' are perpendicular to each other and intersect at the center point of the active surface. The first axis AA' is parallel to the first side of the memory chip 10, and the second axis BB' is parallel to the second side of the memory chip 10. Figure 3 In this embodiment, the first axis AA' can extend along the first direction, and the second axis BB' can extend along the second direction. In other embodiments, the first axis AA' can also extend along the second direction, and the second axis BB' can extend along the first direction. There is no specific limitation on this.

[0098] Further, see Figure 4 It illustrates a schematic diagram of the composition structure of a memory chip provided in an embodiment of this disclosure. Figure 1 .like Figure 4 As shown, in the memory chip 10, the global signal region is divided by n conductive vias 20 ( Figure 4 Only one conductive via group 20 is shown in the figure, and the rest are omitted. All conductive vias in the same conductive via group 20 are used to transmit the same global signal; n is a positive integer; each conductive via group 20 includes a first conductive via D0, a second conductive via D1, a third conductive via D2, and a fourth conductive via D3.

[0099] In particular, Figure 4 This can be viewed as a cross-sectional view of the memory chip 10 along its active surface. Please refer to [reference needed]. Figure 4 For the same group of conductive vias 20, the first conductive via D0 and the second conductive via D1 are symmetrical about the first axis AA', the third conductive via D2 and the fourth conductive via D3 are symmetrical about the first axis AA', and the first conductive via D0 and the fourth conductive via D3 are symmetrical about the second axis BB'.

[0100] like Figure 4 As shown, in one possibility, the memory chip 10 further includes n first OR logic circuits 30 and n first drive circuits 40. Figure 4 Only one first OR logic circuit 30 and one first driving circuit 40 are shown in the figure, and the rest are omitted; the input terminal of the i-th first OR logic circuit 30 is coupled to all the conductive vias in the i-th conductive via group 20, and the output terminal of the i-th first OR logic circuit 30 is coupled to the i-th first driving circuit 40; i is a positive integer less than or equal to n;

[0101] The i-th first driving circuit 40 is configured to receive the i-th global signal from the i-th conductive via group 20 via the i-th first OR logic circuit 30, and send the i-th global signal to the internal circuit of the memory chip 10.

[0102] It should be noted that each of the n first OR logic circuits 30 and the n first driving circuits 40 corresponds one-to-one with each of the n conductive via groups 20.

[0103] It should also be noted that the positions of the conductive via groups 20 in the global signal region vary. Specifically, the number and position of the conductive via groups 20 can be adjusted according to the actual situation and are not limited thereto. However, the number of conductive vias in each conductive via group 20 must be the same, and they must follow the symmetrical distribution rule mentioned above. The following example illustrates this with the global signal region being penetrated by a conductive via group 20, and the number of conductive vias in the conductive via group 20 being 4.

[0104] Understandably, the numbering order of the conductive vias in each conductive via group 20 does not constitute any restriction.

[0105] Specifically, the first OR logic circuit 30 can be coupled to the active surface portion of all conductive vias in the same conductive via group 20. That is, for each memory chip 10, all conductive vias in each conductive via group 20 are coupled to their corresponding first OR logic circuit 30, and the first OR logic circuit 30 is coupled to its corresponding first driving circuit 40. The global signal transmitted by the conductive via group 20 will enter the memory chip 10 through the corresponding coupled first OR logic circuit 30 and first driving circuit 40.

[0106] It should be noted that the driving circuit may include an input driving branch (Receive, RX) and / or an output driving branch (Transmit, TX). For example, as shown... Figure 4 As shown, the first driving circuit 40 includes an input driving branch, which sends the global signal output from the corresponding coupled conductive via group 20 to the internal circuit of the memory chip 10.

[0107] It should also be noted that the conductive vias mentioned above can at least be categorized as through-silicon vias (TSVs), specifically a vertical interconnect structure that penetrates a silicon wafer / memory chip, for example... Figure 1 Type 1 in the above; of course, conductive vias can also be used. Figure 1 Type 2 in the diagram, together with the contact structure, enables signal transmission. In other embodiments, other electrical connection structures can also be selected as conductive vias.

[0108] In this embodiment, for the same group of conductive vias 20 of the memory chip 10, each conductive via transmits the exact same signal, that is, a signal of the same type and value, and further transmits it to the internal circuitry of the memory chip 10. Therefore, in this case, each group of conductive vias 20 only requires one first driving circuit 40 to drive the signal. Alternatively, a driving circuit may also be included between the first OR logic circuit 30 and all conductive vias in the group of conductive vias 20 to drive the global signal; this is not specifically limited.

[0109] For the first OR logic circuit 30, see [link to relevant documentation]. Figure 5 This illustrates a schematic diagram of the composition structure of a memory chip provided in an embodiment of this disclosure. For example... Figure 5 As shown, in some embodiments, the first OR logic circuit 30 may include a first OR gate 301, a second OR gate 302, and a third OR gate 303;

[0110] For the i-th first OR logic circuit 30, the first input terminal of the first OR gate 301 is connected to the first conductive via D0 in the i-th conductive via group 20, the second input terminal of the first OR gate 301 is connected to the fourth conductive via D3 in the i-th conductive via group 20, and the output terminal of the first OR gate 301 is connected to the first input terminal of the third OR gate 303; the first input terminal of the second OR gate 302 is connected to the second conductive via D1 in the i-th conductive via group 20, the second input terminal of the second OR gate 302 is connected to the third conductive via D2 in the i-th conductive via group 20, and the output terminal of the second OR gate 302 is connected to the second input terminal of the third OR gate 303; the output terminal of the third OR gate 303 is used to output a global signal.

[0111] Additionally, for example, please see Figure 5 In some embodiments, the DFT pin pads (DFT PAD, or PAD for short) are placed on the second axis BB', so conductive vias cannot be placed there; each conductive via can only be placed symmetrically on both sides of the DFT PAD.

[0112] Furthermore, such as Figure 5 As shown, in some embodiments, each conductive via is connected to a weak ground terminal; the weak ground terminal includes a resistor and a ground terminal.

[0113] If the conductive via is not transmitting a signal or is not properly connected, the ground terminal controls the voltage level of the conductive via to be low. If the conductive via is properly connected and transmitting a signal, the voltage level of the conductive via depends on the transmitted signal.

[0114] It should be noted that the resistor in the weak ground terminal has a relatively large resistance value, but the specific value of this resistance is not limited. Additionally, the weak ground terminal can be represented by a weak pull "0".

[0115] exist Figure 4 Based on this, see Figure 6 It illustrates a schematic diagram of the composition structure of a memory chip provided in an embodiment of this disclosure. Figure 3 .like Figure 6 As shown, in another possibility, the memory chip 10 further includes n second driving circuits 41; the i-th second driving circuit 41 is coupled to all conductive vias in the i-th conductive via group 20. Figure 6 Only one conductive via group 20 and one second drive circuit 41 are shown in the diagram; the rest are omitted.

[0116] The i-th second driving circuit 41 is configured to send the i-th global signal generated inside the memory chip 10 to all conductive vias coupled thereto.

[0117] Specifically, the second driving circuit 41 can be coupled to the active surface portion of each conductive via in the corresponding conductive via group 20. That is, for the memory chip 10, each conductive via in its conductive via group 20 is connected to the same second driving circuit 41, and the global signal is output from inside the memory chip 10 and sent to all the conductive vias coupled to it.

[0118] For example, such as Figure 6 As shown, the second driving circuit 41 includes an output driving branch, which outputs the global signal generated by the internal circuitry of the memory chip 10 to the corresponding coupled conductive via group 20. Specifically, the input driving branches and output driving branches in the other figures will not be labeled further; please refer to the attached figures. Figure 6 To achieve an adaptive understanding.

[0119] In some embodiments, each conductive via in the memory chip 10 can be fabricated by any one or more of the following processes: via-first, via-middle, via-last, and back side via-last, and different conductive vias in the same memory chip 10 are electrically isolated from each other.

[0120] Pre-via technology refers to a via fabrication process where vias are created before the fabrication of devices, such as Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs). Intermediate via technology involves creating vias during the manufacturing process, often after device fabrication but before the fabrication of stacked layers. Back-via technology involves creating vias from the front side of the wafer after the back-end of line (BEOL) process. Rear-side via technology involves creating vias from the back side of the wafer after the BEOL process. In other words, pre-via technology can refer to creating vias first, then fabricating the circuitry, for example... Figure 1 Type 1 conductive vias; intermediate via fabrication can refer to first fabricating the circuit and part of the metal layer, then fabricating the via, and finally fabricating the remaining vias, for example... Figure 1 Type 2 conductive vias; back-through-hole and reverse-through-hole processes can refer to fabricating the circuitry and metal layers first, and then fabricating the vias last, for example... Figure 1 Type 2 conductive via.

[0121] This disclosure provides a memory chip in which the conductive vias have special symmetry, allowing direct application to stacked structures configured in any manner, such as face-to-face, back-to-back, or face-to-back, without requiring two sets of masks or two sets of conductive vias. Furthermore, it eliminates the need for a data selector to select the conductive vias, reducing the number of devices compared to traditional methods. Figure 1 The reduced parasitic capacitance in the memory chip not only saves circuit area but also reduces chip manufacturing costs; subsequently, when the memory chip 10 is formed into a stacked structure, it can also be compared to... Figure 2A and Figure 2B The memory chip reduces parasitic resistance (see subsequent explanation for details). Furthermore, the structure of transmitting global signals through a 4-quadrant symmetrical via group (i.e., the via group is symmetrical about both the first and second axes) ensures that memory chips in different flip-to-position positions can receive the same global signal output by the logic chip. Simultaneously, the four transmission paths formed by the four vias in the via group constitute a 4-dummy structure, guaranteeing signal transmission accuracy and saving the area of ​​redundant repair circuitry and the testing time for the via transmission paths.

[0122] In another embodiment of this disclosure, see Figure 7 This illustrates a schematic diagram of an active surface in a logic chip provided by an embodiment of this disclosure. For example... Figure 7As shown, the center point of the active surface of the logic chip 50 and its adjacent signal area are defined as the global signal region 11. The center point of the global signal region 11 coincides with the center point of the active surface, and channel signal regions are distributed on both sides of the global signal region 11.

[0123] Both the global signal region 11 and the channel signal region are traversed by numerous conductive vias along a third direction, and this third direction is perpendicular to the active surface. Furthermore, since the PADs in the logic chip 50 are generally located in the center of the chip, the conductive vias for global signals such as DFT are preferably located in a narrower region in the center of the chip, i.e., as shown below. Figure 7 The location of the global signal region 11 shown.

[0124] In addition, the areas of logic chip 50 and memory chip 10 may be the same or different, and no specific limitation is made. However, the global signal regions of both are located in the middle of their respective chips, and the areas of the two global signal regions are the same.

[0125] Please see Figure 7 For the active surface of logic chip 50, there exists a first axis AA' and a second axis BB'. The first axis AA' and the second axis BB' are perpendicular to each other and intersect at the center point of the active surface. The first axis AA' is parallel to the first side of logic chip 50, and the second axis BB' is parallel to the second side of logic chip 50. Figure 7 In this example, the first axis AA' extends along the first direction, and the second axis BB' extends along the second direction, but this is only an example and does not constitute a specific limitation.

[0126] See Figure 8 It illustrates a schematic diagram of the composition structure of a logic chip provided in an embodiment of this disclosure. Figure 1 .like Figure 8 As shown, in logic chip 50, the global signal region is divided by n conductive vias 60 ( Figure 8 Only one conductive via group 60 is shown in the figure, and the rest are omitted. All conductive vias in the same conductive via group 60 are used to transmit the same global signal; n is a positive integer; each conductive via group 60 includes a first conductive via D0, a second conductive via D1, a third conductive via D2 and a fourth conductive via D3.

[0127] In particular, Figure 8 This can be viewed as a cross-sectional view of logic chip 50 along its active surface. Please refer to [reference needed]. Figure 8 For the same group of conductive vias 60, the first conductive via D0 and the second conductive via D1 are symmetrical about the first axis AA', the third conductive via D2 and the fourth conductive via D3 are symmetrical about the first axis AA', and the first conductive via D0 and the fourth conductive via D3 are symmetrical about the second axis BB'.

[0128] It should be noted that the positions of the conductive via groups 60 in the global signal region vary. Specifically, the number and position of the conductive via groups 60 can be adjusted according to the actual situation and are not limited thereto. However, the number of conductive vias in each conductive via group 60 must be the same, and they must follow the symmetrical distribution rule mentioned above. The following example illustrates this with the global signal region being penetrated by a conductive via group 60, and the number of conductive vias in the conductive via group 60 being 4.

[0129] Understandably, the numbering order of the conductive vias in each conductive via group 60 does not constitute any restriction.

[0130] like Figure 8 As shown, in one possibility, the logic chip 50 also includes n third driving circuits 70. Figure 8 Only one third drive circuit 70 is shown in the diagram; the rest are omitted.

[0131] The i-th third driving circuit 70 is coupled to all conductive vias in the i-th conductive via group 60; i is a positive integer less than or equal to n;

[0132] The i-th third driving circuit 70 is configured to send the i-th global signal generated inside the logic chip 50 to all conductive vias coupled to it.

[0133] Understandably, the i-th third driving circuit 70 is configured to send the i-th global signal generated inside the logic chip 50 to all conductive vias in the i-th conductive via group.

[0134] Here, each of the n third driving circuits 70 corresponds to one of the n conductive via groups 60.

[0135] Specifically, the third driving circuit 70 can be coupled to the active surface portion of each conductive via in the corresponding conductive via group 60. That is, for the logic chip 50, each conductive via in its conductive via group 60 is connected to the same third driving circuit 70, and the global signal is output from inside the logic chip 50 and sent to all the conductive vias coupled to it.

[0136] like Figure 8 As shown, the third driving circuit 70 includes an output driving branch that outputs the global signal generated by the internal circuit of the logic chip 50 to the corresponding coupled conductive via group 60.

[0137] It should be noted that, in this embodiment, for the same group of conductive vias 60 of the logic chip 50, each conductive via transmits the exact same signal, that is, a signal of the same type and value, and will further transmit it to different memory chips 10. Therefore, in this case, each group of conductive vias 60 only needs one third driving circuit 70 to drive the signal.

[0138] exist Figure 8 Based on this, see Figure 9 This illustrates a schematic diagram of the composition structure of a logic chip provided in an embodiment of this disclosure. For example... Figure 9 As shown, in another possibility, the logic chip 50 may also include n second OR logic circuits 71 and n fourth drive circuits 72. Figure 9 Only one second OR logic circuit 71 and one fourth driving circuit 72 are shown in the figure, and the rest are omitted; the input terminal of the i-th second OR logic circuit 71 is coupled to all the conductive vias in the i-th conductive via group 60, and the output terminal of the i-th second OR logic circuit 71 is coupled to the i-th fourth driving circuit 72.

[0139] The i-th fourth driving circuit 72 is configured to receive the i-th global signal from the i-th conductive via group 60 via the i-th second OR logic circuit 71, and send the i-th global signal to the internal circuit of logic chip 50.

[0140] It should be noted that each of the n second OR logic circuits 71 and the n fourth driving circuits 72 corresponds one-to-one with each of the n conductive via groups 60.

[0141] Specifically, the second OR logic circuit 71 can be coupled to the active surface portion of all conductive vias in the same conductive via group 60. That is, for the logic chip 50, all conductive vias in each conductive via group 60 are coupled to their corresponding second OR logic circuit 71, and the second OR logic circuit 71 is coupled to its corresponding fourth driving circuit 72. The global signal transmitted by the conductive via group 60 will enter the logic chip 50 through the correspondingly coupled second OR logic circuit 71 and fourth driving circuit 72.

[0142] like Figure 9 As shown, the fourth driving circuit 72 includes an input driving branch that sends the global signal output from the corresponding coupled conductive via group 60 to the internal circuitry of the logic chip 50. Alternatively, a driving circuit may also be included between the second OR logic circuit 71 and all conductive vias in the conductive via group 60 to drive the global signal; this is not specifically limited.

[0143] For the second OR logic circuit 71, see [link to relevant documentation]. Figure 10It illustrates a schematic diagram of the composition structure of a logic chip provided in an embodiment of this disclosure. Figure 3 .like Figure 10 As shown, in some embodiments, the second OR logic circuit 71 may include a fourth OR gate 711, a fifth OR gate 712, and a sixth OR gate 713;

[0144] For the i-th second OR logic circuit 71, the first input terminal of the fourth OR gate 711 is connected to the first conductive via D0 in the i-th conductive via group 60, the second input terminal of the fourth OR gate 711 is connected to the fourth conductive via D3 in the i-th conductive via group 60, and the output terminal of the fourth OR gate 711 is connected to the first input terminal of the sixth OR gate 713; the first input terminal of the fifth OR gate 712 is connected to the second conductive via D1 in the i-th conductive via group 60, the second input terminal of the fifth OR gate 712 is connected to the third conductive via D2 in the i-th conductive via group 60, and the output terminal of the fifth OR gate 712 is connected to the second input terminal of the sixth OR gate 713; the output terminal of the sixth OR gate 713 is used to output a global signal.

[0145] Furthermore, such as Figure 10 As shown, in some embodiments, each conductive via is connected to a weak ground terminal; the weak ground terminal includes a resistor and a ground terminal.

[0146] If the conductive via is not transmitting a signal or is not properly connected, the ground terminal controls the voltage level of the conductive via to be low. If the conductive via is properly connected and transmitting a signal, the voltage level of the conductive via depends on the transmitted signal.

[0147] In this embodiment of the disclosure, when the global signal is transmitted from the memory chip 10 to the logic chip 50, since each conductive via in the logic chip 50 is connected to the weak ground terminal, that is, the default level value of each conductive via is 0, as long as one of the signal transmission channels formed by the four conductive vias can transmit signal data normally, even if some of the conductive vias are disconnected (open), it will not affect the final signal reception, that is, a 4-dummy signal transmission architecture is formed.

[0148] It should be noted that when multiple memory chips send global signals to logic chip 50, memory chip 0 (i.e., the first memory chip 11 in the chip stack structure 80 below) and memory chip 3 (i.e., the fourth memory chip 14 in the chip stack structure 80 below) may pass through the same conductive via. In this case, in order to distinguish which conductive via the global signal was sent from, logic chip 50 can use the following mechanism to determine: if logic chip 50 needs to receive a global signal from a certain memory chip, logic chip 50 will first send an enable signal, for example, send an enable signal to the first memory chip 11, and then the global signal received from the first conductive via D0 or the fourth conductive via D3 will know that it was sent by the first memory chip 11; send an enable signal to the fourth memory chip 14, and then the global signal received from the first conductive via D0 or the fourth conductive via D3 will know that it was sent by the fourth memory chip 14, but this is not specifically limited. In addition, when multiple memory chips transmit global signals to logic chip 50, only one of the output drive branches included in the first drive circuit 40 of all memory chips is enabled at the same time. That is, only one memory chip transmits global signals to logic chip 50 at the same time.

[0149] It should be noted that in some embodiments, global signals can be transmitted bidirectionally, that is, they can be transmitted from logic chip 50 to memory chip 10, or from memory chip 10 to logic chip 50. For example, the CP_DQ signal is a signal that characterizes whether the chip test result is successful (pass) or failed (fail), but this is not specifically limited.

[0150] In some embodiments, each conductive via in the logic chip 50 can be fabricated by any one or more of the following processes: via-first, via-middle, via-last, and back side via-last, and different conductive vias in the same logic chip 50 are electrically isolated from each other.

[0151] This disclosure provides a logic chip, in which the conductive vias are arranged in the same positions as those in the aforementioned memory chip. For details not disclosed in this disclosure, please refer to the description of the foregoing embodiments for clarification.

[0152] In another embodiment of this disclosure, see [reference needed]. Figure 11 This illustrates a schematic diagram of the composition of a chip stacking structure provided in an embodiment of this disclosure. For example... Figure 11 As shown, the chip stacking structure 80 includes a logic chip 50 and at least one stacking unit ( Figure 11Only two stacking units are shown (the rest are omitted), and the logic chip 50 and at least one stacking unit are stacked sequentially along a third direction; each stacking unit includes a first memory chip 11, a second memory chip 12, a third memory chip 13, and a fourth memory chip 14 stacked sequentially along a third direction, the third direction being perpendicular to the top surface of each memory chip; the structure of the first memory chip 11, the second memory chip 12, the third memory chip 13, and the fourth memory chip 14 is the same as the aforementioned memory chip 10, and the structure of the logic chip 50 is the same as the aforementioned logic chip 50. Specifically, in Figure 11 The portion shown is only the global signal region 11 of each chip, not the entire active surface.

[0153] For each stacking unit, the first memory chip 11 and the second memory chip 12 are stacked face to face, the second memory chip 12 and the third memory chip 13 are stacked back to back, and the third memory chip 13 and the fourth memory chip 14 are stacked face to face; the first memory chip 11 and the logic chip 50 in the first stacking unit are stacked back to face, or the first memory chip 11 and the logic chip 50 in the first stacking unit are stacked back to back.

[0154] In this embodiment of the disclosure, face-to-face stacking means that the top surfaces of two chips are approximately aligned along a third direction, and the center points of the two chips, the first axis AA' and the second axis BB' of the top surfaces are also aligned along a third direction; back-to-back stacking means that the bottom surfaces of two chips are approximately aligned along a third direction; face-to-back stacking means that the top surface of one chip is approximately aligned with the bottom surface of another chip along a third direction. Unless otherwise specified, "chip" can refer to either a logic chip or a memory chip.

[0155] n conductive via groups in logic chip 50 ( Figure 11 Only one conductive via group is shown in the figure, and the rest are omitted. It corresponds one-to-one with the n conductive via groups in each first memory chip 11, each second memory chip 12, each third memory chip 13, and each fourth memory chip 14 and is aligned along the third direction, where n is a positive integer.

[0156] It should also be noted that due to process errors, "alignment" in this article is not absolute alignment; deviations within a reasonable range can be considered as alignment.

[0157] In this embodiment, the chip stack structure 80 can specifically be a high-bandwidth memory (HBM) stack product. Particularly, it relates to the repair pattern design of multiple (multidrop) conductive vias in the global signal region of each chip, where each chip is symmetrical in four quadrants (i.e., the via group is symmetrical about both the first and second axes). This utilizes the face-to-face and back-to-back symmetry between the multiple conductive vias and the chips to facilitate signal transmission through the multiple conductive vias, such as command signals and address signals. No specific limitations are imposed on this. Here, the memory chip can be represented as a core die, and the logic chip as a base die.

[0158] It should be noted that, in one possibility, for two chips connected face-to-face, the bonding surfaces (the positions where the conductive vias are aligned along the third direction) are electrically connected using a hybrid bonding process (also known as bonding pillars); for two chips connected back-to-back or back-to-face, the bonding surfaces (the positions where the conductive vias are aligned along the third direction) are electrically connected using a conductive bump bonding process (also known as microbumps).

[0159] In another possibility, for two chips connected face-to-face, or for two chips connected back-to-back, or for two chips connected back-to-face, the bonding surfaces (positions where the conductive vias are aligned along a third direction) of both are electrically connected using a hybrid bonding process.

[0160] In another possibility, for two chips connected face-to-face, or for two chips connected back-to-back, or for two chips connected back-to-face, the bonding surfaces (positions where the conductive vias are aligned along a third direction) of both are electrically connected through a conductive bump bonding process.

[0161] Here, the above chip can refer to either logic chip 50 or memory chip 10.

[0162] It should be noted that compared to conductive bump bonding, face-to-face bonding using hybrid bonding technology allows for a tighter fit between adjacent memory chips, virtually eliminating gaps. This significantly reduces the height of the chip stack structure, which is one of the advantages of face-to-face stacking. Of course, two memory chips connected back-to-back can also be electrically connected using hybrid bonding, but its connection performance is weaker than that achieved through conductive bump bonding. Thus, in this embodiment, the chip stack structure supports face-to-face stacking, resulting in better performance.

[0163] exist Figure 11Based on this, see Figure 12 It illustrates a signal transmission diagram of a chip stacking structure provided in an embodiment of this disclosure. Figure 1 . Figure 12 The signal transmission path is illustrated using only one conductive via group and two stacked units (i.e., eight memory chips). However, in reality, chip stacking structures can have three, four, or more stacked units, and each stacked unit has similar signal transmission characteristics. The signal transmission situations of other stacked units are not shown here; please refer to the following text and... Figure 12 To achieve an adaptive understanding.

[0164] Specifically, Figure 12 This is a vertical cross-sectional view of logic chip 50 and first memory chip 11, second memory chip 12, third memory chip 13, fourth memory chip 14..., which shows how global signals are transmitted from logic chip 50 to each memory chip.

[0165] It should be noted that, Figure 12 In this context, "OR" represents the individual OR gates in the first OR logic circuit. Additionally, Figure 12 It is used to emphasize the alignment relationship between signal areas and conductive vias along a third direction, but does not represent its actual structure; that is, the diagonal stripe bars may not correspond to any physical structure; or, in some working scenarios, Figure 12 The diagonal stripe pillars between the chips can be understood as conductive bumps, hybrid bonding structures, etc., to achieve the connection of conductive vias between different memory chips.

[0166] It should also be noted that because each conductive via in each memory chip is connected to a weak ground terminal, that is, the default voltage level of each conductive via is 0, as long as one of the signal transmission channels formed by the four conductive vias can transmit signal data normally, even if some of the conductive vias are disconnected (open), it will not affect the final signal reception, thus forming a 4-dummy signal transmission architecture.

[0167] In some embodiments, the global signal region in each chip is penetrated by n conductive via groups. Each conductive via group includes a first conductive via D0, a second conductive via D1, a third conductive via D2, and a fourth conductive via D3. The first conductive via D0 and the second conductive via D1 are symmetrical about a first axis AA', the third conductive via D2 and the fourth conductive via D3 are symmetrical about the first axis AA', and the first conductive via D0 and the fourth conductive via D3 are symmetrical about a second axis BB'. The first axis AA' and the second axis BB' are perpendicular to each other and intersect at the center point of the active surface. The first axis AA' is parallel to the first side of the memory chip, and the second axis BB' is parallel to the second side of the memory chip.

[0168] The first axis AA' of logic chip 50 and each memory chip are aligned along a third direction, and the second axis BB' of logic chip 50 and each memory chip are aligned along a third direction.

[0169] It should be understood that logic chip 50 or each memory chip can be divided into a high-order transmission area and a low-order transmission area, and the subsequent... Figures 13A to 16B The arrows are uniformly located in the high-order transmission area of ​​the chip. Specifically, in this embodiment, the high-order transmission area and the low-order transmission area merely distinguish two areas of the logic chip 50 or each memory chip, and do not have any additional restrictions. They may not be directly related to the high-order and low-order data commonly referred to in data transmission. Furthermore, Figures 11 to 17 This example illustrates only one group of conductive vias within the global signal region. However, there are actually multiple groups of conductive vias in the global signal region, and different groups of conductive vias have similar alignment characteristics. The alignment of other conductive vias is not shown here; please refer to the following text description. Figures 11 to 17 To achieve an adaptive understanding.

[0170] It should be noted that the top surface of the logic chip 50 or each memory chip is divided into 2×2 signal regions, namely the first signal region, the second signal region, the third signal region, and the fourth signal region, denoted by C, D, E, and F. Among them, the first signal region (C) and the second signal region (D) are symmetrical along their own first axis AA', the first signal region (C) and the fourth signal region (F) are symmetrical along their own second axis BB', and the third signal region (E) and the fourth signal region (F) are symmetrical along their own first axis AA'. The first axis AA' of the logic chip 50 and each memory chip are aligned along a third direction, and the second axis BB' of the logic chip 50 and each memory chip are aligned along a third direction.

[0171] It should be noted that the first conductive via D0 in each conductive via group is located in the first signal region (C), the second conductive via D1 in each conductive via group is located in the second signal region (D), the third conductive via D2 in each conductive via group is located in the third signal region (E), and the fourth conductive via D3 in each conductive via group is located in the fourth signal region (F).

[0172] When the logic chip 50 and the first memory chip 11 are stacked back-to-back and the logic chip 50 and the fourth memory chip 14 are arranged in the same way, a first specific implementation method and a second specific implementation method are provided; when the logic chip 50 and the first memory chip 11 are stacked back-to-back and the logic chip 50 and the second memory chip 12 are arranged in the same way, a third specific implementation method and a fourth specific implementation method are provided, as detailed below.

[0173] In the first specific embodiment, such as Figure 13A As shown, assuming that the logic chip 50 and each memory chip's respective first axis AA' divides the chip into a high-order transmission region and a low-order transmission region (i.e., the first axis AA' extends along the first direction), the high-order transmission region of the logic chip 50, the high-order transmission region of the first memory chip 11, the low-order transmission region of the second memory chip 12, the low-order transmission region of the third memory chip 13, and the high-order transmission region of the fourth memory chip 14 are aligned along the third direction; the low-order transmission region of the logic chip 50, the low-order transmission region of the first memory chip 11, the high-order transmission region of the second memory chip 12, the high-order transmission region of the third memory chip 13, and the low-order transmission region of the fourth memory chip 14 are aligned along the third direction.

[0174] In the second specific embodiment, such as Figure 14A As shown, assuming that the second axis BB' of each logic chip 50 and each memory chip divides the chip into a high-order transmission region and a low-order transmission region (i.e., the second axis BB' extends along the first direction), the high-order transmission region of the logic chip 50, the low-order transmission region of the first memory chip 11, the low-order transmission region of the second memory chip 12, the high-order transmission region of the third memory chip 13, and the high-order transmission region of the fourth memory chip 14 are aligned along the third direction; the low-order transmission region of the logic chip 50, the high-order transmission region of the first memory chip 11, the high-order transmission region of the second memory chip 12, the low-order transmission region of the third memory chip 13, and the low-order transmission region of the fourth memory chip 14 are aligned along the third direction.

[0175] Please see Figure 13A or Figure 14A For the first and second specific embodiments, each signal region has the following alignment relationship:

[0176] (1) The fourth signal area (F) of the logic chip 50, the first signal area (C) of the first memory chip 11, the second signal area (D) of the second memory chip 12, the third signal area (E) of the third memory chip 13, and the fourth signal area (F) of the fourth memory chip 14 are aligned along the third direction.

[0177] (2) The third signal area (E) of the logic chip 50, the second signal area (D) of the first memory chip 11, the first signal area (C) of the second memory chip 12, the fourth signal area (F) of the third memory chip 13, and the third signal area (E) of the fourth memory chip 14 are aligned along the third direction.

[0178] (3) The second signal area (D) of the logic chip 50, the third signal area (E) of the first memory chip 11, the fourth signal area (F) of the second memory chip 12, the first signal area (C) of the third memory chip 13, and the second signal area (D) of the fourth memory chip 14 are aligned along the third direction;

[0179] (4) The first signal area (C) of the logic chip 50, the fourth signal area (F) of the first memory chip 11, the third signal area (E) of the second memory chip 12, the second signal area (D) of the third memory chip 13, and the first signal area (C) of the fourth memory chip 14 are aligned along the third direction.

[0180] It should also be noted that each conductive via group of the logic chip 50 and each memory chip includes a first conductive via D0, a second conductive via D1, a third conductive via D2 and a fourth conductive via D3 arranged in a 2×2 array.

[0181] Please see Figure 13B or Figure 14B For the first and second specific embodiments, only for multiple signal regions aligned along a third direction, each conductive via has the following alignment relationship:

[0182] (1) The fourth conductive via D3 in the i-th conductive via group of logic chip 50, the first conductive via D0 in the i-th conductive via group of each first memory chip 11, the second conductive via D1 in the i-th conductive via group of each second memory chip 12, the third conductive via D2 in the i-th conductive via group of each third memory chip 13, and the fourth conductive via D3 in the i-th conductive via group of each fourth memory chip 14 are aligned along the third direction and form a signal transmission channel;

[0183] (2) The third conductive via D2 in the i-th conductive via group of logic chip 50, the second conductive via D1 in the i-th conductive via group of each first memory chip 11, the first conductive via D0 in the i-th conductive via group of each second memory chip 12, the fourth conductive via D3 in the i-th conductive via group of each third memory chip 13, and the third conductive via D2 in the i-th conductive via group of each fourth memory chip 14 are aligned along the third direction and form a signal transmission channel;

[0184] (3) The second conductive via D1 in the i-th conductive via group of logic chip 50, the third conductive via D2 in the i-th conductive via group of each first memory chip 11, the fourth conductive via D3 in the i-th conductive via group of each second memory chip 12, the first conductive via D0 in the i-th conductive via group of each third memory chip 13, and the second conductive via D1 in the i-th conductive via group of each fourth memory chip 14 are aligned along the third direction and form a signal transmission channel;

[0185] (4) The first conductive via D0 in the i-th conductive via group of logic chip 50, the fourth conductive via D3 in the i-th conductive via group of each first memory chip 11, the third conductive via D2 in the i-th conductive via group of each second memory chip 12, the second conductive via D1 in the i-th conductive via group of each third memory chip 13, and the first conductive via D0 in the i-th conductive via group of each fourth memory chip 14 are aligned along the third direction and form a signal transmission channel.

[0186] It should be noted that i is a positive integer less than or equal to n.

[0187] In the third specific embodiment, such as Figure 15A As shown, assuming that the logic chip 50 and each memory chip's respective first axis AA' divides the chip into a high-order transmission region and a low-order transmission region (i.e., the first axis AA' extends along the first direction), the low-order transmission region of the logic chip 50, the high-order transmission region of the first memory chip 11, the low-order transmission region of the second memory chip 12, the low-order transmission region of the third memory chip 13, and the high-order transmission region of the fourth memory chip 14 are aligned along the third direction; the high-order transmission region of the logic chip 50, the low-order transmission region of the first memory chip 11, the high-order transmission region of the second memory chip 12, the high-order transmission region of the third memory chip 13, and the low-order transmission region of the fourth memory chip 14 are aligned along the third direction.

[0188] In the fourth specific embodiment, such as Figure 16A As shown, assuming that the second axis BB' of each logic chip 50 and each memory chip divides the chip into a high-order transmission region and a low-order transmission region (i.e., the second axis BB' extends along the first direction), the low-order transmission region of logic chip 50, the low-order transmission region of the first memory chip 11, the low-order transmission region of the second memory chip 12, the high-order transmission region of the third memory chip 13, and the high-order transmission region of the fourth memory chip 14 are aligned along the third direction; the high-order transmission region of logic chip 50, the high-order transmission region of the first memory chip 11, the high-order transmission region of the second memory chip 12, the low-order transmission region of the third memory chip 13, and the low-order transmission region of the fourth memory chip 14 are aligned along the third direction.

[0189] Please see Figure 15A or Figure 16A For the third and fourth specific embodiments, each signal region has the following alignment relationship:

[0190] (1) The second signal area (D) of the logic chip 50, the first signal area (C) of the first memory chip 11, the second signal area (D) of the second memory chip 12, the third signal area (E) of the third memory chip 13, and the fourth signal area (F) of the fourth memory chip 14 are aligned along the third direction;

[0191] (2) The first signal area (C) of the logic chip 50, the second signal area (D) of the first memory chip 11, the first signal area (C) of the second memory chip 12, the fourth signal area (F) of the third memory chip 13, and the third signal area (E) of the fourth memory chip 14 are aligned along the third direction;

[0192] (3) The fourth signal area (F) of the logic chip 50, the third signal area (E) of the first memory chip 11, the fourth signal area (F) of the second memory chip 12, the first signal area (C) of the third memory chip 13, and the second signal area (D) of the fourth memory chip 14 are aligned along the third direction.

[0193] (4) The third signal area (E) of the logic chip 50, the fourth signal area (F) of the first memory chip 11, the third signal area (E) of the second memory chip 12, the second signal area (D) of the third memory chip 13, and the first signal area (C) of the fourth memory chip 14 are aligned along the third direction.

[0194] Please see Figure 15B or Figure 16B For the third and fourth specific embodiments, only for multiple signal regions aligned along a third direction, each conductive via has the following alignment relationship:

[0195] (1) The second conductive via D1 in the i-th conductive via group of logic chip 50, the first conductive via D0 in the i-th conductive via group of each first memory chip 11, the second conductive via D1 in the i-th conductive via group of each second memory chip 12, the third conductive via D2 in the i-th conductive via group of each third memory chip 13, and the fourth conductive via D3 in the i-th conductive via group of each fourth memory chip 14 are aligned along the third direction and form a signal transmission channel;

[0196] (2) The first conductive via D0 in the i-th conductive via group of logic chip 50, the second conductive via D1 in the i-th conductive via group of each first memory chip 11, the first conductive via D0 in the i-th conductive via group of each second memory chip 12, the fourth conductive via D3 in the i-th conductive via group of each third memory chip 13, and the third conductive via D2 in the i-th conductive via group of each fourth memory chip 14 are aligned along the third direction and form a signal transmission channel;

[0197] (3) The fourth conductive via D3 in the i-th conductive via group of logic chip 50, the third conductive via D2 in the i-th conductive via group of each first memory chip 11, the fourth conductive via D3 in the i-th conductive via group of each second memory chip 12, the first conductive via D0 in the i-th conductive via group of each third memory chip 13, and the second conductive via D1 in the i-th conductive via group of each fourth memory chip 14 are aligned along the third direction and form a signal transmission channel;

[0198] (4) The third conductive via D2 in the i-th conductive via group of logic chip 50, the fourth conductive via D3 in the i-th conductive via group of each first memory chip 11, the third conductive via D2 in the i-th conductive via group of each second memory chip 12, the second conductive via D1 in the i-th conductive via group of each third memory chip 13, and the first conductive via D0 in the i-th conductive via group of each fourth memory chip 14 are aligned along the third direction and form a signal transmission channel.

[0199] In some embodiments, see Figure 17 This illustrates a second schematic diagram of signal transmission in a chip stacking structure provided in an embodiment of this disclosure. Specifically, Figure 17 It is aimed at Figures 13A to 14B The chip stacking structure shown is illustrated. Additionally, Figure 17 This is only an abstract circuit schematic. The first OR logic circuit 30 and the third driving circuit 70 are coupled to all conductive vias in their corresponding conductive via groups, and the first OR logic circuit 30 is coupled to its corresponding first driving circuit 40. Please refer to the text description for an adaptive understanding.

[0200] Please refer to the following: Figure 17For the chip stack structure 80, the bottom-up signal transmission path will be similar to the following: the fourth conductive via D3 in the logic chip 50 — the first conductive via D0 in the first memory chip 11 — the second conductive via D1 in the second memory chip 12 — the third conductive via D2 in the third memory chip 13 — the fourth conductive via D3 in the fourth memory chip 14… and so on. Other signals are transmitted similarly. That is to say, from a physical perspective, the conductive vias in the chip stack structure 80 are still in a direct-connect configuration. However, from the perspective of the absolute position of the conductive vias on the active surface, the conductive vias can also be considered as a functionally rotating configuration, that is, achieving a similar… Figure 2B The signal transmission effect (i.e., the rotational transmission effect of conductive via D0-conductive via D1-conductive via D2-conductive via D3...). Simply put, Figure 2B The chip stacking structure in the present invention requires a physical spiral structure, which necessarily contains lateral interconnection structures. However, the chip stacking structure 80 in this embodiment is physically a direct connection structure, which does not require lateral interconnection structures. This significantly reduces parasitic resistance and greatly improves transmission speed and transmission performance.

[0201] As can be seen from the above, the memory chip provided in this embodiment not only reduces the number of driving circuits and data selectors, thereby reducing parasitic capacitance; in addition, the chip stack structure formed by the memory chip achieves signal rotation transmission through the direct connection configuration of conductive vias, further reducing parasitic resistance. Furthermore, although one connection point on the logic chip corresponds to four different connection points for the first, second, third, and fourth memory chips, all conductive vias in the same conductive via group transmit the same global signal. This ensures that memory chips flipped to different positions can receive the same global signal output by the logic chip through four signal transmission channels. In other words, all conductive vias in the same conductive via group transmit the same global signal, meaning the multiple signal transmission channels are redundant. Even if some conductive vias are defective, causing some signal transmission channels to fail to transmit the global signal normally, the other redundant signal transmission channels can still ensure that all memory chips receive the correct global signal, achieving a repair effect. Moreover, this conductive via configuration allows for multi-point connection of the global signal with a minimal number of conductive vias, reducing the occupied area of ​​the global signal region and further reducing the area of ​​the memory chip.

[0202] In another embodiment of this disclosure, see Figure 18 This illustration shows a schematic diagram of the composition structure of a memory provided in an embodiment of this disclosure. For example... Figure 18 As shown, the memory 90 includes the chip stacking structure 80 described in the foregoing embodiments.

[0203] In some embodiments, the chip stack structure 80 can be applied to the memory 90. The memory 90 can be, for example, Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate SDRAM (DDR SDRAM), etc., and is not specifically limited to any particular type.

[0204] In this embodiment of the disclosure, the chip area of ​​the memory 90 can be reduced, thereby reducing the chip manufacturing cost.

[0205] For details not disclosed in the embodiments of this disclosure, please refer to the description of the foregoing embodiments for understanding.

[0206] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure.

[0207] It should be noted that, in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0208] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0209] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0210] The features disclosed in the several product embodiments provided in this disclosure can be combined arbitrarily without conflict to obtain new product embodiments.

[0211] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0212] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A memory chip, characterized in that, The center point of the active surface of the memory chip and its adjacent area are defined as the global signal region, and the center point of the global signal region coincides with the center point of the active surface; the global signal region is penetrated by n conductive via groups, and all conductive vias in the same conductive via group are used to transmit the same global signal; n is a positive integer; The memory chip further includes n first OR logic circuits and n first driving circuits; the input terminal of the i-th first OR logic circuit is coupled to all the conductive vias in the i-th conductive via group, and the output terminal of the i-th first OR logic circuit is coupled to the i-th first driving circuit; i is a positive integer less than or equal to n; The i-th first driving circuit is configured to receive the i-th global signal from the i-th conductive via group via the i-th first OR logic circuit, and send the i-th global signal to the internal circuit of the memory chip; Each of the conductive via groups includes a first conductive via, a second conductive via, a third conductive via, and a fourth conductive via. The first and second conductive vias are symmetrical about a first axis, the third and fourth conductive vias are symmetrical about the first axis, and the first and fourth conductive vias are symmetrical about a second axis. The first axis and the second axis are perpendicular to each other and intersect at the center point of the active surface. The first axis is parallel to the first side of the memory chip, and the second axis is parallel to the second side of the memory chip.

2. The memory chip according to claim 1, characterized in that, The first OR logic circuit includes a first OR gate, a second OR gate, and a third OR gate; For the i-th first OR logic circuit, the first input terminal of the first OR gate is connected to the first conductive via in the i-th conductive via group, the second input terminal of the first OR gate is connected to the fourth conductive via in the i-th conductive via group, and the output terminal of the first OR gate is connected to the first input terminal of the third OR gate; the first input terminal of the second OR gate is connected to the second conductive via in the i-th conductive via group, the second input terminal of the second OR gate is connected to the third conductive via in the i-th conductive via group, and the output terminal of the second OR gate is connected to the second input terminal of the third OR gate; the output terminal of the third OR gate is used to output the global signal.

3. The memory chip according to claim 1, characterized in that, Each of the aforementioned conductive vias is connected to a weak ground terminal; the weak ground terminal includes a resistor and a ground terminal. If the conductive via is not transmitting a signal or is not properly connected, the ground terminal controls the voltage level of the conductive via to be low; if the conductive via is properly connected and transmitting a signal, the voltage level of the conductive via depends on the transmitted signal.

4. The memory chip according to claim 1, characterized in that, The memory chip further includes n second driving circuits; the i-th second driving circuit is coupled to all the conductive vias in the i-th conductive via group; The i-th second driving circuit is configured to send the i-th global signal generated inside the memory chip to all the conductive vias coupled thereto.

5. The memory chip according to claim 1, characterized in that, The conductive vias are fabricated using any one or more of the following processes: via-first, via-middle, via-last, and back side via-last. Different conductive vias in the same memory chip are electrically isolated from each other.

6. A logic chip, characterized in that, The center point of the active surface of the logic chip and its adjacent area are defined as the global signal region, and the center point of the global signal region coincides with the center point of the active surface; the global signal region is penetrated by n conductive via groups, and all conductive vias in the same conductive via group are used to transmit the same global signal; n is a positive integer; Each of the aforementioned conductive via groups includes a first conductive via, a second conductive via, a third conductive via, and a fourth conductive via. The first conductive via and the second conductive via are symmetrical about a first axis, the third conductive via and the fourth conductive via are symmetrical about the first axis, and the first conductive via and the fourth conductive via are symmetrical about a second axis. The first axis and the second axis are perpendicular to each other and intersect at the center point of the active surface. The first axis is parallel to the first side of the logic chip, and the second axis is parallel to the second side of the logic chip.

7. The logic chip according to claim 6, characterized in that, The logic chip also includes n third driving circuits; The i-th third driving circuit is coupled to all the conductive vias in the i-th conductive via group; i is a positive integer less than or equal to n; The i-th third driving circuit is configured to send the i-th global signal generated inside the logic chip to all the conductive vias coupled thereto.

8. The logic chip according to claim 6, characterized in that, The logic chip further includes n second OR logic circuits and n fourth driving circuits; the input terminal of the i-th second OR logic circuit is coupled to all the conductive vias in the i-th conductive via group, and the output terminal of the i-th second OR logic circuit is coupled to the i-th fourth driving circuit. The i-th fourth driving circuit is configured to receive the i-th global signal from the i-th conductive via group via the i-th second OR logic circuit, and send the i-th global signal to the internal circuit of the logic chip.

9. The logic chip according to claim 8, characterized in that, The second OR logic circuit includes a fourth OR gate, a fifth OR gate, and a sixth OR gate; For the i-th second OR logic circuit, the first input terminal of the fourth OR gate is connected to the first conductive via in the i-th conductive via group, the second input terminal of the fourth OR gate is connected to the fourth conductive via in the i-th conductive via group, and the output terminal of the fourth OR gate is connected to the first input terminal of the sixth OR gate; the first input terminal of the fifth OR gate is connected to the second conductive via in the i-th conductive via group, the second input terminal of the fifth OR gate is connected to the third conductive via in the i-th conductive via group, and the output terminal of the fifth OR gate is connected to the second input terminal of the sixth OR gate; the output terminal of the sixth OR gate is used to output the global signal.

10. The logic chip according to claim 6, characterized in that, Each of the aforementioned conductive vias is connected to a weak ground terminal; the weak ground terminal includes a resistor and a ground terminal. If the conductive via is not transmitting a signal or is not properly connected, the ground terminal controls the voltage level of the conductive via to be low; if the conductive via is properly connected and transmitting a signal, the voltage level of the conductive via depends on the transmitted signal.

11. The logic chip according to claim 6, characterized in that, The conductive vias are fabricated using any one or more of the following processes: via-first, via-middle, via-last, and back side via-last. Different conductive vias in the same logic chip are electrically isolated from each other.

12. A chip stacking structure, characterized in that, The chip stacking structure includes a logic chip as described in any one of claims 6-11 and at least one stacking unit, wherein the logic chip and at least one stacking unit are stacked sequentially along a third direction; each stacking unit includes a first memory chip, a second memory chip, a third memory chip, and a fourth memory chip stacked sequentially along the third direction, wherein the third direction is perpendicular to the top surface of each memory chip; The first memory chip, the second memory chip, the third memory chip, and the fourth memory chip are all memory chips as described in any one of claims 1-5; The first memory chip and the second memory chip are stacked face-to-face, the second memory chip and the third memory chip are stacked back-to-back, and the third memory chip and the fourth memory chip are stacked face-to-face. The first memory chip and the logic chip in the first stacking unit are stacked back to back, or the first memory chip and the logic chip in the first stacking unit are stacked back to back. The n conductive via groups in the logic chip correspond one-to-one with the n conductive via groups in each of the first memory chip, the second memory chip, the third memory chip, and the fourth memory chip, and are aligned along the third direction, where n is a positive integer.

13. The chip stacking structure according to claim 12, characterized in that, Each chip's global signal region is penetrated by n sets of conductive vias. Each set of conductive vias includes a first conductive via, a second conductive via, a third conductive via, and a fourth conductive via. The first and second conductive vias are symmetrical about a first axis, the third and fourth conductive vias are symmetrical about the first axis, and the first and fourth conductive vias are symmetrical about a second axis. The first axis and the second axis are perpendicular to each other and intersect at the center point of the active surface. The first axis is parallel to the first side of the memory chip, and the second axis is parallel to the second side of the memory chip. The first axis of each logic chip and each memory chip is aligned along the third direction, and the second axis of each logic chip and each memory chip is aligned along the third direction.

14. The chip stacking structure according to claim 12, characterized in that, When the logic chip and the first memory chip are stacked back-to-back. The fourth conductive via in the i-th conductive via group of the logic chip, the first conductive via in the i-th conductive via group of each first memory chip, the second conductive via in the i-th conductive via group of each second memory chip, the third conductive via in the i-th conductive via group of each third memory chip, and the fourth conductive via in the i-th conductive via group of each fourth memory chip are aligned along the third direction and form a signal transmission channel; The third conductive via in the i-th conductive via group of the logic chip, the second conductive via in the i-th conductive via group of each first memory chip, the first conductive via in the i-th conductive via group of each second memory chip, the fourth conductive via in the i-th conductive via group of each third memory chip, and the third conductive via in the i-th conductive via group of each fourth memory chip are aligned along the third direction and form a signal transmission channel; The second conductive via in the i-th conductive via group of the logic chip, the third conductive via in the i-th conductive via group of each first memory chip, the fourth conductive via in the i-th conductive via group of each second memory chip, the first conductive via in the i-th conductive via group of each third memory chip, and the second conductive via in the i-th conductive via group of each fourth memory chip are aligned along the third direction and form a signal transmission channel; The first conductive via in the i-th conductive via group of the logic chip, the fourth conductive via in the i-th conductive via group of each first memory chip, the third conductive via in the i-th conductive via group of each second memory chip, the second conductive via in the i-th conductive via group of each third memory chip, and the first conductive via in the i-th conductive via group of each fourth memory chip are aligned along the third direction and form a signal transmission channel; Where i is a positive integer less than or equal to n.

15. The chip stacking structure according to claim 12, characterized in that, When the logic chip and the first memory chip are stacked back-to-back. The second conductive via in the i-th conductive via group of the logic chip, the first conductive via in the i-th conductive via group of each first memory chip, the second conductive via in the i-th conductive via group of each second memory chip, the third conductive via in the i-th conductive via group of each third memory chip, and the fourth conductive via in the i-th conductive via group of each fourth memory chip are aligned along the third direction and form a signal transmission channel; The first conductive via in the i-th conductive via group of the logic chip, the second conductive via in the i-th conductive via group of each first memory chip, the first conductive via in the i-th conductive via group of each second memory chip, the fourth conductive via in the i-th conductive via group of each third memory chip, and the third conductive via in the i-th conductive via group of each fourth memory chip are aligned along the third direction and form a signal transmission channel; The fourth conductive via in the i-th conductive via group of the logic chip, the third conductive via in the i-th conductive via group of each first memory chip, the fourth conductive via in the i-th conductive via group of each second memory chip, the first conductive via in the i-th conductive via group of each third memory chip, and the second conductive via in the i-th conductive via group of each fourth memory chip are aligned along the third direction and form a signal transmission channel; The third conductive via in the i-th conductive via group of the logic chip, the fourth conductive via in the i-th conductive via group of each first memory chip, the third conductive via in the i-th conductive via group of each second memory chip, the second conductive via in the i-th conductive via group of each third memory chip, and the first conductive via in the i-th conductive via group of each fourth memory chip are aligned along the third direction and form a signal transmission channel.

16. The chip stacking structure according to any one of claims 12-15, characterized in that, For two chips connected face-to-face, the conductive vias aligned along the third direction are electrically connected using a hybrid bonding process; for two chips connected back-to-back or back-to-face, the conductive vias aligned along the third direction are electrically connected using a conductive bump bonding process; or... For two chips connected face-to-face, or two chips connected back-to-back, or two chips connected back-to-face, the conductive vias aligned along the third direction are electrically connected using the hybrid bonding process; or, For two chips connected face-to-face, or for two chips connected back-to-back, or for two chips connected back-to-face, the conductive vias aligned along the third direction are electrically connected through the conductive bump bonding process.

17. A memory, characterized in that, The memory includes a chip stacking structure as described in any one of claims 12-16.

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