Manufacturing method of LDMOS device

Abstract

The invention discloses a manufacturing method of an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device, which comprises the following steps: providing a substrate, forming a semiconductor device area on the substrate including a first area and a second area, forming a storage unit device in the first area, forming an LDMOS device in the second area, forming a first dielectric layer on the substrate, and forming a second dielectric layer on the first dielectric layer; forming a first groove in the first dielectric layer, the second dielectric layer and the substrate; a second groove is formed in the first dielectric layer, the second dielectric layer and the substrate in the second area, the second groove comprises a first sub-area and a second sub-area, the second sub-area is communicated with the first groove in the second area, and the second sub-area and the first groove communicated with the second sub-area form a field plate groove; filling a third dielectric layer in the first groove and the second groove, wherein the third dielectric layer filled in the field plate groove forms a field plate of the LDMOS device; removing the second dielectric layer; a doped region of the LDMOS device is formed in the substrate below the field plate, and a gate of the LDMOS device is formed above the field plate.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices and integrated circuits, and in particular to a method for manufacturing an LDMOS device. Background Art

[0002] In non-volatile memory (NVM), NOR flash memory is developed based on the ETOX structure proposed by Intel. It uses hot electron injection to write data and erases data based on the tunnel effect. Its notable feature is that it has a fast random read speed. As a NVM memory, NOR flash memory has the characteristics of high device density, low power consumption and electrical rewritability. It is widely used in electronic products with storage functions such as smart phones, tablet computers, digital cameras, and universal serial bus flash disks (USB flash disks, referred to as "U disks")

[0003] Due to market demand, it is usually necessary to integrate storage unit devices, power devices and logic devices on the same wafer. Therefore, integrating lateral double-diffused metal-oxide-semiconductor field-effect transistor (LDMOSFET, referred to as "LDMOS" in this application) devices in the manufacturing process of NOR flash memory has become a conventional choice.

[0004] LDMOS devices usually have a multi-layer field plate or a stepped field plate on the side of the gate close to the drain, which can effectively reduce the peak value of the body electric field in the reverse blocking state, and increase the doping concentration of the drift region as much as possible while ensuring that the breakdown voltage meets the requirements, thereby reducing the on-resistance of the device. However, the multi-layer field plate structure is often complicated to manufacture and requires additional processes to form. Summary of the invention

[0005] The present application provides a method for manufacturing an LDMOS device, which can solve the problem of high manufacturing cost caused by the need for an additional mask plate to form a step-type field plate in the LDMOS manufacturing method provided in the related art. The method comprises:

[0006] A substrate is provided, wherein a region on the substrate for forming a semiconductor device comprises a first region and a second region, the first region is used to form a memory cell device, the second region is used to form an LDMOS device, a first dielectric layer is formed on the substrate, a second dielectric layer is formed on the first dielectric layer, and the first dielectric layer and the second dielectric layer are formed of different materials;

[0007] forming a first trench in the first dielectric layer, the second dielectric layer and the substrate;

[0008] A second trench is formed in the first dielectric layer, the second dielectric layer and the substrate in the second region, wherein the depth of the second trench is different from that of the first trench, the second trench includes a first sub-region and a second sub-region, the second sub-region is connected to the first trench in the second region, and the second sub-region and the first trench connected thereto constitute a field plate trench;

[0009] Filling a third dielectric layer in the first trench and the second trench, the third dielectric layer filled in the first trench of the first region forms an STI structure of a storage unit device, the third dielectric layer filled in the field plate trench forms a field plate of an LDMOS device, and the constituent material of the third dielectric layer is the same as the constituent material of the first dielectric layer;

[0010] removing the second dielectric layer;

[0011] A doped region of the LDMOS device is formed in the substrate below the field plate, and a gate of the LDMOS device is formed above the field plate.

[0012] In some embodiments, forming a doped region of the LDMOS device in the substrate under the field plate, and forming a gate of the LDMOS device on the field plate, comprises:

[0013] forming a first doped region in the substrate below the field plate;

[0014] forming a second doping region in the substrate below the field plate, the second doping region being laterally located on one side of the first doping region, and the conductivity type of the impurities doped in the second doping region being different from the conductivity type of the impurities doped in the first doping region;

[0015] forming a gate of an LDMOS device on the field plate;

[0016] A first heavily doped region and a second heavily doped region are formed in the substrate at both sides of the gate, the first heavily doped region is located in the second doped region, the second heavily doped region is located in the first doped region, the conductivity type of the impurities doped in the first heavily doped region is the same as the conductivity type of the impurities doped in the second heavily doped region, and the conductivity type of the impurities doped in the first heavily doped region is the same as the conductivity type of the impurities doped in the first doped region;

[0017] A third heavily doped region is formed in the second doped region, and the conductivity type of the impurities doped in the third heavily doped region is different from the conductivity type of the impurities doped in the first heavily doped region.

[0018] In some embodiments, the first doping region is a drift region, the second doping region is a well region, and the first doping region is deeper than the second doping region.

[0019] In some embodiments, forming a gate of an LDMOS device on the field plate includes:

[0020] forming a polysilicon layer on the first dielectric layer;

[0021] removing the first dielectric layer and the polysilicon layer in other regions except the first target region, and the remaining first dielectric layer forms a gate dielectric layer of the LDMOS device;

[0022] The polysilicon layer in the areas other than the second target area is removed, and the remaining polysilicon layer forms the gate. The length of the gate in the lateral direction is less than the sum of the lengths of the gate dielectric layer and the field plate.

[0023] In some embodiments, the first dielectric layer and the third dielectric layer include silicon dioxide layers.

[0024] In some embodiments, the second dielectric layer includes a silicon nitride layer.

[0025] The technical solution of this application has at least the following advantages:

[0026] In the process of manufacturing the LDMOS device, a first trench and a second trench are formed in the substrate in sequence, the first trench and the second trench in the second region are connected to form a step-type field plate trench, and then a dielectric layer is filled in the field plate trench to form the field plate of the LDMOS device. Since the first trench can be formed by a mask template of the STI structure of the storage cell device and the second trench can be formed by a mask template of the STI structure of the LDMOS device, there is no need to design an additional mask template to form the step-type field plate. At the same time, the process is relatively simple, thereby reducing the manufacturing cost and process complexity. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0028] Figure 1 is a flow chart of a method for manufacturing an LDMOS device provided by an exemplary embodiment of the present application;

[0029] Figures 2 to 6 It is a schematic diagram of the manufacturing process of an LDMOS device provided by an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0030] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, rather than all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0031] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0032] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0033] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0034] refer to Figure 1, which shows a flow chart of a method for manufacturing an LDMOS device provided by an exemplary embodiment of the present application, such as Figure 1 As shown, the method includes:

[0035] Step S1, providing a substrate, wherein an area on the substrate for forming a semiconductor device includes a first area and a second area, the first area is used to form a memory cell device, the second area is used to form an LDMOS device, a first dielectric layer is formed on the substrate, a second dielectric layer is formed on the first dielectric layer, and the first dielectric layer and the second dielectric layer are formed of different materials.

[0036] Step S2, forming a first trench in the first dielectric layer, the second dielectric layer and the substrate.

[0037] refer to Figure 2 , which shows a cross-sectional schematic diagram after the first trench is formed in the first dielectric layer, the second dielectric layer and the substrate. Figure 2 As shown, the region on the substrate 210 for forming the semiconductor device includes a first region 201 and a second region 202, the first region 201 is used to form a memory cell device, and the second region 202 is used to form an LDMOS device. A first dielectric layer 221 is formed on the substrate 210, and a second dielectric layer 231 is formed on the first dielectric layer 221. The first dielectric layer 221 and the second dielectric layer 231 are made of different materials, wherein the first dielectric layer 221 may include a silicon dioxide (SiO2) layer, and the second dielectric layer 231 includes a silicon nitride (Si3N4) layer.

[0038] For example, the second dielectric layer 231 may be covered with a photoresist ( Figure 2 ), after exposure through a first mask, development is performed to expose a target area (an area corresponding to the first trench), and etching is performed to form a first trench in the first dielectric layer 221, the second dielectric layer 231 and the substrate 210, wherein the first trench 3011 in the first area 201 is used to form a shallow trench isolation (STI) structure of a storage unit device, and the first trench 3012 in the second area 202 is used to form a partial area of ​​a field plate trench.

[0039] Step S3, forming a second trench in the first dielectric layer, the second dielectric layer and the substrate in the second region, wherein the depth of the second trench is different from that of the first trench, the second trench includes a first sub-region and a second sub-region, the second sub-region is connected to the first trench in the second region, and the second sub-region and the first trench connected thereto constitute a field plate trench.

[0040] refer to Figure 3 , which shows a cross-sectional schematic diagram after the second groove is formed. Figure 2As shown, the second dielectric layer 231 may be covered with a photoresist ( Figure 3 ), after exposure through a second mask, development is performed to expose the target area (the area corresponding to the second groove), and etching is performed to form a second groove in the first dielectric layer 221, the second dielectric layer 231 and the substrate 210 of the second area 201, the second groove includes a first sub-area 3021 and a second sub-area 3022, the second sub-area 3022 is connected to the first groove 3012 in the second area 201, and the second sub-area 3022 and the first groove 3012 connected thereto constitute a field plate groove. Among them, the depths of the first groove and the second groove are different, so that the cross-section of the field plate groove is a step type. It should be noted that Figures 2 to 6 In the example, the depth of the second groove is deeper than the depth of the first groove. In practical applications, the depth of the second groove can also be set to be shallower than the first groove.

[0041] Step S4, filling a third dielectric layer in the first trench and the second trench, the third dielectric layer filled in the first trench of the first region forms an STI structure of the storage cell device, the third dielectric layer filled in the field plate trench forms a field plate of the LDMOS device, and the constituent material of the third dielectric layer is the same as the constituent material of the first dielectric layer.

[0042] refer to Figure 4 , which shows a cross-sectional schematic diagram after the third dielectric layer is filled in the first trench and the second trench. Exemplarily, the third dielectric layer may include a silicon dioxide layer, such as Figure 4 As shown, a silicon dioxide layer can be deposited by a chemical vapor deposition (CVD) process to fill the first trench and the second trench, and the silicon dioxide layer outside the first trench and the second trench can be removed by a planarization process (for example, a chemical mechanical polishing (CMP) process). The silicon dioxide layer in the first trench 3011 in the first region 201 constitutes an STI structure 211 of the storage cell device, the silicon dioxide layer in the isolation trench constitutes a field plate 212 of the LDMOS device, and the field plate 212 and the silicon dioxide layer 213 in the first sub-trench 3021 constitute an isolation structure of the LDMOS device.

[0043] Step S5, removing the second dielectric layer.

[0044] Step S6, forming a doped region of the LDMOS device in the substrate below the field plate, and forming a gate of the LDMOS device above the field plate.

[0045] Exemplarily, step S6 includes but is not limited to: forming a first doped region in the substrate below the field plate; forming a second doped region in the substrate below the field plate, the second doped region being laterally located on one side of the first doped region, the conductivity type of the impurities doped in the second doped region being different from the conductivity type of the impurities doped in the first doped region; forming a gate of the LDMOS device on the field plate; forming a first heavily doped region and a second heavily doped region in the substrate on both sides of the gate, the first heavily doped region being located in the second doped region, the second heavily doped region being located in the first doped region, the conductivity type of the impurities doped in the first heavily doped region being the same as the conductivity type of the impurities doped in the second heavily doped region, and the conductivity type of the impurities doped in the first heavily doped region being the same as the conductivity type of the impurities doped in the first doped region; forming a third heavily doped region in the second doped region, the conductivity type of the impurities doped in the third heavily doped region being different from the conductivity type of the impurities doped in the first heavily doped region.

[0046] refer to Figure 5 , which shows a cross-sectional schematic diagram after forming the first doping region and the second doping region. Figure 5 As shown, the second dielectric layer 231 can be removed by a wet etching process, and ion implantation can be performed by a photolithography process to form a first doped region 213 in the substrate 210 below the field plate 212, and a second doped region 214 can be formed in the substrate 210 below the field plate 212, wherein the first doped region 213 is a drift region, and the second doped region 214 is a well region, and the depth of the first doped region 213 is deeper than that of the second doped region 214.

[0047] refer to Figure 6 , which shows a cross-sectional schematic diagram after forming a heavily doped region and a gate. Figure 6 As shown, a polysilicon layer can be formed on the first dielectric layer 221; the first dielectric layer 221 and the polysilicon layer in other regions except the first target region are removed, and the remaining first dielectric layer 221 forms a gate dielectric layer of the LDMOS device; the polysilicon layer in other regions except the second target region is removed, and the remaining polysilicon layer forms a gate 233, and the length of the gate 233 in the lateral direction is less than the sum of the lengths of the gate dielectric layer and the field plate; ion implantation is performed by photolithography to form a first dielectric layer in the substrate 210 on both sides of the gate 233 A heavily doped region 2151 and a second heavily doped region 2152; ion implantation is performed through a photolithography process to form a third heavily doped region 2153 in the second doped region 214, the impurity concentrations doped in the first heavily doped region 2151, the second heavily doped region 2152 and the third heavily doped region 2153 are greater than those in other doped regions, the first heavily doped region 2151 and the third heavily doped region 2153 are located in the second doped region 214 and on both sides of the STI structure 213, and the second heavily doped region 2152 is located in the first doped region 213.

[0048] In the embodiment of the present application, if the impurities doped into the first doping region 213, the first heavily doped region 2151 and the second heavily doped region 2152 are N (negative) type impurities, then the impurities doped into the second doping region 214 and the third heavily doped region 2153 are P (positive) type impurities; if the impurities doped into the first doping region 213, the first heavily doped region 2151 and the second heavily doped region 2152 are P type impurities, then the impurities doped into the second doping region 214 and the third heavily doped region 2153 are N type impurities.

[0049] To summarize, in the embodiment of the present application, during the manufacturing process of the LDMOS device, the first trench and the second trench are successively formed in the substrate, the first trench and the second trench in the second region are connected to form a step-type field plate trench, and then a dielectric layer is filled in the field plate trench to form the field plate of the LDMOS device. Since the first trench can be formed by a mask template of the STI structure of the storage cell device, and the second trench can be formed by a mask template of the STI structure of the LDMOS device, there is no need to design an additional mask template to form a step-type field plate. At the same time, the process is relatively simple, thereby reducing the manufacturing cost and process complexity.

[0050] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection created by this application.

Claims

1. A method for manufacturing an LDMOS device, characterized in that: include: A substrate is provided, wherein a region on the substrate for forming a semiconductor device comprises a first region and a second region, the first region is used to form a memory cell device, the second region is used to form an LDMOS device, a first dielectric layer is formed on the substrate, a second dielectric layer is formed on the first dielectric layer, and the first dielectric layer and the second dielectric layer are formed of different materials; forming a first trench in the first dielectric layer, the second dielectric layer and the substrate; A second trench is formed in the first dielectric layer, the second dielectric layer and the substrate in the second region, wherein the depth of the second trench is different from that of the first trench, the second trench includes a first sub-region and a second sub-region, the second sub-region is connected to the first trench in the second region, and the second sub-region and the first trench connected thereto constitute a field plate trench; Filling a third dielectric layer in the first trench and the second trench, the third dielectric layer filled in the first trench of the first region forms an STI structure of a storage unit device, the third dielectric layer filled in the field plate trench forms a field plate of an LDMOS device, and the constituent material of the third dielectric layer is the same as the constituent material of the first dielectric layer; removing the second dielectric layer; A doped region of the LDMOS device is formed in the substrate below the field plate, and a gate of the LDMOS device is formed above the field plate.

2. The method according to claim 1, characterized in that The step of forming a doped region of the LDMOS device in the substrate under the field plate and forming a gate of the LDMOS device on the field plate comprises: forming a first doped region in the substrate below the field plate; forming a second doping region in the substrate below the field plate, the second doping region being laterally located on one side of the first doping region, and the conductivity type of the impurities doped in the second doping region being different from the conductivity type of the impurities doped in the first doping region; forming a gate of an LDMOS device on the field plate; A first heavily doped region and a second heavily doped region are formed in the substrate at both sides of the gate, the first heavily doped region is located in the second doped region, the second heavily doped region is located in the first doped region, the conductivity type of the impurities doped in the first heavily doped region is the same as the conductivity type of the impurities doped in the second heavily doped region, and the conductivity type of the impurities doped in the first heavily doped region is the same as the conductivity type of the impurities doped in the first doped region; A third heavily doped region is formed in the second doped region, and the conductivity type of the impurities doped in the third heavily doped region is different from the conductivity type of the impurities doped in the first heavily doped region.

3. The method according to claim 2, characterized in that The first doping region is a drift region, the second doping region is a well region, and the first doping region is deeper than the second doping region.

4. The method according to claim 2, characterized in that: The step of forming a gate of an LDMOS device on the field plate comprises: forming a polysilicon layer on the first dielectric layer; removing the first dielectric layer and the polysilicon layer in other regions except the first target region, and the remaining first dielectric layer forms a gate dielectric layer of the LDMOS device; The polysilicon layer in the areas other than the second target area is removed, and the remaining polysilicon layer forms the gate. The length of the gate in the lateral direction is less than the sum of the lengths of the gate dielectric layer and the field plate.

5. The method according to any one of claims 1 to 4, characterized in that: The first dielectric layer and the third dielectric layer include silicon dioxide layers.

6. The method according to claim 5, characterized in that The second dielectric layer includes a silicon nitride layer.

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