Gallium nitride device and preparation method thereof, module and equipment

Abstract

The invention relates to a gallium nitride device and a preparation method thereof, a module, equipment and a gallium nitride device, the gallium nitride device comprises a substrate, a buffer layer, a channel layer, a barrier layer, a p-type layer, a grid electrode, a source electrode and a drain electrode, and the substrate, the buffer layer, the channel layer and the barrier layer are sequentially stacked from bottom to top; the p-type layer is located on the barrier layer; the grid electrode covers the upper surface of the p-type layer and at least one side surface of the p-type layer and is in contact with the barrier layer, and the grid electrode and the p-type layer form a grid cap structure; the source electrode and the drain electrode are located on the barrier layer and distributed on the two sides of the gate cap structure. According to the gallium nitride device, the problems caused by a groove gate structure and a GaN HEMT using a silicon carbide substrate in the prior art are solved, high performance and high stability are kept, meanwhile, the manufacturing cost and the design complexity are remarkably reduced, higher safety and application convenience are achieved, and the gallium nitride device is suitable for large-scale popularization and application. And an ideal solution is provided for integration and miniaturization of modules and equipment.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and specifically relates to a gallium nitride device and a preparation method, module, and equipment thereof. Background Art

[0002] With the increasing progress and development of semiconductor technology, high electron mobility transistors (HEMT) based on the third-generation semiconductor material gallium nitride are widely used in the preparation of power, RF devices and their corresponding modules, among which the performance of HEMT devices will determine the performance of modules and devices. AlGaN / GaN heterojunction HEMT devices have many advantages. They make full use of the two-dimensional electron gas formed by the polarization characteristics of nitride to avoid many scattering mechanisms. It is precisely because of the channel formed by its two-dimensional electron gas that common gallium nitride devices are depletion-type, and the channel remains open without bias. Depletion-type devices require negative gate voltage to turn them off, which increases the difficulty of peripheral circuit design, reduces integration and energy efficiency, and restricts their application in modules and devices. The enhancement-mode device, with its positive gate threshold voltage characteristics, can significantly simplify the difficulty of driving circuit design and realize a driving scheme compatible with CMOS levels without the need for negative voltage drive. This feature, combined with its low on-resistance, high-frequency switching capability and excellent thermal characteristics, enables power supplies, communication modules and devices based on enhancement-mode GaN HEMT to achieve higher power density and system efficiency.

[0003] At present, the schemes for realizing GaN enhancement mode devices include fluorine ion implantation, groove gate MIS structure, common source and common gate structure, and p-GaN gate structure, each of which has its own advantages and disadvantages. Although the F ion implantation device is simple, its process repeatability is poor. After long-term and high-temperature use, the threshold voltage will shift negatively, which will seriously affect the reliability of the device and is completely unsuitable for commercial use. The groove gate MIS structure has obvious disadvantages, including the difficulty in accurately controlling the etching rate, which will affect the repeatability of the process. In severe cases, the channel will be etched and the device will be damaged; the surface roughness after etching is high, which will directly affect the performance of the device, affect the subsequent process and increase the gate leakage current. The device with common source and common gate structure needs to consider the compatibility of Si-based MOSFET and GaN HEMT process, and the cost is high; in addition, the common source and common gate structure is difficult to package, heat dissipation is difficult, power consumption is high and energy efficiency is low. Due to the introduction of Mg-doped GaN into the p-GaN gate, the gate's control ability over the channel is reduced, thereby deteriorating the frequency characteristics of the device. In addition, modules and equipment designed using grooved gate HEMTs cannot adapt to power applications, modules and equipment designed using common source and common gate structures require optimized heat dissipation design and are expensive, and modules and equipment designed using p-GaN gate HEMT devices are severely limited in their application in the frequency field.

[0004] Therefore, the current solutions for realizing GaN enhanced devices have defects such as poor device reliability and stability, large gate leakage current, and low gate control capability resulting in poor device frequency characteristics. Summary of the invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a gallium nitride device and a preparation method, module, and device thereof. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0006] An embodiment of the present invention provides a gallium nitride device, comprising: a substrate, a buffer layer, a channel layer, a barrier layer, a p-type layer, a gate, a source electrode, and a drain electrode, wherein:

[0007] The substrate, the buffer layer, the channel layer, and the barrier layer are stacked in sequence from bottom to top;

[0008] The p-type layer is located on the barrier layer;

[0009] The gate covers the upper surface of the p-type layer and at least one side surface of the p-type layer and is in contact with the barrier layer, and the gate and the p-type layer form a gate cap structure;

[0010] The source electrode and the drain electrode are located on the barrier layer and are distributed on both sides of the gate cap structure.

[0011] In one embodiment of the present invention, the gate comprises a fully encapsulated structure, and the fully encapsulated structure covers the upper surface of the p-type layer and two side surfaces of the p-type layer;

[0012] The fully encapsulated structure forms a Schottky contact with the barrier layer, and forms a Schottky contact with at least a portion of the contact surface between the fully encapsulated structure and the p-type layer.

[0013] In one embodiment of the present invention, the fully encapsulated structure is a Schottky gate metal, and Schottky contacts are formed between the Schottky gate metal and the barrier layer and the p-type layer.

[0014] In one embodiment of the present invention, the fully encapsulated structure includes an ohmic gate metal and a Schottky gate metal, wherein:

[0015] The ohmic gate metal is located on the upper surface of the p-type layer;

[0016] The Schottky gate metal extends from both sides of the ohmic gate metal to a first side surface and a second side surface of the p-type layer respectively until contacting the barrier layer, wherein the first side surface and the second side surface are opposite to each other.

[0017] In one embodiment of the present invention, along the extension direction of the p-type layer, the shape of the ohmic gate metal includes a straight line shape, an S shape, or a Z shape;

[0018] The contact area between the ohmic gate metal and the p-type layer accounts for 0%-20% of the total contact area between the full-encapsulation structure and the p-type layer.

[0019] In one embodiment of the present invention, the gate comprises a semi-encapsulated structure, the semi-encapsulated structure covers the upper surface of the p-type layer and the first side surface of the p-type layer, or covers the upper surface of the p-type layer and the second side surface of the p-type layer;

[0020] The semi-encapsulated structure is a Schottky gate metal or an Ohmic gate metal.

[0021] In one embodiment of the present invention, the gallium nitride device is a rectangular device;

[0022] The material of the substrate includes one or more of silicon, silicon carbide, sapphire, diamond, and aluminum nitride;

[0023] The material of the buffer layer includes one or more of GaN and AlGaN, and the thickness is 200nm-8000nm;

[0024] The material of the channel layer includes GaN, and the thickness is 50nm-800nm;

[0025] The barrier layer includes one or more materials selected from AlN, AlGaN, and AlScN, and has a thickness of 2nm-10nm;

[0026] The material of the p-type layer includes p-GaN, and the doping element includes Mg, with a doping concentration of 10 17 -10 19 cm 3 , thickness is 20nm-100nm;

[0027] The width of the gate is 50nm-500nm; the width of the gate covering the side of the p-type layer is 0nm-200nm;

[0028] The material of the source electrode and the drain electrode includes one or more of gold, titanium, nickel, and aluminum.

[0029] Another embodiment of the present invention provides a method for preparing a gallium nitride device, comprising the steps of:

[0030] Providing an epitaxial wafer, wherein the epitaxial wafer comprises a substrate, a buffer layer, a channel layer and a barrier layer stacked in sequence from bottom to top;

[0031] Epitaxially growing a p-type material on the barrier layer, and etching away the p-type material in the non-gate region to form a p-type layer;

[0032] Depositing source metal and drain metal on the barrier layer, and performing rapid thermal annealing to form a source and a drain, wherein the source and the drain are distributed on both sides of the p-type layer;

[0033] A gate is formed on the upper surface of the p-type layer and at least one side surface of the p-type layer, so that a portion of the gate on the side surface of the p-type layer contacts the barrier layer.

[0034] Yet another embodiment of the present invention provides a module, including the gallium nitride device described in the above embodiment, wherein the module includes a power module, a radio frequency module, and an integrated radio frequency front-end module.

[0035] Yet another embodiment of the present invention provides a device, comprising the module described in the above embodiment.

[0036] Compared with the prior art, the present invention has the following beneficial effects:

[0037] 1. The gallium nitride device of the present invention forms a gate cap structure through the gate and the p-type layer. The gate cap structure enables the electronic device to achieve a positive gate control voltage, changing from a depletion mode to an enhancement mode, effectively solving the problem that the leakage current of the groove gate HEMT device is too large and may affect the reliability and stability of the device. At the same time, it enhances the electrical and thermal stability of the device, simplifies the integrated circuit design, and helps to reduce the difficulty of peripheral circuit design;

[0038] 2. In the gallium nitride device of the present invention, the gate covers the upper surface of the p-type layer and at least one side surface of the p-type layer to form a covered gate structure, which can solve the problem of poor gate control ability of the p-GaN gate, improve the frequency characteristics of the device, and significantly reduce the off-state leakage current of the device, thereby improving the electrical and thermal stability of the device, and can better cope with long-term applications;

[0039] 3. In the gallium nitride device of the present invention, the thickness of the barrier layer is 2nm-10nm. The ultra-thin barrier layer can reduce the on-resistance while ensuring high current density, significantly improve the transconductance characteristics and small signal performance of the device, and improve the high-frequency response of the RF device, which is conducive to the integration of RF devices;

[0040] 4. In the preparation method of the present invention, the gate is directly prepared on the surface of the device, which simplifies the production process and avoids the use of an etching process to form a groove gate, thereby avoiding damage and surface roughness caused by the etching process, reducing the leakage current of the device, enhancing the thermal and electrical stability of the device, and extending the service life of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 A schematic diagram of a cross-sectional structure of a gallium nitride device provided by an embodiment of the present invention;

[0042] Figure 2 A schematic cross-sectional structure diagram of another gallium nitride device provided by an embodiment of the present invention;

[0043] Figure 3 A cross-sectional view of a left half-wrapped gate device provided by an embodiment of the present invention;

[0044] Figure 4 A cross-sectional view of a right half-wrapped gate device provided by an embodiment of the present invention;

[0045] Figure 5 A schematic diagram of the structure of a hybrid gate device provided by an embodiment of the present invention;

[0046] Figure 6 A schematic diagram of the structure of another hybrid gate device provided by an embodiment of the present invention;

[0047] Figure 7 A transfer characteristic simulation test curve of the device provided by the embodiment of the present invention;

[0048] Figure 8 A frequency characteristic simulation test curve of the device provided by the embodiment of the present invention;

[0049] Fig. 9 A schematic flow chart of a method for preparing a gallium nitride device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0050] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0051] Embodiment 1

[0052] See also Figure 1 , Figure 1 A schematic diagram of the cross-sectional structure of a gallium nitride device provided in an embodiment of the present invention.

[0053] The gallium nitride device of this embodiment may be an enhanced high electron mobility device, comprising a substrate, a buffer layer, a channel layer, a barrier layer, a p-type layer, a gate, a source and a drain, wherein the substrate, the buffer layer, the channel layer and the barrier layer are stacked in sequence from bottom to top; the p-type layer is located on the barrier layer; the gate covers the upper surface of the p-type layer and at least one side surface of the p-type layer, and is in contact with the barrier layer, and the gate and the p-type layer form a gate cap structure; the source and the drain are located on the barrier layer, and are distributed on both sides of the gate cap structure.

[0054] The gallium nitride device of this embodiment is a rectangular device. Compared with the annular device, the rectangular device can better utilize the area on the wafer, can arrange the devices more closely, and realize high-density integrated design. In terms of process difficulty, the rectangular device can be better compatible with the process, and the photolithography alignment is easier, which can effectively improve the yield and thus reduce the manufacturing cost. Compared with the annular device, which is easy to form a short channel effect at the edge of the gate, resulting in weak gate control ability and large leakage current, the rectangular device can better control the switching of the channel.

[0055] The substrate provides physical support for material growth and subsequent processes, and factors such as cost, lattice mismatch, and thermal mismatch need to be considered comprehensively. The size of the substrate is not limited. The substrate material is not limited. The substrate material can include one or more of silicon (Si), silicon carbide (SiC), sapphire (Al2O3), diamond, aluminum nitride (AlN), etc. These substrates can improve the quality of epitaxially grown crystals, thereby improving reliability.

[0056] Preferably, the substrate is made of silicon material. Using silicon material as the substrate can effectively reduce manufacturing costs and can be better compatible with silicon-based processes, which is conducive to the integration, miniaturization and portability of devices.

[0057] The material of the buffer layer includes one or more of GaN and AlGaN. Specifically, the buffer layer can be GaN material, or a high-resistance GaN material, or a low-aluminum aluminum gallium nitride (AlGaN) material. The resistivity of the high-resistance GaN material is 10 8 Ω·cm-10 10 Ω·cm, high-resistance GaN material is achieved by doping C and Fe elements in GaN. The Al component in the low-aluminum AlGaN material is less than or equal to 0.07. For example, the buffer layer uses AlGaN material with a low aluminum component, which can effectively alleviate the problem of high leakage current of the buffer layer, thereby improving the breakdown voltage and reliability of the device. The thickness of the buffer layer is not limited, and can range from 200nm to 8000nm.

[0058] The material of the channel layer includes gallium nitride (GaN) material. The barrier layer is an ultra-thin barrier layer, and its material includes one or more of AlN, AlGaN, and AlScN. Specifically, the material of the barrier layer includes at least one of the strong polarization material aluminum nitride (AlN), high Al component aluminum gallium nitride (AlGaN), and aluminum scandium nitride (AlScN). Among them, the Al component in the high Al component aluminum gallium nitride (AlGaN) is greater than or equal to 0.5.

[0059] In this embodiment, the channel layer and the barrier layer form a heterojunction structure, and a high concentration of two-dimensional electron gas is generated at the interface through the polarization effect of the nitride as the conductive channel of the device to avoid scattering affecting the electron mobility. Taking the AlN ultra-thin barrier layer and the GaN channel layer as an example, a strong polarization effect will be generated between AlN and GaN due to the lattice mismatch, and a large amount of two-dimensional electron gas will be generated at the material interface and confined in the potential well of the interface.

[0060] The thickness of the channel layer and the barrier layer is not limited. The thickness of the channel layer can be between 50nm and 800nm, and the thickness of the ultra-thin barrier layer can be between 2nm and 10nm. The thicker the ultra-thin barrier layer, the stronger the polarization effect of the heterojunction between the channel layer and the barrier layer will be, thereby inducing more two-dimensional electron gas, thereby enhancing the current density of the device and obtaining a higher current. However, the growth of a thick barrier layer will reduce the crystal quality and cause more defects, which will have a negative impact on the reliability of the device.

[0061] Optionally, the lattice matching degree between the barrier layer and the channel layer is better than that between the channel layer and the buffer layer. This is beneficial to increase the thickness of the barrier layer while reducing stress defects caused by lattice mismatch, thereby increasing the polarization effect at the interface between the barrier layer and the channel layer, generating more channel electrons, and thereby increasing the current and power density of the device and improving the power of the device.

[0062] The gate cap structure is composed of a p-type layer and a gate metal material, and the p-type layer is between the gate metal and the barrier layer.

[0063] The material of the p-type layer includes p-GaN, and the doping elements include Mg, that is, the p-type layer is p-GaN formed by GaN material doped with Mg atoms. The p-GaN material can adjust the band structure and deplete the two-dimensional electron gas under the gate cap without adding gate bias. The thickness of the p-GaN material layer is not limited, and its thickness can be between 20nm-100nm. The thicker the GaN material, the better the effect of electron depletion in the channel, but thick p-GaN will reduce the gate control ability. The p-type doping of GaN is carried out by material growth through MOCVD, and the doping concentration of p-type GaN is not limited, and the doping concentration can be between 10 17 ~10 19 cm -3 between.

[0064] In this embodiment, p-GaN itself can provide good rectification characteristics, ensuring that the gate leakage current is small and the stability of the device is good.

[0065] The gate is made of metal material. The gate metal type is not limited. It can be a single metal or an alloy of multiple metal elements. The gate width is not limited. The gate width can be between 50nm-500nm. The shorter the gate, the faster the switching speed can be provided. However, a too short gate may cause the gate control ability to be too weak, and the segment channel effect is very obvious.

[0066] The gate cap structure can be used to control the opening and closing of the two-dimensional electron gas channel, thereby controlling the conduction and shutdown of the device. Figure 1 and Figure 2 , Figure 2 A schematic cross-sectional structure diagram of another gallium nitride device provided in an embodiment of the present invention. Figure 1 When the gate voltage is 0 V, the two-dimensional electron gas below the p-type layer is depleted, the two-dimensional electron gas channel is closed, and the device is turned off. Figure 2 When the gate voltage is greater than the threshold voltage Vth, the two-dimensional electron gas channel is turned on and the device is turned on. The voltage that turns on the channel is usually called the threshold voltage Vth. The threshold voltage Vth of the depletion-type HEMT device is negative. In this embodiment, the threshold voltage Vth of the HEMT made of the gate cap structure is positive, which facilitates device integration.

[0067] The gate adopts a wrapped gate structure, and the gate covers the upper surface and at least one side surface of the p-type layer.

[0068] Specifically, the gate may be a fully encapsulated structure, which covers the upper surface of the p-type layer and the two side surfaces of the p-type layer, such as Figure 2 The gate may also be a semi-encapsulated structure, and the semi-encapsulated structure may cover the upper surface of the p-type layer and the first side surface of the p-type layer. When the first side surface is the left side surface of the p-type layer, the semi-encapsulated structure is a left semi-encapsulated structure, as shown in FIG. Figure 3 As shown, Figure 3 A cross-sectional view of a left half-encapsulated gate device provided by an embodiment of the present invention. The half-encapsulated structure may also cover the upper surface of the p-type layer and the second side surface of the p-type layer. When the second side surface is the right side surface of the p-type layer, the half-encapsulated structure is a right half-encapsulated structure. Figure 4 As shown, Figure 4 A cross-sectional view of a right half-wrapped gate device provided in an embodiment of the present invention. The left extension width and the right extension width of the wrapped gate are not limited, wherein the extension width refers to the width of the gate covering the side of the p-type layer, and illustratively, the width of the gate covering the side of the p-type layer ranges from 0nm to 200nm. And the left extension width projection may be equal to or unequal to the right extension width.

[0069] GaN HEMT is a gate-controlled device. Conventional floating gates (Y and T-shaped gates) improve the frequency characteristics by reducing the gate length and increasing the switching speed of the channel, but the smaller the gate, the higher the precision of the process is required. Both the fully-enclosed gate and the semi-enclosed gate are proposed to address this problem. The use of fully-enclosed gate and semi-enclosed gate structures can effectively reduce the gate-drain capacitance and gate-source capacitance, thereby indirectly improving the frequency characteristics of the device; at the same time, the gate contact (the bottom of the gate) is small and the gate head (the top of the gate) is large, which can reduce the resistivity. The fully-enclosed and semi-enclosed gates have the same principle, but they reduce the gate-drain capacitance and gate-source capacitance to different degrees. The fully-enclosed gate has a better effect on reducing capacitance and has better frequency characteristics. At the same time, the electric field distribution is more uniform, which plays a role in dividing the electric field near the gate. The implementation effects of the left and right half-wrapped gates are also different. The reliability of the device that wraps the gate close to the drain (right half-wrapped structure) is better than that of the device that wraps the gate close to the source (left half-wrapped structure). The peak electric field of the device happens to be at the lower right corner of the gate. At this time, the right-wrapped gate can divide the voltage very well; the lower right corner of the gate is also the focus of thermal management, and the right-wrapped gate metal can also better play a role in heat dissipation.

[0070] When the gate is a semi-encapsulated structure, the semi-encapsulated structure may be a Schottky gate metal or an Ohmic gate metal.

[0071] Specifically, the gate contact type of the semi-encapsulated structure is not limited, that is, the contact type between the barrier layer and the gate metal, and the contact type between the p-type layer and the gate metal is not limited. The gate contact type can be an ohmic gate metal or a Schottky gate metal. The leakage current of the ohmic gate metal is smaller, and the leakage current of the Schottky gate metal is larger, but both are within the range that can be considered.

[0072] When the gate is a fully encapsulated structure, the gate metal will be in direct contact with the p-type layer and the barrier layer. If the fully encapsulated structure is pure ohmic metal, the ohmic metal will be in direct contact with the barrier layer, and the function will be similar to that of the source and drain, directly generating a conductive channel, and the gate leakage will increase sharply, seriously affecting the reliability of the device, directly causing the device to fail and completely unable to work in a normal state. An insulating layer can be wrapped around the p-type layer, and then an ohmic gate can be made, but this will increase the difficulty of the process, which goes against the original intention of simplifying the process, and there are interface defects between the insulating layer material and the p-type layer and the barrier layer, which requires a strict insulating layer growth method to meet the use requirements. Therefore, if a fully encapsulated gate structure is adopted, a Schottky contact is formed between the gate and the barrier layer, and a Schottky contact is formed with at least part of the contact surface between the gate and the p-type layer. It can be understood that the contact surface between the fully encapsulated structure and the p-type layer can form a Schottky contact in its entirety, or it can form a Schottky contact in part and an ohmic contact in part. Among them, the contact area of ​​the ohmic contact should be less than 20% of the total contact area of ​​the p-type layer.

[0073] In one embodiment, the fully encapsulated structure is a Schottky gate metal, and Schottky contacts are formed between the Schottky gate metal and the barrier layer and the p-type layer.

[0074] In another embodiment, the fully encapsulated structure is a hybrid gate structure, including an ohmic gate metal and a Schottky gate metal, wherein the ohmic gate metal is located on the upper surface of the p-type layer; the Schottky gate metal extends from both sides of the ohmic gate metal to the first side surface and the second side surface of the p-type layer respectively until it contacts the barrier layer, wherein the first side surface and the second side surface are opposite to each other, such as Figure 5 As shown, Figure 5 A schematic structural diagram of a hybrid gate device provided by an embodiment of the present invention.

[0075] Specifically, the shape of the ohmic gate metal is not limited, and the shape of the ohmic gate metal can be a straight line, such as Figure 5 As shown, it can also be S-shaped or Z-shaped, such as Figure 6 As shown, Figure 6 A schematic structural diagram of another hybrid gate device provided by an embodiment of the present invention.

[0076] The shape of the ohmic gate metal of this embodiment can be S-shaped or Z-shaped. The S-shaped and Z-shaped ohmic contact gates introduce more complex current distribution patterns through the tortuous paths in the design. The S-shaped gate changes the direction of the current through a smooth curve, while the Z-shaped uses multiple broken line segments to form a current channel. Such a structure extends the charge release path, making the current distribution more uniform. The extended path also allows the current to avoid local overload areas when passing through the device, thereby significantly reducing the concentration effect of the electric field. In addition, this distribution improves the thermal management performance within the device, and improves the overall heat dissipation capacity by reducing the formation of hot spots and dispersing heat.

[0077] Too high an ohmic gate contact ratio will result in excessive leakage current, which will cause premature leakage breakdown of the device and reduce reliability. Therefore, in this embodiment, the contact area between the ohmic gate metal and the p-type layer accounts for 0%-20% of the total contact area between the full-encapsulation structure and the p-type layer.

[0078] Ultra-thin barrier layers with large currents will also introduce high leakage, so Schottky contacts are needed to reduce leakage. On the basis of the Schottky gate, an ohmic gate is inserted to form a hybrid gate structure, and the p-type layer and Schottky contact play a rectifying role at the same time; the Schottky contact forms a barrier through the contact between the metal and the semiconductor, and the carriers are mainly conductive through the thermal electron emission or tunneling of the barrier; the insertion of the ohmic contact can reduce the barrier, making it easier to release the charge stored in the p-type layer, alleviating the negative effect of electrical stress on the reliability of the device, effectively suppressing the drift of the threshold voltage, and stabilizing the threshold voltage. Schottky contacts are used for rectification, and ohmic contacts are used to release current injection, so the proportion of ohmic contacts is limited to less than 20% of the contact area. The hybrid gate structure can also optimize the electric field distribution of the device, mainly to alleviate the accumulation of charge, thereby alleviating the problem of excessive local electric field in the p-type layer and improving reliability.

[0079] The source and drain are arranged at both ends above the barrier layer, and the distance between the source and the drain is not limited. The distance between the gate cap structure and the drain is usually greater than the distance between the gate cap structure and the source. Optionally, the source and the drain can pass through the barrier layer to the bottom channel layer, which can effectively reduce the series resistance of the device, reduce losses, and improve efficiency.

[0080] The source and the drain are made of conductive materials, and the type of the material is not limited. For example, the conductive material can be a metal single substance or alloy of at least one element of gold, titanium, nickel, and aluminum to ensure that it can be conductive with the channel.

[0081] Optionally, a passivation layer can be grown on the unfilled portion above the barrier layer to protect the device, that is, the barrier layer between the source and the gate, and the barrier layer between the drain and the gate are covered with a passivation layer. The material of the passivation protection layer is not limited, and the material can be silicon nitride (SiNx), aluminum oxide (Al2O3), silicon dioxide (SiO2), hafnium oxide (HfO2), etc. By growing a passivation layer, the current collapse effect can be reduced and the reliability of the device can be improved. The thickness of the passivation layer is not limited, and the range can be 3nm-20nm. The appropriate thickness of the passivation layer slightly increases the current density while reducing the influence of the surface state, thereby improving the stability of the device.

[0082] In the above-mentioned GaN devices, a two-dimensional electron gas (2DEG) is formed between the channel layer and the barrier layer due to the polarization effect. Both the full-enclosed and semi-enclosed gate HEMT devices are gate-controlled devices, and the gate voltage controls the conduction of the two-dimensional electron gas channel. Specifically, there are three states: when the gate voltage is less than the threshold voltage, the channel is closed; when the gate voltage increases to the threshold voltage, the channel is partially turned on, which is the "partially on state" of conduction; when the gate voltage increases to a certain level, the channel is fully turned on, and the current is saturated at this time. The gate is responsible for regulating the switching state of the channel, and the source and drain drive the current flow through the voltage difference. Furthermore, the ohmic contact formed by the metal and part of the p-type layer can be equivalent to a resistor for guiding current. The Schottky contact formed by the metal and the barrier layer material will increase the equivalent capacitance of the circuit. Since the capacitance introduced by the Schottky contact is usually connected in parallel to the circuit, thereby increasing the total capacitance value, this may affect the high-frequency response of the circuit, thereby limiting the frequency characteristics.

[0083] Based on the above-mentioned gallium nitride device, this embodiment uses an enhanced-mode GaN high electron mobility transistor device based on an ultra-thin barrier layer as an example for simulation testing.

[0084] See also Figure 1 and Figure 2 The enhanced GaN high electron mobility transistor device based on the ultra-thin barrier layer includes a substrate, a buffer layer, a channel layer and a barrier layer arranged in sequence from bottom to top, a source and a drain are arranged at both ends of the barrier layer surface, and a gate cap structure is arranged in the middle of the barrier layer. The gate cap structure consists of a p-type layer and a gate metal. The p-type layer is above the barrier layer, and the gate metal covers the upper surface and two side surfaces of the p-type layer. A passivation layer is also arranged on the barrier layer between the gate cap and the source, and between the gate cap and the drain.

[0085] Specifically, the substrate is made of silicon (Si) material, and the device is epitaxially grown on the substrate by chemical and physical methods. The buffer layer is made of low Al component AlGaN material (for example, Al component is 0.03) with a thickness of 400nm, which can effectively reduce the impact of buffer layer leakage current on the device and improve reliability. The channel layer material is GaN, and the channel layer thickness is 100nm; the barrier layer and the channel layer of GaN material will give the manufactured device a strong current handling capability through the polarization effect. The barrier layer can be made of a strongly polarized material, which can be aluminum nitride (AlN) with a thickness of 4nm; an ultra-thin barrier layer can be obtained by using a strongly polarized material to reduce transconductance while maintaining a high concentration of two-dimensional electron gas. The source and drain are respectively arranged at both ends of the barrier layer surface, and the spacing between the source and the drain is not limited, but the distance between the gate and the drain is greater than the distance between the source and the source. In this embodiment, the distance between the gate and the source is 1 micron, and the distance between the gate and the drain is 2 microns. The material of the p-type layer is p-GaN, a p-type doped GaN material with a thickness of 40nm and a width of 100nm. The gate metal is set around the p-type doped GaN material, covering the p-type GaN material, and extending 50nm in the left and right directions respectively, forming a fully covered structure. The p-GaN layer can adjust the energy band to deplete the two-dimensional electron gas under the gate, thereby achieving a positive threshold voltage. The p-type doping concentration is 3*10 17 cm -3 The higher the concentration, the better the depletion effect on the gate, which is more conducive to achieving enhancement mode. The passivation layer is silicon nitride (SiN x ), with a thickness of 10nm, provides performance protection for the device.

[0086] According to the device parameters defined above, at the drain voltage V D =6V, the simulation results are as follows Figure 7 As shown, Figure 7 The transfer characteristic simulation test curve of the device provided in the embodiment of the present invention. Curve 1 in the figure represents the drain current of the device (denoted as I D ) with the gate voltage (denoted as V G ) changes, curve 2 represents the transconductance of the device (denoted as G m )With V G From curve 1, we can see that the threshold voltage V th At about 1V, the saturation current is close to 1800mA / mm. From curve 2, it can be seen that the transconductance Gm is close to 650mS / mm. Figure 7 On the surface, the device is an enhanced device with high current density, high transconductance and small series resistance, which is conducive to the preparation of low-loss and high-efficiency electronic devices.

[0087] The small signal characteristics are more important for the device frequency characteristic test. Therefore, this embodiment simulates the small signal characteristics of the device. The results are as follows: Figure 8 As shown, Figure 8 The frequency characteristic simulation test curve of the device provided by the embodiment of the present invention. The cut-off frequency f of the device T Reached 58.75GHz, the maximum frequency f max The frequency reaches 119.5GHz, which is about 10% higher than the performance of the same size device without full-coverage gate structure. Thanks to the excellent gate control capability, the cutoff frequency and maximum frequency of this device are at a relatively high level, which is suitable for making RF electronic devices with good gain and high performance.

[0088] The gallium nitride device of this embodiment forms a gate cap structure through the gate and the p-type layer. The gate cap structure enables the electronic device to achieve a positive gate control voltage, changing from a depletion mode to an enhancement mode, effectively solving the problem that excessive leakage current of the recessed gate HEMT device may affect the reliability and stability of the device, while enhancing the electrical and thermal stability of the device, achieving high versatility of the device, simplifying the integrated circuit design, and helping to reduce the difficulty of peripheral circuit design.

[0089] In the gallium nitride device of this embodiment, the gate covers the upper surface of the p-type layer and at least one side surface of the p-type layer to form a covered gate structure, which can solve the problem of poor gate control capability of the p-GaN gate, improve the frequency characteristics of the device, and significantly reduce the off-state leakage current of the device, thereby improving the electrical and thermal stability of the device, and can better cope with long-term applications.

[0090] In the gallium nitride device of the present invention, the thickness of the barrier layer is 2nm-10nm. The ultra-thin barrier layer can reduce the on-resistance while ensuring high current density, significantly improve the transconductance characteristics and small signal performance of the device, and improve the high-frequency response of the radio frequency device. While improving the frequency characteristics, it is conducive to realizing the integration of the radio frequency device.

[0091] Therefore, the gallium nitride device of this embodiment overcomes the problems brought about by the groove gate structure and the GaN HEMT using a silicon carbide substrate in the prior art, and while maintaining high performance and high stability, significantly reduces the manufacturing cost and design complexity, achieves higher safety and application convenience, and provides an ideal solution for the integration and miniaturization of modules and equipment, and has broad application prospects and economic benefits.

[0092] Embodiment 2

[0093] Based on the first embodiment, this embodiment provides a method for preparing a gallium nitride device.

[0094] See also Fig. 9 , Fig. 9A schematic flow chart of a method for preparing a gallium nitride device provided in an embodiment of the present invention. The method for preparing a gallium nitride device comprises the following steps:

[0095] S1. Provide an epitaxial wafer, wherein the epitaxial wafer includes a substrate, a buffer layer, a channel layer and a barrier layer stacked in sequence from bottom to top.

[0096] First, the epitaxial wafer is cleaned. Due to environmental factors, inorganic and organic compounds such as dust and oil will inevitably be introduced. These inconspicuous stains have a huge impact on process stability. Cleaning organic and inorganic stains on the epitaxial wafer is conducive to further epitaxial growth and improved process stability. The solvents and solvent combinations for cleaning the epitaxial wafer are not limited, and can be various acids, bases, and organic solvents. At the same time, the order of cleaning is not limited. Exemplarily, acetone, isopropanol, and stripping liquid can be used to remove impurities from the epitaxial wafer. Ultrasonic assisted cleaning is used during the process, and finally it is cleaned with ultrapure water and blown dry with nitrogen (N2).

[0097] For example, the buffer layer, channel layer and barrier layer in the epitaxial wafer are epitaxially grown on a substrate by MOCVD, MBE and other techniques, and the substrate, buffer layer, channel layer and barrier layer are made of Si, Al and Si, respectively. 0.03 GaN, GaN, AlN.

[0098] S2. epitaxially grow a p-type material on the barrier layer, and etch away the p-type material in the non-gate region to form a p-type layer.

[0099] First, p-type GaN is epitaxially grown as the p-type layer using MOCVD technology, where ammonia (NH3) is used as a nitrogen source, trimethylgallium (TMGa) is used as a gallium source, cyclopentadienyl magnesium (Cp2Mg) is used as a magnesium source, and hydrogen (H2) is used as a carrier gas. The thickness of the p-type layer can be 20nm-100nm. Through the p-type doped GaN material, the rectification characteristics can be effectively provided and the device can be turned into an enhancement type.

[0100] Then etch the p-type GaN. The purpose of using p-GaN is to deplete the two-dimensional electron gas under the gate, and the p-GaN in the non-gate part will affect the current concentration. This step requires precise control of the accuracy and uniformity of etching, and only retains the p-GaN material in the gate cap part. Etching too deep will destroy the barrier layer and reduce the current density; etching too shallowly will retain part of the p-GaN, which will have a depletion effect and reduce the current density. Therefore, this embodiment uses inductively coupled plasma etching and uses a two-etching process to etch away the p-GaN material in the non-gate cap part to ensure the uniformity and depth control of the etching. Among them, the two-etching process refers to a fast etching + slow etching process. The fast etching is to ensure that most of the p-GaN material can be etched away, and the slow etching is to minimize the etching amount of AlGaN. Using two etchings can achieve a better etching quality in a shorter time.

[0101] S3. Depositing source metal and drain metal on the barrier layer, and performing rapid thermal annealing to form a source and a drain, wherein the source and the drain are distributed on both sides of the p-type layer.

[0102] Optionally, the source and drain electrode metals can be deposited using electron beam evaporation or sputtering. The rapid thermal annealing temperature is not limited and can be 800-1000 degrees Celsius. The gas atmosphere must be nitrogen. After rapid annealing, a good ohmic contact can be formed to ensure the stability and quality of the ohmic contact production and reduce the on-resistance.

[0103] Exemplarily, after cleaning the substrate surface, the substrate is transferred to a sputtering machine to prepare for a metal evaporation process, and the ohmic metal combination that can be selected is Ti / Al / Ni / Au. After the evaporation is completed, the metal is stripped and annealed using a rapid thermal annealing process to form a source and a drain.

[0104] S4. Isolate the non-device area.

[0105] Specifically, there may be leakage current between adjacent devices, which will affect the reliability of the devices. Therefore, the mesa isolation process is implemented by the mesa etching method, and an isolation area groove with a depth greater than the channel is etched between the devices to completely block the conductive channel between the devices.

[0106] S5. Prepare a passivation layer on the barrier layer between the p-type layer and the source electrode and on the barrier layer between the p-type layer and the drain electrode.

[0107] Optionally, the passivation layer can be grown by LPCVD, PECVD, ALD and other methods. The uniformity and density of the passivation layer grown by different methods are different, and the environmental conditions for growth are also different. The thickness and composition of the passivation layer film growth are not limited, and the proportion of the passivation layer material can be adjusted to optimize the film properties as needed.

[0108] Specifically, silicon nitride (SiN) is grown on the surface of the device by a PECVD process. x ) material as a passivation layer. The passivation layer can prevent the device from being oxidized or contaminated, and can also protect the device to maintain stability, effectively suppress the current collapse phenomenon that occurs when HEMT is working, suppress the influence of material defects and surface states on the device, and to a certain extent can increase the intensity of the polarization effect and slightly increase the current density.

[0109] S6. Open holes in the gate region, the source region, and the drain region on the passivation layer.

[0110] Specifically, during the surface passivation process, the gate region, source region, and drain region are all covered by silicon nitride (SiNx) materials, and gate metal cannot be deposited, nor can electrodes be drawn out for testing. Therefore, ICP technology is used to perform hole etching in the gate region, source region, and drain region of the passivation layer to expose the source, drain, and gate regions. After etching is completed, the device is cleaned.

[0111] S7. Prepare a gate on the upper surface of the p-type layer and at least one side surface of the p-type layer, so that a portion of the gate on the side surface of the p-type layer contacts the barrier layer.

[0112] Specifically, a thick gate process is used to evaporate gate metal in the gate area to ensure that the gate has sufficient thickness and stability. During evaporation, the gate width direction needs to be parallel to the plating disk radius direction to ensure the accuracy and consistency of the gate structure.

[0113] S8. Make interconnected metal.

[0114] Specifically, interconnecting metal lead-out electrodes are fabricated on the source metal, drain metal and evaporated gate metal exposed by the openings, which is beneficial for testing the electrical characteristics of the device. Thus, the preparation of the GaN HEMT is completed.

[0115] Furthermore, the prepared GaN HEMT can be packaged into a single chip or integrated into a module (RF, power) and applied to a complete system.

[0116] It should be noted that the order of the process steps in the above-mentioned preparation method can be adjusted. For example, the gate metal deposition can be performed before the passivation layer is grown.

[0117] In the preparation method of this embodiment, the gate is directly prepared on the surface of the device, avoiding the use of an etching process to form a groove gate, thereby avoiding damage and surface roughness caused by the etching process, reducing the leakage current of the device, enhancing the thermal and electrical stability of the device, and extending the service life of the device. The preparation method of this embodiment simplifies the production process, reduces the overall manufacturing cost, and improves the feasibility of mass production.

[0118] Embodiment 3

[0119] Based on the first and second embodiments, this embodiment provides a module and a device.

[0120] The module of this embodiment includes one or more transistor devices described in the first embodiment, wherein at least one transistor device adopts the gallium nitride device described in the first embodiment.

[0121] Optionally, the module can be designed as a power module for realizing a buck-boost power supply module, a switching power supply module, etc. Using the gallium nitride device provided in the first embodiment in these power modules can significantly improve the reliability and integration of the module, making it more suitable for high-efficiency power management applications, for example, using the gallium nitride device of the first embodiment in a DC-DC voltage conversion circuit.

[0122] Optionally, the module may be a radio frequency module, which may include one or more gallium nitride devices provided in Embodiment 1. Suitable for scenarios such as initial communications, radio frequency identification and positioning systems, transistor components in the radio frequency module, such as power amplifiers (PA), are used to achieve high linearity and extend service life. Optionally, the radio frequency module may also include a low noise amplifier (LNA) and a switch (SW) circuit to enhance the efficiency and quality of signal processing.

[0123] Optionally, the module can also be an integrated RF front-end module, such as PAMiD (RF front-end integrated module of power amplifier, switch, filter) or L-PAMiD (RF front-end module with low noise amplifier). These modules integrate multiple RF functions and provide one-stop RF solutions. They process signal amplification, conversion and modulation through transistor components to ensure high efficiency and high quality of communication equipment during transmission.

[0124] The device of this embodiment includes any one of the above modules, which is conducive to achieving integration, high reliability and high stability.

[0125] Taking a device including a power module as an example, the device may be any device that needs power supply, such as automotive electronic equipment. Taking a device including a radio frequency module as an example, the device may be a router device.

[0126] The module and device of this embodiment include gallium nitride devices, which can improve the operating current and stability while reducing the difficulty of circuit design, reducing the size of the device, and simplifying the process flow, thereby effectively reducing production costs.

[0127] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A gallium nitride device, characterized in that: include: substrate, buffer layer, channel layer, barrier layer, p-type layer, gate, source and drain, wherein: The substrate, the buffer layer, the channel layer, and the barrier layer are stacked in sequence from bottom to top; The p-type layer is located on the barrier layer; The gate covers the upper surface of the p-type layer and at least one side surface of the p-type layer and is in contact with the barrier layer, and the gate and the p-type layer form a gate cap structure; The source electrode and the drain electrode are located on the barrier layer and are distributed on both sides of the gate cap structure.

2. The gallium nitride device according to claim 1, characterized in that: The gate comprises a fully encapsulated structure, and the fully encapsulated structure covers the upper surface of the p-type layer and two side surfaces of the p-type layer; The fully encapsulated structure forms a Schottky contact with the barrier layer, and forms a Schottky contact with at least a portion of the contact surface between the fully encapsulated structure and the p-type layer.

3. The gallium nitride device according to claim 2, characterized in that: The fully encapsulated structure is a Schottky gate metal, and Schottky contacts are formed between the Schottky gate metal and the barrier layer and the p-type layer.

4. The gallium nitride device according to claim 2, characterized in that: The fully encapsulated structure includes an ohmic gate metal and a Schottky gate metal, wherein: The ohmic gate metal is located on the upper surface of the p-type layer; The Schottky gate metal extends from both sides of the ohmic gate metal to a first side surface and a second side surface of the p-type layer respectively until contacting the barrier layer, wherein the first side surface and the second side surface are opposite to each other.

5. The gallium nitride device according to claim 4, characterized in that: Along the extension direction of the p-type layer, the shape of the ohmic gate metal includes a straight line shape, an S shape or a Z shape; The contact area between the ohmic gate metal and the p-type layer accounts for 0%-20% of the total contact area between the full-encapsulation structure and the p-type layer.

6. The gallium nitride device according to claim 1, characterized in that: The gate comprises a semi-encapsulated structure, wherein the semi-encapsulated structure covers the upper surface of the p-type layer and the first side surface of the p-type layer, or covers the upper surface of the p-type layer and the second side surface of the p-type layer; The semi-encapsulated structure is a Schottky gate metal or an Ohmic gate metal.

7. The gallium nitride device according to claim 1, characterized in that: The gallium nitride device is a rectangular device; The material of the substrate includes one or more of silicon, silicon carbide, sapphire, diamond, and aluminum nitride; The material of the buffer layer includes one or more of GaN and AlGaN, and the thickness is 200nm-8000nm; The material of the channel layer includes GaN, and the thickness is 50nm-800nm; The barrier layer includes one or more materials selected from AlN, AlGaN, and AlScN, and has a thickness of 2nm-10nm; The material of the p-type layer includes p-GaN, and the doping element includes Mg, with a doping concentration of 10 17 -10 19 cm 3 , thickness is 20nm-100nm; The width of the gate is 50nm-500nm; the width of the gate covering the side of the p-type layer is 0nm-200nm; The material of the source electrode and the drain electrode includes one or more of gold, titanium, nickel, and aluminum.

8. A method for preparing a gallium nitride device, characterized in that: Includes steps: Providing an epitaxial wafer, wherein the epitaxial wafer comprises a substrate, a buffer layer, a channel layer and a barrier layer stacked in sequence from bottom to top; Epitaxially growing a p-type material on the barrier layer, and etching away the p-type material in the non-gate region to form a p-type layer; Depositing source metal and drain metal on the barrier layer, and performing rapid thermal annealing to form a source and a drain, wherein the source and the drain are distributed on both sides of the p-type layer; A gate is formed on the upper surface of the p-type layer and at least one side surface of the p-type layer, so that a portion of the gate on the side surface of the p-type layer contacts the barrier layer.

9. A module, characterized in that: Comprising the gallium nitride device as described in any one of claims 1 to 7, the module comprises a power module, a radio frequency module, and an integrated radio frequency front-end module.

10. A device, characterized in that: Comprising the module as claimed in claim 9.

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