Semiconductor device, preparation method, power module, conversion circuit and vehicle

Abstract

The invention discloses a semiconductor device, a preparation method, a power module, a conversion circuit and a vehicle. The preparation method of the semiconductor device comprises the steps of forming a semiconductor body; the semiconductor body comprises a first surface and a second surface which are opposite, and the first surface comprises a first area surface and a second area surface; forming a first contact region on the surface of the first region of the semiconductor body, forming a body region on one side, close to the second surface, of the first contact region, and forming a planar gate structure on one side, away from the second surface, of the first contact region; the first contact region comprises a first electrode contact region and a channel region which are connected, and the plane gate structure covers the channel region; forming a contact metal layer on the surface of the second region of the semiconductor body; the contact metal layer forms a Schottky contact with the second region surface of the semiconductor body. According to the technical scheme provided by the invention, the preparation method of the semiconductor device is simplified, and the energy loss of the device in a reverse freewheeling state is reduced.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor technology, and in particular to a semiconductor device, a manufacturing method, a power module, a conversion circuit, and a vehicle. Background Art

[0002] As a representative of third-generation semiconductor materials, silicon carbide (SiC) possesses excellent physical and electrical properties. Compared to silicon, SiC has a wider bandgap, a higher breakdown electric field, higher thermal conductivity, a higher electron saturation rate, and strong radiation resistance. Therefore, semiconductor devices made with SiC can not only operate stably at higher temperatures, but are also suitable for high-voltage and high-frequency applications.

[0003] Power Metal-Oxide-Semiconductor-Field-Effect-Transistor (MOSFET) is widely used in the field of high speed and high power. The MOS device made of SiC material commonly used in related technologies is an enhancement-mode device. The enhancement-mode device is not conductive under normal conditions, and a positive voltage needs to be applied to the gate to make the device conductive. The depletion-mode MOS device is conductive under normal conditions, and a negative voltage needs to be applied to the gate to cut off the device channel in the cut-off state. Therefore, the depletion-mode MOS device can respond and control the current flow faster, has less conduction loss, and is more suitable for high-frequency circuits and switching circuits. In the current preparation method of depletion-type planar MOS devices, an external anti-parallel diode is usually connected to the depletion-type planar MOS device for reverse freewheeling. However, the external anti-parallel diode of the depletion-type planar MOS device increases the difficulty of device preparation, and the conduction voltage drop of the diode is large, and the energy loss of the device in the reverse freewheeling state is large, which affects the performance of the device. Summary of the Invention

[0004] Embodiments of the present invention provide a semiconductor device, a manufacturing method, a power module, a conversion circuit, and a vehicle to reduce the difficulty of manufacturing the semiconductor device and reduce the energy loss of the device in a reverse freewheeling state.

[0005] According to one aspect of the present invention, there is provided a semiconductor device comprising:

[0006] A semiconductor body; the semiconductor body includes a first surface and a second surface disposed opposite to each other, the first surface including a first region surface and a second region surface; wherein the semiconductor body includes a first contact region located on the first region surface and a body region located on a side of the first contact region close to the second surface; the first contact region includes a first electrode contact region and a channel region connected to each other;

[0007] a planar gate structure, located on a side of the first contact region away from the second surface and covering a channel region of the first contact region;

[0008] The contact metal layer is located on the surface of the second region of the semiconductor body, and the contact metal layer forms a Schottky contact with the surface of the second region of the semiconductor body.

[0009] Optionally, the semiconductor device further includes:

[0010] a first electrode located on a surface of the first region of the semiconductor body and in contact with a first electrode contact region of the first contact region;

[0011] a gate electrode, located on a surface of the first region of the semiconductor body and in contact with the planar gate structure;

[0012] Wherein, the first electrode, the gate electrode and the contact metal layer are arranged in the same layer.

[0013] Optionally, the semiconductor device further includes:

[0014] a second contact region, the second contact region being located on a side of the first electrode contact region away from the channel region and located on a surface of the first region of the semiconductor body; the first contact region and the second contact region having different conductivity types;

[0015] The first electrode is also in contact with the second contact region.

[0016] Optionally, the first surface further includes a third area surface;

[0017] The semiconductor body further includes a body diode, and a second conductive type region of the body diode is located on the surface of the third region.

[0018] Optionally, the surface of the first region further includes a JEFT region, which is located on a side of the channel region away from the first electrode contact region and contacts the side surface of the body region; the first contact region and the JEFT region have different conductivity types.

[0019] According to another aspect of the present invention, there is provided a method for preparing a semiconductor device, comprising:

[0020] forming a semiconductor body; the semiconductor body comprising a first surface and a second surface opposite to each other, the first surface comprising a first region surface and a second region surface;

[0021] forming a first contact region on the surface of the first region of the semiconductor body, forming a body region on a side of the first contact region close to the second surface, and forming a planar gate structure on a side of the first contact region away from the second surface; wherein the first contact region includes a first electrode contact region and a channel region connected to each other, and the planar gate structure covers the channel region;

[0022] A contact metal layer is formed on the surface of the second region of the semiconductor body; the contact metal layer forms a Schottky contact with the surface of the second region of the semiconductor body.

[0023] Optionally, while forming a contact metal layer on the surface of the second region of the semiconductor body, the method further comprises:

[0024] A first electrode is formed on the surface of the first region of the semiconductor body and is in contact with the first electrode contact region. A gate electrode is formed on a side of the planar gate structure away from the semiconductor body and is in contact with the planar gate structure.

[0025] Optionally, forming a first contact region on the surface of the first region of the semiconductor body, forming a body region on a side of the first contact region close to the second surface, and forming a planar gate structure on a side of the first contact region away from the second surface, comprising:

[0026] forming a first mask layer on the first surface of the semiconductor body, and patterning the first mask layer to form at least one first opening in the first mask layer exposing the surface of the first region;

[0027] Based on the patterned first mask layer, implanting ions of the second conductive type into the surface of the first region of the semiconductor body to form an initial body region;

[0028] implanting first conductive type ions based on the patterned first mask layer to form a first sub-region of the first contact region on the surface of the initial body region;

[0029] forming a barrier layer on a sidewall of the first opening to form a second opening in the first opening having a width smaller than that of the first opening;

[0030] Implanting first conductive type ions into the surface of the first region exposed by the second opening to form a first electrode contact region of the first contact region on a side of the first sub-region close to the second surface; wherein the first sub-region not exposed by the second opening is used as the channel region, and the ion doping concentration of the channel region is greater than the ion doping concentration of the first electrode contact region; and the region of the initial body region not implanted with the first conductive type ions is used as the body region;

[0031] The first mask layer is removed, and the planar gate structure is formed on the surface of the first region of the semiconductor body.

[0032] Optionally, the method for preparing the semiconductor device further includes:

[0033] A second contact region is formed on the surface of the first region of the semiconductor body; the second contact region is located on a side of the first electrode contact region away from the trench in the channel region and has a different conductivity type from that of the first contact region.

[0034] Optionally, forming a second contact region on the surface of the first region of the semiconductor body includes:

[0035] After removing the first mask layer, forming a second mask layer on the first surface of the semiconductor body, and patterning the second mask layer to form a third opening in the second mask layer that exposes a predetermined position of the second contact region;

[0036] Ions of the second conductive type are implanted based on the patterned second mask layer to form the second contact region, and the second mask layer is removed.

[0037] Optionally, the patterned first mask layer includes at least one pair of first openings exposing the surface of the first region, and the two first openings in the same pair are adjacent to each other;

[0038] The patterned second mask layer has a third opening in the middle area of ​​each pair of two first openings exposing the surface of the first region, and the width of the third opening is greater than or equal to the width between the two second openings respectively located in the corresponding two first openings.

[0039] Optionally, the method for preparing the semiconductor device further includes:

[0040] forming a JEFT region on the surface of the first region, the JEFT region being located on a side of the channel region away from the first electrode contact region and in contact with a side surface of the body region; the first contact region and the JEFT region have different conductivity types;

[0041] The JEFT region is formed on the surface of the first region, comprising:

[0042] After removing the second mask layer, forming a third mask layer on the first surface of the semiconductor body, and patterning the third mask layer to form a plurality of fourth openings in the third mask layer that expose predetermined positions of the JEFT region;

[0043] Based on the patterned third mask layer, second conductive ions are implanted into the surface of the first region to form the JEFT region, and the third mask layer is removed.

[0044] Optionally, the first surface further includes a third region surface, and while forming the initial body region, it also includes:

[0045] Implanting second conductive type ions into the surface of the third region to form a second conductive type region of the body diode;

[0046] While forming the second contact area, the method further comprises:

[0047] The second conductive type ions are implanted again into the second conductive type region of the body diode to increase the ion doping concentration on the surface of the second conductive type region of the body diode.

[0048] Optionally, forming the planar gate structure includes:

[0049] forming a gate insulating layer on the first surface of the semiconductor body;

[0050] forming a polysilicon gate layer on a side of the gate insulating layer away from the gate insulating layer and away from the semiconductor body;

[0051] patterning the polysilicon gate layer to form a polysilicon gate at least above the channel region;

[0052] The gate insulating layer is patterned to form an opening in the gate insulating layer that exposes at least a portion of the first electrode contact region.

[0053] Optionally, before forming a gate electrode in contact with the planar gate structure and a first electrode in contact with the first contact region on the surface of the first region of the semiconductor body, the method further includes:

[0054] A passivation layer is formed on the surface of the first region of the semiconductor body, and a first electrode connection port exposing the first contact region and a gate connection port exposing the gate structure are formed in the passivation layer.

[0055] According to another aspect of the present invention, a power module is provided, comprising a substrate and at least one semiconductor device according to any one embodiment of the present invention, wherein the substrate is used to support the semiconductor device.

[0056] According to another aspect of the present invention, there is provided a power conversion circuit, the power conversion circuit being used for one or more of current conversion, voltage conversion, and power factor correction;

[0057] The power conversion circuit includes a circuit board and at least one semiconductor device according to any embodiment of the present invention, and the semiconductor device is electrically connected to the circuit board.

[0058] According to another aspect of the present invention, a vehicle is provided, comprising a load and a power conversion circuit as described in any embodiment of the present invention, wherein the power conversion circuit is configured to convert alternating current (AC) into direct current (DC), convert DC into DC, or convert DC into AC, and then input the converted DC into AC, and then input the converted DC into the load.

[0059] The technical solution provided by the embodiment of the present invention integrates a Schottky barrier diode (SBD) within the semiconductor device body. Compared with a diode connected in anti-parallel outside the semiconductor device body for reverse freewheeling, the Schottky barrier diode can be formed at the same time as a depletion-type planar MOS device is prepared, thereby simplifying the device preparation process and avoiding the increase in device packaging cost and stray inductance caused by external parallel SBD, thereby preventing the degradation of the device switching characteristics. In addition, during reverse freewheeling, since the turn-on voltage of the Schottky diode is lower than that of the PN junction diode, the integrated Schottky diode is turned on before the body diode, and current flows through the Schottky junction, greatly reducing the energy loss of the device in the reverse freewheeling state.

[0060] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0062] Figure 1 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention;

[0063] Figure 2 is a flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0064] Figure 3 1 is a schematic structural diagram corresponding to step S10 in a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0065] Figure 4 1 is a schematic structural diagram corresponding to step S20 in a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0066] Figure 52 is a schematic structural diagram corresponding to step S210 in a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0067] Figure 6 2 is a schematic structural diagram corresponding to step S220 in a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0068] Figures 7 and 8 2 is a schematic structural diagram corresponding to step S2301 in a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0069] Figure 9 2 is a schematic structural diagram corresponding to step S230 in a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0070] Figures 10 and 11 2 is a schematic structural diagram corresponding to step S240 in a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0071] Figure 12 2 is a schematic structural diagram corresponding to step S250 in a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0072] Figure 13 2 is a schematic structural diagram corresponding to step S260 in a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0073] Figures 14 to 17 2 is a schematic structural diagram corresponding to steps S2601 to S2604 in a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0074] Figure 18 It is a structural schematic diagram corresponding to step S270 in a method for manufacturing a semiconductor device provided by an embodiment of the present invention.

[0075] Figure 19 It is a schematic structural diagram corresponding to the formation of a passivation layer in a method for preparing a semiconductor device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0076] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0077] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0078] An embodiment of the present invention further provides a semiconductor device, Figure 1 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention, with reference to Figure 1 , semiconductor devices include:

[0079] The semiconductor body 1 includes a first surface 11 and a second surface 12 disposed opposite to each other, wherein the first surface 11 includes a first region surface and a second region surface; wherein the semiconductor body 1 includes a first contact region 22 located on the first region surface and a body region 21 located on a side of the first contact region 22 close to the second surface 12; the first contact region 22 includes a first electrode contact region 221 and a channel region 222 connected to each other;

[0080] a planar gate structure 30 , located on a side of the first contact region 22 away from the second surface 12 and covering the channel region 222 of the first contact region 22 ;

[0081] The contact metal layer 70 is located on the surface of the second region of the semiconductor body 1 , and the contact metal layer 70 forms a Schottky contact with the surface of the second region of the semiconductor body 1 .

[0082] The semiconductor device of the embodiment of the present invention is a planar and depletion-mode semiconductor device. Under normal conditions, the depletion-mode device is conductive. Current flows through the second surface 12 of the semiconductor body 1, through the drift region 24, and along the channel region 222 in contact with the planar gate structure 30 to the first electrode contact region 221. When the depletion-mode device switches to the off state, a negative voltage is applied to the planar gate structure 30 to turn off the channel region 222 of the device. Therefore, the depletion-mode semiconductor device can respond more quickly and control current flow, with low conduction losses, making it more suitable for high-frequency circuits and switching circuits.

[0083] In addition, by integrating a Schottky barrier diode within the semiconductor device body, compared to a diode connected in anti-parallel outside the semiconductor device body for reverse freewheeling, a Schottky barrier diode can be formed at the same time as preparing a depletion-type planar gate MOS device, thereby simplifying the device preparation process and avoiding the increase in device packaging cost and stray inductance caused by external parallel SBD, thereby preventing the device switching characteristics from degrading; during reverse freewheeling, since the turn-on voltage of the Schottky diode 102 is lower than that of the PN junction diode, the integrated Schottky diode 102 is turned on before the body diode 103, and current flows through the Schottky junction, thereby greatly reducing the energy loss of the device in the reverse freewheeling state.

[0084] Optional, reference Figure 1 , semiconductor devices also include:

[0085] A first electrode is located on the surface of the first region of the semiconductor body 1 and contacts the first electrode contact region 221 of the first contact region 22;

[0086] The gate electrode G is located on the surface of the first region of the semiconductor body 1 and contacts the planar gate structure 30 ;

[0087] The first electrode, the gate electrode G and the contact metal layer 70 are provided in the same layer. The first electrode may be a source electrode S.

[0088] Optional, reference Figure 1 , semiconductor devices also include:

[0089] The second contact region 23 is located on a side of the first electrode contact region 221 away from the channel region 222 and on the surface of the first region of the semiconductor body 1. The conductivity type of the second contact region 23 is different from that of the first contact region 22. The first electrode also contacts the second contact region 23.

[0090] Optionally, the first surface 11 further includes a third region surface; the semiconductor body 1 further includes a body diode 103 , and the second conductivity type region of the body diode 103 is located on the third region surface.

[0091] Optional, please continue to refer to Figure 1 The surface of the first region further includes a JEFT region 25. The JEFT region 25 is located on a side of the channel region 222 away from the first electrode contact region 221. The JEFT region 25 covers a portion of the body region 21, and the JEFT region 25 that contacts the side surfaces of the body regions 21 is located between adjacent body regions 21. The first contact region 22 and the JEFT region 25 have different conductivity types. The surface of the JEFT region 25 away from the second surface 12 contacts the planar gate structure 30. The doping concentration of the second conductivity type ions in the JEFT region 25 is greater than the doping concentration of the second conductivity type ions in the drift region 24.

[0092] An embodiment of the present invention provides a method for manufacturing a semiconductor device, which is used to manufacture the semiconductor device according to any embodiment of the present invention. Figure 2 This is a flow chart of a method for preparing a semiconductor device provided by an embodiment of the present invention, with reference to Figure 2 , a method for preparing a semiconductor device includes:

[0093] S10 , forming a semiconductor body; the semiconductor body includes a first surface and a second surface opposite to each other, the first surface including a first region surface and a second region surface.

[0094] Specifically, the semiconductor body can be formed through a single epitaxial growth process or multiple epitaxial growth processes. That is, the semiconductor body can be a single semiconductor epitaxial layer or a stacked structure formed of multiple semiconductor epitaxial layers. The semiconductor body can also include a substrate, that is, the semiconductor body includes a substrate and at least one semiconductor epitaxial layer formed on one side of the substrate. The material of the substrate can be the same as the material of the semiconductor epitaxial layer, or the material of the substrate can be different from the material of the semiconductor epitaxial layer.

[0095] refer to Figure 3 Optionally, the material of the semiconductor body 1 may be SiC, that is, the semiconductor device in the embodiment of the present invention may be a planar SiC power device. The semiconductor body 1 includes a substrate 10 and at least one semiconductor epitaxial layer 20 formed on one side of the substrate 10. SiC has excellent physical and electrical properties. Compared with silicon materials, SiC materials have a large band gap and have the advantages of high breakdown electric field, high thermal conductivity, high electron saturation rate, and strong radiation resistance. Therefore, semiconductor devices made of SiC materials can not only operate stably at higher temperatures, but are also suitable for high voltage and high frequency scenarios.

[0096] The semiconductor body 1 includes a first surface 11 and a second surface 12 that are arranged opposite to each other. When the semiconductor body 1 includes only the semiconductor epitaxial layer 20, the second surface 12 is the surface of the semiconductor body 1 on the side close to the substrate 10, and the first surface 11 is the surface of the semiconductor body 1 on the side away from the substrate 10. When the semiconductor body 1 includes the substrate 10 and at least one semiconductor epitaxial layer 20, the second surface 12 is the surface of the substrate 10 on the side away from the semiconductor epitaxial layer 20, and the first surface 11 is the surface of the semiconductor epitaxial layer 20 that is farthest from the substrate 10 and is away from the substrate 10.

[0097] The first surface 11 includes a first region surface Q1 and a second region surface Q2. The first region surface Q1 and the second region surface Q2 may be adjacent to each other or spaced apart. It can be understood that the semiconductor body 1 includes a first region and a second region. The first region surface Q1 is the first surface 11 of the semiconductor body 1 located in the first region, and the second region surface Q2 is the first surface 11 of the semiconductor body 1 located in the second region. The semiconductor body 1 located in the first region is used to fabricate a planar MOS device, while the semiconductor body 1 located in the second region is used to form a Schottky diode.

[0098] S20. Form a first contact region on the surface of the first region of the semiconductor body, form a body region on a side of the first contact region close to the second surface, and form a planar gate structure on a side of the first contact region away from the second surface; wherein the first contact region includes a connected first electrode contact region and a channel region, and the planar gate structure covers the channel region.

[0099] Specifically, refer to Figure 4 The body region 21 can be formed by implanting ions of the second conductivity type into the surface of the semiconductor epitaxial layer 20 after forming the semiconductor epitaxial layer 20; the first contact region 22 is formed by implanting ions of the first conductivity type into the body region 21. The first contact region 22 includes a first electrode contact region 221 and a channel region 222 that are connected to each other.

[0100] The number of planar gate structures 30 formed on the first region surface Q1 of the semiconductor body 1 can be one or more. Each planar gate structure 30 covers at least one channel region 222 and has a certain overlap with the first electrode contact region 221, that is, the semiconductor device of the embodiment of the present invention includes at least one depletion-type planar SiC power device. The depletion-type device is conductive under normal conditions, and current flows in through the second surface 12 of the semiconductor body 1, flows through the drift region 24 along the channel region 222 in contact with the planar gate structure 30 to the first electrode contact region 221. When the depletion-type device switches to the cut-off state, a negative voltage is provided to the planar gate structure 30 to cut off the channel region 222 of the device. Therefore, the depletion-type semiconductor device can respond and control the current flow faster, has low conduction loss, and is more suitable for high-frequency circuits and switching circuits.

[0101] The conductivity type of the first contact region 22 is the same as that of the semiconductor body 1, and both are doped with ions of the first conductivity type. The ion doping concentration of the first contact region 22 is greater than that of the semiconductor body 1. The conductivity type of the body region 21 is different from that of the semiconductor body 1, and ions of the second conductivity type are doped in the body region 21. The semiconductor epitaxial layer 20 between the body region 21 and the second surface 12 serves as a drift region 24. The ions of the first conductivity type may be N-type doping ions, and the ions of the second conductivity type may be P-type doping ions; alternatively, the ions of the first conductivity type may be P-type doping ions, and the ions of the second conductivity type may be N-type doping ions. The N-type doping ions may be P (phosphorus) or N (nitrogen) ions, and the P-type doping ions may be Al (aluminum) ions or B (boron) ions. In embodiments of the present invention, the ions of the first conductivity type are N-type doping ions, and the ions of the second conductivity type are P-type doping ions.

[0102] Forming a planar gate structure 30 on the first surface Q1 of the semiconductor body 1 includes: forming a gate insulating layer 31 on the first surface 11 of the semiconductor body 1; forming a polysilicon gate layer on a side of the gate insulating layer 31 remote from the semiconductor body 1; patterning the polysilicon gate layer to form a polysilicon gate 32 located at least above the channel region 222; and patterning the gate insulating layer 31 to form an opening in the gate insulating layer 31 that exposes at least a portion of the first electrode contact region 221. The planar gate structure 30 includes a polysilicon gate 32 and a gate insulating layer 31 located between the polysilicon gate 32 and the semiconductor body 1. The material of the gate insulating layer 31 may include at least one of aluminum oxide and silicon oxide.

[0103] S30, forming a contact metal layer on the surface of the second region of the semiconductor body; the contact metal layer forms a Schottky contact with the surface of the second region of the semiconductor body.

[0104] Specifically, a Schottky diode is a low-power, high-current, ultra-high-speed semiconductor device manufactured using the metal-semiconductor junction principle formed by the contact between metal and semiconductor. A Schottky diode generally includes a cathode metal layer, a first conductive type substrate, a first conductive type epitaxial layer, a barrier metal or metal silicide, and an anode metal layer; the barrier metal or metal silicide and the first conductive type epitaxial layer form a Schottky contact. Figure 1 In this embodiment of the present invention, the semiconductor body 1 is a semiconductor layer of the first conductivity type, and the semiconductor body 1 in the second region is doped only with ions of the first conductivity type. At least the portion of the contact metal layer 70 adjacent to the semiconductor body 1 is a barrier metal or a metal silicide. The contact metal layer 70 is formed on the surface Q2 of the second region of the semiconductor body 1 and annealed, thereby forming a Schottky contact between the contact metal layer 70 and the surface Q2 of the second region of the semiconductor body 1, thereby forming a Schottky diode 102.

[0105] Optionally, the contact metal layer 70 includes not only the barrier metal or metal silicide but also an anode metal layer of the Schottky diode 102 .

[0106] Optional, please continue to refer to Figure 1 While forming the contact metal layer 70 on the second region surface Q2 of the semiconductor body 1, it also includes: forming a first electrode in contact with the first electrode contact region 221 on the first region surface Q1 of the semiconductor body 1, and forming a gate electrode G in contact with the planar gate structure 30 on a layer away from the semiconductor body 1, thereby simplifying the preparation process of the semiconductor device.

[0107] For example, the first electrode, the gate electrode G, and the contact metal layer 70 can be formed simultaneously by sequentially depositing a Ti layer, a TiN layer, and an Al layer, followed by metal etching. A second electrode (not shown) is further provided on the side of the semiconductor body 1 away from the first surface 11. The first electrode can be a source electrode S, and the second electrode can be a drain electrode D; alternatively, the first electrode can be a drain electrode D, and the second electrode can be a source electrode S. Figure 1 The first electrode is exemplarily shown as a source electrode S, and the second electrode is a drain electrode D. The cathode metal layer of the Schottky diode 102 can be electrically connected to or share the second electrode; the anode metal layer of the Schottky diode 102 can be electrically connected to or share the first electrode.

[0108] The method for preparing a semiconductor device provided by an embodiment of the present invention integrates a Schottky barrier diode within the semiconductor device body. Compared to a diode connected in anti-parallel outside the semiconductor device body for reverse freewheeling, a Schottky diode can be formed while preparing a depletion-type planar gate MOS device, thereby simplifying the device preparation process and avoiding the increase in device packaging cost and stray inductance caused by external parallel SBD, thereby preventing the degradation of the device switching characteristics. In addition, during reverse freewheeling, since the turn-on voltage of the Schottky diode 102 is lower than that of the PN junction diode, the integrated Schottky diode 102 is turned on before the body diode 103, and current flows through the Schottky junction, thereby greatly reducing the energy loss of the device in the reverse freewheeling state.

[0109] Based on the above embodiments, optionally, step S20 includes forming a first contact region on the surface of the first region of the semiconductor body, forming a body region on a side of the first contact region close to the second surface, and forming a planar gate structure on a side of the first contact region away from the second surface, including:

[0110] S210 , forming a first mask layer on a first surface of the semiconductor body, and patterning the first mask layer to form at least one first opening in the first mask layer that exposes a surface of the first region.

[0111] Specifically, refer to Figure 5 PECVD (Plasma Enhanced Chemical Vapor Deposition) can be used to deposit SiO2 to form the first mask layer 100; the first mask layer 100 is patterned by photolithography. The photolithography process is an important step in the semiconductor device manufacturing process. This step uses exposure and development to depict geometric structures on the photoresist layer, and then the pattern of the photoresist layer is transferred to the first mask layer 100 by an etching process to achieve patterning of the first mask layer 100. The width of the first opening 01 located on the first region surface Q1 is equal to or less than the width of the first region surface Q1. Figure 5 As exemplarily shown, the width of the first opening 01 is smaller than the width of the first region surface Q1 , and the first mask layer 100 includes four first openings 01 exposing the first region surface Q1 .

[0112] S220 , based on the patterned first mask layer, implant second conductive type ions into the surface of the first region of the semiconductor body to form an initial body region.

[0113] Specifically, refer to Figure 6 Based on the patterned first mask layer 100, the second conductive type ions are implanted into the first region surface Q1 of the semiconductor body 1 to form an initial body region 211. The initial body region 211 located on the first region surface Q1 is a film layer formed during the preparation of the semiconductor device, and the body region 21 is formed on the basis of the initial body region 211. In the embodiment of the present invention, the initial body region 211 is a doped region formed by implanting the second conductive type ions into the surface of the semiconductor epitaxial layer 20 after the semiconductor epitaxial layer 20 is formed; compared with the method of doping the second conductive type ions into the epitaxial material during the epitaxial process, the embodiment of the present invention can enable the semiconductor epitaxial layer 20 used to prepare the initial body region 211 and the semiconductor epitaxial layer 20 used to prepare the Schottky diode 102 to be formed in the same epitaxial process, thereby simplifying the preparation process of the semiconductor device.

[0114] Optionally, the semiconductor body further includes a third region, and the first surface 11 further includes a third region surface Q3 ; the third region of the semiconductor body is used to prepare the body diode 103 .

[0115] Reference Figure 5In step S210, the first mask layer 100 is patterned to form at least one first opening 01 exposing the first region surface Q1 in the first mask layer 100. The process also includes forming at least one first opening 01 exposing the third region surface Q3 in the first mask layer 100. The third region surface Q3 may be located between the first region surface Q1 and the second region surface Q2, or on a side of the second region surface Q2 away from the first region surface Q1. The positions and number of the first region surface Q1, the second region surface Q2, and the third region surface Q3 may be set according to actual needs.

[0116] refer to Figure 6 In step S220, based on the patterned first mask layer 100, second conductivity type ions are implanted into the first region surface Q1 of the semiconductor body 1 to form the initial body region 211. Simultaneously, second conductivity type ions are implanted into the third region surface Q3 of the semiconductor body 1 to form the second conductivity type region 1021 of the body diode 103. The simultaneous fabrication of the initial body region 211 and the second conductivity type region 1021 of the body diode 103 can simplify the fabrication process of the semiconductor device.

[0117] In the embodiment of the present invention, in step S230, the first conductive type ions are implanted based on the patterned first mask layer 100, and before the first sub-region of the first contact region 22 is formed on the surface of the initial body region 211, the following steps are also included:

[0118] S2301 , forming a barrier layer on a surface of the first mask layer away from the semiconductor body, in the first opening, and on the first surface of the semiconductor body exposed by the first opening, and removing the barrier layer located above the surface of the first region.

[0119] Specifically, refer to Figure 7 and Figure 8 A barrier layer 40 is formed on the surface of the first mask layer 100 away from the semiconductor body 1, in the first opening 01, and on the first surface 11 of the semiconductor body 1 exposed by the first opening 01. The barrier layer 40 located above the first region surface Q1 is removed, and the barrier layer 40 located outside the first region surface Q1 is retained, so that the barrier layer 40 can cover the third region surface Q3 of the semiconductor body 1. Therefore, in the subsequent step 230, when the first conductive type ions are implanted based on the patterned first mask layer 100 to form the first sub-region of the first contact region 22, the barrier layer 40 can prevent the first conductive type ions from being implanted into the third region surface Q3. The material of the barrier layer 40 can be different from that of the first mask layer 100, thereby reducing the impact on the first mask layer 100 during the patterning process of the barrier layer 40. The material of the barrier layer 40 can be polycrystalline silicon.

[0120] S230 , implanting first conductive type ions based on the patterned first mask layer to form a first sub-region of the first contact region on the surface of the initial body region.

[0121] Specifically, refer to Figure 9 First conductive type ions are implanted based on the patterned first mask layer 100 to form a first sub-region 201 of the first contact region 22 on the surface of the initial body region 211. The thickness of the first sub-region 201 is less than that of the initial body region 21. The first sub-region 201 includes a channel region 222 and a portion of the first electrode contact region 221. The first sub-region 201 and the initial body region 211 are formed based on the same mask layer (first mask layer 100), which can simplify the manufacturing process of the semiconductor device.

[0122] S240 , forming a barrier layer on a sidewall of the first opening to form a second opening in the first opening whose width is smaller than that of the first opening.

[0123] Specifically, refer to Figure 10 and Figure 11 SiN material can be deposited to form a spacer layer 50 on the surface of the first mask layer 100 away from the semiconductor body 1, the sidewalls of the first opening 01, and the first surface 11 of the semiconductor body 1 exposed by the first opening 01. The spacer layer 50 located on the surface of the first mask layer 100 away from the semiconductor body 1 and the first surface 11 of the semiconductor body 1 exposed by the first opening 01 are then removed by a dry etching process, thereby forming a spacer layer 50 on the sidewalls of the first opening 01. The spacer layer 50 on one side of the first opening 01 can be retained, or the spacer layer 50 on opposite sides of the first opening 01 can be retained.

[0124] S250. Implant first conductive type ions into the surface of the first region exposed by the second opening to form a first electrode contact region of the first contact region on the surface of the first region exposed by the second opening; wherein the first sub-region not exposed by the second opening is used as a channel region, and the ion doping concentration of the channel region is greater than the ion doping concentration of the first electrode contact region; the region of the initial body region into which the first conductive type ions are not implanted is used as a body region.

[0125] Specifically, refer to Figure 12, the first conductive type ions are implanted again on the first region surface Q1 exposed by the second opening 02, forming the first electrode contact region 221 of the first contact region 22. The first sub-region 201 (the first sub-region 201 located below the spacer layer 50) not exposed by the second opening 02 is used as the channel region 222; the area of ​​the initial body region 211 not implanted with the first conductive type ions is used as the body region 21; the ion doping concentration of the channel region 222 is greater than the ion doping concentration of the first electrode contact region 221. In this embodiment of the present invention, the spacer layer 50 is retained on opposite sides of the first opening 01, so that channel regions 222 are formed on opposite sides of the first electrode contact region 221.

[0126] S260 , removing the first mask layer.

[0127] Specifically, refer to Figure 13 The first mask layer 100 of the silicon dioxide material can be etched away with a hydrofluoric acid solution to expose the first surface 11 of the semiconductor body 1, thereby forming a planar gate structure 30 on the first region surface Q1 of the semiconductor body 1. Optionally, before etching away the first mask layer of the silicon dioxide material with the hydrofluoric acid solution, the barrier layer 40 can be removed with a nitric acid solution.

[0128] Based on the above embodiments, the method for manufacturing a semiconductor device may optionally further include: forming a second contact region 23 on the first region surface Q1 of the semiconductor body 1; the second contact region 23 is located on a side of the first electrode contact region 221 away from the trench of the channel region 222. The second contact region 23 is doped with ions of the second conductivity type, and the ion doping concentration in the second contact region 23 is greater than the ion doping concentration in the body region 21.

[0129] The forming of the second contact region 23 on the first region surface Q1 of the semiconductor body 1 may include:

[0130] After removing the first mask layer 100 in step S260, the following steps are included:

[0131] S2601 , forming a second mask layer on the first surface of the semiconductor body, and patterning the second mask layer to form a third opening in the second mask layer that exposes a preset position of the second contact region.

[0132] Specifically, refer to Figure 14 , SiO 2 may be deposited by PECVD to form a second mask layer 200 , and the second mask layer 200 may be patterned by a photolithography process to form a third opening 03 in the second mask layer 200 to expose a predetermined position of the second contact region 23 .

[0133] Optional, reference Figure 5 and Figure 14The patterned first mask layer 100 includes at least one pair of first openings 01 exposing the first region surface Q1, with the two first openings 01 in the same pair adjacent to each other. The patterned second mask layer 200 can include a third opening 03 in the middle region between each pair of first openings 01 exposing the first region surface Q1. The number of third openings 03 exposing the first region surface Q1 in the patterned second mask layer 200 is the same as the number of pairs of first openings 01 exposing the first region surface Q1 in the first mask layer 100. Figure 5 The first mask layer 100 includes four first openings 01 exposing the first region surface Q1. Figure 14 The second mask layer 200 is shown to include two first openings 01 that expose the first region surface Q1. The width of the third opening 03 is greater than or equal to the width between the two second openings 02 in the corresponding pair of first openings 01, thereby ensuring that the sidewalls of the second contact region 23 formed based on the third opening 03 in step S2602 contact the sidewalls of the first electrode contact regions 221 located on opposite sides of the second contact region 23. The thickness of the second contact region 23 can be less than, equal to, or greater than the thickness of the initial body region 211.

[0134] S2602 , implanting second conductive type ions based on the patterned second mask layer 200 to form a second contact region 23 , and removing the second mask layer 200 .

[0135] Specifically, refer to Figure 15 The patterned second mask layer 200 exposes the predetermined position of the second contact region 23. Second conductivity type ions are implanted based on the patterned second mask layer 200, thereby forming the second contact region 23 at the predetermined position of the second contact region 23. The second mask layer 200 made of silicon dioxide can be etched away with a hydrofluoric acid solution, thereby exposing the first surface 11 of the semiconductor body 1.

[0136] Based on the above embodiments, while forming the second contact region 23 in step S2602 , the step further includes: injecting the second conductive type ions into the second conductive type region of the body diode 103 again to increase the ion doping concentration on the surface of the second conductive type region of the body diode 103 .

[0137] Specifically, refer to Figure 15In step S2601, a second mask layer 200 is formed on the first surface 11 of the semiconductor body 1 and patterned. While forming a third opening 03 in the second mask layer 200 to expose a predetermined position of the second contact region 23, the second mask layer 200 also includes forming a third opening 03 to expose the third region surface Q3. In step S2602, while forming the second contact region 23, second conductivity type ions may be implanted again into the second conductivity type region of the body diode 103 to increase the ion doping concentration on the surface of the second conductivity type region 1021 of the body diode 103.

[0138] Based on the above embodiments, optionally, the method for manufacturing a semiconductor device further includes: forming a second conductivity type JEFT (Junction Field Effect Transistor) region on the surface Q1 of the first region.

[0139] A JEF region is formed on the first region surface Q1, including:

[0140] After removing the second mask layer in step S2602, the following steps are included:

[0141] S2603, forming a third mask layer 300 on the first surface 11 of the semiconductor body 1, and patterning the third mask layer 300 to form a plurality of fourth openings 04 in the third mask layer 300 to expose predetermined positions of the second conductive type JFET regions. (Refer to Figure 16 )

[0142] S2604, based on the patterned third mask layer 300, the second conductive ions are implanted into the predetermined position of the JEFT area to form the JEFT area 25, and the third mask layer 300 is removed. (Refer to Figure 17 )

[0143] Among them, the JEFT region 25 is located on a side of the channel region 222 away from the first electrode contact region 221 and is arranged along the side walls of the channel region 222 and the body region 21; the doping concentration of the second conductive type ions in the JEFT region 25 is greater than the doping concentration of the second conductive type ions in the drift region 24.

[0144] S270 , forming a planar gate structure on the surface of the first region of the semiconductor body.

[0145] Specifically, forming the planar gate structure 30 on the first region surface Q1 of the semiconductor body 1 includes: forming a gate insulating layer 31 on the first surface 11 of the semiconductor body 1, and forming a polysilicon gate layer on a side of the gate insulating layer 31 away from the semiconductor body 1; patterning the polysilicon gate layer to form a polysilicon gate 32 located at least above the channel region 222, referring to Figure 18The vertical projection of the polysilicon gate 32 on the semiconductor body 1 covers at least the channel region 222. The vertical projection of the polysilicon gate 32 on the semiconductor body 1 may also cover the area of ​​the first electrode contact region 221 adjacent to the channel region 222, to ensure that the vertical projection of the polysilicon gate 32 on the semiconductor body 1 completely covers the channel region 222. The vertical projection of the polysilicon gate 32 on the semiconductor body 1 also covers at least a portion of the JEFT region 25. The gate insulating layer 31 is patterned to form an opening in the gate insulating layer 31 that exposes at least a portion of the first electrode contact region 221.

[0146] Based on the above embodiments, Figure 19 Optionally, after forming the planar gate structure 30 and before forming the gate electrode G in contact with the planar gate structure 30 and the first electrode in contact with the first contact region 22 on the surface Q1 of the first region of the semiconductor body 1, the method further includes:

[0147] A passivation layer 60 is formed on the first region surface Q1 of the semiconductor body 1 , and a first electrode connection port 61 exposing the first contact region 22 and a gate connection port 62 exposing the planar gate structure 30 are formed in the passivation layer 60 .

[0148] The patterning of the gate insulating layer 31 can be performed in the same process step as forming the connection ports in the passivation layer 60 , thereby simplifying the manufacturing process of the semiconductor device.

[0149] refer to Figure 1 A contact metal layer 70 is formed on the second region surface Q2 of the semiconductor body 1, and a gate electrode in contact with the planar gate structure 30 and a first electrode in contact with the first contact region 22 are formed on the first region surface Q1 of the semiconductor body 1; the contact metal layer 70 forms a Schottky contact with the second region surface Q2 of the semiconductor body 1.

[0150] An embodiment of the present invention further provides a power module comprising a substrate and at least one semiconductor device according to any embodiment of the present invention, wherein the substrate is used to support the semiconductor device. The power module has the same technical effects and will not be described in detail here.

[0151] An embodiment of the present invention further provides a power conversion circuit for one or more of current conversion, voltage conversion, and power factor correction. The power conversion circuit includes a circuit board and at least one semiconductor device as described in any embodiment of the present invention, the semiconductor device being electrically connected to the circuit board. The circuit has the same technical effects and is not further described here.

[0152] An embodiment of the present invention further provides a vehicle including a load and a power conversion circuit according to any embodiment of the present invention, wherein the power conversion circuit is configured to convert AC power to DC power, AC power to AC power, DC power to DC power, or DC power to AC power, and then input the converted power to the load. The embodiments have the same technical effects and are not further described here.

[0153] Note that the above are only preferred embodiments of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments and may include many other equivalent embodiments without departing from the concept of the present invention. The scope of the present invention is determined by the scope of the appended claims.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor body; the semiconductor body comprises a first surface and a second surface arranged opposite to each other, the first surface comprises a first region surface and a second region surface; wherein the semiconductor body comprises a first contact region located on the first region surface and a body region located on a side of the first contact region close to the second surface; the first contact region comprises a first electrode contact region and a channel region connected to each other; a planar gate structure, located on a side of the first contact region away from the second surface and covering a channel region of the first contact region; The contact metal layer is located on the surface of the second region of the semiconductor body, and the contact metal layer forms a Schottky contact with the surface of the second region of the semiconductor body.

2. The semiconductor device according to claim 1, wherein: Also includes: A first electrode, located on a surface of a first region of the semiconductor body and in contact with a first electrode contact region of the first contact region; A gate electrode, located on the surface of the first region of the semiconductor body and in contact with the planar gate structure; Wherein, the first electrode, the gate electrode and the contact metal layer are arranged in the same layer.

3. The semiconductor device according to claim 2, characterized in that Also includes: a second contact region, the second contact region being located at a side of the first electrode contact region away from the channel region and being located at a surface of the first region of the semiconductor body; The first contact region and the second contact region have different conductivity types; The first electrode is also in contact with the second contact region.

4. The semiconductor device according to claim 1, wherein: The first surface also includes a third zone surface; The semiconductor body also includes a body diode, and the second conductivity type region of the body diode is located on the surface of the third region.

5. The semiconductor device according to claim 1, wherein: The surface of the first region further includes a JEFT region, which is located on a side of the channel region away from the first electrode contact region and in contact with a side surface of the body region; the first contact region and the JEFT region have different conductivity types.

6. A method for preparing a semiconductor device, characterized in that: include: forming a semiconductor body; the semiconductor body comprising a first surface and a second surface opposite to each other, the first surface comprising a first region surface and a second region surface; A first contact region is formed on the surface of the first region of the semiconductor body, a body region is formed on a side of the first contact region close to the second surface, and a planar gate structure is formed on a side of the first contact region away from the second surface; wherein the first contact region includes a first electrode contact region and a channel region connected to each other, and the planar gate structure covers the channel region; A contact metal layer is formed on the surface of the second region of the semiconductor body; the contact metal layer forms a Schottky contact with the surface of the second region of the semiconductor body.

7. The method for preparing a semiconductor device according to claim 6, characterized in that: While forming a contact metal layer on the surface of the second region of the semiconductor body, the method further comprises: A first electrode in contact with the first electrode contact region is formed on the surface of the first region of the semiconductor body, and a gate electrode in contact with the planar gate structure is formed on a side of the planar gate structure away from the semiconductor body.

8. The method for preparing a semiconductor device according to claim 6, characterized in that: A first contact region is formed on the surface of the first region of the semiconductor body, a body region is formed on a side of the first contact region close to the second surface, and a planar gate structure is formed on a side of the first contact region away from the second surface, including: forming a first mask layer on the first surface of the semiconductor body, and patterning the first mask layer to form at least one first opening in the first mask layer that exposes the surface of the first region; Based on the patterned first mask layer, implanting second conductive type ions into the surface of the first region of the semiconductor body to form an initial body region; Implanting first conductive type ions based on the patterned first mask layer to form a first sub-region of the first contact region on the surface of the initial body region; forming a barrier layer on a sidewall of the first opening to form a second opening in the first opening whose width is smaller than that of the first opening; Implanting first conductive type ions into the surface of the first region exposed by the second opening, forming a first electrode contact region of the first contact region on the surface of the first region exposed by the second opening; wherein the first sub-region not exposed by the second opening is used as the channel region, and the ion doping concentration of the channel region is greater than the ion doping concentration of the first electrode contact region; and the region of the initial body region not implanted with first conductive type ions is used as the body region; The first mask layer is removed, and the planar gate structure is formed on the surface of the first region of the semiconductor body.

9. The method for preparing a semiconductor device according to claim 8, characterized in that: Also includes: A second contact region is formed on the surface of the first region of the semiconductor body; the second contact region is located on a side of the first electrode contact region away from the channel region and has a different conductivity type from that of the first contact region.

10. The method for preparing a semiconductor device according to claim 9, characterized in that: Forming a second contact region on the surface of the first region of the semiconductor body comprises: After removing the first mask layer, forming a second mask layer on the first surface of the semiconductor body, and patterning the second mask layer to form a third opening in the second mask layer that exposes a preset position of the second contact region; Implantation of second conductive type ions is performed based on the patterned second mask layer to form the second contact region, and the second mask layer is removed.

11. The method for preparing a semiconductor device according to claim 10, characterized in that: The patterned first mask layer comprises at least one pair of first openings exposing the surface of the first region, and the two first openings of the same pair are adjacently arranged; The patterned second mask layer has a third opening in the middle area of ​​each pair of two first openings exposing the surface of the first region, and the width of the third opening is greater than or equal to the width between the two second openings respectively located in the corresponding two first openings.

12. The method for preparing a semiconductor device according to claim 10, characterized in that: Also includes: forming a JEFT region on the surface of the first region, wherein the JEFT region is located on a side of the channel region away from the first electrode contact region and in contact with a side surface of the body region; The first contact region and the JEFT region have different conductivity types; Wherein, forming a JEFT region on the surface of the first region comprises: After removing the second mask layer, forming a third mask layer on the first surface of the semiconductor body, and patterning the third mask layer to form a plurality of fourth openings in the third mask layer that expose predetermined positions of the JEFT region; Based on the patterned third mask layer, second conductive ions are implanted into the surface of the first region to form the JEFT region, and then the third mask layer is removed.

13. The method for preparing a semiconductor device according to claim 10 or 12, characterized in that: The first surface also includes a third region surface, and while forming the initial body region, it also includes: Implanting second conductive type ions into the surface of the third region to form a second conductive type region of the body diode; While forming the second contact area, the method further comprises: The second conductive type ions are implanted again into the second conductive type region of the body diode to increase the ion doping concentration on the surface of the second conductive type region of the body diode.

14. The method for preparing a semiconductor device according to claim 6, characterized in that: Forming the planar gate structure includes: forming a gate insulating layer on a first surface of the semiconductor body; forming a polysilicon gate layer on a side of the gate insulating layer away from the gate insulating layer and away from the semiconductor body; Patterning the polysilicon gate layer to form a polysilicon gate at least located above the channel region; The gate insulating layer is patterned to form an opening in the gate insulating layer that exposes at least a portion of the first electrode contact region.

15. The method for preparing a semiconductor device according to claim 7, characterized in that: Before forming a gate electrode in contact with the planar gate structure and a first electrode in contact with the first contact region on the surface of the first region of the semiconductor body, the method further includes: A passivation layer is formed on the surface of the first region of the semiconductor body, and a first electrode connection port exposing the first contact region and a gate connection port exposing the gate structure are formed in the passivation layer.

16. A power module, characterized in that: It comprises a substrate and at least one semiconductor device according to any one of claims 1 to 5, wherein the substrate is used for carrying the semiconductor device.

17. A power conversion circuit, characterized in that: The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit comprises a circuit board and at least one semiconductor device according to any one of claims 1 to 5, wherein the semiconductor device is electrically connected to the circuit board.

18. A vehicle, characterized in that: It includes a load and a power conversion circuit as described in claim 17, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

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