Semiconductor device and inverter system

Abstract

The invention relates to a semiconductor device and an inverter system. A semiconductor device includes a first semiconductor chip, a second semiconductor chip, and a third semiconductor chip. One of the first semiconductor chip and the second semiconductor chip includes a first switch. The other of the first semiconductor chip and the second semiconductor chip includes a second switch. The third semiconductor chip includes a first transformer. When the first switch is turned off and the second switch is turned on, a signal is transmitted from the first semiconductor chip to the second semiconductor chip through the first transformer. When the second switch is turned off and the first switch is turned on, a signal is transmitted from the second semiconductor chip to the first semiconductor chip through the first transformer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The disclosure of Japanese Patent Application No. 2023-194464 filed on November 15, 2023, including the specification, drawings and abstract, is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a semiconductor device and an inverter system. Background Art

[0004] One publicly available technique is listed below.

[0005] [Patent Document 1] International Patent Application Publication No. WO2014 / 097425

[0006] For example, Patent Document 1 describes a semiconductor device. The semiconductor device described in Patent Document 1 includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip includes a first transmitting circuit, a first receiving circuit, and a first transformer. The second semiconductor chip includes a second transmitting circuit, a second receiving circuit, and a second transformer. In the semiconductor device described in Patent Document 1, a signal is transmitted from the first semiconductor chip to the second semiconductor chip through the first transformer, and a signal is transmitted from the second semiconductor chip to the first semiconductor chip through the second transformer. Summary of the invention

[0007] In the semiconductor device described in Patent Document 1, since two transformers are required to transmit and receive signals, the chip area increases. Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

[0008] A semiconductor device according to the present disclosure includes a first semiconductor chip, a second semiconductor chip, and a third semiconductor chip. One of the first semiconductor chip and the second semiconductor chip includes a first switch. The other of the first semiconductor chip and the second semiconductor chip includes a second switch. The third semiconductor chip includes a first transformer. When the first switch is turned off and the second switch is turned on, a signal is transmitted from the first semiconductor chip to the second semiconductor chip through the first transformer. When the second switch is turned off and the first switch is turned on, a signal is transmitted from the second semiconductor chip to the first semiconductor chip through the first transformer.

[0009] According to the semiconductor device of the present disclosure, the chip area can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a block diagram of a semiconductor device DEV;

[0011] Figure 2is an explanatory diagram illustrating an example in which a signal is transmitted from the semiconductor chip CHP1 to the semiconductor chip CHP2;

[0012] Figure 3 is a first plan view of the semiconductor chip CHP3;

[0013] Figure 4 is a second plan view of the semiconductor chip CHP3;

[0014] Figure 5 is a third plan view of the semiconductor chip CHP3;

[0015] Figure 6 It is along Figure 3 A cross-sectional view taken along line VI-VI is shown;

[0016] Figure 7 It is along Figure 3 A cross-sectional view taken along line VII-VII is shown;

[0017] Figure 8 is a block diagram of the inverter system INV;

[0018] Fig. 9 is a flow chart for manufacturing a semiconductor chip CHP3;

[0019] Fig.10 is a cross-sectional view for explaining the ion implantation step S2;

[0020] Fig.11 is a cross-sectional view for explaining the first insulating film forming step S3;

[0021] Fig.12 is a cross-sectional view for explaining the first via plug forming step S4;

[0022] Fig.13 is a cross-sectional view for explaining the first wiring layer forming step S5;

[0023] Fig.14 is a cross-sectional view for explaining the second insulating film forming step S6;

[0024] Fig.15 is a cross-sectional view for explaining the second via plug forming step S7;

[0025] Fig.16 is a cross-sectional view for explaining the second wiring layer forming step S8;

[0026] Fig.17 is a cross-sectional view for explaining the third insulating film forming step S9;

[0027] Fig.18is a cross-sectional view for explaining the third via plug forming step S10; and

[0028] Fig.19 is a cross-sectional view for explaining the third wiring layer forming step S11. DETAILED DESCRIPTION

[0029] The details of the embodiments of the present disclosure will be described with reference to the accompanying drawings. In the drawings described below, the same or corresponding components are represented by the same reference numerals, and their overlapping descriptions are not repeated. The semiconductor device according to the embodiment is described as a semiconductor device DEV, and the inverter system according to the embodiment is described as an inverter system INV.

[0030] (Configuration of semiconductor device DEV)

[0031] The configuration of the semiconductor device DEV will be described below.

[0032] Figure 1 is a block diagram of a semiconductor device DEV. Figure 1 As shown, the semiconductor device DEV includes a semiconductor chip CHP1, a semiconductor chip CHP2, and a semiconductor chip CHP3.

[0033] The semiconductor chip CHP1 includes a transmitting / receiving circuit TRX1, a transmitting circuit TX1, a receiving circuit RX1, a switch SW1, and a control circuit CC1. The semiconductor chip CHP2 includes a transmitting / receiving circuit TRX2, a transmitting circuit TX2, a receiving circuit RX2, a switch SW2, a control circuit CC2, and a driving circuit DR. The semiconductor chip CHP3 includes transformers TR1, TR2, and TR3, and lead wirings PL1, PL2, PL3, and PL4. The transmitting / receiving circuit TRX1 includes a transmitting circuit TRX1a and a receiving circuit TRX1b. The transmitting / receiving circuit TRX2 includes a transmitting circuit TRX2a and a receiving circuit TRX2b.

[0034] Transformer TR1 includes a transmitting / receiving coil CL1 and a transmitting / receiving coil CL2. The transmitting / receiving coil CL1 and the transmitting / receiving coil CL2 are electrically connected to the transmitting / receiving circuit TRX1 and the transmitting / receiving circuit TRX2, respectively. The transmitting / receiving coil CL1 includes a coil CL11 and a coil CL12. The coil CL11 and the coil CL12 are electrically connected in series with each other through the lead-out wiring PL1. The transmitting / receiving coil CL2 includes a coil CL21 and a coil CL22. The coil CL21 and the coil CL22 are electrically connected in series with each other through the lead-out wiring PL2.

[0035] The lead wiring PL1 is electrically connected to the switch SW1. The switch SW1 is connected to the ground potential. Therefore, when the switch SW1 is turned on, the lead wiring PL1 is electrically connected to the ground potential. The lead wiring PL2 is electrically connected to the switch SW2. The switch SW2 is connected to the ground potential. Therefore, when the switch SW2 is turned on, the lead wiring PL2 is electrically connected to the ground potential. Each of the switch SW1 and the switch SW2 is, for example, a MOSFET (metal oxide semiconductor field effect transistor). Each of the gate width of the MOSFET configuring the switch SW1 and the gate width of the MOSFET configuring the switch SW2 may be, for example, equal to or greater than 5 μm, so as to reduce the loss caused by the on-resistance. When the gate of one MOSFET is divided to stabilize its gate potential, the gate width is the sum of the divided gate widths. Each of the gate width of the MOSFET configuring the switch SW1 and the gate width of the MOSFET configuring the switch SW2 may be, for example, equal to or greater than 0.5 μm, so as to reduce the loss caused by leakage.

[0036] Transformer TR2 includes a transmitting coil CL3 and a receiving coil CL4. The transmitting coil CL3 and the receiving coil CL4 are electrically connected to the transmitting circuit TX1 and the receiving circuit RX2, respectively. The transmitting coil CL3 includes a coil CL31 and a coil CL32. The coil CL31 and the coil CL32 are electrically connected in series with each other. The receiving coil CL4 includes a coil CL41 and a coil CL42. The coil CL41 and the coil CL42 are electrically connected in series with each other through the lead-out wiring PL3.

[0037] Transformer TR3 includes a transmitting coil CL5 and a receiving coil CL6. The transmitting coil CL5 and the receiving coil CL6 are electrically connected to the transmitting circuit TX2 and the receiving circuit RX1, respectively. The transmitting coil CL5 includes a coil CL51 and a coil CL52. The coil CL51 and the coil CL52 are electrically connected in series with each other. The receiving coil CL6 includes a coil CL61 and a coil CL62. The coil CL61 and the coil CL62 are electrically connected in series with each other through the lead-out wiring PL4.

[0038] Although not shown, the control circuit CC1 is electrically connected to the transmission / reception circuit TRX1, the transmission circuit TX1, the reception circuit RX1, and the switch SW1, and the control circuit CC2 is electrically connected to the transmission / reception circuit TRX2, the transmission circuit TX2, the reception circuit RX2, and the switch SW2. Although not shown, the drive circuit DR is electrically connected to the control circuit CC2.

[0039] Figure 2 is an explanatory diagram illustrating an example in which a signal is transmitted from the semiconductor chip CHP1 to the semiconductor chip CHP2. Figure 2As shown, first, the control circuit CC1 turns off the switch SW1, and the control circuit CC2 turns on the switch SW2. As a result, the transmitting / receiving coil CL1 is used as a transmitting coil, and the transmitting / receiving coil CL2 is used as a receiving coil. In this case, the control circuit CC1 electrically connects the transmitting circuit TRX1a to the transmitting / receiving coil CL1, and the control circuit CC2 electrically connects the receiving circuit TRX2b to the transmitting / receiving coil CL2.

[0040] Next, the control circuit CC1 outputs a signal SG1 to the transmitting / receiving circuit TRX1 (transmitting circuit TRX1a). The signal SG1 is a square wave. The transmitting circuit TRX1a modulates the signal SG1 into a signal SG2, and transmits the signal SG2 to the transmitting / receiving coil CL1. When the signal SG2 flows through the transmitting / receiving coil CL1, a signal SG3 corresponding to the signal SG2 flows through the transmitting / receiving coil CL2 by an induced electromotive force. The transmitting / receiving circuit TRX2 (receiving circuit TRX2b) amplifies the signal SG3, and demodulates the signal SG3 into a square wave.

[0041] When a signal is transmitted from the semiconductor chip CHP2 to the semiconductor chip CHP1, the control circuit CC1 turns on the switch SW1, and the control circuit CC2 turns off the switch SW2. As a result, the transmitting / receiving coil CL1 is used as a receiving coil, and the transmitting / receiving coil CL2 is used as a transmitting coil. In this case, the control circuit CC1 electrically connects the receiving circuit TRX1b to the transmitting / receiving coil CL1, and the control circuit CC2 electrically connects the transmitting circuit TRX2a to the transmitting / receiving coil CL2. In other respects, the signal is similarly transmitted from the semiconductor chip CHP2 to the semiconductor chip CHP1 through the transformer TR1.

[0042] Therefore, signal transmission from the semiconductor chip CHP1 to the semiconductor chip CHP2 and signal transmission from the semiconductor chip CHP2 to the semiconductor chip CHP1 through the transformer TR1 are performed in a pulse communication mode. More specifically, these signal transmissions are performed in an SPI (Serial Peripheral Interface) communication mode.

[0043] Even in the signal transmission from the semiconductor chip CHP1 to the semiconductor chip CHP2 through the transformer TR2, the signal is output from the control circuit CC1 to the transmitting circuit TX1, is transmitted to the transmitting coil CL3, and flows through the receiving coil CL4 by the induced electromotive force. The signal flowing through the receiving coil CL4 is amplified and demodulated by the receiving circuit RX2, and then received.

[0044] Note that the control circuit CC2 drives the drive circuit DR based on the signal received by the receiving circuit RX2. That is, the signal transmission from the semiconductor chip CHP1 to the semiconductor chip CHP2 through the transformer TR2 is also performed in the pulse communication mode. More specifically, the signal transmission is performed in the PWM (pulse width modulation) communication mode. The signal transmission from the semiconductor chip CHP2 to the semiconductor chip CHP1 through the transformer TR3 is also performed similarly to the signal transmission from the semiconductor chip CHP1 to the semiconductor chip CHP2 through the transformer TR2.

[0045] Figure 3 is a first plan view of the semiconductor chip CHP3. Figure 4 4 is a second plan view of the semiconductor chip CHP3. Figure 5 is a third plan view of the semiconductor chip CHP3. Figure 6 It is along Figure 3 A cross-sectional view taken along line VI-VI is shown. Figures 3 to 6 As shown, the semiconductor chip CHP3 further includes a semiconductor substrate SUB.

[0046] The semiconductor substrate SUB has a first surface FS and a second surface SS. The second surface SS is an opposite surface to the first surface FS. Each first surface FS and each second surface SS are end surfaces of the semiconductor substrate SUB in the thickness direction. The material configuring the semiconductor substrate SUB is, for example, single crystal silicon. The semiconductor substrate SUB includes an impurity injection region IR. The impurity injection region IR is formed at the first surface FS. The conductivity type of the semiconductor substrate SUB is, for example, a p-type. The dopant concentration in the impurity injection region IR is higher than the dopant concentration outside the impurity injection region IR.

[0047] The semiconductor chip CHP3 further includes an insulating film IF1. The insulating film IF1 is arranged on the semiconductor substrate SUB. More specifically, the insulating film IF1 is arranged on the first surface FS. The material configuring the insulating film IF1 is, for example, silicon oxide.

[0048] The semiconductor chip CHP3 also includes a wiring layer WL1. The wiring layer WL1 is arranged on the insulating film IF1. The wiring layer WL1 includes wiring WL1a, wiring WL1b, wiring WL1c, wiring WL1d, wiring WL1e, and wiring WL1f. The wiring WL1a, wiring WL1b, wiring WL1c, wiring WL1d, wiring WL1e, and wiring WL1f extend in a first direction DR1 in a plan view. The material configuring the wiring layer WL1 is, for example, a conductive material including aluminum as a main component.

[0049] The semiconductor chip CHP3 further includes an insulating film IF2. The insulating film IF2 is arranged on the insulating film IF1 to cover the wiring layer WL1. The material configuring the insulating film IF2 is, for example, silicon oxide.

[0050] The semiconductor chip CHP3 also includes a wiring layer WL2. The wiring layer WL2 is arranged on the insulating film IF2. The wiring layer WL2 includes a transmitting / receiving coil CL1 (coil CL11 and coil CL12), a transmitting coil CL3 (coil CL31 and coil CL32), a receiving coil CL6 (coil CL61 and coil CL62), wiring WL2a, wiring WL2b, wiring WL2c, wiring WL2d, wiring WL2e, wiring WL2f, lead-out wiring PL1, and lead-out wiring PL4. The material configuring the wiring layer WL2 is, for example, a conductive material including aluminum as a main component.

[0051] The coil CL11 and the coil CL12 are adjacent to each other in the first direction DR1. The coil CL11 and the coil CL12 are spirally wound in a plan view. More specifically, Figure 4 In the example shown, the coil CL11 is wound counterclockwise in a plan view from its innermost circumference toward its outermost circumference, and the coil CL12 is wound spirally clockwise in a plan view from its outermost circumference toward its innermost circumference. The coil CL11 and the coil CL12 are electrically connected to each other in series via the lead-out wiring PL1. More specifically, the outermost end of the coil CL11 is connected to the outermost end of the coil CL12 via one end of the lead-out wiring PL1.

[0052] The coil CL31 and the coil CL32 are adjacent to each other in the first direction DR1. The coil CL31 and the coil CL32 are spirally wound in a plan view. More specifically, Figure 4 In the example shown, the coil CL31 is wound counterclockwise in a plan view from its innermost circumference toward its outermost circumference, and the coil CL32 is wound spirally clockwise in a plan view from its outermost circumference toward its innermost circumference. The coil CL31 and the coil CL32 are electrically connected in series with each other. More specifically, the outermost end of the coil CL31 is connected to the outermost end of the coil CL32.

[0053] The coil CL61 and the coil CL62 are adjacent to each other in the first direction DR1. The coil CL61 and the coil CL62 are spirally wound in a plan view. More specifically, Figure 4In the example shown, the coil CL61 is wound counterclockwise in a plan view from its innermost circumference toward its outermost circumference, and the coil CL62 is wound spirally clockwise in a plan view from its outermost circumference toward its innermost circumference. The coil CL61 and the coil CL62 are electrically connected to each other in series via the lead-out wiring PL4. More specifically, the outermost end of the coil CL61 is connected to the outermost end of the coil CL62 via one end of the lead-out wiring PL4.

[0054] The transmitting / receiving coil CL1, the transmitting coil CL3, and the receiving coil CL6 are arranged side by side in the first direction DR1. In the first direction DR1, the transmitting / receiving coil CL1 is arranged between the transmitting coil CL3 and the receiving coil CL6.

[0055] Wiring WL2a, wiring WL2b, wiring WL2c, wiring WL2d, wiring WL2e, and wiring WL2f extend in a second direction DR2 in a plan view. The second direction DR2 is a direction perpendicular to the first direction DR1 in a plan view. One end of the wiring WL2a and one end of the wiring WL2b are adjacent to the coil CL11 and the coil CL12, respectively. One end of the wiring WL2c and one end of the wiring WL2d are adjacent to the coil CL31 and the coil CL32, respectively. One end of the wiring WL2ce and one end of the wiring WL2f are adjacent to the coil CL61 and the coil CL62, respectively.

[0056] One end of the wiring WL2a and the innermost end of the coil CL11 are electrically connected to each other through the wiring WL1a and the via plug VP2, and one end of the wiring WL2b and the innermost end of the coil CL12 are electrically connected to each other through the wiring WL1b and the via plug VP2. One end of the wiring WL2c and the innermost end of the coil CL31 are electrically connected to each other through the wiring WL1c and the via plug VP2, and one end of the wiring WL2d and the innermost end of the coil CL32 are electrically connected to each other through the wiring WL1d and the via plug VP2.

[0057] One end of the wiring WL2e and the innermost end of the coil CL61 are electrically connected to each other through the wiring WL1e and the via plug VP2, and one end of the wiring WL2f and the innermost end of the coil CL62 are electrically connected to each other through the wiring WL1f and the via plug VP2. The via plug VP2 is embedded in the insulating film IF2. The material configuring the via plug VP2 is, for example, a conductive material including tungsten as a main component.

[0058] The semiconductor chip CHP3 also includes a plurality of insulating films IF3. The plurality of insulating films IF3 are stacked. The insulating film IF3 as the bottom layer is arranged on the insulating film IF2 to cover the wiring layer WL2. The material configuring the insulating film IF3 is, for example, silicon oxide. The semiconductor chip CHP3 also includes a plurality of wiring layers WL3. Each wiring layer WL3 is arranged on one insulating film IF3 and is covered by another insulating film IF3 on one insulating film IF3.

[0059] The semiconductor chip CHP3 also includes a wiring layer WL4. The wiring layer WL4 includes a transmitting / receiving coil CL2 (coil CL21 and coil CL22), a receiving coil CL4 (coil CL41 and coil CL42), a transmitting coil CL5 (coil CL51 and coil CL52), lead wiring PL2, and lead wiring PL3. The material configuring the wiring layer WL4 is, for example, a conductive material including aluminum as a main component.

[0060] The coil CL21 and the coil CL22 are adjacent to each other in the first direction DR1. The coil CL21 and the coil CL22 are spirally wound in a plan view. More specifically, Figure 5 In the example shown, the coil CL21 is wound counterclockwise from its innermost circumference toward its outermost circumference in a plan view, and the coil CL22 is wound spirally clockwise from its outermost circumference toward its innermost circumference in a plan view. The coil CL21 and the coil CL22 are electrically connected to each other in series via the lead-out wiring PL2. More specifically, the outermost end of the coil CL21 is connected to the outermost end of the coil CL22 via one end of the lead-out wiring PL2.

[0061] The coil CL41 and the coil CL42 are adjacent to each other in the first direction DR1. The coil CL41 and the coil CL42 are spirally wound in a plan view. More specifically, Figure 5 In the example shown, the coil CL41 is wound counterclockwise in a plan view from its innermost circumference toward its outermost circumference, and the coil CL42 is wound spirally clockwise in a plan view from its outermost circumference toward its innermost circumference. The coil CL41 and the coil CL42 are electrically connected to each other in series via lead-out wiring PL3. More specifically, the outermost end of the coil CL41 is connected to the outermost end of the coil CL42 via one end of the lead-out wiring PL3.

[0062] The coil CL51 and the coil CL52 are adjacent to each other in the first direction DR1. The coil CL51 and the coil CL52 are spirally wound in a plan view. More specifically, Figure 5In the example shown, coil CL51 is wound counterclockwise in a plan view from its innermost circumference toward its outermost circumference, and coil CL52 is wound spirally clockwise in a plan view from its outermost circumference toward its innermost circumference. Coil CL51 and coil CL52 are electrically connected in series with each other. More specifically, the outermost end of coil CL51 is connected to the outermost end of coil CL52.

[0063] Wiring layer WL4 also includes pads PD1, pads PD2, pads PD3, pads PD4, pads PD5, and pads PD6. Pads PD1 and PD2 are respectively connected to the innermost end of coil CL21 and the innermost end of coil CL22. Pads PD3 and PD4 are respectively connected to the innermost end of coil CL41 and the innermost end of coil CL42. Pads PD5 and PD6 are respectively connected to the innermost end of coil CL51 and the innermost end of coil CL52.

[0064] The wiring layer WL4 also includes pads PD7, pads PD8, pads PD9, pads PD10, pads PD11, and pads PD12. Pads PD7 and pads PD8 are electrically connected to the other end of the wiring WL2a and the other end of the wiring WL2b through the wiring layer WL4 and the via plug VP3, respectively. Pads PD9 and pads PD10 are electrically connected to the other end of the wiring WL2c and the other end of the wiring WL2d through the wiring layer WL4 and the via plug VP3, respectively. Pads PD11 and pads PD12 are electrically connected to the other end of the wiring WL2e and the other end of the wiring WL2f through the wiring layer WL4 and the via plug VP3, respectively. The via plug VP3 is embedded in the insulating film IF3. The material configuring the via plug VP3 is, for example, a conductive material including tungsten as a main component.

[0065] Wiring layer WL4 further includes pads PD13, pads PD14, pads PD15, and pads PD16. Pads PD13 and PD14 are respectively connected to the other end of lead wiring PL2 and the other end of lead wiring PL3. Pad PD15 is electrically connected to the other end of lead wiring PL1 through wiring layer WL3 and via plug VP3. Pad PD16 is electrically connected to the other end of lead wiring PL4 through wiring layer WL3 and via plug VP3.

[0066] The semiconductor chip CHP3 is electrically connected to the semiconductor chip CHP2 in pads PD1, PD2, PD3, PD4, PD5, PD6, PD13, and PD14. The semiconductor chip CHP3 is electrically connected to the semiconductor chip CHP1 in pads PD7, PD8, PD9, PD10, PD11, PD12, PD15, and PD16.

[0067] The wiring layer WL4 is arranged on the insulating film IF3 which is the uppermost layer. In a plan view, the transmitting / receiving coil CL2 overlaps with the transmitting / receiving coil CL1. In a plan view, the receiving coil CL4 overlaps with the transmitting coil CL3. In a plan view, the transmitting coil CL5 overlaps with the receiving coil CL6. Therefore, the transmitting / receiving coil CL2, the receiving coil CL4 and the transmitting coil CL5 are arranged to face the transmitting / receiving coil CL1, the transmitting coil CL3 and the receiving coil CL6 respectively through the insulating layer (multiple insulating films IF3).

[0068] As described above, the transmitting / receiving coil CL1, the transmitting coil CL3, and the receiving coil CL6 are arranged side by side in the first direction DR1, so that the transmitting / receiving coil CL1 is located between the transmitting coil CL3 and the receiving coil CL4. Therefore, the transformer TR1, the transformer TR2, and the transformer TR3 are arranged side by side in the first direction DR1, so that the transformer TR1 is located between the transformer TR2 and the transformer TR3.

[0069] The number of coil windings of transformer TR1 is greater than, for example, the number of coil windings of transformer TR2 and the number of coil windings of transformer TR3. The number of coil windings of a transformer is defined as the number of windings of a coil included in the transformer. For example, the number of coil windings of transformer TR1 is the number of windings of coil CL11 (coil CL12, coil CL21, coil CL22). When the number of coil windings included in the transformer is equal to or greater than "n" and less than "(n+1)", the number of coil windings is regarded as "(n+1)". The number of coil windings of transformer TR1 is, for example, one or two more than the number of coil windings of transformer TR2 and the number of coil windings of transformer TR3.

[0070] Figure 7 It is along Figure 3 The cross-sectional view taken along the line VII-VII is shown. Figure 7 As shown, the semiconductor chip CHP3 further includes a guard ring GR. The guard ring GR surrounds the transformer TR1, the transformer TR2, and the transformer TR3 in a plan view.

[0071] The guard ring GR is made of a wiring layer WL4, a wiring layer WL3, a wiring layer WL2, a wiring layer WL1, a via plug VP1, a via plug VP2, and a via plug VP3. In the guard ring GR, the wiring layer WL4 and the wiring layer WL3 as the uppermost layer are connected to each other through the via plug VP3, the stacked wiring layers WL3 are connected to each other, and the wiring layer WL3 as the lowermost layer and the wiring layer WL2 are connected to each other. In the guard ring GR, the wiring layer WL2 and the wiring layer WL1 are connected to each other through the via plug VP2, and the wiring layer WL1 and the semiconductor substrate SUB are connected to each other through the via plug VP1. The via plug VP1 is embedded in the insulating film IF1. The material configuring the via plug VP1 is, for example, a conductive material including tungsten as a main component.

[0072] The distance between the transformer TR1 and the transformer TR2 in a plan view and the distance between the transformer TR1 and the transformer TR3 in a plan view are, for example, equal to or greater than 15 μm. The distance between the transformer TR1 and the guard ring GR in a plan view, the distance between the transformer TR2 and the guard ring GR in a plan view and the distance between the transformer TR3 and the guard ring GR in a plan view are, for example, equal to or greater than 50 μm.

[0073] Although not shown, the semiconductor chip CHP3 further includes a passivation film. The passivation film is arranged on the insulating film IF3 as the uppermost layer to cover the wiring layer WL4. In the passivation film, an opening is formed to expose the pad PD1 to the pad PD16.

[0074] Figure 8 is a block diagram of the inverter system INV. Figure 8 As shown, the inverter system INV includes a semiconductor device DEV and an inverter circuit INVC. The inverter circuit INVC includes a switching circuit configured by a plurality of power semiconductor elements PWS. For example, the power semiconductor element PWS is an IGBT (insulated gate bipolar transistor). The power semiconductor element PWS is driven by a drive circuit DR.

[0075] Fig. 9 1 is a flow chart for manufacturing semiconductor chip CHP3. Fig. 9 As shown, the method for manufacturing the semiconductor chip CHP3 includes a preparation step S1, an ion implantation step S2, a first insulating film forming step S3, a first via plug forming step S4, a first wiring layer forming step S5, and a second insulating film forming step S6. The method for manufacturing the semiconductor chip CHP3 also includes a second via plug forming step S7, a second wiring layer forming step S8, a third insulating film forming step S9, a third via plug forming step S10, a third wiring layer forming step S11, a fourth wiring layer forming step S12, and a passivation film forming step S13.

[0076] In the preparation step S1, a semiconductor substrate SUB is prepared. After the preparation step S1, an ion implantation step S2 is performed. Fig.10 2 is a cross-sectional view for explaining the ion implantation step S2. Fig.10 As shown, when ion implantation is performed in the ion implantation step S2, the impurity implantation region IR is formed. After the ion implantation step S2, the first insulating film forming step S3 is performed.

[0077] Fig.11 2 is a cross-sectional view for explaining the first insulating film forming step S3. Fig.11 As shown, in the first insulating film forming step S3, the insulating film IF1 is formed on the semiconductor substrate SUB by, for example, a CVD (Chemical Vapor Deposition) method. After the first insulating film forming step S3, a first via plug forming step S4 is performed.

[0078] Fig.12 2 is a cross-sectional view for explaining the first via plug forming step S4. Fig.12 As shown, in the first via plug forming step S4, the via plug VP1 is embedded in the insulating film IF1. In the first via plug forming step S4, first, a via hole is formed in the insulating film IF1 by dry etching using a resist pattern formed by photolithography as a mask. Second, a material configuring the via plug VP1 is embedded in the via hole by, for example, a CVD method. Third, a material configuring the via plug VP1 protruding from the via hole is removed by, for example, a CMP (chemical mechanical polishing) method. After the first via plug forming step S4, a first wiring layer forming step S5 is performed.

[0079] Fig.13 2 is a cross-sectional view for explaining the first wiring layer forming step S5. Fig.13 As shown, in the first wiring layer forming step S5, the wiring layer WL1 is formed on the insulating film IF1. In the first wiring layer forming step S5, first, a material configuring the wiring layer WL1 is formed by, for example, a sputtering method. Next, the material configuring the formed wiring layer WL1 is patterned by, for example, dry etching using a resist pattern formed by photolithography as a mask. After the first wiring layer forming step S5, a second insulating film forming step S6 is performed.

[0080] Fig.14 2 is a cross-sectional view for explaining the second insulating film forming step S6. Fig.14As shown, in the second insulating film forming step S6, the insulating film IF2 is formed on the insulating film IF1 to cover the wiring layer WL1. In the second insulating film forming step S6, first, a material configuring the insulating film IF2 is formed by, for example, a CVD method. Next, the material configuring the formed insulating film IF2 is flattened by, for example, a CMP method. After the second insulating film forming step S6, a second via plug forming step S7 is performed.

[0081] Fig.15 2 is a cross-sectional view for explaining the second via plug forming step S7. Fig.15 As shown, in the second via plug forming step S7, the via plug VP2 is embedded in the insulating film IF2 by a method similar to that in the first via plug forming step S4. After the second via plug forming step S7, the second wiring layer forming step S8 is performed.

[0082] Fig.16 2 is a cross-sectional view for explaining the second wiring layer forming step S8. Fig.16 As shown, in the second wiring layer forming step S8, the wiring layer WL2 is formed on the insulating film IF2. In the second wiring layer forming step S8, first, a material configuring the wiring layer WL2 is formed by, for example, sputtering. Next, the material configuring the formed wiring layer WL2 is patterned by, for example, dry etching using a resist pattern formed by photolithography as a mask. After the second wiring layer forming step S8, a third insulating film forming step S9 is performed.

[0083] Fig.17 2 is a cross-sectional view for explaining the third insulating film forming step S9. Fig.17 As shown, in the third insulating film forming step S9, the insulating film IF3 is formed on the insulating film IF2 to cover the wiring layer WL2. After the third insulating film forming step S9, a third via plug forming step S10 is performed.

[0084] Fig.18 2 is a cross-sectional view for explaining the third via plug forming step S10. Fig.18 As shown, in the third via plug forming step S10, the via plug VP3 is embedded in the insulating film IF3 by a method similar to that in the second via plug forming step S7. After the third via plug forming step S10, the third wiring layer forming step S11 is performed.

[0085] Fig.19 2 is a cross-sectional view for explaining the third wiring layer forming step S11. Fig.19As shown, in the third wiring layer forming step S11, the wiring layer WL3 is formed by a method similar to that in the second wiring layer forming step S8. The third insulating film forming step S9, the third through-hole plug forming step S10, and the third wiring layer forming step S11 are repeated until the insulating film IF3 as the uppermost layer is formed. After the insulating film IF3 as the uppermost layer is formed, the fourth wiring layer forming step S12 is performed.

[0086] In the fourth wiring layer forming step S12, the wiring layer WL4 is formed on the insulating film IF3 as the uppermost layer by a method similar to that in the second wiring layer forming step S8. After the fourth wiring layer forming step S12, a passivation film forming step S13 is performed.

[0087] In the passivation film forming step S13, the passivation film PF is formed on the insulating film IF3 as the uppermost layer to cover the wiring layer WL4. In the passivation film forming step S13, first, a material configuring the passivation film is formed by, for example, a CVD method. Next, using a resist pattern formed by photolithography as a mask, the material configuring the passivation film is patterned by, for example, dry etching. When the passivation film is divided by dicing or the like after the aforementioned step, the passivation film PF is formed. Figures 3 to 7 The structure of the semiconductor chip CHP3 is shown.

[0088] <Influence of semiconductor equipment DEV>

[0089] Next, the effects of the semiconductor device DEV will be described.

[0090] In the semiconductor device DEV, by switching of the switch SW1 and switching of the switch SW2, one of the transmitting / receiving coil CL1 and the transmitting / receiving coil CL2 can be used as a transmitting coil, and the other of the transmitting / receiving coil CL1 and the transmitting / receiving coil CL2 can be used as a receiving coil. Therefore, the corresponding functions of the two transformers can be performed by the transformer TR1, and therefore, the chip area can be reduced.

[0091] In the semiconductor device DEV, the switch SW1 and the switch SW2 are not formed on the semiconductor chip CHP3, but are formed on each of the semiconductor chip CHP1 and the semiconductor chip CHP2. Therefore, in the semiconductor device DEV, it is not necessary to apply a CMOS (Complementary Metal Oxide Semiconductor) process to the semiconductor chip CHP3, and the steps of manufacturing the semiconductor chip CHP3 can be simplified.

[0092] By increasing the number of coil windings of the transformer TR1, the coupling coefficient between the transmitting / receiving coil CL1 and the transmitting / receiving coil CL2 is improved, and the loss caused by signal transmission is reduced. In the semiconductor device DEV, the loss may be caused by the respective resistances of the switch SW1 and the switch SW2. However, by increasing the number of coil windings of the transformer TR1 to be greater than the number of coil windings of the transformer TR2 and the number of coil windings of the transformer TR3, the loss caused by the respective resistances of the switch SW1 and the switch SW2 may be eliminated.

[0093] On the other hand, if the number of coil windings of the transformer TR1 is much larger than the number of coil windings of the transformer TR2 and the number of coil windings of the transformer TR3, the chip area is undesirably large. Therefore, when the number of coil windings of the transformer TR1 is equal to or less than 1.2 times the number of coil windings of the transformer TR2 and the number of coil windings of the transformer TR3, the chip area can be reduced while the loss caused by the respective resistances of the switches SW1 and SW2 can be eliminated.

[0094] In the semiconductor device DEV, in a plan view, the transformer TR1 is arranged between the transformer TR2 and the transformer TR3. Therefore, the distance between the transmitting coil CL3 and the transmitting coil CL5 and the distance between the receiving coil CL4 and the receiving coil CL6 are large. As a result, according to the semiconductor device DEV, the crosstalk between the transformer TR2 and the transformer TR3 can be suppressed.

[0095] In the above, the invention made by the inventors of the present application has been specifically described based on the embodiments. However, it goes without saying that the present invention is not limited to the aforementioned embodiments, and various modifications can be made within the scope of the present invention.

Claims

1. A semiconductor device comprising: a first semiconductor chip; a second semiconductor chip; as well as The third semiconductor chip, wherein one of the first semiconductor chip and the second semiconductor chip comprises a first switch, wherein the other of the first semiconductor chip and the second semiconductor chip comprises a second switch, wherein the third semiconductor chip comprises a first transformer, wherein when the first switch is turned off and the second switch is turned on, a signal is transmitted from the first semiconductor chip to the second semiconductor chip through the first transformer, and When the second switch is turned off and the first switch is turned on, a signal is transmitted from the second semiconductor chip to the first semiconductor chip through the first transformer.

2. The semiconductor device according to claim 1, The third semiconductor chip comprises: Semiconductor substrate; a first transmitting / receiving coil and a second transmitting / receiving coil, wherein the first transmitting / receiving coil and the second transmitting / receiving coil are configured with the first transformer; first lead-out wiring; A second lead-out wiring; as well as Insulation layer, The first transmitting / receiving coil includes a first coil and a second coil, wherein the first coil and the second coil are arranged side by side in a plan view and are connected in series to each other through the first lead wiring, The second transmitting / receiving coil includes a third coil and a fourth coil, wherein the third coil and the fourth coil are arranged to face the first coil and the second coil respectively through the insulating layer, and are connected in series to each other through the second lead-out wiring, and The first lead wiring and the second lead wiring are electrically connected to the first switch and the second switch, respectively.

3. The semiconductor device according to claim 2, The first semiconductor chip further includes a first transmitting / receiving circuit electrically connected to the first transmitting / receiving coil, The first transmitting / receiving circuit includes a first transmitting circuit and a first receiving circuit, wherein the second semiconductor chip further comprises a second transmitting / receiving circuit electrically connected to the second transmitting / receiving coil, The second transmitting / receiving circuit includes a second transmitting circuit and a second receiving circuit, wherein when the first switch is turned off and the second switch is turned on, the first transmitting circuit is electrically connected to the first transmitting / receiving coil, and the second receiving circuit is electrically connected to the second transmitting / receiving coil, and When the second switch is turned off and the first switch is turned on, the first receiving circuit is electrically connected to the first transmitting / receiving coil, and the second transmitting circuit is electrically connected to the second transmitting / receiving coil.

4. The semiconductor device according to claim 2, The first semiconductor chip further includes a first control circuit, wherein the first control circuit is configured to switch an “on” state and an “off” state of the first switch, and The second semiconductor chip further includes a second control circuit, and the second control circuit is configured to switch the “on” state and the “off” state of the second switch.

5. The semiconductor device according to claim 1, wherein the first switch is a first MOSFET, wherein the second switch is a second MOSFET, and Wherein each of a gate width of the first MOSFET and a gate width of the second MOSFET is equal to or greater than 5 μm.

6. The semiconductor device according to claim 2, wherein the third semiconductor chip includes a second transformer and a third transformer, The second transformer includes a first transmitting coil and a first receiving coil, The third transformer includes a second transmitting coil and a second receiving coil, The first transmitting coil and the second transmitting coil are arranged to face the first receiving coil and the second receiving coil respectively through the insulating layer, wherein a signal is transmitted from the first semiconductor chip to the second semiconductor chip through the second transformer, and The signal is transmitted from the second semiconductor chip to the first semiconductor chip through the third transformer.

7. The semiconductor device according to claim 6, The first transformer, the second transformer and the third transformer are arranged side by side, so that the first transformer is located between the second transformer and the third transformer in a plan view.

8. The semiconductor device according to claim 7, The third semiconductor chip further includes a guard ring. wherein the guard ring surrounds the first transformer, the second transformer and the third transformer in a plan view, wherein each of a distance between the first transformer and the second transformer and a distance between the first transformer and the third transformer is equal to or greater than 15 μm, and Each of a distance between the first transformer and the guard ring, a distance between the second transformer and the guard ring, and a distance between the third transformer and the guard ring is equal to or greater than 50 μm.

9. The semiconductor device according to claim 6, The number of coil windings of the first transformer is greater than the number of coil windings of the second transformer and the number of coil windings of the third transformer.

10. The semiconductor device according to claim 7, The number of coil windings of the first transformer is equal to or less than 1.2 times the number of coil windings of the second transformer and 1.2 times the number of coil windings of the third transformer.

11. The semiconductor device according to claim 6, wherein a signal transmission mode between the first semiconductor chip and the second semiconductor chip through the first transformer is an SPI communication mode, and Wherein each of a signal transmission mode between the first semiconductor chip and the second semiconductor chip through the second transformer and a signal transmission mode between the first semiconductor chip and the second semiconductor chip through the third transformer is a PWM communication mode.

12. An inverter system, comprising: An inverter circuit, the inverter circuit comprising a power semiconductor element; a first semiconductor chip; a second semiconductor chip; as well as The third semiconductor chip, wherein one of the first semiconductor chip and the second semiconductor chip comprises a first switch, wherein the other of the first semiconductor chip and the second semiconductor chip comprises a second switch, wherein the second semiconductor chip is electrically connected to the inverter circuit, wherein the third semiconductor chip comprises a first transformer, wherein when the first switch is turned off and the second switch is turned on, a signal is transmitted from the first semiconductor chip to the second semiconductor chip through the first transformer, and When the second switch is turned off and the first switch is turned on, a signal is transmitted from the second semiconductor chip to the first semiconductor chip through the first transformer.

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