Method for forming semiconductor device structure

Abstract

The forming method of the semiconductor device structure comprises the following steps: forming a fin-shaped structure from a semiconductor layer stack comprising a plurality of first semiconductor layers and a plurality of second semiconductor layers which are stacked in a staggered manner; removing an edge portion of the second semiconductor layer by an etching process; after the etching process, a post-processing process is performed on the exposed surface of the second semiconductor layer to remove residues from the exposed surface of the second semiconductor layer. The method also includes, after the post-processing process, performing a pre-cleaning process on the processed surface of the second semiconductor layer. The method also includes forming an inner spacer to contact a treated surface of the second semiconductor layer.

Description

Technical Field

[0001] The present invention relates to a method for forming a semiconductor device structure, and in particular to a step of forming an inner spacer. Background Art

[0002] The semiconductor integrated circuit industry has experienced exponential growth. Technological advances in integrated circuit materials and design have enabled each generation of integrated circuits to have smaller and more complex circuits than the previous generation. In the evolution of integrated circuits, functional density (e.g., the number of interconnect devices per unit chip area) generally increases as geometric size (e.g., the smallest component or line that can be produced by the manufacturing process used) decreases. The process size reduction is generally beneficial to increase production capacity and reduce the associated costs. However, the size reduction presents new challenges. For example, transistors use nanostructured channels to improve carrier mobility and drive current in the device. Inner spacers are generally located between the metal gate and the source / drain structure to protect the source / drain structure from damage during the subsequent gate replacement process. Although the formation method of the inner spacer is generally suitable for the intended purpose, it cannot fully meet all requirements. Summary of the invention

[0003] One embodiment is a method for forming a semiconductor device structure. The method includes forming a fin structure from a semiconductor layer stack including a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked in an alternating manner; removing an edge portion of the second semiconductor layer by an etching process; performing a post-treatment process on an exposed surface of the second semiconductor layer after the etching process. The method also includes performing a pre-cleaning process on a treated surface of the second semiconductor layer after the post-treatment process; and forming an inner spacer to contact the treated surface of the second semiconductor layer.

[0004] Another embodiment is a method for forming a semiconductor device structure. The method includes forming a sacrificial gate structure on a portion of a fin-shaped structure, and the fin-shaped structure includes a plurality of first semiconductor layers and a plurality of second semiconductor layers that are staggered and stacked; removing the portion of the fin-shaped structure not covered by the sacrificial gate structure; and using an etching process to remove an edge portion of the second semiconductor layer to form a cavity between two adjacent first semiconductor layers, wherein the exposed surface of the second semiconductor layer after the etching process has a first line width roughness. The method also includes, after the etching process, performing a treatment process on the exposed surface of the second semiconductor layer, so that the exposed surface of the second semiconductor layer after the treatment process has a second line width roughness, and the second line width roughness is different from the first line width roughness. The method further includes forming an inner spacer in the cavity.

[0005] Another embodiment is a method for forming a semiconductor device structure. The method includes providing a fin structure including a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked in an alternating manner; forming a sacrificial gate structure and a gate spacer on a portion of the fin structure; selectively removing a portion of each of the second semiconductor layers so that fluorine covers the exposed surface of the second semiconductor layer. The method also includes treating the exposed surface of each of the second semiconductor layers to remove the fluorine; cleaning the treated surface of each of the second semiconductor layers with a wet etchant; and forming an inner spacer between two adjacent first semiconductor layers to contact the cleaned surface of each of the second semiconductor layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 ,and Figure 6 are perspective views of various stages in the fabrication of a semiconductor device structure in some embodiments.

[0007] Fig. 7A , Fig. 8A , Fig.13A , Fig.14A , Fig.15A , Fig.16A , Fig.17A , Fig.18A , Fig.19A ,and Fig. 20A In some embodiments, the various stages of manufacturing a semiconductor device structure are as follows Figure 6 Side sectional view of section AA.

[0008] Figure 7B , Figure 8B , Fig. 13B , Fig. 14B , Fig. 15B , Fig. 16B , Fig. 17B , Fig.18B , Fig.19B ,and Fig. 20B In some embodiments, the various stages of manufacturing a semiconductor device structure are as follows Figure 6 Side sectional view of section BB.

[0009] Figure 7C , Figure 8C , Fig. 13C , Fig. 14C , Fig. 15C , Fig. 16C , Fig. 17C , Fig.18C , Fig.19C ,and Fig. 20C In some embodiments, the various stages of manufacturing a semiconductor device structure are as follows Figure 6Side sectional view of section CC.

[0010] Fig.7D , Fig.8D , Fig.13D , Fig.14D , Fig.15D , Fig.16D , Fig.17D , Fig.18D , Fig.19D ,and Fig.20D In some embodiments, the various stages of manufacturing a semiconductor device structure are as follows Figure 6 Top view of section DD.

[0011] Fig. 9 FIG. 1 is a diagram of a semiconductor device structure exposed to a post-processing process in some embodiments.

[0012] Fig.10 and Fig.12 FIG. 1 is a top view of a portion of a semiconductor device structure after exposure to a post-processing process in some embodiments.

[0013] Fig.11 is a cross-sectional view of a portion of a semiconductor device structure after exposure to a post-processing process in some embodiments.

[0014] The reference numerals are described as follows:

[0015] θ1, θ2, θ3, θ4: angle

[0016] A, B, C, D: Corner area

[0017] AA, BB, CC, DD: Section

[0018] 100: Semiconductor device structure

[0019] 101: Substrate

[0020] 104: Semiconductor layer stacking

[0021] 106, 106a, 106b, 106c: first semiconductor layer

[0022] 108, 108a, 108b, 108c: second semiconductor layer

[0023] 108a1.108b1, 108c1: upper part

[0024] 108a2, 108b2, 108c2: middle part

[0025] 108a3, 108b3, 108c3: lower part

[0026] 108s: Sidewall

[0027] 108-1: First side wall

[0028] 108-2: Second side wall

[0029] 108-3: Third side wall

[0030] 108-4: Fourth side wall

[0031] 112: Fin structure

[0032] 114, 119: Grooves

[0033] 116: Ibe

[0034] 118: Insulation material

[0035] 120: Quarantine

[0036] 130: Sacrificial gate structure

[0037] 131: Hollow

[0038] 132: Sacrificial gate dielectric layer

[0039] 134: Sacrificial gate layer

[0040] 136: Mask layer

[0041] 138: Gate spacer

[0042] 138a: first dielectric layer

[0043] 138b: Second dielectric layer

[0044] 144: Medial spacer

[0045] 144a: Dielectric layer

[0046] 146: Source / drain structure

[0047] 162: Contact Etch Stop Layer

[0048] 164: First interlayer dielectric layer

[0049] 166: Opening

[0050] 177-1: Post-processing

[0051] 180: Gate dielectric layer

[0052] 182: Gate layer

[0053] 184: Silicide layer

[0054] 186: Source / Drain Contact

[0055] 190: Replacement gate structure DETAILED DESCRIPTION

[0056] The following detailed description may be accompanied by drawings to facilitate understanding of various aspects of the present invention. It is worth noting that the various structures are only for illustrative purposes and are not drawn to scale, as is common practice in the industry. In fact, the dimensions of the various structures may be increased or decreased arbitrarily for clarity of description.

[0057] The following disclosure provides many different embodiments or examples to implement different features of the present invention. The following disclosure describes specific examples of each component and its arrangement to simplify the description. These specific examples are not intended to limit the embodiments of the present invention. For example, if an embodiment of the present invention describes that a first structure is formed on a second structure, it means that the first structure may be in direct contact with the second structure, or an additional structure may be formed between the first structure and the second structure so that the first structure is not in direct contact with the second structure. In addition, multiple examples of the present invention may be repeatedly labeled to simplify the description or make the description clear, which does not mean that structures with the same labels in multiple embodiments and / or settings have the same relative relationship.

[0058] In addition, spatially relative terms such as "below," "beneath," "lower," "above," "upper," or the like are used to describe the relationship of some elements or structures to another element or structure in the drawings. These spatially relative terms include different orientations of the device in use or operation, as well as the orientation depicted in the drawings. When the device is rotated in a different orientation (rotated 90 degrees or other orientations), the spatially relative adjectives used will also be interpreted based on the orientation.

[0059] Although the embodiments of the present invention are described with nanostructure channel field effect transistors, some embodiments of the present invention can be used for other processes and / or other devices such as planar field effect transistors, fin field effect transistors, horizontal all-around gate field effect transistors, vertical all-around gate field effect transistors, or other suitable devices. Those with ordinary knowledge in the art should easily understand that other adjustments also fall within the scope of the embodiments of the present invention. In the example of using a all-around gate transistor structure, the patterning method of the all-around gate transistor structure can be any suitable method. For example, one or more photolithography processes such as a double patterning process or a multiple patterning process can be used to pattern the structure. Generally speaking, the double patterning or multiple patterning process combines photolithography with a self-alignment process, and the pattern spacing produced can be smaller than the pattern spacing obtained by using a single direct photolithography process. For example, one embodiment forms a sacrificial layer on a substrate and uses a photolithography process to pattern the sacrificial layer. A self-alignment process is used to form spacers along the sides of the patterned sacrificial layer. The sacrificial layer is then removed, and the retained spacers can be used to pattern the all-around gate structure.

[0060] Figures 1 to 20D is a non-limiting process for manufacturing the semiconductor device structure 100 in accordance with an embodiment of the present invention. It should be understood that for additional embodiments of the method, Figures 1 to 20D Additional steps may be provided before, during, or after the processes shown, and some of the steps described below may be replaced or omitted. The order of steps or processes may be changed and is not limited to the order described.

[0061] Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 ,and Figure 6 1 is a perspective view of various stages of manufacturing a semiconductor device structure 100 in some embodiments. Figure 1 As shown, the semiconductor device structure 100 includes a semiconductor layer stack 104 formed on the front side of a substrate 101. The substrate 101 may be a semiconductor substrate. The substrate 101 may include a crystalline semiconductor material, such as but not limited to silicon, germanium, silicon germanium, gallium arsenide, indium antimonide, gallium phosphide, gallium antimonide, indium aluminum arsenide, indium gallium arsenide, gallium antimony phosphide, gallium antimony arsenide, indium phosphide, or a combination thereof. In other embodiments, the composition of the substrate 101 is silicon. The substrate 101 may be doped or undoped. The substrate 101 may be a base semiconductor substrate, such as a base silicon substrate such as a wafer, a silicon-on-insulator substrate, a multi-layer substrate, a composition gradient substrate, or the like.

[0062] The substrate 101 may include various regions doped with impurities (eg, dopants having p-type or n-type conductivity). Depending on the circuit design, the dopant may be phosphorus for n-type field effect transistors or boron for p-type field effect transistors.

[0063] The semiconductor layer stack 104 includes semiconductor layers of different materials interlaced to facilitate the formation of a nanosheet channel in a multi-gate device such as a nanosheet channel field effect transistor. In some embodiments, the semiconductor layer stack 104 includes a first semiconductor layer 106 and a second semiconductor layer 108 vertically stacked on the substrate 101. In some embodiments, the semiconductor layer stack 104 includes an interlaced first semiconductor layer 106 and a second semiconductor layer 108. The first semiconductor layer 106 and the second semiconductor layer 108 are composed of semiconductor materials with different etching selectivities and / or oxidation rates. For example, the first semiconductor layer 106 may be composed of silicon, and the second semiconductor layer 108 may be composed of silicon germanium. In some examples, the first semiconductor layer 106 may be composed of silicon germanium, and the second semiconductor layer 108 may be composed of silicon. In some embodiments, the first semiconductor layer 106 or the second semiconductor layer 108 may be or include other materials such as germanium, silicon carbide, germanium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, indium gallium arsenide, gallium indium phosphide, gallium indium arsenide phosphide, or any combination of the foregoing.

[0064] The first semiconductor layer 106 and the second semiconductor layer 108 may be formed by any suitable deposition process such as epitaxy. For example, the method of epitaxially growing the semiconductor layer stack 104 may be a molecular beam epitaxy process, an organic metal chemical vapor deposition process, and / or other suitable epitaxial growth processes.

[0065] The first semiconductor layer 106 or a portion thereof may form a nanosheet channel of the semiconductor device structure 100 in a subsequent manufacturing stage. The term nanosheet as used herein refers to any material portion having a nanometer size or even a micrometer size and having an elongated shape, regardless of the cross-sectional shape of the portion. Thus, the term may refer to an elongated material portion having a circular or substantially circular cross-section, or a beam-shaped or rod-shaped material portion having a cylindrical or substantially rectangular cross-section. The gate may surround the nanosheet channel of the semiconductor device structure 100. The semiconductor device structure 100 may include a nanosheet transistor. The nanosheet transistor may be considered a nanowire transistor, a fully wrapped gate transistor, a multi-bridge channel transistor, or any transistor having a gate surrounding a channel. The method of using the first semiconductor layer 106 to define the channel of the semiconductor device structure 100 will be described below.

[0066] The thickness of each first semiconductor layer 106 may be about 5 nm to about 30 nm. The thickness of each second semiconductor layer 108 may be greater than, equal to, or less than the thickness of the first semiconductor layer 106. In some embodiments, the thickness of each second semiconductor layer 108 may be about 2 nm to about 50 nm. Figure 1 The three first semiconductor layers 106 and the three second semiconductor layers 108 are shown in an alternating configuration, which is only for illustrative purposes and does not limit the embodiments of the present invention to the point where the claims are not actually recorded. It should be understood that any number of first semiconductor layers 106 and second semiconductor layers 108 can be formed in the semiconductor layer stack 104, and the number of layers depends on the predetermined number of channels used in the semiconductor device structure 100.

[0067] exist Figure 2, a fin structure 112 is formed from the semiconductor layer stack 104. The fin structures 112 each have an upper portion, which includes a first semiconductor layer 106, a second semiconductor layer 108, and a well 116 formed from the substrate 101. The method for forming the fin structure 112 may be to pattern a hard mask layer (not shown) on the semiconductor layer stack 104, which may adopt multiple patterning steps including photolithography and etching processes. The etching process may include dry etching, wet etching, reactive ion etching, and / or other suitable processes. The photolithography process may include forming a photoresist layer (not shown) on the hard mask layer, exposing the photoresist layer to a pattern, performing a post-exposure baking process, and developing the photoresist layer to form a mask unit containing the photoresist layer. In some embodiments, the method of patterning the photoresist layer to form the mask unit may adopt an electron beam lithography process. The etching process forms a trench 114 in the unprotected area to pass through the hard mask layer and through the semiconductor layer stack 104 to the substrate 101, and retains a plurality of extended fin structures 112. The trench 114 extends along the X direction. The etching method of the trench 114 can adopt dry etching such as reactive ion etching, wet etching, and / or a combination thereof.

[0068] exist Figure 3 In the process, after forming the fin structure 112, an insulating material 118 may be formed on the substrate 101. The insulating material 118 fills the trenches 114 between adjacent fin structures 112 until the fin structure 112 is buried in the insulating material 118. A planarization step such as chemical mechanical polishing and / or etch back may then be performed to expose the top of the fin structure 112. The insulating material 118 may be composed of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride oxide, silicon carbonitride, fluorosilicate glass, a low dielectric constant dielectric material, or any suitable dielectric material. The insulating material 118 may be formed by any suitable method, such as low pressure chemical vapor deposition, plasma assisted chemical vapor deposition, or flowable chemical vapor deposition.

[0069] exist Figure 4 In the embodiment of the present invention, the insulating material 118 is recessed to form an isolation region 120. The recess of the insulating material 118 exposes a portion of the fin structure 112 such as the semiconductor layer stack 104. The recess of the insulating material 118 exposes the trench 114 between adjacent fin structures 112. The isolation region 120 may be formed by a suitable process, such as a dry etching process, a wet etching process, or a combination thereof. The upper surface of the insulating material 118 may be lower than or flush with the surface of the second semiconductor layer 108 contacting the well 116 formed from the substrate 101.

[0070] exist Figure 51 , one or more sacrificial gate structures 130 (only one is shown) are formed on the semiconductor device structure 100. The sacrificial gate structure 130 is formed on a portion of the fin structure 112. The sacrificial gate structures 130 may each include a sacrificial gate dielectric layer 132, a sacrificial gate layer 134, and a mask layer 136. The sacrificial gate dielectric layer 132, the sacrificial gate layer 134, and the mask layer 136 may be formed by sequentially depositing a blanket layer of the sacrificial gate dielectric layer 132, the sacrificial gate layer 134, and the mask layer 136, and then patterning these layers into the sacrificial gate structure 130. Gate spacers 138 are then formed on the sidewalls of the sacrificial gate structure 130. For example, the gate spacers 138 may be formed by conformally depositing one or more layers for the gate spacers 138, rather than isotropically etching one or more layers. Although one sacrificial gate structure 130 is shown, two or more sacrificial gate structures 130 may be arranged along the X direction in some embodiments.

[0071] The sacrificial gate dielectric layer 132 may include one or more layers of dielectric materials such as silicon oxide or silicon oxide-based materials. The sacrificial gate layer 134 may include silicon such as polycrystalline silicon or amorphous silicon. The mask layer 136 may include multiple layers, such as an oxide layer and a nitride layer. The gate spacer 138 may be composed of a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, silicon oxycarbide, silicon carbon oxynitride, and / or combinations thereof. In some embodiments, the gate spacer 138 may be a double layer, comprising a first dielectric layer 138a (such as silicon oxide) and a second dielectric layer 138b (such as silicon nitride).

[0072] The portion of the fin structure 112 covered by the sacrificial gate layer 134 of the sacrificial gate structure 130 can be used as a channel region for the semiconductor device structure 100. The partially exposed fin structure 112 on both sides of the sacrificial gate structure 130 can define the source / drain region used by the semiconductor device structure 100. In some examples, some source / drain regions can be shared between multiple transistors. For example, multiple source / drain regions can be connected together and implemented as multifunctional transistors. It should be understood that the source region and the drain region can be used interchangeably because the epitaxial structures formed in these regions are substantially the same. The source / drain region can refer to the source or drain separately or together, depending on the context.

[0073] exist Figure 6In the embodiment, a portion of the fin structure 112 in the source / drain region (such as the region on both sides of the sacrificial gate structure 130) can be recessed downward to below the upper surface of the isolation region 120 (or the insulating material 118), such as by removing the portion of the fin structure 112 not covered by the sacrificial gate structure 130. The method of recessing a portion of the fin structure 112 can be an etching process such as an isotropic or anisotropic etching process, and it is selective with respect to one or more crystal planes of the substrate 101. The etching process can be dry etching (such as reactive ion etching, neutral beam etching, or the like) or wet etching (such as using tetramethylammonium hydroxide, ammonium hydroxide, or any suitable etchant). By recessing a portion of the fin structure 112, a trench 119 can be formed in the source / drain region.

[0074] Fig. 7A , Fig. 8A , Fig.13A , Fig.14A , Fig.15A , Fig.16A , Fig.17A , Fig.18A , Fig.19A ,and Fig. 20A In some embodiments, the various stages of manufacturing the semiconductor device structure 100 are as follows: Figure 6 Side sectional view of section AA. Figure 7B , Figure 8B , Fig. 13B , Fig. 14B , Fig. 15B , Fig. 16B , Fig. 17B , Fig.18B , Fig.19B ,and Fig. 20B In some embodiments, the various stages of manufacturing the semiconductor device structure 100 are as follows: Figure 6 Side sectional view of section BB. Figure 7C , Figure 8C , Fig. 13C , Fig. 14C , Fig. 15C , Fig. 16C , Fig. 17C , Fig.18C , Fig.19C ,and Fig. 20C In some embodiments, the various stages of manufacturing the semiconductor device structure 100 are as follows: Figure 6 Side sectional view of section CC. Fig.7D , 8D 、13D、 Fig.14D , Fig.15D , Fig.16D , Fig.17D , Fig.18D , Fig.19D ,and Fig.20DIn some embodiments, the various stages of manufacturing the semiconductor device structure 100 are as follows: Figure 6 The cross section AA is a top view of the fin structure 112 ( Figure 4 ) in a plane along the X direction. Section BB is perpendicular to section AA and is in a plane along the Y direction of the sacrificial gate structure 130. Section CC is perpendicular to section AA and is in a plane along the Y direction of the epitaxial source / drain structure 146 ( Fig.15A ) is in a plane along the Y direction. The cross section DD is in a plane of the second semiconductor layer 108 along the X direction.

[0075] exist Fig. 8A , Figure 8B , Figure 8C ,and Fig.8D , the edge portions of the second semiconductor layers 108 of the semiconductor layer stack 104 can be removed horizontally along the X direction. Removing the edge portions of the second semiconductor layer 108 can form the cavity 131. In some embodiments, the portion of the second semiconductor layer 108 can be removed by a selective etching process such as an isotropic dry etching process. In examples where the second semiconductor layer 108 is composed of silicon germanium and the first semiconductor layer 106 is composed of silicon, a fluorine-containing etchant such as fluorine gas, nitrogen trifluoride, carbon tetrafluoride, sulfur hexafluoride, difluoromethane, fluoroform, and / or hexafluoroethane, or hydrogen fluoride can be used to selectively isotropically etch the second semiconductor layer 108. A selective wet etching process can be used to remove the second semiconductor layer 108 instead. In these examples, a wet etchant such as ammonium hydroxide, tetramethylammonium hydroxide, ethylenediamine-o-catechol, or potassium hydroxide solution can be used.

[0076] In some embodiments, the semiconductor device structure 100 may be exposed to a fluorine-containing etchant to remove the edge portion of the second semiconductor layer 108, and the process temperature may be less than or equal to about 350° C., such as about 50° C. to about 250° C. or lower. In some embodiments, the fluorine-containing etchant includes hydrogen fluoride, carbon tetrafluoride, fluorine gas, hexafluoroethane, a combination of hydrofluoric acid and fluorine gas, or other suitable fluorine-containing etchants. The process pressure may be about 0.1 Torr to about 10 Torr. The semiconductor device structure 100 may be exposed to the fluorine-containing etchant for a time period of about 1 minute to about 30 minutes.

[0077] In the case where the dry etching process uses a fluorine-based etchant, fluorine residues (i.e., surface fluorination) may remain on the exposed surfaces of the second semiconductor layer 108, the sacrificial gate dielectric layer 132, and the gate spacer 138. After the dry etching process, a pre-cleaning process is performed to remove the residues. However, after the pre-cleaning process, the exposed surface of the second semiconductor layer 108 may have considerable critical dimension variations and irregular surface roughness, such as Fig.8DAs shown. This is because the fluorine residues on the second semiconductor layer 108 may react with the wet etchant to produce unwanted oxide deposition. The second semiconductor layer 108 has large critical dimension variations and degraded roughness, which will affect the thickness of the inner spacer formed subsequently, which may cause unwanted damage to the epitaxial source / drain structure 146 due to the damaged inner spacer. In addition, the fluorine oxide is difficult to remove and requires a longer wet etching process time, which may damage the thin sacrificial gate dielectric layer 132 and form a weak point at or near the interface between the sacrificial gate dielectric layer 132 and the second semiconductor layer 108. The oxide loss of the sacrificial gate dielectric layer 132 induced by this weakness may increase. In some examples, these weaknesses may further damage the sacrificial gate dielectric layer 132 and expose the subsequent epitaxial source / drain structure during the subsequent gate replacement process. In this way, the epitaxial source / drain structure may be damaged. The consistency of surface roughness is one of the key parameters affecting device performance. Various embodiments of the present invention control the critical dimension variation and surface roughness of the second semiconductor layer 108 in a post-processing process and improve the tolerance range of epitaxial damage, thereby improving the electrical performance of the device.

[0078] After removing the respective edge portions of the second semiconductor layer 108, some embodiments may expose the semiconductor device structure 100 to a post-treatment process 177-1, such as Fig. 9 The post-treatment process can remove fluorine and other etchant residues from the exposed surface of the semiconductor device structure 100. In some embodiments, the post-treatment process can remove fluorine and other etchant residues on the second semiconductor layer 108 exposed by the void 131. In some embodiments, a portion of the second semiconductor layer 108 can be further removed after the post-treatment process. After the post-treatment process, the amount of fluorine can be effectively reduced by 54% or more.

[0079] The post-treatment process may be a plasma process or a thermal process without plasma. The process recipe used in the post-treatment process is different from the process recipe used to remove the edge portion of the second semiconductor layer 108. For example, the etching process used to remove the edge portion of the second semiconductor layer may be a plasma dry etching process, and the post-treatment process may be a thermal process. In the example of a thermal process, the semiconductor device structure 100 may be exposed to a gas mixture, which includes a nitrogen-containing gas and a hydrogen-containing gas. The thermal process may be performed in a furnace, a rapid thermal process chamber, or any suitable thermal chamber using a heating lamp. Nitrogen-containing gases such as nitrogen and hydrogen-containing gases such as hydrogen may react with fluorine to form nitrogen trifluoride and hydrogen fluoride, which are volatile gases and can be removed by a vacuum pump. The pressure of the process chamber may be maintained at about 10 Torr to about 500 Torr, the temperature may be maintained at about 250°C to about 550°C, and it may take about 30 seconds to about 30 minutes. Suitable nitrogen-containing gases may include, but are not limited to, nitrogen, ammonia, nitrous oxide, or the like. Suitable hydrogen-containing gases may include hydrogen gas.

[0080] In some embodiments, the post-treatment process 177-1 is a plasma etching process that uses free radicals of species or plasma. For example, the post-treatment process 177-1 may use reactive species generated by nitrogen-containing gas and / or hydrogen-containing gas upstream of the reaction chamber (such as from a remote plasma generator) or in situ in the reaction chamber. Exemplary reactive species may include nitrogen plasma or neutral free radical species of nitrogen (such as nitrogen free radicals or nitrogen atoms), or hydrogen plasma or neutral free radical species of hydrogen (such as hydrogen free radicals or hydrogen atoms). Other chemical agents such as chlorine-containing gases, oxygen-containing gases, or combinations thereof may also be used. The plasma etching process may be any suitable plasma-based process, such as a decoupled plasma process, a remote plasma process, or a combination thereof. The plasma may be formed by a capacitively coupled plasma source or an inductively coupled plasma source driven by an RF power generator.

[0081] Fig.10 In some embodiments, after post-processing process 177-1 Fig.8D FIG. 1 is a diagram of a portion of a semiconductor device structure 100 of FIG. 2 . As shown, the surface roughness of the sidewall 108s of the second semiconductor layer 108 is improved due to the removal of fluorine residues by the post-treatment process 177-1. In some embodiments, which may be combined with any other embodiments of the present invention, the sidewall 108s of the second semiconductor layer 108 along the Y direction or the Z direction is substantially flat and smooth. The line width variation along the sidewall 108s (sometimes referred to as line width roughness) can be improved by at least 16% or more. In some embodiments, the line width roughness on the sidewall 108s before the post-treatment process is approximately 5.6nm, while the line width roughness on the sidewall 108s after the post-treatment process is less than 5nm (e.g., approximately 4.7nm). Improving the line width roughness can make the critical dimensions of the metal gate consistent and improve device performance. In addition, the corners A, B, C, and D of the second semiconductor layer 108 are removed (such as the junctions between the second semiconductor layer 108, the gate spacer 138, and the sacrificial gate dielectric layer 132) to form a sharper angle (approximately vertical), which will be matched with Fig.12 Details are given below.

[0082] Fig.11 In some embodiments, after post-processing process 177-1 Fig. 8AFIG. 1 is a diagram of a portion of a semiconductor device structure 100 of FIG. 1. A second semiconductor layer 108a between first semiconductor layers 106a and 106b has a uniform critical dimension, wherein an upper portion 108a1 has a first critical dimension, a middle portion 108a2 has a second critical dimension (which is substantially equal to the first critical dimension), and a lower portion 108a3 has a third critical dimension (which is substantially equal to the second critical dimension). In some embodiments, which may be combined with any other embodiments of the present invention, the first critical dimension, the second critical dimension, and the third critical dimension are slightly different from each other. In one example, the difference between the first critical dimension, the second critical dimension, and the third critical dimension is less than 3 nm.

[0083] Similarly, the second semiconductor layer 108b between the first semiconductor layers 106b and 106c has a uniform critical dimension, wherein the upper portion 108b1 has a fourth critical dimension, the middle portion 108b2 has a fifth critical dimension (which is substantially equal to the fourth critical dimension), and the lower portion 108b3 has a sixth critical dimension (which is substantially equal to the fifth critical dimension). In some embodiments, which can be combined with any other embodiments of the present invention, the fourth critical dimension, the fifth critical dimension, and the sixth critical dimension are slightly different from each other. In one example, the difference between the fourth critical dimension, the fifth critical dimension, and the sixth critical dimension is less than 3nm.

[0084] Similarly, the second semiconductor layer 108c between the first semiconductor layer 106c and the well 116 of the substrate 101 has a consistent critical dimension, wherein the upper portion 108c1 has a seventh critical dimension, the middle portion 108c2 has an eighth critical dimension (which is substantially equal to the seventh critical dimension), and the lower portion 108c3 has a ninth critical dimension (which is substantially equal to the eighth critical dimension). In some embodiments, which can be combined with any other embodiments of the present invention, the seventh critical dimension, the eighth critical dimension, and the ninth critical dimension are slightly different from each other. In one example, the difference between the seventh critical dimension, the eighth critical dimension, and the ninth critical dimension is less than 3nm.

[0085] In one embodiment, the first critical dimension, the second critical dimension, the third critical dimension, the fourth critical dimension, the fifth critical dimension, the sixth critical dimension, the seventh critical dimension, the eighth critical dimension, and the ninth critical dimension in the first device area have a first size, and the first critical dimension, the second critical dimension, the third critical dimension, the fourth critical dimension, the fifth critical dimension, the sixth critical dimension, the seventh critical dimension, the eighth critical dimension, and the ninth critical dimension in the second device area have a second size, and the second size is different from the first size.

[0086] In some embodiments, which can be combined with any other embodiments of the present invention, the first critical dimension, the second critical dimension, and the third critical dimension each have a first width W1, the fourth critical dimension, the fifth critical dimension, and the sixth critical dimension each have a second width W2 (the second width W2 is substantially equal to the first width W1), and the seventh critical dimension, the eighth critical dimension, and the ninth critical dimension each have a third width W3 (the third width W3 is substantially equal to the second width W2)

[0087] In some embodiments, which can be combined with any other embodiments of the present invention, the first critical dimension, the second critical dimension, and the third critical dimension each have a first width W1, the fourth critical dimension, the fifth critical dimension, and the sixth critical dimension each have a second width W2 (the second width W2 is substantially equal to the first width W1), and the seventh critical dimension, the eighth critical dimension, and the ninth critical dimension each have a third width W3 (the third width W3 is greater than the second width W2).

[0088] In some embodiments, which can be combined with any other embodiments of the present invention, the first critical dimension, the second critical dimension, and the third critical dimension each have a first width W1, the fourth critical dimension, the fifth critical dimension, and the sixth critical dimension each have a second width W2 (the second width W2 is greater than the first width W1), and the seventh critical dimension, the eighth critical dimension, and the ninth critical dimension each have a third width W3 (the third width W3 is greater than the second width W2), partly due to the large aspect ratio of the structure.

[0089] In some embodiments, the first width W1, the second width W2, and the third width W3 in the first device area each have a first size, and the first width W1, the second width W2, and the third width W3 in the second device area each have a second size, and the first size is different from the second size.

[0090] Although not shown, please note Fig.10 and Fig.12 The embodiments can be used with Fig.11 Various embodiments are combined to improve critical dimension variation and surface roughness after post-processing.

[0091] Fig.12 In some embodiments, after post-processing process 177-1 Fig.8DFIG. 1 is a diagram of a portion of a semiconductor device structure 100. In one embodiment, the second semiconductor layer 108 has a first sidewall 108-1 close to the sacrificial gate dielectric layer 132 on a first side of the sacrificial gate structure 130, a second sidewall 108-2 opposite to the first sidewall 108-1 and close to the sacrificial gate dielectric layer 132 on a second side of the sacrificial gate structure 130, a third sidewall 108-3 connecting the first sidewall 108-1 to the second sidewall 108-2, and a fourth sidewall 108-4 opposite to the third sidewall 108-3 and connecting the first sidewall 108-1 to the second sidewall 108-2.

[0092] In some embodiments, the angle θ1 formed by the first sidewall 108-1 and the third sidewall 108-3 is about 45 degrees to about 90 degrees. The angle θ2 formed by the first sidewall 108-1 and the fourth sidewall 108-4 is about 45 degrees to about 90 degrees. The angle θ3 formed by the second sidewall 108-2 and the third sidewall 108-3 is about 45 degrees to about 90 degrees. The angle θ4 formed by the second sidewall 108-2 and the fourth sidewall 108-4 is about 45 degrees to about 90 degrees.

[0093] In some embodiments, which can be combined with other embodiments of the present invention, angle θ1, angle θ2, angle θ3, and angle θ4 are substantially the same. In one example, angle θ1, angle θ2, angle θ3, and angle θ4 are about 50 degrees to about 70 degrees, such as about 60 degrees.

[0094] In some embodiments, which can be combined with other embodiments of the present invention, angle θ1 is substantially the same as angle θ2, and angle θ3 is substantially the same as angle θ4, wherein angle θ1 is different from angle θ3. For example, angle θ1 is greater than angle θ3. Angle θ1 can be changed to be smaller than angle θ3.

[0095] In some embodiments, which may be combined with any other embodiments of the present invention, angle θ1 is substantially the same as angle θ3, and angle θ2 is substantially the same as angle θ4, wherein angle θ1 is different from angle θ2. For example, angle θ1 is greater than angle θ2. Angle θ1 may be changed to be smaller than angle θ2.

[0096] exist Fig.12 In any of the illustrated embodiments, the second semiconductor layer 108 has a flat or smooth roughness along the Y direction and a consistent critical dimension on the third sidewall 108 - 3 and the fourth sidewall 108 - 4 .

[0097] exist Fig.13A , Fig. 13B , Fig. 13C ,and Fig.13DIn the process, a dielectric layer 144a is deposited on the exposed surface of the semiconductor device structure 100. The dielectric layer 144a also fills the cavity 131 ( Fig. 8A ). The dielectric layer 144a contacts the treated surface of the second semiconductor layer 108 exposed by the void 131. Suitable materials used for the dielectric layer 144a may include, but are not limited to, silicon oxide, silicon nitride, silicon carbide, silicon carbon phosphide, silicon oxynitride, silicon carbon oxycarbon, silicon carbon nitride, silicon carbon oxynitride, and / or other suitable materials. Other materials such as low dielectric constant materials having a dielectric constant lower than about 3.5 may also be used. The method for forming the dielectric layer 144a may be a conformal deposition process such as atomic layer deposition. In some embodiments, the dielectric layer 144a is a single-layer structure. In some embodiments, the dielectric layer 144a is a multi-layer structure containing two or more of the materials described herein.

[0098] In some embodiments, a pre-cleaning process may be performed before depositing the dielectric layer 144a. The pre-cleaning process may remove any residues or byproducts from the post-treatment process 177-1 or the etching process used to remove the second semiconductor layer 108. The pre-cleaning process may be any suitable wet cleaning process, which may use ammonium hydroxide, hydrofluoric acid or diluted hydrofluoric acid, deionized water, tetramethylammonium hydroxide, other suitable solutions, or combinations thereof. In some embodiments, the pre-cleaning process may be a standard clean 2 (SC2) followed by a standard clean 1 (SC1), wherein SC2 is a mixture of deionized water, hydrogen chloride, and hydrogen peroxide, and SC1 is a mixture of deionized water, ammonium hydroxide, and hydrogen peroxide. In some embodiments, isopropyl alcohol may be used after SC1. Other suitable wet etching processes may also be used, such as an APM process (which includes at least water, ammonium hydroxide, and hydrogen peroxide), an HPM process (which includes at least water, hydrogen peroxide, and hydrogen chloride), an SPM process (also known as piranha cleaning, which includes at least hydrogen peroxide and sulfuric acid), or any combination of the above.

[0099] exist Fig.14A , Fig. 14B , Fig. 14C ,and Fig.14D In the process, an etching process is performed to leave only a portion of the dielectric layer 144a in the cavity 131 ( Fig. 8A) and form the inner spacer 144. The removal process may be any suitable etching process such as dry etching, wet etching, or a combination thereof. The etching process may be a selective etching process, wherein the etchant used may selectively remove the dielectric layer 144a without substantially removing the sacrificial gate structure 130 and the first semiconductor layer 106. The method of removing a portion of the dielectric layer 144a may be anisotropic etching. During the anisotropic etching process, the first semiconductor layer 106 protects the dielectric layer 144a in the cavity 131. The retained second semiconductor layer 108 between the inner spacers 144 may be covered along the X direction.

[0100] exist Fig.15A , Fig. 15B , Fig. 15C ,and Fig.15D , an epitaxial source / drain structure 146 is formed in the source / drain region. The epitaxial source / drain structure 146 may be grown laterally from the first semiconductor layer 106. The epitaxial source / drain structure 146 may include one or more layers of silicon, silicon phosphide, silicon carbide, or silicon carbon phosphide (for n-type field effect transistors), or silicon, silicon germanium, or germanium (for p-type field effect transistors). The epitaxial source / drain structure 146 may be formed by an epitaxial growth method using selective epitaxial growth, chemical vapor deposition, atomic layer deposition, or molecular beam epitaxy. The second semiconductor layer 108 below the sacrificial gate structure 130 may be separated from the epitaxial source / drain structure 146 by an inner spacer 144. The epitaxial source / drain structure 146 may grow vertically and horizontally to form crystal planes, which may correspond to the crystal planes of the material used in the first semiconductor layer 106. In some examples, the epitaxial source / drain structures 146 of the fin structures may be grown and merged with the epitaxial source / drain structures 146 of adjacent fin structures, such as Fig. 15C An example is shown.

[0101] The epitaxial source / drain structure 146 may be a source / drain region. For example, one of a pair of epitaxial source / drain structures 146 is located on one side of the sacrificial gate structure 130 and may be a source region, while the other of a pair of epitaxial source / drain structures 146 is located on the other side of the sacrificial gate structure 130 and may be a drain region. A pair of epitaxial source / drain structures 146 includes an epitaxial source structure and an epitaxial drain structure connected by a channel (such as the first semiconductor layer 106). The source / drain region may be referred to as a source or a drain separately or together, depending on the context. In the embodiment of the present invention, the source and the drain may be used interchangeably, and their structures are substantially the same.

[0102] exist Fig.16A , Fig. 16B , Fig. 16C ,and Fig.16DIn the embodiment of the present invention, a contact etch stop layer 162 is conformally formed on the exposed surface of the semiconductor device structure 100. The contact etch stop layer 162 covers the sacrificial gate structure 130, the insulating material 118, the upper surface of the epitaxial source / drain structure 146, and the exposed surface of the semiconductor layer stack 104. The contact etch stop layer 162 may include an oxygen-containing material or a nitrogen-containing material, such as silicon nitride, silicon carbonitride, silicon oxynitride, carbon nitride, silicon oxide, silicon oxycarbide, the like, or a combination thereof, and may be formed by chemical vapor deposition, plasma-assisted chemical vapor deposition, atomic layer deposition, or any suitable deposition technique. Then, a first interlayer dielectric layer 164 is formed on the contact etch stop layer 162 on the semiconductor device structure 100. The material used for the first interlayer dielectric layer 164 may include a compound containing silicon, oxygen, carbon, and / or hydrogen, such as silicon oxide, an oxide of tetraethoxysilane, silicon hydroxide carbide, or silicon oxycarbide. Organic materials such as polymers may also be used for the first interlayer dielectric layer 164. The first interlayer dielectric layer 164 may be deposited by a plasma-assisted chemical vapor deposition process or other suitable deposition techniques. In some embodiments, after forming the first interlayer dielectric layer 164, a thermal process may be performed on the semiconductor device structure 100 to anneal the first interlayer dielectric layer 164.

[0103] exist Fig.17A , Fig. 17B , Fig. 17C ,and Fig.17D In the process, after forming the first interlayer dielectric layer 164 , a planarization step such as chemical mechanical polishing may be performed on the semiconductor device structure 100 until the sacrificial gate layer 134 is exposed.

[0104] exist Fig.18A , Fig.18B , Fig.18C ,and Fig.18D , the sacrificial gate structure 130 and the second semiconductor layer 108 are removed in sequence. The sacrificial gate structure 130 and the second semiconductor layer 108 are removed to form an opening 166 between the gate spacers 138 and between the adjacent first semiconductor layers 106. The first interlayer dielectric layer 164 can protect the epitaxial source / drain structure 146 during the removal process. The sacrificial gate structure 130 can be removed by plasma dry etching and / or wet etching. The sacrificial gate layer 134 can be removed by a suitable process such as dry etching, wet etching, or a combination thereof, and then the sacrificial gate dielectric layer 132 can be removed by any suitable process such as dry etching, wet etching, or a combination thereof. In some embodiments, a wet etchant such as a tetramethylammonium hydroxide solution can be used to selectively remove the sacrificial gate layer 134 without removing the gate spacers 138, the first interlayer dielectric layer 164, and the contact etch stop layer 162.

[0105] Removing the sacrificial gate structure 130 may expose the first semiconductor layer 106 and the second semiconductor layer 108. An etching process such as any suitable etching process (e.g., dry etching, wet etching, or a combination thereof) may then be performed to remove the second semiconductor layer 108. The etching process may be a selective etching process that removes the second semiconductor layer 108 but does not remove the gate spacer 138, the first interlayer dielectric layer 164, the contact etch stop layer 162, and the first semiconductor layer 106. In the example where the second semiconductor layer 108 is composed of silicon germanium or germanium and the first semiconductor layer 106 is composed of silicon, the chemistry used in the selective wet etching process may remove silicon germanium without substantially affecting the silicon and the dielectric materials of the gate spacer 138, the inner spacer 144, the first interlayer dielectric layer 164, and the contact etch stop layer 162. In one embodiment, the method for removing the second semiconductor layer 108 may be a wet etchant (such as but not limited to hydrofluoric acid, nitric acid, hydrogen chloride, or phosphoric acid), a dry etchant (such as a fluorine-based gas such as fluorine gas or a chlorine-based gas such as chlorine gas), or any suitable isotropic etchant. Once the etching process is completed, a portion of the first semiconductor layer 106 not covered by the inner spacer 144 will be exposed to the opening 166.

[0106] exist Fig.19A , Fig.19B , Fig.19C ,and Fig.19D In the embodiment of the present invention, a replacement gate structure 190 is formed. The replacement gate structures 190 may each include a gate dielectric layer 180 and a gate layer 182. In some embodiments, an interfacial layer (not shown) may be formed between the gate dielectric layer 180 and the first semiconductor layer 106. The interfacial layer may also be formed on the exposed surface of the substrate 101. The interfacial layer may include or may be an oxide (such as silicon oxide), a nitride (such as silicon nitride, silicon oxynitride, oxynitride, or the like) formed by thermal oxidation or chemical oxidation of the first semiconductor layer 106, and / or a dielectric layer (such as hafnium silicate). The gate dielectric layer 180 is then formed on the exposed surface of the semiconductor device structure 100, such as on the interfacial layer (if present), the sidewalls of the gate spacer 138, the first interlayer dielectric layer 164, and the upper surface of the contact etch stop layer 162. The gate dielectric layer 180 is formed of a material having different chemical properties from the material of the sacrificial gate dielectric layer 132. The gate dielectric layer 180 may include or may be a high-k dielectric material such as hafnium oxide, hafnium silicate, hafnium silicon oxynitride, hafnium aluminum oxide, hafnium lanthanum oxide, hafnium zirconium oxide, hafnium tantalum oxide, hafnium titanium oxide, lanthanum oxide, aluminum oxide, aluminum silicon oxide, zirconium oxide, titanium oxide, tantalum oxide, yttrium oxide, silicon oxynitride, or other suitable high-k dielectric materials. The gate dielectric layer 180 may be a compliant layer formed by a compliant process such as an atomic layer deposition process, a plasma-assisted chemical vapor deposition process, a molecular beam deposition process, the like, or a combination thereof. The gate dielectric layer 180 may have a thickness of about 0.3 nm to about 5 nm.

[0107] After forming the interfacial layer (if any) and the gate dielectric layer 180, a gate layer 182 may be formed on the gate dielectric layer 180. The gate layer 182 fills the opening 166 ( Fig.15A ) and surround a portion of each of the first semiconductor layer 106. The gate layer 182 includes one or more layers of conductive materials such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, titanium nitride, tungsten nitride, tungsten carbonitride, titanium aluminum, titanium tantalum nitride, titanium aluminum nitride, tantalum nitride, tantalum carbonitride, tantalum carbide, tantalum silicon nitride, metal alloys, other suitable materials, and / or combinations thereof. The gate layer 182 may be formed by physical vapor deposition, chemical vapor deposition, atomic layer deposition, electroplating, or other suitable methods. In some embodiments, one or more compliant layers (not shown, if multiple layers are formed, they are deposited sequentially) may be deposited between the gate dielectric layer 180 and the gate layer 182 as appropriate. The one or more compliant layers formed as appropriate may include one or more barrier and / or capping layers and one or more work function adjustment layers. One or more barrier and / or capping layers may include or be nitrides, silicon nitrides, carbonitrides, and / or aluminum nitrides of tantalum and / or titanium; nitrides, carbonitrides, and / or carbides of tungsten; the like, or a combination thereof. One or more work function adjustment layers may include or be nitrides, silicon nitrides, carbonitrides, aluminum nitrides, aluminum oxides, and / or aluminum carbides of titanium and / or tantalum; nitrides, carbonitrides, and / or carbides of tungsten, cobalt, platinum; the like, or a combination thereof.

[0108] Portions of the gate layer 182, one or more optional compliant layers (if present), and the gate dielectric layer 180 that are above the upper surfaces of the first interlayer dielectric layer 164, the contact etch stop layer 162, and the gate spacers 138 may be removed by a planarization process such as a chemical mechanical polishing process. After the chemical mechanical polishing process, the upper surfaces of the first interlayer dielectric layer 164, the contact etch stop layer 162, the gate spacers 138, and the gate layer 182 are substantially coplanar.

[0109] exist Fig. 20A , Fig. 20B , Fig. 20C ,and Fig.20D In the embodiment of the present invention, a contact opening is formed through the first interlayer dielectric layer 164 and the contact etch stop layer 162 to expose the epitaxial source / drain structure 146. A silicide layer 184 is then formed on the epitaxial source / drain structure 146, and a source / drain contact 186 is formed in the contact opening on the silicide layer 184. The source / drain contact 186 may include a conductive material such as ruthenium, molybdenum, cobalt, nickel, tungsten, titanium, tantalum, copper, aluminum, titanium nitride, or tantalum nitride. Although not shown, a barrier layer (such as titanium nitride, tantalum nitride, or the like) may be formed on the sidewalls of the contact opening before forming the source / drain contact 186.

[0110] After forming the contact opening, a silicide layer 184 may be formed on the epitaxial source / drain structure 146. The silicide layer 184 conductively couples the epitaxial source / drain structure 146 to the source / drain contact 186 subsequently formed in the contact opening. The silicide layer 184 may be formed by depositing a metal source layer on the epitaxial source / drain structure 146 and performing a rapid thermal annealing process. During the rapid thermal annealing process, a portion of the metal source layer on the epitaxial source / drain structure 146 may react with silicon in the epitaxial source / drain structure 146 to form the silicide layer 184. The unreacted portion of the metal source is then removed. The silicide layer 184 may include a silicide of a metal or a metal alloy, and the metal includes a noble metal, a refractory metal, a rare earth metal, an alloy thereof, or a combination thereof. A conductive material is then formed in the contact opening, and the source / drain contact 186 is formed. The conductive material may include one or more of ruthenium, molybdenum, cobalt, nickel, tungsten, titanium, tantalum, copper, aluminum, titanium nitride, and tantalum nitride. Although not shown, a barrier layer (such as titanium nitride, tantalum nitride, or the like) may be formed on the sidewalls of the contact opening before forming the source / drain contacts 186. A planarization process such as chemical mechanical polishing may then be performed to remove excess deposited contact material and expose the upper surface of the gate layer 182.

[0111] It should be understood that the semiconductor device structure 100 may be subjected to subsequent CMOS and / or BEOL processes to form a variety of structures such as transistors, contacts / vias, interconnect metal layers, dielectric layers, passivation layers, or the like. The semiconductor device structure 100 may also include backside contacts (not shown) on the back side of the substrate 101, such that the source or drain of the epitaxial source / drain structure 146 is connected to a backside power rail (e.g., a positive voltage or a negative voltage) via the backside contacts.

[0112] The various embodiments or examples described herein may provide more advantages than the prior art. In the embodiments of the present invention, before forming the inner spacer, a post-treatment process is performed using reactive species or free radicals generated from a nitrogen-containing gas and / or a hydrogen-containing gas to remove fluorine residues from the exposed surface of the silicon germanium layer. The silicon germanium layer and the nanostructured channel layer are stacked alternately. The post-treatment process can reduce the surface roughness and critical dimension variation of the silicon germanium layer, and avoid damage to the sacrificial gate dielectric layer and the inner spacer. In this way, the integrity of the epitaxial source / drain structure can be maintained during the subsequent gate replacement process.

[0113] One embodiment is a method for forming a semiconductor device structure. The method includes forming a fin structure from a semiconductor layer stack including a plurality of first semiconductor layers and a plurality of second semiconductor layers that are staggered and stacked; removing an edge portion of the second semiconductor layer by an etching process; performing a post-treatment process on an exposed surface of the second semiconductor layer after the etching process to remove residues from the exposed surface of the second semiconductor layer. The method also includes performing a pre-cleaning process on a treated surface of the second semiconductor layer after the post-treatment process; and forming an inner spacer to contact the treated surface of the second semiconductor layer.

[0114] In some embodiments, the post-treatment process includes exposing the second semiconductor layer to a gas mixture in a thermal chamber, and the gas mixture includes a nitrogen-containing gas and a hydrogen-containing gas.

[0115] In some embodiments, the post-treatment process performed in the thermal chamber is maintained at a pressure greater than or equal to about 10 Torr.

[0116] In some embodiments, the temperature of the post-treatment process in the thermal chamber is about 250°C to about 450°C.

[0117] In some embodiments, the post-treatment process includes exposing the second semiconductor layer to reactive species generated by a nitrogen-containing gas and a hydrogen-containing gas.

[0118] In some embodiments, the post-treatment process includes exposing the second semiconductor layer to nitrogen radicals or nitrogen atoms generated in a reaction chamber upstream from a remote plasma generator.

[0119] In some embodiments, the post-treatment process further includes exposing the second semiconductor layer to hydrogen radicals or hydrogen atoms.

[0120] In some embodiments, the etching process is a plasma-based etching process using a fluorine-containing etchant.

[0121] In some embodiments, the pre-cleaning process is a wet etching process.

[0122] Another embodiment is a method for forming a semiconductor device structure. The method includes forming a sacrificial gate structure on a portion of a fin-shaped structure, and the fin-shaped structure includes a plurality of first semiconductor layers and a plurality of second semiconductor layers that are staggered and stacked; removing the portion of the fin-shaped structure not covered by the sacrificial gate structure; and using an etching process to remove an edge portion of the second semiconductor layer to form a cavity between two adjacent first semiconductor layers, wherein the exposed surface of the second semiconductor layer after the etching process has a first line width roughness. The method also includes, after the etching process, performing a treatment process on the exposed surface of the second semiconductor layer, so that the exposed surface of the second semiconductor layer after the treatment process has a second line width roughness, and the second line width roughness is different from the first line width roughness. The method further includes forming an inner spacer in the cavity.

[0123] In some embodiments, the second LWR is less than the first LWR.

[0124] In some embodiments, the etching process is a plasma-based etching process using a fluorine-containing etchant.

[0125] In some embodiments, an angle formed by a sidewall of the second semiconductor layer and the inter-gate spacer formed on the sacrificial gate structure is between about 50 degrees and about 70 degrees.

[0126] In some embodiments, the method further comprises exposing the exposed surface of the second semiconductor layer to a pre-cleaning process after the treating process.

[0127] In some embodiments, the pre-cleaning process is a wet etching process using hydrofluoric acid or diluted hydrofluoric acid.

[0128] Another embodiment is a method for forming a semiconductor device structure. The method includes providing a fin structure including a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked in an alternating manner; forming a sacrificial gate structure and a gate spacer on a portion of the fin structure; selectively removing a portion of each of the second semiconductor layers so that fluorine covers the exposed surface of the second semiconductor layer. The method also includes treating the exposed surface of each of the second semiconductor layers to remove the fluorine; cleaning the treated surface of each of the second semiconductor layers with a wet etchant; and forming an inner spacer between two adjacent first semiconductor layers to contact the cleaned surface of each of the second semiconductor layers.

[0129] In some embodiments, free radicals in the process step are formed from nitrogen-containing gases and hydrogen-containing gases in a thermal process chamber.

[0130] In some embodiments, the temperature of the thermal processing chamber is maintained at about 250°C to about 350°C.

[0131] In some embodiments, the line width roughness of each processed surface of the second semiconductor layer is less than or equal to about 5 nm.

[0132] In some embodiments, the gate spacer forms an angle of about 45 degrees to about 90 degrees with the processed surface of the second semiconductor layer.

[0133] The features of the above embodiments are helpful for those with ordinary knowledge in the art to understand the present invention. Those with ordinary knowledge in the art should understand that the present invention can be used as a basis to design and change other processes and structures to achieve the same purpose and / or the same advantages of the above embodiments. Those with ordinary knowledge in the art should also understand that these equivalent substitutions do not depart from the spirit and scope of the present invention, and can be changed, replaced, or modified without departing from the spirit and scope of the present invention.

Claims

1. A method for forming a semiconductor device structure, comprising: Forming a fin structure from a semiconductor layer stack including a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked alternately; removing edge portions of the plurality of second semiconductor layers by an etching process; After the etching process, performing a post-treatment process on the exposed surfaces of the plurality of second semiconductor layers; After the post-treatment process, performing a pre-cleaning process on the treated surfaces of the plurality of second semiconductor layers; as well as An inner spacer is formed to contact the processed surfaces of the plurality of second semiconductor layers.

2. The method for forming a semiconductor device structure as claimed in claim 1, wherein the post-treatment process comprises exposing the plurality of second semiconductor layers to a gas mixture in a thermal chamber, and the gas mixture comprises a nitrogen-containing gas and a hydrogen-containing gas.

3. The method for forming a semiconductor device structure as claimed in claim 2, wherein the pressure of the post-treatment process performed in the thermal chamber is maintained at a pressure greater than or equal to about 10 Torr. 4 . The method for forming a semiconductor device structure as claimed in claim 2 , wherein the temperature of performing the post-treatment process in the thermal chamber is about 250° C. to about 450° C. 5 . The method for forming a semiconductor device structure as claimed in claim 1 , wherein the post-treatment process comprises exposing the plurality of second semiconductor layers to reactive species generated by a nitrogen-containing gas and a hydrogen-containing gas. 6 . The method for forming a semiconductor device structure as claimed in claim 5 , wherein the post-treatment process comprises exposing the plurality of second semiconductor layers to nitrogen radicals or nitrogen atoms generated in an upstream reaction chamber from a remote plasma generator. 7 . The method for forming a semiconductor device structure as claimed in claim 6 , wherein the post-treatment process further comprises exposing the plurality of second semiconductor layers to hydrogen radicals or hydrogen atoms.

8. The method for forming a semiconductor device structure as claimed in claim 1, wherein the etching process is a plasma-based etching process using a fluorine-containing etchant. 9 . The method for forming a semiconductor device structure as claimed in claim 8 , wherein the pre-cleaning process is a wet etching process.

10. A method for forming a semiconductor device structure, comprising: Forming a sacrificial gate structure on a portion of a fin-shaped structure, wherein the fin-shaped structure includes a plurality of first semiconductor layers and a plurality of second semiconductor layers that are alternately stacked; removing a portion of the fin structure not covered by the sacrificial gate structure; Using an etching process to remove edge portions of the plurality of second semiconductor layers to form a cavity between two adjacent plurality of first semiconductor layers, wherein exposed surfaces of the plurality of second semiconductor layers after the etching process have a first line width roughness; After the etching process, a treatment process is performed on the exposed surfaces of the plurality of second semiconductor layers, so that the exposed surfaces of the plurality of second semiconductor layers after the treatment process have a second line width roughness, and the second line width roughness is different from the first line width roughness; and An inner spacer is formed in the cavity. 11 . The method for forming a semiconductor device structure as claimed in claim 10 , wherein the second line width roughness is smaller than the first line width roughness.

12. The method for forming a semiconductor device structure as claimed in claim 10, wherein the etching process is a plasma-based etching process using a fluorine-containing etchant. 13 . The method for forming a semiconductor device structure as claimed in claim 10 , wherein an angle formed by a sidewall of the second semiconductor layer and an inter-gate spacer formed on the sacrificial gate structure is between about 50 degrees and about 70 degrees.

14. The method for forming a semiconductor device structure according to claim 10, further comprising: After the treating process, the exposed surfaces of the plurality of second semiconductor layers are exposed to a pre-cleaning process. 15 . The method for forming a semiconductor device structure as claimed in claim 14 , wherein the pre-cleaning process is a wet etching process using hydrofluoric acid or diluted hydrofluoric acid.

16. A method for forming a semiconductor device structure, comprising: A fin structure is provided, which includes a plurality of first semiconductor layers and a plurality of second semiconductor layers which are alternately stacked; forming a sacrificial gate structure and a gate spacer on a portion of the fin structure; Selectively removing a portion of each of the plurality of second semiconductor layers so that fluorine covers the exposed surfaces of the plurality of second semiconductor layers; treating the exposed surfaces of each of the plurality of second semiconductor layers to remove fluorine; Cleaning the processed surfaces of each of the plurality of second semiconductor layers with a wet etchant; as well as An inner spacer is formed between two adjacent first semiconductor layers to contact the cleaned surfaces of the second semiconductor layers.

17. The method of forming a semiconductor device structure as claimed in claim 16, wherein the free radicals in the treating step are formed by nitrogen-containing gas and hydrogen-containing gas in a thermal process chamber.

18. The method for forming a semiconductor device structure as claimed in claim 17, wherein the temperature of the thermal process chamber is maintained at about 250°C to about 350°C. 19 . The method for forming a semiconductor device structure as claimed in claim 17 , wherein a line width roughness of a surface of each of the plurality of second semiconductor layers after being processed is less than or equal to about 5 nm. 20 . The method for forming a semiconductor device structure as claimed in claim 16 , wherein an angle formed between the gate spacer and the processed surfaces of the plurality of second semiconductor layers is about 45 degrees to about 90 degrees.

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