Semiconductor Structure and Method for Forming the Same

Abstract

An embodiment of the present invention provides a semiconductor structure and a method for forming the same. The forming method includes: providing a substrate including a first region and a second region surrounding and connected to the first region; sequentially forming a stacked first source layer, a first source trench layer, a first channel layer, and a first channel-drain layer in the first region; forming a first gate dielectric layer in the second region to surround and cover the sidewalls of the first source trench layer, the first channel layer, and the first channel-drain layer; forming a first gate structure layer to surround and cover the first gate dielectric layer; sequentially forming a stacked first drain layer, a sacrificial layer, a second source layer, a second source trench layer, a second channel layer, and a second channel-drain layer on the first channel-drain layer; forming a second gate dielectric layer in the second region to surround and cover the sidewalls of the second source trench layer, the second channel layer, and the second channel-drain layer; forming a second gate structure layer to surround and cover the second gate dielectric layer; and forming a second drain layer covering the second channel-drain layer. By adopting the above forming method, the on-state current of the semiconductor transistor can be further improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same. Background Art

[0002] A semiconductor transistor is one of the most important components in modern integrated circuits. The basic structure of a transistor includes: a semiconductor substrate; a gate structure located on the surface of the semiconductor substrate, the gate structure including a gate dielectric layer located on the surface of the semiconductor substrate and a gate layer located on the surface of the gate dielectric layer; source / drain doping regions in the semiconductor substrate on both sides of the gate structure; and a semiconductor channel between the source / drain doping regions.

[0003] However, in the existing transistor structure, the increase in the on-state current of the transistor is limited, and it is impossible to further increase the on-state current of the semiconductor transistor. Summary of the Invention

[0004] The technical problem solved by the present invention is to further increase the on-state current of a semiconductor transistor by providing a semiconductor structure and a method for forming the same.

[0005] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate including a first region and a second region surrounding and connected to the first region; sequentially forming a stacked first source layer, a first source channel layer, a first channel layer, and a first channel drain layer in the first region; forming a first gate dielectric layer in the second region surrounding and covering the sidewalls of the first source channel layer, the first channel layer, and the first channel drain layer; forming a first gate structure layer surrounding and covering the first gate dielectric layer; sequentially forming a stacked first drain layer, a sacrificial layer, a second source layer, a second source channel layer, a second channel layer, and a second channel drain layer on the first channel drain layer; forming a second gate dielectric layer in the second region surrounding and covering the sidewalls of the second source channel layer, the second channel layer, and the second channel drain layer; forming a second gate structure layer surrounding and covering the second gate dielectric layer; and forming a second drain layer covering the second channel drain layer.

[0006] Optionally, in a direction perpendicular to the surface of the substrate, the sidewalls of the first source layer, the first source channel layer, the first channel layer, the first channel drain layer, the first drain layer, the sacrificial layer, the second source layer, the second source channel layer, the second channel layer, the second channel drain layer, and the second drain layer are flush.

[0007] Optionally, the material of the first source channel layer includes: silicon germanide, the material of the first channel drain layer includes: silicon germanide, the material of the second source channel layer includes: silicon carbide, the material of the second channel drain layer includes: silicon carbide, and the material of the sacrificial layer includes: silicon germanide.

[0008] Optionally, after forming the first drain-source layer and before forming the first gate dielectric layer, the forming method further includes: forming a first filling layer on the substrate in the second region, where the first filling layer covers sidewalls of the first source layer, the first source-drain layer, the first channel layer, and the first drain-source layer; removing a part of the first filling layer to expose the sidewalls of the first source-drain layer, the first channel layer, and the first drain-source layer, so as to form a first filling layer trench; the first filling layer trench includes: a first filling layer trench sidewall opposite to the sidewalls of the first source-drain layer, the first channel layer, and the first drain-source layer, and a first filling layer trench bottom.

[0009] Optionally, in the first filling layer trench, a first gate dielectric layer is formed to surround and cover the sidewalls of the first source-drain layer, the first channel layer, and the first drain-source layer; the first gate dielectric layer further covers the first filling layer trench bottom and the first filling layer trench sidewall.

[0010] Optionally, after forming the first filling layer trench and before forming the first gate dielectric layer, the forming method further includes: forming a first metal layer outside the first filling layer trench to cover the surfaces of the first filling layer and the first drain-source layer.

[0011] Optionally, the first gate structure layer is filled in the first filling layer trench, and the first gate structure layer surrounds and covers the first gate dielectric layer.

[0012] Optionally, the forming method further includes: forming a first thin layer covering the surface of the first gate structure layer; the first thin layer further covers the first filling layer.

[0013] Optionally, after forming the second drain-source layer and before forming the second gate dielectric layer, the forming method further includes: forming a second filling layer on the first thin layer, where the second filling layer covers sidewalls of the first drain layer, the sacrificial layer, the second source layer, the second source-drain layer, the second channel layer, and the second drain-source layer; removing a part of the second filling layer to expose the sidewalls of the sacrificial layer, the second source layer, the second source-drain layer, the second channel layer, and the second drain-source layer, so as to form a second filling layer trench, and removing the sacrificial layer to form a first gap between the first drain layer and the second source layer.

[0014] Optionally, a third filling layer is filled in the second filling layer trench and the first gap; removing a part of the third filling layer to expose the sidewalls of the second source-drain layer, the second channel layer, and the second drain-source layer, so as to form a third filling layer trench; the third filling layer trench includes: a third filling layer trench sidewall opposite to the sidewalls of the second source-drain layer, the second channel layer, and the second drain-source layer, and a third filling layer trench bottom.

[0015] Optionally, a second gate dielectric layer is formed in the third filling layer trench to surround and cover the sidewalls of the second source trench layer, the second channel layer, and the second drain trench layer; the second gate dielectric layer also covers the bottom and sidewalls of the third filling layer trench.

[0016] Optionally, after forming the third filling layer trench and before forming the second gate dielectric layer, the forming method further includes: forming a second metal layer outside the third filling layer trench to cover the surfaces of the second filling layer and the second drain trench layer.

[0017] Optionally, the second gate structure layer is filled in the third filling layer trench, and the second gate structure layer surrounds and covers the second gate dielectric layer.

[0018] Optionally, the forming method further includes: forming a second thin layer on the surface of the second gate structure layer after forming the second gate structure layer and before forming the second drain layer, and the second thin layer also covers the second filling layer.

[0019] Optionally, an interlayer dielectric layer covering the second thin layer and the second drain layer is formed; a first source layer via hole penetrating through the interlayer dielectric layer, the second drain layer, the second drain-channel layer, the second channel layer, the second source-channel layer, the second source layer, the third filling layer, the first drain layer, the first drain-channel layer, the first channel layer, and the first source-channel layer is formed; a first channel layer via hole penetrating through the interlayer dielectric layer, the second drain layer, the second drain-channel layer, the second channel layer, the second source-channel layer, the second source layer, the third filling layer, the first drain layer, and the first drain-channel layer is formed; a first drain layer via hole penetrating through the interlayer dielectric layer, the second drain layer, the second drain-channel layer, the second channel layer, the second source-channel layer, and the second source layer is formed; a second source layer via hole penetrating through the interlayer dielectric layer, the second drain layer, the second drain-channel layer, and the second channel layer is formed; a second channel layer via hole penetrating through the interlayer dielectric layer and the second drain layer is formed; a second drain layer via hole penetrating through the interlayer dielectric layer is formed; a first gate structure layer via hole penetrating through the interlayer dielectric layer, the second thin layer, the second filling layer, and the first thin layer is formed; a second gate structure layer via hole penetrating through the interlayer dielectric layer and the second thin layer is formed; a via isolation layer covering the sidewalls of the first source layer via hole, the first channel layer via hole, the first drain layer via hole, the second source layer via hole, the second channel layer via hole, and the second drain layer via hole is formed; a first source layer plug filling the first source layer via hole is formed; a first channel layer plug filling the first channel layer via hole is formed; a first drain layer plug filling the first drain layer via hole is formed; a second source layer plug filling the second source layer via hole is formed; a second channel layer plug filling the second channel layer via hole is formed; a second drain layer plug filling the second drain layer via hole is formed; a first gate structure layer plug filling the first gate structure layer via hole is formed; a second gate structure layer plug filling the second gate structure layer via hole is formed.

[0020] Optionally, in the formation method, the first source layer, the first source-channel layer, the first channel layer, the first drain-channel layer, the first drain layer, the second source layer, the second source-channel layer, the second channel layer, and the second drain-channel layer are all formed by an epitaxial process.

[0021] Optionally, the parameters of the epitaxial process include: the temperature ranges from 600 degrees Celsius to 800 degrees Celsius.

[0022] Optionally, the parameters of the epitaxial process at least further include one of the following: the pressure is from 70 Torr to 90 Torr; the flow rate of Purge MainH2 is from 3200 sccm to 3800 sccm; the flow rate of Purge SlitH2 is from 80 sccm to 120 sccm; the flow rate of the silicon source gas is from 120 sccm to 180 sccm; the epitaxial rate is from 200 angstroms per minute to 300 angstroms per minute.

[0023] Correspondingly, the present application further provides a semiconductor structure, including: a substrate, including a first region and a second region surrounding and connected to the first region; a first source layer, a first source trench layer, a first channel layer, and a first drain trench layer sequentially stacked in the first region; a first gate dielectric layer, located in the second region and surrounding and covering the sidewalls of the first source trench layer, the first channel layer, and the first drain trench layer; a first gate structure layer, surrounding and covering the first gate dielectric layer; a first drain layer, a second source layer, a second source trench layer, a second channel layer, and a second drain trench layer sequentially stacked on the first drain trench layer; a second gate dielectric layer, located in the second region and surrounding and covering the sidewalls of the second source trench layer, the second channel layer, and the second drain trench layer; a second gate structure layer, surrounding and covering the second gate dielectric layer; and a second drain layer, located on the second drain trench layer.

[0024] Optionally, along the direction perpendicular to the surface of the substrate, the sidewalls of the first source layer, the first source trench layer, the first channel layer, the first drain trench layer, the first drain layer, the second source layer, the second source trench layer, the second channel layer, the second drain trench layer, and the second drain layer are flush.

[0025] Optionally, the semiconductor structure further includes: a first filling layer, located in the second region, and flush with the surface of the first drain trench layer along the direction parallel to the surface of the substrate; a first filling layer trench, located in the first filling layer, and exposing the sidewalls of the first source trench layer, the first channel layer, and the first drain trench layer; the first filling layer trench includes: a first filling layer trench sidewall and a first filling layer trench bottom opposite to the sidewalls of the first source trench layer, the first channel layer, and the first drain trench layer; the first gate dielectric layer is located in the first filling layer trench, surrounding and covering the sidewalls of the first source trench layer, the first channel layer, and the first drain trench layer; the first gate dielectric layer also covers the first filling layer trench sidewall and the first filling layer trench bottom; and a first gate structure layer, filling the first filling layer trench and surrounding and covering the first gate dielectric layer.

[0026] Optionally, the semiconductor structure further includes: a first thin layer covering the surfaces of the first filling layer and the first gate structure layer; a second filling layer located in the second region and flush with the surface of the second drain and source layer in the first region along a direction parallel to the surface of the substrate; a first spacer located between the first drain layer and the second source layer; a second filling layer trench located in the second filling layer, the second filling layer trench exposing the sidewalls of the second source layer, the second source trench layer, the second channel layer, the second drain and source layer, and the first spacer; a third filling layer filling the first spacer and also filling a part of the second filling layer trench to form a third filling layer trench, the third filling layer trench exposing the sidewalls of the second source trench layer, the second channel layer, and the second drain and source layer; the third filling layer trench including: the sidewall of the third filling layer trench opposite to the sidewalls of the second source trench layer, the second channel layer, and the second drain and source layer, and the bottom of the third filling layer trench; the second gate dielectric layer located in the third filling layer trench and surrounding and covering the sidewalls of the second source trench layer, the second channel layer, and the second drain and source layer; the second gate dielectric layer further covering the sidewall and the bottom of the third filling layer trench; a second gate structure layer filling the third filling layer trench and surrounding and covering the second gate dielectric layer.

[0027] Optionally, the semiconductor structure further includes: a second thin layer covering the surfaces of the second filling layer and the second gate structure layer; an interlayer dielectric layer covering the surfaces of the second thin layer and the second drain layer.

[0028] Optionally, the semiconductor structure further includes: a first source layer via: penetrating the interlayer dielectric layer, the second drain layer, the second drain-channel layer, the second channel layer, the second source-channel layer, the second source layer, the third filling layer, the first drain layer, the first drain-channel layer, the first channel layer, and the first source-channel layer; a first channel layer via, penetrating the interlayer dielectric layer, the second drain layer, the second drain-channel layer, the second channel layer, the second source-channel layer, the second source layer, the third filling layer, the first drain layer, the first drain-channel layer; a first drain layer via, penetrating the interlayer dielectric layer, the second drain layer, the second drain-channel layer, the second channel layer, the second source-channel layer, the second source layer, the third filling layer; a second source layer via, penetrating the interlayer dielectric layer, the second drain layer, the second drain-channel layer, the second channel layer, the second source-channel layer; a second channel layer via, formed to penetrate the interlayer dielectric layer, the second drain layer, the second drain-channel layer; a second drain layer via, penetrating the interlayer dielectric layer; a via isolation layer, covering the sidewalls of the first source layer via, the first channel layer via, the first drain layer via, the second source layer via, the second channel layer via, and the second drain layer via; a first gate structure layer via, penetrating the interlayer dielectric layer, the second thin layer, the second filling layer, and the first thin layer; a second gate structure layer via, penetrating the interlayer dielectric layer and the second thin layer; a first source layer plug, filled in the first source layer via and contacting the first source layer; a first channel layer plug, filled in the first channel layer via and contacting the first channel layer; a first drain layer plug, filled in the first drain layer via and contacting the first drain layer; a second source layer plug, filled in the second source layer via and contacting the second source layer; a second channel layer plug, filled in the second channel layer via and contacting the second channel layer; a second drain layer plug, filled in the second drain layer via and contacting the second drain layer; a first gate structure layer plug, filled in the first gate structure layer via and contacting the first gate structure layer; a second gate structure layer plug, filled in the second gate structure layer via and contacting the second gate structure layer.

[0029] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0030] A method for forming a semiconductor structure provided by an embodiment of the present invention includes: providing a substrate, the substrate including a first region; sequentially forming a stacked first source layer, a first source trench layer, a first channel layer, and a first channel-drain layer in the first region, and sequentially forming a stacked first drain layer, a second source layer, a second source trench layer, a second channel layer, and a second channel-drain layer on the first channel-drain layer; one type of carrier of the semiconductor structure flows from the first source layer through the first source trench layer, the first channel layer, and the first channel-drain layer to the first drain layer in a direction perpendicular to the surface of the substrate, and another type of carrier of the semiconductor structure flows from the second source layer through the second source trench layer, the second channel layer, and the second channel-drain layer to the second drain layer; in a direction perpendicular to the surface of the substrate, the thickness of the first channel layer corresponds to the channel length of one type of carrier, and the thickness of the second channel layer corresponds to the channel length of another type of carrier. The thicknesses of the first channel layer and the second channel layer can be reduced by a film-forming process to reduce the channel length of the carriers, further improving the on-state current of the semiconductor transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained according to the provided drawings without creative efforts.

[0032] Figure 1 is a schematic structural diagram of a semiconductor transistor;

[0033] Figures 2 to 22 is a schematic structural diagram of the method for forming a semiconductor structure according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0034] The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present application.

[0035] As described in the background art, in the existing transistor structure, there is a problem that the improvement of the on-state current of the transistor is limited. The following will analyze the reason why the improvement of the on-state current of the transistor is limited in combination with Figure 1 the transistor structure shown,

[0036] Refer to Figure 1 , which is a schematic structural diagram of a semiconductor transistor.

[0037] The structure of the semiconductor transistor includes:

[0038] A semiconductor substrate 100.

[0039] A gate structure located on the surface of the semiconductor substrate 100, the gate structure including a gate dielectric layer 101 located on the surface of the semiconductor substrate 100 and a gate layer 102 located on the surface of the gate dielectric layer.

[0040] Source doping regions 103 and drain doping regions 104 on the semiconductor substrate on both sides of the gate structure.

[0041] A semiconductor channel 105 located between the source doping region 103 and the drain doping region 104.

[0042] Continue to refer to Figure 1 , carriers of the semiconductor structure flow from the source doping region 103 to the drain doping region 104 along the direction F parallel to the surface of the semiconductor substrate 100, the displacement magnitude of the carriers is the length L of the semiconductor channel 105, and the length L determines the on-state current of the semiconductor transistor.

[0043] To increase the on-state current of the semiconductor transistor, the common practice is: along the direction parallel to the surface of the semiconductor substrate 100, by means of an exposure process, to reduce the length L of the semiconductor channel. However, the resolution of the lithography machine (the minimum resolvable feature size) is limited, so the reduction of the semiconductor channel length L is limited, resulting in limited improvement of the transistor on-state current, that is, the on-state current of the semiconductor transistor cannot be further increased.

[0044] To solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure. The forming method includes: providing a substrate including a first region and a second region surrounding and connected to the first region, sequentially forming a stacked first source layer, a first source channel layer, a first channel layer, and a first channel-drain layer in the first region, forming a first gate dielectric layer in the second region surrounding and covering the sidewalls of the first source channel layer, the first channel layer, and the first channel-drain layer, forming a first gate structure layer surrounding and covering the first gate dielectric layer, sequentially forming a stacked first drain layer, a sacrificial layer, a second source layer, a second source channel layer, a second channel layer, and a second channel-drain layer on the first channel-drain layer, forming a second gate dielectric layer in the second region surrounding and covering the sidewalls of the second source channel layer, the second channel layer, and the second channel-drain layer; forming a second gate structure layer surrounding and covering the second gate dielectric layer, and forming a second drain layer covering the second channel-drain layer, further increasing the on-state current of the semiconductor transistor.

[0045] Using the semiconductor structure forming method provided by the embodiments of the present invention, one type of carrier of the semiconductor structure flows from the first source layer through the first source trench layer, the first channel layer, and the first channel-drain layer to the first drain layer in a direction perpendicular to the surface of the substrate, and another type of carrier of the semiconductor structure flows from the second source layer through the second source trench layer, the second channel layer, and the second channel-drain layer to the second drain layer; in a direction perpendicular to the surface of the substrate, the thickness of the first channel layer corresponds to the channel length of one type of carrier, and the thickness of the second channel layer corresponds to the channel length of another type of carrier. The thicknesses of the first channel layer and the second channel layer can be reduced through a film-forming process to reduce the channel length of the carriers, further improving the on-state current of the semiconductor transistor.

[0046] To make the above objects, features, and advantages of the present invention more obvious and understandable, the following provides a detailed description of the specific embodiments of the present invention with reference to the accompanying drawings.

[0047] Reference Figures 2 to 22 , is a schematic structural diagram of the semiconductor structure forming method according to the embodiments of the present invention, where Figure 2 is a schematic top view of the semiconductor structure according to the embodiments of the present invention, Figure 20 is Figure 2 a cross-sectional view along the A1A2 direction in Figure 21 is Figure 2 a cross-sectional view along the B1B2 direction in Figure 22 is Figure 2 a cross-sectional view along the C1C2 direction in

[0048] Reference Figure 3 provides a substrate 200, and the substrate 200 includes a first region 201 and a second region 202 surrounding and connected to the first region 201.

[0049] The first region 201 includes an outer edge of the first region (not shown), the second region 202 includes an inner edge of the second region (not shown), the inner edge of the second region is connected to the outer edge of the first region, and the second region 202 surrounds the first region 201 so that the second region 202 is adjacent to the first region 201 in a surrounding manner. In some embodiments, the second region 202 is adjacent to the first region 201 in a surrounding manner to form a "hui" character shape. In other embodiments, the second region 202 is adjacent to the first region 201 in a surrounding manner to form a "U" character shape, which does not limit this application.

[0050] The substrate 200 is used to provide a process platform for the formation of a semiconductor structure, that is, the substrate 200 is used to form a first semiconductor device and a second semiconductor device stacked on the first semiconductor device. The types of the first semiconductor device include: PMOS transistors or NMOS transistors. The types of the second semiconductor device include: PMOS transistors or NMOS transistors. In this embodiment, the first semiconductor device is a PMOS transistor and the second semiconductor device is an NMOS transistor. The transistor types of the first semiconductor device and the second semiconductor device stacked on the substrate 200 can be selected according to actual needs, which does not limit this application. In some embodiments, the first semiconductor device is an NMOS transistor and the second semiconductor device is a PMOS transistor, or the first semiconductor device is a PMOS transistor and the second semiconductor device is a PMOS transistor, or the first semiconductor device is an NMOS transistor and the second semiconductor device is an NMOS transistor.

[0051] In this embodiment, the substrate 200 is a silicon substrate 200, and the material of the substrate 200 is single crystal silicon. In some other embodiments, the material of the substrate 200 can also be one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium. The substrate 200 can also be other types of substrates 200 such as silicon-on-insulator substrate 200 or germanium-on-insulator substrate 200. In other embodiments, an epitaxial layer (not shown) having the same crystal structure as the substrate 200 can also be formed on the surface of the substrate 200 to improve the quality of pattern transfer.

[0052] Reference Figure 4 , a stacked first source layer 300, a first source-channel layer 301, a first channel layer 302, and a first channel-drain layer 303 are sequentially formed in the first region 201.

[0053] The first source layer 300 is used as the source of the first semiconductor device.

[0054] The first channel layer 302 is used as the channel of the first semiconductor device.

[0055] The first source-channel layer 301 is used as a barrier layer (also referred to as the first barrier layer) between the first source layer 300 and the first channel layer 302, which can effectively prevent the doping ions in the first channel layer 302 from diffusing with the doping ions in the first source layer 300, thereby improving the reliability and stability of the semiconductor device.

[0056] The first channel-drain layer 303 is used as a connection layer between the first channel layer 302 and the first drain layer 310 (see Figure 9A blocking layer (also referred to as the second blocking layer) between them can effectively prevent the diffusion of doping ions between the first drain layer 310 and the doping ions in the first channel layer 302, thereby improving the reliability and stability of the semiconductor device.

[0057] In this embodiment, along the direction perpendicular to the surface of the substrate 200, the carriers of the first semiconductor device flow from the first source layer 300 through the first source-channel layer 301, the first channel layer 302, and the first channel-drain layer 303 to the first drain layer 310. That is, the channel length of the first semiconductor device is the thickness of the first channel layer 302. Relative to the lithography exposure process, a first channel layer 302 with a smaller thickness can be formed by chemical vapor deposition or epitaxial growth processes, thereby reducing the carrier flow path of the first semiconductor device and further improving the on-state current of the semiconductor transistor.

[0058] In this embodiment, the first source layer 300, the first source-channel layer 301, the first channel layer 302, and the first channel-drain layer 303 are all formed by epitaxial growth processes, and doping processes are performed during the epitaxial growth process. Among them, each layer has its own doping type and doping concentration.

[0059] In this embodiment, along the direction perpendicular to the surface of the substrate 200, the main process steps of sequentially forming the stacked first source layer 300, the first source-channel layer 301, the first channel layer 302, and the first channel-drain layer 303 on the substrate 200 of the first region 201 are as follows:

[0060] Through epitaxial growth and doping with phosphorus ions, a material layer (not shown) of the first source layer 300 is formed on the substrate 200. Among them, the material of the first source layer 300 is silicon, and the doping concentration of the first source layer 300 can be 1E 14 atom / cm 3 to 1E 15 atom / cm 3 , and the thickness of the first source layer 300 can be 500 angstroms to 1000 angstroms.

[0061] Through epitaxial growth, a material layer (not shown) of the first source-channel layer 301 is formed on the first source layer 300. Among them, the material of the first source-channel layer 301 is silicon germanide (SiGe), and the thickness of the first source-channel layer 301 can be 500 angstroms to 1000 angstroms. In other embodiments, the material of the first source-channel layer 301 can be one or more of silicon nitride, silicon oxide, and silicon oxynitride.

[0062] A material layer (not shown) of the first channel layer 302 is formed on the first source-channel layer 301 through an epitaxial process and a boron ion doping process. The material of the first channel layer 302 is silicon, and the doping concentration of the first channel layer 302 can be 1E 12 atom / cm 3 to 1E 13 atom / cm 3 , and the thickness of the first channel layer 302 can be greater than or equal to 20 angstroms.

[0063] A material layer (not shown) of the first channel-drain layer 303 is formed on the first channel layer 302 through an epitaxial process. The material of the first channel-drain layer 303 is silicon germanide (SiGe), and the thickness of the first channel-drain layer 303 can be 500 angstroms to 1000 angstroms. In other embodiments, the material of the first channel-drain layer 303 can be one or more of silicon nitride, silicon oxide, and silicon oxynitride.

[0064] In this embodiment, the epitaxial process can include an atomic layer deposition process or a molecular beam epitaxy process.

[0065] In this embodiment, the materials, doping concentrations, doping ion types, and thicknesses of the first source layer 300, the first source-channel layer 301, the first channel layer 302, and the first channel-drain layer 303 can be selected according to actual needs, and the present application is not limited thereto.

[0066] The parameters of the epitaxial process include: the temperature ranges from 600 degrees Celsius to 800 degrees Celsius. In this embodiment, the formation temperatures of the first source layer 300, the first source-channel layer 301, the first channel layer 302, and the first channel-drain layer 303 range from 600 degrees Celsius to 800 degrees Celsius, which can reduce or avoid the phenomenon of mutual diffusion between carriers in the first source layer 300, the first source-channel layer 301, the first channel layer 302, and the first channel-drain layer 303, enabling each layer to maintain its own characteristics and improving the performance of the semiconductor structure.

[0067] The parameters of the epitaxial process at least further include the following:

[0068] The pressure is 70 Torr to 90 Torr;

[0069] The flow rate of Purge MainH2 is 3200 sccm to 3800 sccm;

[0070] The flow rate of Purge SlitH2 is 80 sccm to 120 sccm;

[0071] The flow rate of the silicon source gas is 120 sccm to 180 sccm;

[0072] The epitaxial growth rate is from 200 angstroms per minute to 300 angstroms per minute.

[0073] In this embodiment, the parameters of the epitaxial process for forming the first source layer 300, the first source trench layer 301, the first channel layer 302, and the first channel-drain layer 303 further include: the pressure is from 70 Torr to 90 Torr (the pressure in the epitaxial reaction chamber); the flow rate of Purge MainH2 is from 3200 sccm to 3800 sccm; the flow rate of Purge SlitH2 is from 80 sccm to 120 sccm; the flow rate of the silicon source gas is from 120 sccm to 180 sccm; the epitaxial growth rate is from 200 angstroms per minute to 300 angstroms per minute, so as to obtain the first source layer 300, the first source trench layer 301, the first channel layer 302, and the first channel-drain layer 303 with high quality (such as fewer holes in the film layer, higher density, purer film quality, better film thickness uniformity, etc.).

[0074] The Purge MainH2 (Purge Main Hydrogen) is the purge main hydrogen, and the purge main hydrogen has the following beneficial effects:

[0075] First, as a diluent.

[0076] Hydrogen can also be used as a diluent to reduce the concentration of the reaction gas (such as the silicon source gas), control the reaction rate and the film growth rate, so as to control the film thickness and doping concentration.

[0077] Second, a protective atmosphere.

[0078] Hydrogen can prevent the epitaxial film from being oxidized or contaminated by other gases during the growth process.

[0079] The Purge SlitH2 (Purge Slit Hydrogen) is the purge slit hydrogen, and the purge slit hydrogen has the following beneficial effects:

[0080] First, clean the reaction chamber.

[0081] By using hydrogen to flush the slits of the reaction chamber, the particulate matter, by-products, and residues that may be generated during the growth process can be removed, which helps to maintain the cleanliness of the reaction chamber and prevent these impurities from affecting the growth quality of the subsequent epitaxial film.

[0082] Second, prevent cross-contamination.

[0083] Flushing the slits of the reaction chamber between different batches of epitaxial growth can avoid cross-contamination between different materials or dopants, and ensure the purity and consistency of each batch of epitaxial films.

[0084] Third, extend the equipment life.

[0085] Performing gap flushing regularly can reduce corrosion and wear inside the epitaxial reaction chamber, thereby extending the service life of the equipment and reducing maintenance costs.

[0086] Through processes such as exposure, development, etching or laser cutting process, remove the material layers of the first source layer 300, the first source trench layer 301, the first channel layer 302, and the first drain trench layer 303 of the second region 202, so as to sequentially form a stacked first source layer 300, first source trench layer 301, first channel layer 302, and first drain trench layer 303 in the first region 201.

[0087] Continue to refer to Figure 4 , after forming the first drain trench layer 303 and before forming the first gate dielectric layer 307, the forming method further includes: forming a first filling layer 304 on the substrate 200 of the second region 202, and the first filling layer 304 covers the sidewalls of the first source layer 300, the first source trench layer 301, the first channel layer 302, and the first drain trench layer 303.

[0088] The first filling layer 304 has the following beneficial effects:

[0089] First, provide a process space for forming the first gate dielectric layer 307 (see Figure 7 ) and the first gate structure layer 308 (see Figure 7 ).

[0090] Second, used for electrical isolation between semiconductor devices to prevent electrical interference between different regions. The material of the first filling layer 304 includes: one or more of silicon oxide, silicon nitride, silicon carbide, and silicon carbonitride. In this embodiment, the material of the first filling layer 304 is silicon oxide.

[0091] In this embodiment, a chemical vapor deposition process is used to form a first filling material layer (also referred to as the first filling layer 304) on the substrate 200, and the first filling material layer covers the surface of the second region 202 and the first drain trench layer 303.

[0092] Using the first drain trench layer 303 as a stop layer, perform a first planarization process on the first filling material layer to form a first filling layer 304 on the substrate 200 of the second region 202, and the first filling layer 304 covers the sidewalls of the first source layer 300, the first source trench layer 301, the first channel layer 302, and the first drain trench layer 303.

[0093] Refer to Figure 5, remove a part of the first filling layer 304 to expose the sidewalls of the first source trench layer 301, the first channel layer 302, and the first drain trench layer 303, so as to form a first filling layer trench 305.

[0094] The first filling layer trench 305 is used to provide a process basis for subsequently forming a first gate dielectric layer 307 (see Figure 7 ) and a first gate structure layer 308 (see Figure 7 ).

[0095] In this embodiment, through processes such as exposure, development, and etching, a part of the first filling layer 304 is removed to expose the sidewalls of the first source trench layer 301, the first channel layer 302, and the first drain trench layer 303, so as to form a first filling layer trench 305; a part of the sidewall of the first source electrode layer 300 is also exposed. The first filling layer trench 305 includes: a first filling layer trench sidewall opposite to the sidewalls of the first source trench layer 301, the first channel layer 302, and the first drain trench layer 303, and a first filling layer trench bottom.

[0096] Refer to Figure 6 , after forming the first filling layer trench 305 and before forming the first gate dielectric layer 307, the forming method further includes: forming a first metal layer 306 outside the first filling layer trench 305 to cover the surfaces of the first filling layer 304 and the first drain trench layer 303.

[0097] The first metal layer 306 has the following beneficial effects:

[0098] First, as a barrier layer (which can also be called the third barrier layer).

[0099] The first metal layer 306 can prevent the material of the subsequently formed first gate structure layer 308 from diffusing into the first drain trench layer 303 in the direction perpendicular to the substrate surface, affecting the performance of the first drain trench layer 303, and thus affecting the stability and reliability of the first semiconductor device.

[0100] Second, reduce stress.

[0101] The first metal layer 306, as a buffer layer, can reduce the stress between the subsequently formed first gate structure layer 308 and the first drain trench layer 303, and improve the reliability of the first semiconductor device.

[0102] The material of the first metal layer 306 includes: titanium nitride (TiN) and tantalum nitride (TaN). In this embodiment, the material of the first metal layer 306 is titanium nitride (TiN).

[0103] The process of forming the first metal layer 306 includes one or more of physical vapor deposition, chemical vapor deposition, and atomic layer deposition processes. In this embodiment, a first metal material layer (which can also be referred to as the first metal layer 306) (not shown) covering the substrate 200 is formed through physical vapor deposition process. The first metal material layer covers the sidewalls of the first source trench layer 301, the first channel layer 302, and the first drain trench layer 303, and also covers the sidewalls and the bottom of the first fill layer trench and the surface of the first fill layer 304.

[0104] For the first metal material layer, through processes such as exposure, development, and etching, outside the first fill layer trench 305, a first metal layer 306 covering the surface of the first fill layer 304 and the first drain trench layer 303 is formed. That is, the first metal layer 306 covers the surface of the first fill layer 304 and the surface of the first drain trench layer 303.

[0105] It should be noted that the first metal layer 306 should not be regarded as a limitation of this application. Whether the first metal layer 306 is needed can be selected according to actual needs. In other embodiments, the first metal layer 306 may not be formed.

[0106] Continue to refer to Figure 6 , in the second region 202, a first gate dielectric layer 307 surrounding and covering the sidewalls of the first source trench layer 301, the first channel layer 302, and the first drain trench layer 303 is formed.

[0107] The first gate dielectric layer 307, as an electrical insulating material, electrically isolates the subsequently formed first gate structure layer 308 from the first source layer 300, the first source trench layer 301, the first channel layer 302, the first drain trench layer 303, and the first drain layer 310 of the first semiconductor device.

[0108] The material of the first gate dielectric layer 307 includes one or more of silicon oxide and high-k gate dielectric layer materials. The silicon oxide has good insulation, coverage, and stability. In this embodiment, the material of the first gate dielectric layer 307 is silicon oxide.

[0109] The film thickness of the first gate dielectric layer 307 being silicon oxide is in the range of greater than or equal to 50 nanometers and less than or equal to 200 nanometers.

[0110] By making the film thickness of the silicon oxide greater than or equal to 50 nanometers, a good electrical insulation and isolation effect can be achieved; by making the film thickness of the silicon oxide less than or equal to 200 nanometers, the process fabrication cycle can be reduced and the characteristics of the semiconductor device can be ensured.

[0111] It should be noted that the high-k gate dielectric layer material includes a dielectric material with a dielectric constant greater than that of silicon dioxide (3.9); the high-k gate dielectric layer material includes one or more of hafnium oxide, zirconium oxide, hafnium silicon oxide, hafnium oxynitride, hafnium silicon oxynitride, hafnium tantalum oxynitride, zirconium oxynitride, zirconium silicon oxynitride, zirconium silicon oxide, lanthanum oxide, titanium oxide, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate. Preferably, the dielectric constant of the high-k gate dielectric layer material is greater than 8 to reduce the thickness of the first gate dielectric layer 307 and improve the performance of the transistor.

[0112] The process for forming the first gate dielectric layer 307 includes one or more of chemical vapor deposition process, furnace tube process, and atomic layer deposition process.

[0113] In this embodiment, the main process steps for forming the first gate dielectric layer 307 that circumferentially covers the sidewalls of the first source trench layer 301, the first channel layer 302, and the first drain trench layer 303 in the second region 202 are as follows:

[0114] Through chemical vapor deposition process, a first gate dielectric material layer (which can also be referred to as the first gate dielectric layer 307) (not shown) is formed on the substrate 200, and the first gate dielectric material layer covers the first metal layer 306 and the first filling layer trench.

[0115] For the first gate dielectric material layer, processes such as exposure, development, and etching are used to form the first gate dielectric layer 307 that circumferentially covers the sidewalls of the first source trench layer 301, the first channel layer 302, and the first drain trench layer 303 in the first filling layer trench 305. The first gate dielectric layer 307 also covers the bottom and sidewalls of the first filling layer trench.

[0116] Reference Figure 7 , a first gate structure layer 308 that circumferentially covers the first gate dielectric layer 307 is formed.

[0117] The first gate structure layer 308 is used to control the turn-on and turn-off of the first semiconductor device.

[0118] The material of the first gate structure layer 308 includes one or more of titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), titanium (Ti), titanium aluminide (TiAl), tungsten (W), aluminum (Al), titanium silicon nitride (TiSiN), and titanium aluminum carbide (TiAlC).

[0119] In this embodiment, the material of the first gate structure layer 308 is titanium nitride (TiN).

[0120] The process for forming the first gate structure layer 308 includes one or more of physical vapor deposition, chemical vapor deposition, and atomic layer deposition. In this embodiment, the first gate structure layer 308 that surrounds and covers the first gate dielectric layer 307 is formed by physical vapor deposition process.

[0121] In this embodiment, the main process steps for forming the first gate structure layer 308 that surrounds and covers the first gate dielectric layer 307 include:

[0122] By physical vapor deposition process, a first gate structure material layer (which can also be called the first gate structure layer 308) (not shown) is formed on the substrate 200, and the first gate structure material layer covers the first metal layer 306 and fills the first fill layer trench.

[0123] Using the first drain / gate layer 303 as the stop layer, a second planarization process is performed on the first gate structure material layer to remove a part of the first metal layer 306, a part of the first gate dielectric layer 307 in the first fill layer trench 305, and a part of the first gate structure material layer, so as to form the first gate structure layer 308 filled in the first fill layer trench 305, thereby forming the first gate structure layer 308 that surrounds and covers the first gate dielectric layer 307, and at the same time making the surfaces of the first gate structure layer 308, the first drain / gate layer 303, the top of the first gate dielectric layer 307, and the first fill layer 304 be at the same level.

[0124] Reference Figure 8 , a first thin layer 309 covering the surface of the first gate structure layer 308 is formed.

[0125] The first thin layer 309 is used to protect the first gate structure layer 308.

[0126] The material of the first thin layer 309 includes one or more of silicon oxide, silicon nitride, silicon carbide, and silicon carbonitride. In this embodiment, the material of the first thin layer 309 is silicon oxide.

[0127] In this embodiment, the main process steps for forming the first thin layer 309 covering the surface of the first gate structure layer 308 include:

[0128] By chemical vapor deposition process, a first thin layer 309 material layer (which can also be called the first thin layer 309) is formed on the substrate 200, and the first thin layer 309 material layer covers the surfaces of the first drain / gate layer 303, the first gate structure layer 308, the first gate dielectric layer 307, and the first fill layer 304.

[0129] For the first thin layer 309 material layer, processes such as exposure, development, and etching are performed to form the first thin layer 309 covering the surface of the first gate structure layer 308, and the first thin layer 309 also covers the first filling layer 304.

[0130] It should be noted that the first thin layer 309 cannot be used as a limitation of this application, and whether the first thin layer 309 is required can be selected according to actual needs. In some embodiments, the first thin layer 309 is not formed, and the second filling layer 404 (see Figure 9 ) is directly formed to cover the surface of the first filling layer 304, the first gate structure layer 308, and the top end face of the first gate dielectric layer 307.

[0131] Refer to Figure 9 , and a stacked first drain layer 310, a sacrificial layer 311, a second source layer 400, a second source-channel layer 401, a second channel layer 402, and a second drain-channel layer 403 are sequentially formed on the first drain-channel layer 303.

[0132] The first drain layer 310 is used as the drain of the first semiconductor device.

[0133] The sacrificial layer 311 is used to provide space for forming a third filling layer 407 (see Figure 11 ) between the first drain layer 310 and the second source layer 400 later.

[0134] The second source layer 400 is used as the source of the second semiconductor device.

[0135] The second channel layer 402 is used as the channel of the second semiconductor device.

[0136] The second source-channel layer 401 is used as a blocking layer (also called the fourth blocking layer) between the second source layer 400 and the second channel layer 402, which can effectively prevent the doping ions in the second channel layer 402 from diffusing with the doping ions in the second source layer 400, thereby improving the reliability and stability of the semiconductor device.

[0137] The second drain-channel layer 403 is used as a blocking layer (also called the fifth blocking layer) between the second channel layer 402 and the second drain layer 413 (see Figure 15 ), which can effectively prevent the doping ions in the second drain layer 413 from diffusing with the doping ions in the second channel layer 402, thereby improving the reliability and stability of the semiconductor device.

[0138] In this embodiment, along the direction perpendicular to the surface of the substrate 200, the carriers of the second semiconductor device flow from the second source layer 400 through the second source-channel layer 401, the second channel layer 402, and the second channel-drain layer 403 to the second drain layer 413. That is, the channel length of the second semiconductor device is the thickness of the second channel layer 402. Relative to the lithography exposure process, a second channel layer 402 with a smaller thickness can be formed by chemical vapor deposition or epitaxial growth processes, thereby reducing the carrier flow path of the second semiconductor device and further enhancing the on-state current of the semiconductor transistor.

[0139] In this embodiment, the first drain layer 310, the sacrificial layer 311, the second source layer 400, the second source-channel layer 401, the second channel layer 402, and the second channel-drain layer 403 are all formed by epitaxial growth processes, and doping treatments are performed during the epitaxial growth process, where each layer has its own doping type and doping concentration.

[0140] In this embodiment, the main process steps for sequentially forming the stacked first drain layer 310, sacrificial layer 311, second source layer 400, second source-channel layer 401, second channel layer 402, and second channel-drain layer 403 in the first region 201 are as follows:

[0141] A material layer (not shown) of the first drain layer 310 is formed on the first channel-drain layer 303 through epitaxial growth and phosphorus ion doping processes. Here, the material of the first drain layer 310 is silicon, and the doping concentration of the first drain layer 310 can be 1E 14 atom / cm 3 to 1E 15 atom / cm 3 , and the thickness of the first drain layer 310 can be 500 angstroms to 1000 angstroms.

[0142] A material layer (not shown) of the sacrificial layer 311 is formed on the first drain layer 310 through epitaxial growth processes. Here, the material of the sacrificial layer 311 is silicon germanide (SiGe), and the thickness of the sacrificial layer 311 can be 500 angstroms to 1000 angstroms. In other embodiments, the material of the sacrificial layer 311 can be one or more of silicon nitride, silicon oxide, and silicon oxynitride, and the sacrificial layer is formed by chemical vapor deposition processes.

[0143] A material layer (not shown) of the second source layer 400 is formed on the sacrificial layer 311 through epitaxial growth and boron ion doping processes. Here, the material of the second source layer 400 is silicon, and the doping concentration of the second source layer 400 can be 1E 14 atom / cm 3 to 1E 15 atom / cm3 The thickness of the second source layer 400 may be from 500 angstroms to 1000 angstroms.

[0144] Through an epitaxial process, a material layer (not shown) of the second source trench layer 401 is formed on the second source layer 400. Wherein, the material of the second source trench layer 401 is silicon carbide (SiC), and the thickness of the second source trench layer 401 may be from 500 angstroms to 1000 angstroms. In other embodiments, the material of the second source trench layer 401 may be one or more of silicon nitride, silicon oxide, and silicon oxynitride.

[0145] Through an epitaxial and phosphorus ion doping process, a material layer (not shown) of the second channel layer 402 is formed on the second source trench layer 401. Wherein, the material of the second channel layer 402 is silicon, and the doping concentration of the second channel layer 402 may be 1E 12 atom / cm 3 to 1E 13 atom / cm 3 The thickness of the second channel layer 402 may be greater than or equal to 20 angstroms.

[0146] Through an epitaxial process, a material layer (not shown) of the second drain trench layer 403 is formed on the second channel layer 402. Wherein, the material of the second drain trench layer 403 is silicon carbide (SiC), and the thickness of the second drain trench layer 403 may be from 500 angstroms to 1000 angstroms. In other embodiments, the material of the second source trench layer 401 may be one or more of silicon nitride, silicon oxide, and silicon oxynitride.

[0147] In this embodiment, the epitaxial process may include an atomic layer deposition process or a molecular beam epitaxy process.

[0148] In this embodiment, the materials, doping concentrations, doping ion types, and thicknesses of the first drain layer 310, the sacrificial layer 311, the second source layer 400, the second source trench layer 401, the second channel layer 402, and the second drain trench layer 403 may be selected according to actual needs, and this does not limit the present application.

[0149] The parameters of the epitaxial process include: the temperature ranges from 600 degrees Celsius to 800 degrees Celsius. In this embodiment, the formation temperatures of the first drain layer 310, the sacrificial layer 311, the second source layer 400, the second source trench layer 401, the second channel layer 402, and the second drain trench layer 403 range from 600 degrees Celsius to 800 degrees Celsius, which can reduce or avoid the phenomenon of mutual diffusion between carriers in the first drain layer 310, the sacrificial layer 311, the second source layer 400, the second source trench layer 401, the second channel layer 402, and the second drain trench layer 403, enabling each layer to maintain its own characteristics and improving the performance of the semiconductor structure.

[0150] The parameters of the epitaxial process further include at least one of the following:

[0151] The pressure is from 70 Torr to 90 Torr;

[0152] The flow rate of Purge MainH2 is from 3200 sccm to 3800 sccm;

[0153] The flow rate of Purge SlitH2 is from 80 sccm to 120 sccm;

[0154] The flow rate of the silicon source gas is from 120 sccm to 180 sccm;

[0155] The epitaxial rate is from 200 Å / min to 300 Å / min.

[0156] In this embodiment, the parameters of the epitaxial process for forming the first drain layer 310, the sacrificial layer 311, the second source layer 400, the second source trench layer 401, the second channel layer 402, and the second channel-drain layer 403 further include: the pressure is from 70 Torr to 90 Torr (the pressure in the epitaxial reaction chamber); the flow rate of Purge MainH2 is from 3200 sccm to 3800 sccm; the flow rate of Purge SlitH2 is from 80 sccm to 120 sccm; the flow rate of the silicon source gas is from 120 sccm to 180 sccm; the epitaxial rate is from 200 Å / min to 300 Å / min, so as to achieve high-quality (such as fewer holes in the film layer, higher density, purer film quality, better film thickness uniformity, etc.) first drain layer 310, sacrificial layer 311, second source layer 400, second source trench layer 401, second channel layer 402, and second channel-drain layer 403.

[0157] The Purge MainH2 (Purge Main Hydrogen) is the purge main hydrogen, and the purge main hydrogen has the following beneficial effects:

[0158] First, as a diluent.

[0159] Hydrogen can also be used as a diluent to reduce the concentration of the reaction gas (such as the silicon source gas), control the reaction rate and the growth rate of the film layer, so as to control the thickness and doping concentration of the thin film.

[0160] Second, a protective atmosphere.

[0161] Hydrogen can prevent the epitaxial film from being oxidized or contaminated by other gases during the growth process.

[0162] The Purge SlitH2 (Purge Slit Hydrogen) is the purge slit hydrogen, and the purge slit hydrogen has the following beneficial effects:

[0163] Second, clean the reaction chamber.

[0164] By using hydrogen to flush the slit of the reaction chamber, particulate matter, by-products, and residues that may be generated during growth can be removed, which helps to maintain the cleanliness of the reaction chamber and prevent these impurities from affecting the growth quality of the subsequent epitaxial film.

[0165] Second, prevent cross-contamination.

[0166] Flushing the slit of the reaction chamber for different batches of epitaxial growth can avoid cross-contamination between different materials or dopants, ensuring the purity and consistency of each batch of epitaxial films.

[0167] Third, extend the equipment life.

[0168] Regularly flushing the slit can reduce the corrosion and wear inside the epitaxial reaction chamber, thereby extending the service life of the equipment and reducing the maintenance cost.

[0169] Through processes such as exposure, development, etching, or laser cutting, the material layers of the first drain layer 310, the sacrificial layer 311, the second source layer 400, the second source trench layer 401, the second channel layer 402, and the second channel-drain layer 403 in the second region 202 are removed to sequentially form a stacked first drain layer 310, sacrificial layer 311, second source layer 400, second source trench layer 401, second channel layer 402, and second channel-drain layer 403 in the first region 201.

[0170] Continue to refer to Figure 9 , after forming the second channel-drain layer 403 and before forming the second gate dielectric layer 410, the forming method further includes: forming a second filling layer 404 on the first thin layer 309, and the second filling layer 404 covers the sidewalls of the first drain layer 310, the sacrificial layer 311, the second source layer 400, the second source trench layer 401, the second channel layer 402, and the second channel-drain layer 403.

[0171] The second filling layer 404 has the following beneficial effects:

[0172] First, provide a process space for forming the second gate dielectric layer 410 (see Figure 14 ) and the second gate structure layer 411 (see Figure 14 ).

[0173] Second, it is used for isolation between semiconductor devices to prevent electrical interference between different regions.

[0174] The material of the second filling layer 404 includes one or more of silicon oxide, silicon nitride, silicon carbide, and silicon carbonitride. In this embodiment, the material of the second filling layer 404 is silicon oxide.

[0175] In this embodiment, the main process steps for forming the second filling layer 404 on the first thin layer 309 include:

[0176] Adopting a chemical vapor deposition process, a second filling material layer (also referred to as the second filling layer 404) is formed on the substrate 200, and the second filling material layer covers the sidewalls of the first thin layer 309, the second drain groove layer 403, the first drain layer 310, the sacrificial layer 311, the second source layer 400, the second source groove layer 401, the second channel layer 402, and the second drain groove layer 403.

[0177] Using the second drain groove layer 403 as a stop layer, the second filling material layer is subjected to a third planarization process to form the second filling layer 404 on the first thin layer 309. The second filling layer 404 covers the sidewalls of the first drain layer 310, the sacrificial layer 311, the second source layer 400, the second source groove layer 401, the second channel layer 402, and the second drain groove layer 403, and the surface of the second filling layer 404 is at the same horizontal plane as the surface of the second drain groove layer 403.

[0178] Reference Figure 10 , a part of the second filling layer 404 is removed to expose the sidewalls of the sacrificial layer 311, the second source layer 400, the second source groove layer 401, the second channel layer 402, and the second drain groove layer 403 to form a second filling layer trench 405, and the sacrificial layer 311 is removed to form a first spacer 406 between the first drain layer 310 and the second source layer 400.

[0179] The second filling layer trench 405 is used to provide a position space for forming the third filling layer 407 (see Figure 11 ).

[0180] The first spacer 406 is used to provide a position space for forming the third filling layer 407 between the first semiconductor device and the second semiconductor device.

[0181] In this embodiment, through processes such as exposure, development, and etching, a part of the second filling layer 404 is removed to expose the sidewalls of the sacrificial layer 311, the second source layer 400, the second source groove layer 401, the second channel layer 402, and the second drain groove layer 403 to form the second filling layer trench 405.

[0182] Through a dry etching process, the sacrificial layer 311 is removed to form a first spacer 406 between the first drain layer 310 and the second source layer 400.

[0183] Reference Figure 11 , a third filling layer 407 is filled in the second filling layer trench 405 and the first spacer 406.

[0184] The third filling layer 407 in the first spacer 406 is used to electrically isolate the first semiconductor device and the second semiconductor device.

[0185] The third filling layer 407 in the second filling layer trench 405 is used to cover the sidewalls of the second source layer 400, the second source trench layer 401, the second channel layer 402, and the second drain-channel layer 403.

[0186] The material of the third filling layer 407 includes one or more of silicon oxide, silicon nitride, silicon carbide, and silicon carbonitride. In this embodiment, the material of the first filling layer 304 is silicon oxide.

[0187] In this embodiment, a chemical vapor deposition process is used to form a third filling material layer (which can also be referred to as the third filling layer 407) on the substrate 200. The third filling material layer is filled in the second filling layer trench 405 and the first spacer 406, and also covers the first thin layer 309 and the second drain-channel layer 403.

[0188] Taking the second drain-channel layer 403 as a stop layer, a fourth planarization process is performed on the third filling material layer to fill the third filling layer 407 in the second filling layer trench 405 and the first spacer 406.

[0189] Reference Figure 12 , a part of the third filling layer 407 is removed to expose the sidewalls of the second source trench layer 401, the second channel layer 402, and the second drain-channel layer 403, so as to form a third filling layer trench 408.

[0190] The third filling layer trench 408 provides a process basis for subsequent formation of the second gate dielectric layer 410 and the second gate structure layer 411.

[0191] In this embodiment, through processes such as exposure, development, and etching, a part of the third filling layer 407 is removed to expose the sidewalls of the second source trench layer 401, the second channel layer 402, and the second drain-channel layer 403, so as to form a third filling layer trench 408.

[0192] In this embodiment, the third fill layer trench 408 includes: a third fill layer trench sidewall opposite to the sidewalls of the second source trench layer 401, the second channel layer 402, and the second drain trench layer 403, and a third fill layer trench bottom.

[0193] Reference Figure 13 , after forming the third fill layer trench 408 and before forming the second gate dielectric layer 410, the forming method further includes: forming a second metal layer 409 outside the third fill layer trench 408 to cover the surfaces of the second fill layer 404 and the second drain trench layer 403.

[0194] The second metal layer 409 has the following beneficial effects:

[0195] First, as a barrier layer (also referred to as the sixth barrier layer).

[0196] The second metal layer 409 can prevent the material of the subsequently formed second gate structure layer 411 from diffusing into the second drain trench layer 403 in the direction perpendicular to the substrate surface, which may affect the performance of the second drain trench layer 403 and thus the stability and reliability of the second semiconductor device.

[0197] Second, reduce stress.

[0198] The second metal layer 409, as a buffer layer, can reduce the stress between the subsequently formed second gate structure layer 411 and the second drain trench layer 403, improving the reliability of the second semiconductor device.

[0199] The material of the second metal layer 409 includes: titanium nitride (TiN) and tantalum nitride (TaN). In this embodiment, the material of the second metal layer 409 is titanium nitride (TiN).

[0200] The process of forming the second metal layer 409 includes: one or more of physical vapor deposition, chemical vapor deposition, and atomic layer deposition processes. In this embodiment, a second metal material layer (also referred to as the second metal layer 409) (not shown) covering the substrate 200 is formed by physical vapor deposition process. The second metal material layer covers the sidewalls of the second source trench layer 401, the second channel layer 402, and the second drain trench layer 403, and also covers the third fill layer trench sidewall, the third fill layer trench bottom, and the surface of the second fill layer 404.

[0201] For the second metal material layer, through processes such as exposure, development, and etching, a second metal layer 409 covering the surfaces of the second fill layer 404 and the second drain trench layer 403 is formed outside the third fill layer trench 408.

[0202] It should be noted that the second metal layer 409 should not be regarded as a limitation of this application. Whether the second metal layer 409 is needed can be selected according to actual requirements. In other embodiments, the second metal layer 409 may not be formed.

[0203] Continue to refer to Figure 13 , a second gate dielectric layer 410 is formed in the second region 202 to surround and cover the sidewalls of the second source trench layer 401, the second channel layer 402, and the second trench drain layer 403.

[0204] The second gate dielectric layer 410, as an electrical insulating material, electrically isolates the subsequently formed second gate structure layer 411 (see Figure 16 ) from the second source layer 400, the second source trench layer 401, the second channel layer 402, the second trench drain layer 403, and the second drain layer 413 of the second semiconductor device (see Figure 16 ).

[0205] The material of the second gate dielectric layer 410 includes one or more of silicon oxide and high-k gate dielectric layer materials. The silicon oxide has good insulation, coverage, and stability. In this embodiment, the material of the second gate dielectric layer 410 is silicon oxide.

[0206] The film thickness of the second gate dielectric layer 410 being silicon oxide is in the range of greater than or equal to 50 nanometers and less than or equal to 200 nanometers.

[0207] By making the film thickness of the silicon oxide greater than or equal to 50 nanometers, a good electrical insulation and isolation effect can be achieved; by making the film thickness of the silicon oxide less than or equal to 200 nanometers, the process fabrication cycle can be reduced and the characteristics of the semiconductor device can be ensured.

[0208] It should be noted that the high-k gate dielectric layer material includes dielectric materials with a dielectric constant greater than that of silicon oxide (3.9); the high-k gate dielectric layer material includes one or more of hafnium oxide, zirconium oxide, hafnium silicon oxide, hafnium oxynitride, hafnium silicon oxynitride, hafnium tantalum oxynitride, zirconium oxynitride, zirconium silicon oxynitride, zirconium silicon oxide, lanthanum oxide, titanium oxide, tantalum oxide, barium strontium titanate, barium titanate, and strontium titanate. Preferably, the dielectric constant of the high-k gate dielectric layer material is greater than 8 to reduce the thickness of the second gate dielectric layer 410 and improve the performance of the transistor.

[0209] The process for forming the second gate dielectric layer 410 includes one or more of chemical vapor deposition process, furnace tube process, and atomic layer deposition process.

[0210] In this embodiment, the main process steps for forming the second gate dielectric layer 410 that surrounds and covers the sidewalls of the second source trench layer 401, the second channel layer 402, and the second drain trench layer 403 in the second region 202 are as follows:

[0211] Through chemical vapor deposition, a second gate dielectric material layer (which can also be referred to as the second gate dielectric layer 410) is formed on the substrate 200, and the second gate dielectric material layer covers the second metal layer 409 and the third fill layer trench 408.

[0212] For the second gate dielectric material layer, processes such as exposure, development, and etching are used to form, within the third fill layer trench 408, the second gate dielectric layer 410 that surrounds and covers the sidewalls of the second source trench layer 401, the second channel layer 402, and the second drain trench layer 403. The second gate dielectric layer 410 also covers the bottom and sidewalls of the third fill layer trench.

[0213] Reference Figure 14 , a second gate structure layer 411 is formed that surrounds and covers the second gate dielectric layer 410.

[0214] The second gate structure layer 411 is used to control the turn-on and turn-off of the second semiconductor device.

[0215] The material of the second gate structure layer 411 includes one or more of titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), titanium (Ti), titanium aluminide (TiAl), tungsten (W), aluminum (Al), titanium silicon nitride (TiSiN), and titanium aluminum carbide (TiAlC).

[0216] In this embodiment, the material of the second gate structure layer 411 is titanium nitride (TiN).

[0217] The process for forming the second gate structure layer 411 includes one or more of physical vapor deposition, chemical vapor deposition, and atomic layer deposition. In this embodiment, the second gate structure layer 411 that surrounds and covers the second gate dielectric layer 410 is formed through physical vapor deposition.

[0218] In this embodiment, the main process steps for forming the second gate structure layer 411 that surrounds and covers the second gate dielectric layer 410 include:

[0219] Through physical vapor deposition, a second gate structure material layer (which can also be referred to as the second gate structure layer 411) (not shown) is formed on the substrate 200, and the second gate structure material layer covers the second metal layer 409 and is filled in the third fill layer trench 408.

[0220] Using the second trench leakage layer 403 as the stop layer, a fifth planarization process is performed on the second gate structure material layer to remove a part of the second gate structure material layer in the second metal layer 409 and the third filling layer trench 408 and a part of the second gate dielectric layer 410, so as to form the second gate structure layer 411 in the third filling layer trench 408, thereby forming the second gate structure layer 411 that surrounds and covers the second gate dielectric layer 410, and at the same time making the top ends of the second gate structure layer 411, the second trench leakage layer 403, the second gate dielectric layer 410 and the surface of the second filling layer 404 be at the same level.

[0221] Reference Figure 15 , the forming method further includes: after forming the second gate structure layer 411 and before forming the second drain layer 413, forming a second thin layer 412 on the surface of the second gate structure layer 411.

[0222] The second thin layer 412 is used to protect the second gate structure layer 411.

[0223] The material of the second thin layer 412 includes one or more of silicon oxide, silicon nitride, silicon carbide, and silicon carbonitride. In this embodiment, the material of the second thin layer 412 is silicon oxide.

[0224] In this embodiment, the main process steps for forming the second thin layer 412 covering the surface of the second gate structure layer 411 include:

[0225] Adopting a chemical vapor deposition process to form a second thin layer 412 material layer on the substrate 200, and the second thin layer 412 material layer covers the surfaces of the second trench leakage layer 403, the second gate structure layer 411, the second gate dielectric layer 410 and the second filling layer 404.

[0226] Performing processes such as exposure, development, and etching on the second thin layer 412 material layer to form the second thin layer 412 covering the surface of the second gate structure layer 411, and the second thin layer 412 also covers the second filling layer 404.

[0227] It should be noted that the second thin layer 412 cannot be used as a limitation of this application, and whether the second thin layer 412 is needed can be selected according to actual needs. In some embodiments, the second thin layer 412 is not formed, and the interlayer dielectric layer 414 (see Figure 16 ) is directly formed to cover the surface of the second filling layer 404, the second gate structure layer 411 and the top end face of the second gate dielectric layer 410.

[0228] Continue to refer to Figure 15 , and form a second drain layer 413 covering the second trench leakage layer 403.

[0229] The second drain layer 413 is used as the drain of the second semiconductor device.

[0230] Regarding the second drain layer 413, the epitaxial growth and doping process parameters of the second source layer 400 can be followed, which will not be elaborated here.

[0231] It should be noted that in some embodiments, along the direction perpendicular to the surface of the substrate 200, the sidewalls of the first source layer 300, the first source trench layer 301, the first channel layer 302, the first channel-drain layer 303, the first drain layer 310, the sacrificial layer 311, the second source layer 400, the second source trench layer 401, the second channel layer 402, the second channel-drain layer 403, and the second drain layer 413 are flush. Moreover, each of the above-mentioned film layers has four sidewalls, namely the front sidewall, the rear sidewall, the left sidewall, and the right sidewall. The front sidewalls of each film layer are located on the front side, the rear sidewalls of each film layer are located on the rear side, the left sidewalls of each film layer are located on the left side, and the right sidewalls of each film layer are located on the right side.

[0232] The first gate dielectric layer 307 forms a surrounding coverage of the front sidewall, the rear sidewall, and the left sidewall of the first source trench layer 301, the first channel layer 302, and the first channel-drain layer 303 in the second region 202. The second gate dielectric layer 410 forms a surrounding coverage of the front sidewall, the rear sidewall, and the left sidewall of the second source trench layer 401, the second channel layer 402, and the second channel-drain layer 403 in the second region 202.

[0233] It should be noted that referring to Figure 10 , when forming the first spacer 406, a second filling layer 404 is formed on the right sidewalls of the film layers of the first drain layer 310, the second source layer 400, the second source trench layer 401, the second channel layer 402, and the second channel-drain layer 403 for supporting the above-mentioned film layers.

[0234] In other embodiments, the number of sidewalls of each film layer can be designed according to actual needs, and the present application is not limited thereto.

[0235] Referring to Figure 16 , an interlayer dielectric layer 414 is formed to cover the second thin layer 412 and the second drain layer 413.

[0236] The interlayer dielectric layer 414 has the following beneficial effects:

[0237] First, electrical isolation. The interlayer dielectric layer 414 isolates different metal layers (such as interconnect lines), avoiding short circuits caused by direct contact between metal layers, reducing electromagnetic interference (crosstalk) between signal lines, and improving signal transmission quality.

[0238] Second, reduce the parasitic capacitance. By using a low dielectric constant material, the interlayer dielectric layer 414 can reduce the parasitic capacitance between metal layers.

[0239] Third, flattening effect. The interlayer dielectric layer 414 achieves surface flattening through processes such as chemical mechanical polishing, providing a good foundation for the subsequent deposition and lithography of metal layers.

[0240] The material of the interlayer dielectric layer 414 includes one or more of silicon oxide, silicon nitride, silicon carbide, and silicon carbonitride. In this embodiment, the material of the interlayer dielectric layer 414 is silicon oxide.

[0241] In this embodiment, the main process steps for forming the interlayer dielectric layer 414 covering the second thin layer 412 and the second drain layer 413 include:

[0242] Adopt chemical vapor deposition process to form an interlayer dielectric material layer (also called interlayer dielectric layer 414) on the substrate 200, and the interlayer dielectric material layer covers the surfaces of the second thin layer 412 and the second drain layer 413 to form the interlayer dielectric layer 414.

[0243] Reference Figures 17 to 19 , form a first source electrode via 500 that penetrates the interlayer dielectric layer 414, the second drain layer 413, the second drain-channel layer 403, the second channel layer 402, the second source-channel layer 401, the second source electrode layer 400, the third filling layer 407, the first drain layer 310, the first drain-channel layer 303, the first channel layer 302, and the first source-channel layer 301 (see Figure 19 ); form a first channel layer via 501 that penetrates the interlayer dielectric layer 414, the second drain layer 413, the second drain-channel layer 403, the second channel layer 402, the second source-channel layer 401, the second source electrode layer 400, the third filling layer 407, the first drain layer 310, and the first drain-channel layer 303 (see Figure 17 ); form a first drain layer via 502 that penetrates the interlayer dielectric layer 414, the second drain layer 413, the second drain-channel layer 403, the second channel layer 402, the second source-channel layer 401, and the second source electrode layer 400, the third filling layer 407 (see Figure 18 ); form a second source electrode via 503 that penetrates the interlayer dielectric layer 414, the second drain layer 413, the second drain-channel layer 403, the second channel layer 402, and the second source-channel layer 401 (see Figure 19 ); form a second channel layer via 504 that penetrates the interlayer dielectric layer 414, the second drain layer 413, and the second drain-channel layer 403 (see Figure 17 ); form a second drain layer via 505 that penetrates the interlayer dielectric layer 414 ( Figure 18); form a first gate structure layer via hole 506 that penetrates through the interlayer dielectric layer 414, the second thin layer 412, the second filling layer 404, and the first thin layer 309 (see Figure 17 ); form a second gate structure layer via hole 507 that penetrates through the interlayer dielectric layer 414 and the second thin layer 412 (see Figure 17 ).

[0244] Combined with reference Figures 20 to 22 , the first source layer via hole 500 is used to provide a position space for the first source layer plug 600; the first channel layer via hole 501 is used to provide a position space for the first channel layer plug 601; the first drain layer via hole 502 is used to provide a position space for the first drain layer plug 602; the second source layer via hole 503 is used to provide a position space for the second source layer plug 603; the second channel layer via hole 504 is used to provide a position space for the second channel layer plug 604; the second drain layer via hole 505 is used to provide a position space for the second drain layer plug 605; the first gate structure layer via hole 506 is used to provide a position space for the first gate structure layer plug 606; the second gate structure layer via hole 507 is used to provide a position space for the second gate structure layer plug 607.

[0245] The first source layer via hole 500, the first channel layer via hole 501, the first drain layer via hole 502, the second source layer via hole 503, the second channel layer via hole 504, the second drain layer via hole 505, the first gate structure layer via hole 506, and the second gate structure layer via hole 507 can be formed respectively through processes such as independent exposure, development, and etching, that is, 8 independent exposure, development, and etching processes are required.

[0246] Alternatively, through a single exposure, development, and etching process, the first source layer via hole 500, the first channel layer via hole 501, the first drain layer via hole 502, the second source layer via hole 503, the second channel layer via hole 504, the second drain layer via hole 505, the first gate structure layer via hole 506, and the second gate structure layer via hole 507 can be formed at once. By designing 8 different light transmittances on the mask plate corresponding to the above 8 vias, the deeper the via, the greater the light transmittance, and the thinner the photoresist thickness at the via, and the photoresist thickness at the deepest via is 0.

[0247] Continue to refer to Figures 17 to 19 , and form a via isolation layer 508 that covers the sidewalls of the first source layer via hole 500, the first channel layer via hole 501, the first drain layer via hole 502, the second source layer via hole 503, the second channel layer via hole 504, and the second drain layer via hole 505.

[0248] The via isolation layer 508 has the following beneficial effects:

[0249] For electrical isolation between the first source layer plug 600 and the second drain layer 413, the second drain-channel layer 403, the second channel layer 402, the second source-channel layer 401, the second source layer 400, the first drain layer 310, the first drain-channel layer 303, the first channel layer 302, and the first source-channel layer 301;

[0250] For electrical isolation between the first channel layer plug 601 and the second drain layer 413, the second drain-channel layer 403, the second channel layer 402, the second source-channel layer 401, the second source layer 400, the first drain layer 310, and the first drain-channel layer 303;

[0251] For electrical isolation between the first drain layer plug 602 and the second drain layer 413, the second drain-channel layer 403, the second channel layer 402, the second source-channel layer 401, and the second source layer 400;

[0252] For electrical isolation between the second source layer plug 603 and the second drain layer 413, the second drain-channel layer 403, the second channel layer 402, and the second source-channel layer 401;

[0253] For electrical isolation between the second channel layer plug 604 and the second drain layer 413 and the second drain-channel layer 403.

[0254] The material of the via isolation layer 508 includes one or more of silicon nitride, silicon oxide, silicon carbide, and silicon carbonitride. In this embodiment, the material of the via isolation layer 508 is silicon nitride.

[0255] In this embodiment, a conformal coating process is used to form the via isolation material layer on the inner walls and bottoms of the first source layer via 500, the first channel layer via 501, the first drain layer via 502, the second source layer via 503, the second channel layer via 504, and the second drain layer via 505.

[0256] A re-etching process is used to remove the via isolation material layer at the bottoms of the first source layer via 500, the first channel layer via 501, the first drain layer via 502, the second source layer via 503, the second channel layer via 504, and the second drain layer via 505 to form the via isolation layer 508 covering the sidewalls of the first source layer via 500, the first channel layer via 501, the first drain layer via 502, the second source layer via 503, the second channel layer via 504, and the second drain layer via 505.

[0257] Reference Figures 20 to 22 , a first source layer plug 600 filling the first source layer via 500 is formed (see Figure 22 ), and a first channel layer plug 601 filling the first channel layer via 501 is formed (see Figure 20), a first drain layer plug 602 is formed to fill the first drain layer via 502 (see Figure 21 ), a second source layer plug 603 is formed to fill the second source layer via 503 (see Figure 22 ), a second channel layer plug 604 is formed to fill the second channel layer via 504 (see Figure 20 ), a second drain layer plug 605 is formed to fill the second drain layer via 505 (see Figure 21 ), a first gate structure layer plug 606 is formed to fill the first gate structure layer via 506 (see Figure 20 ), a second gate structure layer plug 607 is formed to fill the second gate structure layer via 507 (see Figure 20 ).

[0258] The materials of the first source layer plug 600, the first channel layer plug 601, the first drain layer plug 602, the second source layer plug 603, the second channel layer plug 604, the second drain layer plug 605, the first gate structure layer plug 606, and the second gate structure layer plug 607 include one or more of cobalt, copper, aluminum, and tungsten. In this embodiment, the materials of the first source layer plug 600, the first channel layer plug 601, the first drain layer plug 602, the second source layer plug 603, the second channel layer plug 604, the second drain layer plug 605, the first gate structure layer plug 606, and the second gate structure layer plug 607 are all tungsten.

[0259] In this embodiment, the main process steps for forming the above plugs include:

[0260] A plug material layer is formed on the substrate 200 by chemical vapor deposition, and the plug material layer covers the surface of the interlayer dielectric layer 414 and the inside of the first source layer via 500, the first channel layer via 501, the first drain layer via 502, the second source layer via 503, the second channel layer via 504, the second drain layer via 505, the first gate structure layer via 506, and the second gate structure layer via 507.

[0261] Using the interlayer dielectric layer 414 as a stop layer, the plug material layer is subjected to a sixth planarization process to form the first source layer plug 600, the first channel layer plug 601, the first drain layer plug 602, the second source layer plug 603, the second channel layer plug 604, the second drain layer plug 605, the first gate structure layer plug 606, and the second gate structure layer plug 607.

[0262] It should be noted that in some embodiments, when forming each via, a part of the thickness of the film layer at the bottom of each via can be removed so that the plug in each via is in electrical contact with the corresponding film layer.

[0263] It should be noted that one type of carrier in the semiconductor structure corresponds to the carrier of the first semiconductor device, and the other type of carrier in the semiconductor structure corresponds to the carrier of the second semiconductor device.

[0264] To solve the above technical problems, correspondingly, the present invention further provides a semiconductor structure. Figure 2 It is a top view schematic diagram of the semiconductor structure according to an embodiment of the present invention, corresponding to the method for forming the semiconductor structure of the present invention.

[0265] It should be noted that Figure 2 It needs to be combined with Figures 3 to 22 so as to more clearly display and elaborate a semiconductor structure according to an embodiment of the present invention.

[0266] The semiconductor structure of this embodiment includes: a substrate 200, including a first region 201 and a second region 202 surrounding and connected to the first region 201; a first source layer 300, a first source-channel layer 301, a first channel layer 302, and a first channel-drain layer 303 sequentially stacked on the first region 201; a first gate dielectric layer 307 located in the second region 202 and surrounding and covering the sidewalls of the first source-channel layer 301, the first channel layer 302, and the first channel-drain layer 303; a first gate structure layer 308 surrounding and covering the first gate dielectric layer 307; a first drain layer 310, a second source layer 400, a second source-channel layer 401, a second channel layer 402, and a second channel-drain layer 403 sequentially stacked on the first channel-drain layer 303; a second gate dielectric layer 410 located in the second region 202 and surrounding and covering the sidewalls of the second source-channel layer 401, the second channel layer 402, and the second channel-drain layer 403; a second gate structure layer 411 surrounding and covering the second gate dielectric layer 410; and a second drain layer 413 located on the second channel-drain layer 403.

[0267] By using the semiconductor structure provided by the embodiment of the present invention, one type of carrier in the semiconductor structure flows from the first source layer through the first source-channel layer, the first channel layer, and the first channel-drain layer to the first drain layer along a direction perpendicular to the surface of the substrate, and the other type of carrier in the semiconductor structure flows from the second source layer through the second source-channel layer, the second channel layer, and the second channel-drain layer to the second drain layer; along a direction perpendicular to the surface of the substrate, the thickness of the first channel layer corresponds to the channel length of one type of carrier, and the thickness of the second channel layer corresponds to the channel length of the other type of carrier. The thicknesses of the first channel layer and the second channel layer can be reduced by a film-forming process to reduce the channel length of the carriers, thereby further improving the on-state current of the semiconductor transistor.

[0268] Referring to Figure 20 , the semiconductor structure includes: a substrate 200.

[0269] The substrate 200 is used to provide a process platform for the formation of a semiconductor structure.

[0270] It should be noted that the substrate 200 is used to form a first semiconductor device and a second semiconductor device stacked on the first semiconductor device. The types of the first semiconductor device include: PMOS transistor or NMOS transistor. The types of the second semiconductor device include: PMOS transistor or NMOS transistor. In this embodiment, the first semiconductor device is a PMOS transistor, and the second semiconductor device is an NMOS transistor; the transistor types of the first semiconductor device and the second semiconductor device stacked in the first region 201 can be selected according to actual needs, and this does not limit the present application. In some embodiments, the first semiconductor device is an NMOS transistor, and the second semiconductor device is a PMOS transistor, or, the first semiconductor device is a PMOS transistor, and the second semiconductor device is a PMOS transistor, or, the first semiconductor device is an NMOS transistor, and the second semiconductor device is an NMOS transistor.

[0271] In this embodiment, the substrate 200 is a silicon substrate 200, and the material of the substrate 200 is single crystal silicon. In some other embodiments, the material of the substrate 200 can also be one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium arsenide. The substrate 200 can also be other types of substrates 200 such as silicon-on-insulator substrate 200 or germanium-on-insulator substrate 200. In other embodiments, an epitaxial layer (not shown) having the same crystal structure as the substrate 200 can be formed on the surface of the substrate 200 to improve the pattern transfer quality.

[0272] The substrate 200 includes a first region 201 and a second region 202 surrounding and connected to the first region 201.

[0273] The first region 201 includes an outer edge of the first region (not shown), and the second region 202 includes an inner edge of the second region (not shown). The inner edge of the second region is connected to the outer edge of the first region. The second region 202 surrounds the first region 201 so that the second region 202 is adjacent to the first region 201 in a surrounding manner. In some embodiments, the second region 202 is adjacent to the first region 201 in a surrounding manner to form a "hui" character shape. In some other embodiments, the second region 202 is adjacent to the first region 201 in a surrounding manner to form a "U" character shape, and this does not limit the present application.

[0274] Reference Figure 20, the semiconductor structure includes: a first source layer 300, a first source-channel layer 301, a first channel layer 302, and a first channel-drain layer 303 that are sequentially stacked in the first region 201; a first drain layer 310, a second source layer 400, a second source-channel layer 401, a second channel layer 402, and a second channel-drain layer 403 that are sequentially stacked on the first channel-drain layer 303;

[0275] The first source layer 300 is used as the source of the first semiconductor device.

[0276] The first channel layer 302 is used as the channel of the first semiconductor device.

[0277] The first source-channel layer 301 is used as a blocking layer between the first source layer 300 and the first channel layer 302, which can effectively prevent the mutual diffusion of doping ions in the first channel layer 302 and the doping ions in the first source layer 300, thereby improving the reliability and stability of the semiconductor device.

[0278] The first channel-drain layer 303 is used as a blocking layer between the first channel layer 302 and the first drain layer 310, which can effectively prevent the mutual diffusion of doping ions in the first drain layer 310 and the doping ions in the first channel layer 302, thereby improving the reliability and stability of the semiconductor device.

[0279] In this embodiment, along the direction perpendicular to the surface of the substrate 200, the carriers of the first semiconductor device flow from the first source layer 300 through the first source-channel layer 301, the first channel layer 302, and the first channel-drain layer 303 to the first drain layer 310. That is, the channel length of the first semiconductor device is the thickness of the first channel layer 302. Compared with the lithography exposure process, a first channel layer 302 with a smaller thickness can be formed by chemical vapor deposition process or epitaxial process, thereby reducing the carrier flow path of the first semiconductor device and further increasing the on-state current of the semiconductor transistor.

[0280] In this embodiment, along the direction perpendicular to the surface of the substrate 200, the carriers of the second semiconductor device flow from the second source layer 400 through the second source-channel layer 401, the second channel layer 402, and the second channel-drain layer 403 to the second drain layer 413. That is, the channel length of the second semiconductor device is the thickness of the second channel layer 402. Compared with the lithography exposure process, a second channel layer 402 with a smaller thickness can be formed by chemical vapor deposition process or epitaxial process, thereby reducing the carrier flow path of the second semiconductor device and further increasing the on-state current of the semiconductor transistor.

[0281] Regarding the materials, thicknesses, doping concentrations, types of doping ions, etc. of the first source layer 300, the first source trench layer 301, the first channel layer 302, the first channel-drain layer 303, the first drain layer 310, the second source layer 400, the second source trench layer 401, the second channel layer 402, and the second channel-drain layer 403, reference can be made to the aforementioned method for forming a semiconductor structure, which will not be elaborated herein.

[0282] Continue to refer to Figure 20 , the semiconductor structure includes: a first filling layer 304, located in the second region 202, along a direction parallel to the surface of the substrate 200, and the surface of the first filling layer 304 is flush with the surface of the first channel-drain layer 303.

[0283] The first filling layer 304 is used for isolation between semiconductor devices to prevent electrical interference between different regions.

[0284] The material of the first filling layer 304 includes one or more of silicon oxide, silicon nitride, silicon carbide, and silicon carbonitride. In this embodiment, the material of the first filling layer 304 is silicon oxide.

[0285] Continue to refer to Figure 20 , in combination with Figure 5 , the semiconductor structure includes: a first filling layer trench 305, located within the first filling layer 304, and the first filling layer trench 305 exposes the sidewalls of the first source trench layer 301, the first channel layer 302, and the first channel-drain layer 303.

[0286] The first filling layer trench 305 includes: a first filling layer trench sidewall opposite to the sidewalls of the first source trench layer 301, the first channel layer 302, and the first channel-drain layer 303, and a first filling layer trench bottom.

[0287] The first filling layer trench 305 is used to accommodate the first gate dielectric layer 307 and the first gate structure layer 308.

[0288] Continue to refer to Figure 20 , the semiconductor structure includes: a first gate dielectric layer 307, located in the second region 202, surrounding and covering the sidewalls of the first source trench layer 301, the first channel layer 302, and the first channel-drain layer 303.

[0289] The first gate dielectric layer 307, as an electrical insulating material, is used to electrically isolate the first gate structure layer 308 from the first source layer 300, the first source trench layer 301, the first channel layer 302, the first channel-drain layer 303, and the first drain layer 310 of the first semiconductor device.

[0290] The material of the first gate dielectric layer 307 includes one or more of silicon oxide and high-k gate dielectric layer materials. The silicon oxide has good insulation, coverage, and stability. In this embodiment, the material of the first gate dielectric layer 307 is silicon oxide.

[0291] The film thickness of the first gate dielectric layer 307 being silicon oxide is in the range of greater than or equal to 50 nanometers and less than or equal to 200 nanometers.

[0292] By making the film thickness of the silicon oxide greater than or equal to 50 nanometers, good electrical insulation and isolation effects can be achieved; by making the film thickness of the silicon oxide less than or equal to 200 nanometers, the process fabrication cycle can be reduced and the characteristics of semiconductor devices can be ensured.

[0293] It should be noted that the high-k gate dielectric layer materials include dielectric materials with a dielectric constant greater than that of silicon oxide (3.9); the high-k gate dielectric layer materials include one or more of hafnium oxide, zirconium oxide, hafnium silicon oxide, hafnium oxynitride, hafnium silicon oxynitride, hafnium tantalum oxynitride, zirconium oxynitride, zirconium silicon oxynitride, zirconium silicon oxide, lanthanum oxide, titanium oxide, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate. Preferably, the dielectric constant of the high-k gate dielectric layer materials is greater than 8 to reduce the thickness of the first gate dielectric layer 307 and improve the performance of the transistor.

[0294] In this embodiment, the first gate dielectric layer 307 is located within the first fill layer trench 305, that is, the first gate dielectric layer 307 is located on the sidewalls of the first source trench layer 301, the first channel layer 302, and the first drain trench layer 303 surrounded by the second region 202, and the first gate dielectric layer 307 also covers the sidewalls and the bottom of the first fill layer trench.

[0295] Continue to refer to Figure 20 , the semiconductor structure includes: a first gate structure layer 308, which surrounds and covers the first gate dielectric layer 307.

[0296] The first gate structure layer 308 is used to control the turn-on and turn-off of the first semiconductor device.

[0297] The material of the first gate structure layer 308 includes one or more of titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), titanium (Ti), titanium aluminide (TiAl), tungsten (W), aluminum (Al), titanium silicon nitride (TiSiN), titanium aluminum carbide (TiAlC).

[0298] In this embodiment, the material of the first gate structure layer 308 is titanium nitride (TiN).

[0299] In this embodiment, the first gate structure layer 308 is filled in the first filling layer trench 305 and surrounds and covers the first gate dielectric layer 307. That is, the first gate structure layer 308 surrounds and covers the surface of the first gate dielectric layer 307 on the sidewalls of the first source trench layer 301, the first channel layer 302, and the first drain trench layer 303, also surrounds and covers the surface of the first gate dielectric layer 307 on the sidewall of the first filling layer trench 305, and covers the surface of the first gate dielectric layer 307 at the bottom of the first filling layer trench 305.

[0300] Continuing to refer Figure 20 , the semiconductor structure includes: a first thin layer 309, covering the surfaces of the first filling layer 304 and the first gate structure layer 308.

[0301] The first thin layer 309 is used to protect the first gate structure layer 308.

[0302] The material of the first thin layer 309 includes one or more of silicon oxide, silicon nitride, silicon carbide, and silicon carbonitride. In this embodiment, the material of the first thin layer 309 is silicon oxide.

[0303] Continuing to refer Figure 20 , the semiconductor structure includes: a second filling layer 404, located in the second region 202, along the surface direction parallel to the substrate 200, the surface of the second filling layer 404 is flush with the surface of the second drain trench layer 403 in the first region 201.

[0304] The second filling layer 404 is used for isolation between semiconductor devices to prevent electrical interference between different regions.

[0305] The material of the second filling layer 404 includes one or more of silicon oxide, silicon nitride, silicon carbide, and silicon carbonitride. In this embodiment, the material of the first filling layer 304 is silicon oxide.

[0306] In this embodiment, the second filling layer 404 covers the surface of the first thin layer 309 in the second region 202, and along the surface direction parallel to the substrate 200, the surface of the second filling layer 404 is flush with the surface of the second drain trench layer 403 in the first region 201.

[0307] Continuing to refer Figure 20 , in combination with Figure 10 , the semiconductor structure includes: a first spacer 406, located between the first drain layer 310 and the second source layer 400.

[0308] The first spacer 406 is used to accommodate the third filling layer 407 located between the first drain layer 310 and the second source layer 400.

[0309] Continue to refer to Figure 20 , in combination with Figure 10 , the semiconductor structure includes: a second fill layer trench 405 located within the second fill layer 404, and the second fill layer trench 405 exposes the sidewalls of the second source layer 400, the second source trench layer 401, the second channel layer 402, the second drain trench layer 403, and the first spacer 406.

[0310] Continue to refer to Figure 20 , in combination with Figure 12 , the semiconductor structure includes: a third fill layer 407 filled within the first spacer 406 and also filled in a part of the second fill layer trench 405 to form a third fill layer trench 408, and the third fill layer trench 408 exposes the sidewalls of the second source trench layer 401, the second channel layer 402, and the second drain trench layer 403.

[0311] The third fill layer trench 408 includes: the sidewall of the third fill layer trench opposite to the sidewalls of the second source trench layer 401, the second channel layer 402, and the second drain trench layer 403, and the bottom of the third fill layer trench.

[0312] The third fill layer 407 within the first spacer 406 is used to electrically isolate the first semiconductor device and the second semiconductor device, that is, the third fill layer 407 is located within the first spacer 406 between the first drain layer 310 and the second source layer 400.

[0313] Continue to refer to Figure 20 , the semiconductor structure includes: a second gate dielectric layer 410 located in the second region 202 and surrounding and covering the sidewalls of the second source trench layer 401, the second channel layer 402, and the second drain trench layer 403.

[0314] The second gate dielectric layer 410, as an electrical insulating material, electrically isolates the subsequently formed second gate structure layer 411 from the second source layer 400, the second source trench layer 401, the second channel layer 402, the second drain trench layer 403, and the second drain layer 413 of the second semiconductor device.

[0315] The material of the second gate dielectric layer 410 includes: one or more of silicon oxide and a high-k gate dielectric layer material. The silicon oxide has good insulation, coverage, and stability. In this embodiment, the material of the second gate dielectric layer 410 is silicon oxide.

[0316] The film thickness of the second gate dielectric layer 410 being silicon oxide is in the range of greater than or equal to 50 nanometers and less than or equal to 200 nanometers.

[0317] By making the film thickness of the silicon oxide greater than or equal to 50 nm, a good electrical insulation and isolation effect can be achieved; by making the film thickness of the silicon oxide less than or equal to 200 nm, the process fabrication cycle can be reduced and the characteristics of the semiconductor device can be ensured.

[0318] It should be noted that the high-k gate dielectric layer material includes a dielectric material with a dielectric constant greater than that of silicon oxide (3.9); the high-k gate dielectric layer material includes one or more of hafnium oxide, zirconium oxide, hafnium silicon oxide, hafnium oxynitride, hafnium silicon oxynitride, hafnium tantalum oxynitride, zirconium oxynitride, zirconium silicon oxynitride, zirconium silicon oxide, lanthanum oxide, titanium oxide, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate. Preferably, the dielectric constant of the high-k gate dielectric layer material is greater than 8 to reduce the thickness of the second gate dielectric layer 410 and improve the performance of the transistor.

[0319] In this embodiment, the second gate dielectric layer 410 is located in the third filling layer trench 408, that is, the second gate dielectric layer 410 is located on the sidewalls of the second source trench layer 401, the second channel layer 402, and the second drain trench layer 403 surrounded by the second region 202, and the second gate dielectric layer 410 also covers the sidewall and the bottom of the third filling layer trench.

[0320] Continue to refer to Figure 20 , the semiconductor structure includes: a second gate structure layer 411, which surrounds and covers the second gate dielectric layer 410.

[0321] The second gate structure layer 411 is used to control the turn-on and turn-off of the second semiconductor device.

[0322] The material of the second gate structure layer 411 includes one or more of titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), titanium (Ti), titanium aluminide (TiAl), tungsten (W), aluminum (Al), titanium silicon nitride (TiSiN), titanium aluminum carbide (TiAlC).

[0323] In this embodiment, the material of the second gate structure layer 411 is titanium nitride (TiN).

[0324] In this embodiment, the second gate structure layer 411 is filled in the third filling layer trench 408 and surrounds and covers the second gate dielectric layer 410, that is, the second gate structure layer 411 surrounds and covers the surface of the second gate dielectric layer 410 on the sidewalls of the second source trench layer 401, the second channel layer 402, and the second drain trench layer 403, also surrounds and covers the surface of the second gate dielectric layer 410 on the sidewall of the third filling layer trench, and covers the surface of the second gate dielectric layer 410 at the bottom of the third filling layer trench.

[0325] Continue to refer to Figure 20 The semiconductor structure includes a second thin layer 412 covering the surfaces of the second filling layer 404 and the second gate structure layer 411.

[0326] The second thin layer 412 is used to protect the second gate structure layer 411.

[0327] The material of the second thin layer 412 includes one or more of silicon oxide, silicon nitride, silicon carbide, and silicon carbonitride. In this embodiment, the material of the second thin layer 412 is silicon oxide.

[0328] Continue to refer to Figure 20 The semiconductor structure includes a second drain layer 413 located on the second drain-channel layer 403.

[0329] The second drain layer 413 is used as the drain of the second semiconductor device.

[0330] Continue to refer to Figure 20 The semiconductor structure includes an interlayer dielectric layer 414 covering the surfaces of the second thin layer 412 and the second drain layer 413.

[0331] The interlayer dielectric layer 414 has the following beneficial effects:

[0332] First, electrical isolation. The interlayer dielectric layer 414 isolates different metal layers (such as interconnect lines), avoiding short circuits caused by direct contact between metal layers, reducing electromagnetic interference (crosstalk) between signal lines, and improving signal transmission quality.

[0333] Second, reducing parasitic capacitance. By using a low dielectric constant material, the interlayer dielectric layer 414 can reduce the parasitic capacitance between metal layers.

[0334] The material of the interlayer dielectric layer 414 includes one or more of silicon oxide, silicon nitride, silicon carbide, and silicon carbonitride. In this embodiment, the material of the interlayer dielectric layer 414 is silicon oxide.

[0335] In the direction perpendicular to the surface of the substrate 200, the sidewalls of the first source layer 300, the first source-channel layer 301, the first channel layer 302, the first drain-channel layer 303, the first drain layer 310, the third filling layer 407 in the first spacer 406, the second source layer 400, the second source-channel layer 401, the second channel layer 402, the second drain-channel layer 403, and the second drain layer 413 are flush.

[0336] Continue to refer to Figures 17 to 22 Combined with Figure 2 The semiconductor structure includes:

[0337] The first source layer via 500: penetrates through the interlayer dielectric layer 414, the second drain layer 413, the second drain-channel layer 403, the second channel layer 402, the second source-channel layer 401, the second source layer 400, the third filling layer 407, the first drain layer 310, the first drain-channel layer 303, the first channel layer 302, and the first source-channel layer 301;

[0338] The first channel layer via 501 penetrates through the interlayer dielectric layer 414, the second drain layer 413, the second drain-channel layer 403, the second channel layer 402, the second source-channel layer 401, the second source layer 400, the third filling layer 407, the first drain layer 310, and the first drain-channel layer 303;

[0339] The first drain layer via 502 penetrates through the interlayer dielectric layer 414, the second drain layer 413, the second drain-channel layer 403, the second channel layer 402, the second source-channel layer 401, the second source layer 400, and the third filling layer 407;

[0340] The second source layer via 503 penetrates through the interlayer dielectric layer 414, the second drain layer 413, the second drain-channel layer 403, the second channel layer 402, and the second source-channel layer 401;

[0341] The second channel layer via 504 is formed to penetrate through the interlayer dielectric layer 414, the second drain layer 413, and the second drain-channel layer 403;

[0342] The second drain layer via 505 penetrates through the interlayer dielectric layer 414;

[0343] The via isolation layer 508 covers the sidewalls of the first source layer via 500, the first channel layer via 501, the first drain layer via 502, the second source layer via 503, the second channel layer via 504, and the second drain layer via 505;

[0344] The first gate structure layer via 506 penetrates through the interlayer dielectric layer 414, the second thin layer 412, the second filling layer 404, and the first thin layer 309;

[0345] The second gate structure layer via 507 penetrates through the interlayer dielectric layer 414 and the second thin layer 412;

[0346] The first source layer plug 600 is filled in the first source layer via 500 and is in contact with the first source layer 300, i.e., electrical contact.

[0347] The first channel layer plug 601 is filled in the first channel layer via 501 and is in contact with the first channel layer 302, i.e., electrical contact.

[0348] The first drain layer plug 602 is filled in the first drain layer via 502 and contacts the first drain layer 310, i.e., makes electrical contact.

[0349] The second source layer plug 603 is filled in the second source layer via 503 and contacts the second source layer 400, i.e., makes electrical contact.

[0350] The second channel layer plug 604 is filled in the second channel layer via 504 and contacts the second channel layer 402, i.e., makes electrical contact.

[0351] The second drain layer plug 605 is filled in the second drain layer via 505 and contacts the second drain layer 413, i.e., makes electrical contact.

[0352] The first gate structure layer plug 606 is filled in the first gate structure layer via 506 and contacts the first gate structure layer 308, i.e., makes electrical contact.

[0353] The second gate structure layer plug 607 is filled in the second gate structure layer via 507 and contacts the second gate structure layer 411, i.e., makes electrical contact.

[0354] Regarding the via isolation layer 508, the various vias and the various plugs above, reference can be made to the description of the semiconductor structure forming method, which will not be elaborated here.

[0355] The first semiconductor device at least includes: a first source layer 300, a first source-channel layer 301, a first channel layer 302, a first channel-drain layer 303, a first drain layer 310, a first gate dielectric layer 307, a first gate structure layer 308, a first source layer plug 600, a first channel layer plug 601, a first drain layer plug 602, a first gate structure layer plug 606, a first source layer plug 600, a first channel layer plug 601, a first drain layer plug 602, a first gate structure layer plug 606.

[0356] The second semiconductor device at least includes: a second source layer 400, a second source-channel layer 401, a second channel layer 402, a second channel-drain layer 403, a second drain layer 413, a second gate dielectric layer 410, a second gate structure layer 411, a second source layer plug 603, a second channel layer plug 604, a second drain layer plug 605, a second gate structure layer plug 607, a second source layer plug 603, a second channel layer plug 604, a second drain layer plug 605, a second gate structure layer plug 607.

[0357] Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and decorations made to the above embodiments based on the technical essence of the present invention without departing from the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A method for forming a semiconductor structure, characterized in that, Comprising: Providing a substrate including a first region and a second region surrounding and connected to the first region; Sequentially forming a stacked first source layer, first source trench layer, first channel layer, and first trench-drain layer in the first region; Forming a first gate dielectric layer in the second region to surround and cover the sidewalls of the first source trench layer, first channel layer, and first trench-drain layer; Forming a first gate structure layer to surround and cover the first gate dielectric layer; Sequentially forming a stacked first drain layer, sacrificial layer, second source layer, second source trench layer, second channel layer, and second trench-drain layer on the first trench-drain layer; Forming a third filling layer on the substrate; Forming a second gate dielectric layer in the second region to surround and cover the sidewalls of the second source trench layer, second channel layer, and second trench-drain layer; Forming a second gate structure layer to surround and cover the second gate dielectric layer; Forming a second drain layer covering the second trench-drain layer; Forming an interlayer dielectric layer on the substrate; Forming a first channel plug that penetrates the interlayer dielectric layer, second drain layer, second trench-drain layer, second channel layer, second source trench layer, second source layer, third filling layer, first drain layer, and first trench-drain layer; Forming a second channel plug that penetrates the interlayer dielectric layer and second drain layer and second trench-drain layer; The material of the first source trench layer includes: silicon germanide, the material of the first trench-drain layer includes: silicon germanide, the material of the second source trench layer includes: silicon carbide, and the material of the second trench-drain layer includes: silicon carbide.

2. The forming method according to claim 1, wherein In a direction perpendicular to the surface of the substrate, the sidewalls of the first source layer, first source trench layer, first channel layer, first trench-drain layer, first drain layer, sacrificial layer, second source layer, second source trench layer, second channel layer, second trench-drain layer, and second drain layer are flush.

3. The forming method according to claim 1, characterized in that, The material of the sacrificial layer includes: silicon germanide.

4. The forming method according to claim 1, characterized in that, After forming the first trench-drain layer and before forming the first gate dielectric layer, the forming method further includes: Forming a first filling layer on the substrate in the second region, the first filling layer covering the sidewalls of the first source layer, first source trench layer, first channel layer, and first trench-drain layer; Removing a part of the first filling layer to expose the sidewalls of the first source trench layer, first channel layer, and first trench-drain layer to form a first filling layer trench; The first filling layer trench includes: a first filling layer trench sidewall opposite to the sidewalls of the first source trench layer, first channel layer, and first trench-drain layer, and a first filling layer trench bottom; 5. The forming method according to claim 4, characterized in that, Forming a first gate dielectric layer in the first filling layer trench to surround and cover the sidewalls of the first source trench layer, first channel layer, and first trench-drain layer; The first gate dielectric layer also covers the first filling layer trench bottom and the first filling layer trench sidewall; 6. The forming method according to claim 4, characterized in that After forming the first filling layer trench and before forming the first gate dielectric layer, the forming method further includes: Forming a first metal layer outside the first filling layer trench to cover the surfaces of the first filling layer and the first trench-drain layer; 7. The forming method according to claim 4, characterized in that Filling the first gate structure layer in the first filling layer trench, the first gate structure layer surrounding and covering the first gate dielectric layer; 8. The forming method according to claim 5, characterized in that, The forming method further includes: forming a first thin layer covering the surface of the first gate structure layer; The first thin layer also covers the first filling layer.

9. The forming method according to claim 8, wherein After forming the second drain-gate layer and before forming the second gate dielectric layer, the forming method further includes: Forming a second filling layer on the first thin layer, the second filling layer covering sidewalls of the first drain layer, the sacrificial layer, the second source layer, the second source-gate layer, the second channel layer, and the second drain-gate layer; Removing a part of the second filling layer to expose sidewalls of the sacrificial layer, the second source layer, the second source-gate layer, the second channel layer, and the second drain-gate layer to form a second filling layer trench, and removing the sacrificial layer to form a first spacer between the first drain layer and the second source layer; 10. The forming method according to claim 9, characterized in that, Filling a third filling layer in the second filling layer trench and the first spacer; Removing a part of the third filling layer to expose sidewalls of the second source-gate layer, the second channel layer, and the second drain-gate layer to form a third filling layer trench; The third filling layer trench includes: a third filling layer trench sidewall opposite to sidewalls of the second source-gate layer, the second channel layer, and the second drain-gate layer, and a third filling layer trench bottom; 11. The forming method according to claim 10, characterized in that, Forming a second gate dielectric layer in the third filling layer trench to surround and cover sidewalls of the second source-gate layer, the second channel layer, and the second drain-gate layer; The second gate dielectric layer also covers the third filling layer trench bottom and the third filling layer trench sidewall; 12. The forming method according to claim 11, wherein, After forming the third filling layer trench and before forming the second gate dielectric layer, the forming method further includes: Forming a second metal layer outside the third filling layer trench to cover surfaces of the second filling layer and the second drain-gate layer; 13. The forming method according to claim 11, characterized in that, Filling the second gate structure layer in the third filling layer trench, the second gate structure layer surrounding and covering the second gate dielectric layer; 14. The forming method according to claim 13, wherein, The forming method further includes: After forming the second gate structure layer and before forming the second drain layer, forming a second thin layer on a surface of the second gate structure layer, the second thin layer also covering the second filling layer; 15. The forming method according to claim 14, characterized in that, Forming an interlayer dielectric layer covering the second thin layer and the second drain layer; Forming a first source layer via hole penetrating through the interlayer dielectric layer, the second drain layer, the second drain-gate layer, the second channel layer, the second source-gate layer, the second source layer, the third filling layer, the first drain layer, the first drain-gate layer, the first channel layer, and the first source-gate layer; Forming a first channel layer via hole penetrating through the interlayer dielectric layer, the second drain layer, the second drain-gate layer, the second channel layer, the second source-gate layer, the second source layer, and the third filling layer; Forming a first drain layer via hole penetrating through the interlayer dielectric layer, the second drain layer, the second drain-gate layer, the second channel layer, the second source-gate layer, and the second source layer; Forming a second source layer via hole penetrating through the interlayer dielectric layer, the second drain layer, the second drain-gate layer, the second channel layer, and the second source-gate layer; Forming a second channel layer via hole penetrating through the interlayer dielectric layer and the second drain-gate layer; Forming a second drain layer via hole penetrating through the interlayer dielectric layer; Forming a first gate structure layer via hole penetrating through the interlayer dielectric layer, the second thin layer, the second filling layer, and the first thin layer; Forming a second gate structure layer via hole penetrating through the interlayer dielectric layer and the second thin layer; Form a via isolation layer covering the sidewalls of the first source layer via, the first channel layer via, the first drain layer via, the second source layer via, the second channel layer via, and the second drain layer via; Form a first source layer plug filling the first source layer via; Form a first channel layer plug filling the first channel layer via; Form a first drain layer plug filling the first drain layer via; Form a second source layer plug filling the second source layer via; Form a second channel layer plug filling the second channel layer via; Form a second drain layer plug filling the second drain layer via; Form a first gate structure layer plug filling the first gate structure layer via; Form a second gate structure layer plug filling the second gate structure layer via.

16. The forming method according to claim 1, wherein The first source layer, the first source-channel layer, the first channel layer, the first channel-drain layer, the first drain layer, the second source layer, the second source-channel layer, the second channel layer, and the second channel-drain layer are all formed by an epitaxial process.

17. The forming method according to claim 16, wherein The parameters of the epitaxial process include: the temperature ranges from 600 degrees Celsius to 800 degrees Celsius.

18. The forming method according to claim 17, wherein The parameters of the epitaxial process at least further include one of the following: The pressure is from 70 Torr to 90 Torr; The flow rate of Purge MainH2 is from 3200 sccm to 3800 sccm; The flow rate of Purge SlitH2 is from 80 sccm to 120 sccm; The flow rate of the silicon source gas is from 120 sccm to 180 sccm; The epitaxial rate is from 200 angstroms per minute to 300 angstroms per minute.

19. A semiconductor structure, characterized in that, Comprising: A substrate including a first region and a second region surrounding and connected to the first region; A first source layer, a first source-channel layer, a first channel layer, and a first channel-drain layer sequentially stacked in the first region; A first gate dielectric layer located in the second region and surrounding and covering the sidewalls of the first source-channel layer, the first channel layer, and the first channel-drain layer; A first gate structure layer surrounding and covering the first gate dielectric layer; A first drain layer, a second source layer, a second source-channel layer, a second channel layer, and a second channel-drain layer sequentially stacked on the first channel-drain layer; A third filling layer located on the substrate; A second gate dielectric layer located in the second region and surrounding and covering the sidewalls of the second source-channel layer, the second channel layer, and the second channel-drain layer; A second gate structure layer surrounding and covering the second gate dielectric layer; A second drain layer located on the second channel-drain layer; An interlayer dielectric layer located on the substrate; A first channel layer plug penetrating through the interlayer dielectric layer, the second drain layer, the second channel-drain layer, the second channel layer, the second source-channel layer, the second source layer, the third filling layer, the first drain layer, and the first channel-drain layer; A second channel layer plug penetrating through the interlayer dielectric layer, the second drain layer, and the second channel-drain layer.

20. The semiconductor structure according to claim 19, wherein In a direction perpendicular to the surface of the substrate, the sidewalls of the first source layer, the first source-channel layer, the first channel layer, the first channel-drain layer, the first drain layer, the second source layer, the second source-channel layer, the second channel layer, the second channel-drain layer, and the second drain layer are flush.

21. The semiconductor structure according to claim 19, wherein Further comprising: A first filling layer located in the second region and flush with the surface of the first channel-drain layer in a direction parallel to the surface of the substrate; The first fill layer trench is located within the first fill layer, and the first fill layer trench exposes the sidewalls of the first source trench layer, the first channel layer, and the first drain trench layer; The first fill layer trench includes: a first fill layer trench sidewall and a first fill layer trench bottom that are opposite to the sidewalls of the first source trench layer, the first channel layer, and the first drain trench layer; The first gate dielectric layer is located within the first fill layer trench and surrounds and covers the sidewalls of the first source trench layer, the first channel layer, and the first drain trench layer; The first gate dielectric layer also covers the first fill layer trench sidewall and the first fill layer trench bottom; A first gate structure layer is filled within the first fill layer trench and surrounds and covers the first gate dielectric layer.

22. The semiconductor structure according to claim 21, wherein It further includes: A first thin layer covers the surfaces of the first fill layer and the first gate structure layer; The second fill layer is located in the second region and is flush with the surface of the second drain trench layer in the first region along the surface direction parallel to the substrate; A first spacer is located between the first drain layer and the second source layer; The second fill layer trench is located within the second fill layer, and the second fill layer trench exposes the sidewalls of the second source layer, the second source trench layer, the second channel layer, the second drain trench layer, and the first spacer; A third fill layer is filled within the first spacer and also fills a part of the second fill layer trench to form a third fill layer trench, and the third fill layer trench exposes the sidewalls of the second source trench layer, the second channel layer, and the second drain trench layer; The third fill layer trench includes: a third fill layer trench sidewall and a third fill layer trench bottom that are opposite to the sidewalls of the second source trench layer, the second channel layer, and the second drain trench layer; The second gate dielectric layer is located within the third fill layer trench and surrounds and covers the sidewalls of the second source trench layer, the second channel layer, and the second drain trench layer; The second gate dielectric layer also covers the third fill layer trench sidewall and the third fill layer trench bottom; A second gate structure layer is filled within the third fill layer trench and surrounds and covers the second gate dielectric layer.

23. The semiconductor structure according to claim 22, wherein, It further includes: A second thin layer covers the surfaces of the second fill layer and the second gate structure layer; An interlayer dielectric layer covers the surfaces of the second thin layer and the second drain layer.

24. The semiconductor structure according to claim 23, wherein, It further includes: A first source layer via: penetrating through the interlayer dielectric layer, the second drain layer, the second drain trench layer, the second channel layer, the second source trench layer, the second source layer, the third fill layer, the first drain layer, the first drain trench layer, the first channel layer, and the first source trench layer; A first channel layer via, penetrating through the interlayer dielectric layer, the second drain layer, the second drain trench layer, the second channel layer, the second source trench layer, the second source layer, the third fill layer, the first drain layer, the first drain trench layer; a first drain layer via, penetrating through the interlayer dielectric layer, the second drain layer, the second drain trench layer, the second channel layer, the second source trench layer, the second source layer, the third fill layer; A second source layer via, penetrating through the interlayer dielectric layer, the second drain layer, the second drain trench layer, the second channel layer, the second source trench layer; A second channel layer via is formed to penetrate through the interlayer dielectric layer, the second drain layer, the second drain trench layer; The second drain layer via, penetrating through the interlayer dielectric layer; The via isolation layer, covering the sidewalls of the first source layer via, the first channel layer via, the first drain layer via, the second source layer via, the second channel layer via, and the second drain layer via; The first gate structure layer via, penetrating through the interlayer dielectric layer, the second thin layer, the second filling layer, and the first thin layer; The second gate structure layer via, penetrating through the interlayer dielectric layer and the second thin layer; The first source layer plug, filled in the first source layer via and contacting the first source layer; The first channel layer plug, filled in the first channel layer via and contacting the first channel layer; The first drain layer plug, filled in the first drain layer via and contacting the first drain layer; The second source layer plug, filled in the second source layer via and contacting the second source layer; The second channel layer plug, filled in the second channel layer via and contacting the second channel layer; The second drain layer plug, filled in the second drain layer via and contacting the second drain layer; The first gate structure layer plug, filled in the first gate structure layer via and contacting the first gate structure layer; The second gate structure layer plug, filled in the second gate structure layer via and contacting the second gate structure layer.

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