Electrostatic discharge protection circuit

Abstract

Described herein is an electrostatic discharge protection circuit (100) configured to provide electrostatic discharge protection between a first rail of an operating potential (111) and a second rail of a reference potential (112). The electrostatic discharge protection circuit (100) includes a detection unit (120) configured to detect an electrostatic discharge event between the first rail and the second rail. Further, the electrostatic discharge protection circuit (100) includes a clamping unit (130) configured to provide a discharge path between the first rail and the second rail in response to an electrostatic discharge event detected by the detection unit (120), where the clamping unit (130) includes a main bipolar junction transistor (107) configured to provide a discharge path between the first rail and the second rail in response to an electrostatic discharge event detected by the detection unit (120). The main bipolar junction transistor (107) is cascode with an additional bipolar junction transistor (108, 308, 408) for providing the discharge path.

Description

Technical Field

[0001] The invention relates to an electrostatic discharge protection circuit. Background Art

[0002] Integrated circuits may be exposed to electrostatic discharge. Electrostatic discharge protection circuits can be used to protect integrated circuits from electrostatic discharge. Electrostatic discharge protection circuits are typically configured to provide a temporary discharge path to dissipate electrostatic charge, thereby protecting the integrated circuit.

[0003] The technical problem of providing a particularly space-efficient and energy-saving electrostatic discharge protection circuit with low leakage current is solved herein. The technical problem is solved by the independent claim. Preferred examples are described in the dependent claims. Summary of the invention

[0004] According to one aspect, an electrostatic discharge protection circuit is described, which is configured to provide electrostatic discharge protection between a first rail at an operating potential and a second rail at a reference potential. The electrostatic discharge protection circuit includes a detection unit, which is configured to detect an electrostatic discharge event between the first rail and the second rail. In addition, the electrostatic discharge protection circuit includes a clamping unit, which is configured to provide a (temporary) discharge path between the first rail and the second rail in response to an electrostatic discharge event detected by the detection unit. The clamping unit includes a main bipolar junction transistor, which is communal with an additional bipolar junction transistor to provide a discharge path.

[0005] It should be noted that the system including the preferred embodiments outlined herein can be used alone or in combination with other systems disclosed herein. Furthermore, features outlined in the context of the system also apply to the corresponding method. Furthermore, all aspects of the system outlined herein can be combined arbitrarily. In particular, the features of the claims can be combined with each other in any manner. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present invention is explained below in an exemplary manner with reference to the accompanying drawings, in which

[0008] Figure 1 An example of an electrostatic discharge protection circuit is shown;

[0009] Figure 2 Another example of another electrostatic discharge protection circuit is shown;

[0010] Figure 3 Another example of another electrostatic discharge protection circuit is shown; and

[0011] Figure 4 A further example of another electrostatic discharge protection circuit is shown. DETAILED DESCRIPTION

[0012] As mentioned above, the present invention aims to provide a particularly compact and efficient electrostatic discharge protection circuit. Figures 1 to 4 Different examples of an electrostatic discharge protection circuit 100 are shown, which can be implemented in a space-efficient and energy-saving manner. The electrostatic discharge protection circuit 100 operates between an operating potential VDD 111 (where the first rail is located) and a reference potential VSS 112 (where the second rail is located). The first rail and / or the second rail may be subjected to electrostatic discharge (ESD), which may cause a sudden increase in the voltage level of the first rail. The electrostatic discharge protection circuit 100 includes a detection unit 120 configured to detect an electrostatic discharge event. The detection unit 120 may include a resistor 101 and a capacitor 102, which are arranged in series between the operating potential 111 (where the first rail is located) and the reference potential 112 (where the second rail is located). The voltage level of a detection node 103 may indicate an electrostatic discharge event. The detection node 103 may be a midpoint between the resistor 101 and the capacitor 102.

[0013] The voltage level at the detection node 103 can be used to control the clamping unit 130, which is configured to clamp, in particular, to limit the working potential 111 (i.e., the voltage level of the first rail) affected by the electrostatic discharge event. The clamping unit 130 includes a switching element, which is arranged between the working potential 111 (where the first rail is located) and the reference potential 112 (where the second rail is located), and is configured to provide a discharge path from the working potential 111 (i.e., from the first rail) to the reference potential 112 (i.e., to the second rail) for the electrostatic discharge charge when closed. The electrostatic discharge protection circuit 100 is generally designed so that the switch element of the clamping unit 130 is closed when an electrostatic discharge event is detected. On the other hand, when no electrostatic discharge event is detected, the switch element is generally kept in an open state. Therefore, a discharge path can be temporarily provided for a single electrostatic discharge event.

[0014] exist Figure 1 In the example shown, the clamping unit 130 includes a (NPN type) bipolar junction transistor (BJT) 107 as a switching element, wherein the use of the BJT 107 allows a particularly space-efficient clamping unit 130. Electrostatic discharge protection can be provided by the snap-back mechanism of the BJT 107.

[0015] The bipolar junction transistor 107 (which may be referred to as a main BJT) may be arranged in series and / or may be communal with another bipolar junction transistor 108 (which may be referred to as a cascode bipolar junction transistor 108). The cascode bipolar junction transistor 108 may be part of a silicon controlled rectifier (SCR), such as Figure 1 As an alternative or in addition, another NPN bipolar junction transistor 408 may be used, such as Figure 4 Alternatively, a PNP bipolar junction transistor 308 may be used, such as Figure 3 By composing another bipolar junction transistor 108, 308, 408 and the main bipolar junction transistor 107 in common source and gate, the leakage current of the clamping unit 130 can be reduced, thereby improving the energy efficiency of the electrostatic discharge protection circuit 100.

[0016] The main bipolar junction transistor 107 and the possible cascode bipolar junction transistors 108, 308, 408 are controlled according to the signal, in particular the voltage level, at the detection node 103. The control, in particular the triggering, of the main bipolar junction transistor 107 and the cascode bipolar junction transistors 108, 308, 408 is preferably synchronized, for example, so that the main bipolar junction transistor 107 and the possible cascode bipolar junction transistors 108, 308, 408 are closed substantially at the same time. The inverter unit 140 can be used to generate a control signal based on the voltage level at the detection node 103 for controlling the main bipolar junction transistor 107 and possibly for controlling the cascode bipolar junction transistors 108, 308, 408. The inverter unit 140 can be configured to provide a high-level control signal when the voltage level at the detection node 103 is low, and to provide a low-level control signal when the voltage level at the detection node 104 is high. In the example shown, the inverter unit 140 includes a PMOS transistor 104 and a resistor 105, which are arranged in series between an operating potential 111 (where the first rail is located) and a reference potential 112 (where the second rail is located). The control signal is provided at an intermediate node 106 between the PMOS transistor 104 and the resistor 105.

[0017] exist Figure 1 In the embodiment, the main bipolar junction transistor 107 and the cascode thyristor 108 are coupled to the intermediate node 106 , so that the main bipolar junction transistor 107 and the cascode thyristor 108 are closed according to the control signal provided at the intermediate node 106 of the inverter unit 140 . Figure 4The NPN bipolar junction transistor 408 is also coupled to the intermediate node 106 of the inverter unit 140, so that the cascode NPN bipolar junction transistor 408 can be closed according to the control signal provided at the intermediate node 106 of the inverter unit 140. Figure 3 In the example, the emitter and base of the PNP bipolar junction transistor 308 are coupled to the working potential 111, so that when the main bipolar junction transistor 107 is closed, the communal source and communal gate PNP bipolar junction transistor 308 can also be automatically closed.

[0018] Figure 2 The electrostatic discharge protection circuit 100 is shown, and in addition to the clamping unit 130 including the bipolar junction transistor 107, the circuit also includes a MOS (metal oxide semiconductor) based clamping unit 230. The clamping unit 230 includes an NMOS (N-channel metal oxide semiconductor) transistor 207 as a switching element, which is used to provide a second discharge path between the working potential 111 (where the first rail is located) and the reference potential 112 (where the second rail is located). For example, using an inverter unit 140, a control signal for controlling the NMOS transistor 207 is generated based on the voltage level at the detection node 103 of the detection unit 120. Figure 2 In the example shown, two additional inverter units having resistors 201 , 206 and MOS transistors 202 , 204 are used to generate a control signal for controlling the main bipolar junction transistor 107 based on a control signal at the intermediate node 106 of the inverter unit 140 , thereby providing a control signal for controlling the main bipolar junction transistor 107 at the node 206 .

[0019] In other words, an active ESD clamp 100 based on RC-triggered snap-back is described, which combines a synchronously triggered NPN transistor 107 with a thyristor 108 or a PNP transistor 308 or an NPN transistor 408 cascode, which are used as stacked discharge elements. Therefore, a space-efficient and low-leakage ESD protection circuit 100 is provided. The ESD protection circuit 100 exhibits a relatively low trigger voltage and a relatively high holding voltage. The ESD protection circuit 100 can be used, for example, for 5.5V+ ESD protection in the context of USB applications.

[0020] Thus, an ESD protection circuit 100 is described that is configured to provide ESD protection between a first rail at an operating potential 111 and a second rail at a reference potential 112 (e.g., ground). The operating potential 111 may be between 2 V and 6 V, for example, the operating potential 111 is 5 V. The ESD protection circuit 100 may be configured to provide ESD protection for an integrated circuit operating between the first rail and the second rail.

[0021] The electrostatic discharge protection circuit 100 includes a detection unit 120, which is configured to detect an electrostatic discharge event between a first rail and a second rail. The detection unit 120 may include a resistor 101 and a capacitor 102 arranged in series between the first rail and the second rail. In other words, the detection unit 120 may include an RC circuit. The signal at the detection node 103 between the resistor 101 and the capacitor 102, in particular the voltage level, may indicate an electrostatic discharge event. Specifically, a sudden increase or decrease in the voltage level at the detection node 103 may indicate an electrostatic discharge event. The detection unit 120, in particular the RC circuit, may have a predetermined time constant, wherein the predetermined time constant may be used to set the duration of a time interval during which the electrostatic discharge protection circuit 100 provides a discharge path for an electrostatic discharge event.

[0022] In addition, the electrostatic discharge protection circuit 100 includes a clamping unit 130, which is configured to provide a discharge path between the first rail and the second rail in response to an electrostatic discharge event detected by the detection unit 120. Charge can be guided from the first rail to the second rail through the discharge path, thereby removing the charge caused by the electrostatic discharge event, thereby providing electrostatic discharge protection. The discharge path is usually only provided temporarily.

[0023] The clamping unit 130 includes a main bipolar junction transistor 107, which is communal with an additional bipolar junction transistor 108, 308, 408 for providing a discharge path. The main bipolar junction transistor 107 can be an NPN bipolar junction transistor. The main bipolar junction transistor 107 and the additional bipolar junction transistor 108, 308, 408 are preferably operated in a synchronous manner, in particular, closed and / or opened, to provide and / or interrupt the discharge path.

[0024] By utilizing the clamping unit 130 having the main BJT 107 communcated with the additional BJT 108 , 308 , 408 , a space-efficient ESD protection circuit 100 with relatively low leakage current may be provided.

[0025] The additional BJT 108 , 308 , 408 may be part of the SCR 108 , such that the main BJT 107 is commutated with the SCR 107 to provide a discharge path.

[0026] Alternatively or additionally, the additional bipolar junction transistor 108, 308, 408 may be a PNP bipolar junction transistor 308. The base of the PNP bipolar junction transistor 308 may be directly coupled to the emitter of the PNP bipolar junction transistor 308, so that the PNP bipolar junction transistor 308 is closed when the main bipolar junction transistor 107 is closed.

[0027] Alternatively or additionally, the additional bipolar junction transistor 108 , 308 , 408 may be an NPN bipolar junction transistor 408 .

[0028] The main bipolar junction transistor 107 and the additional bipolar junction transistor 108, 308, 408 may be arranged in series between a first rail at an operating potential 111 and a second rail at a reference potential 112. The main bipolar junction transistor 107, in particular the collector of the main bipolar junction transistor 107, may be directly coupled to the second rail. The additional bipolar junction transistor 108, 308, 408, in particular the emitter of the additional bipolar junction transistor 108, 308, 408, may be directly coupled to the first rail. Furthermore, the collector of the additional bipolar junction transistor 108, 308, 408, in particular the collector of the additional bipolar junction transistor 108, 308, 408, may be directly coupled to the main bipolar junction transistor 107, in particular the emitter of the main bipolar junction transistor 107.

[0029] The electrostatic discharge protection circuit 100 can be configured to close the main bipolar transistor 107 and the additional bipolar transistor 108, 308, 408 (in a synchronous manner) in response to the electrostatic discharge event detected by the detection unit 120 to provide a discharge path. In addition, the electrostatic discharge protection circuit 100 can be configured to open the main bipolar junction transistor 107 and the additional bipolar junction transistor 108, 308, 408 (in a synchronous manner) after a certain duration has passed since the moment when the electrostatic discharge event is detected to interrupt the discharge path. Therefore, particularly effective and reliable electrostatic discharge protection can be provided.

[0030] As described above, the detection unit 120 can be configured to cause the signal at the detection node 103, in particular the voltage level, to change when an electrostatic discharge event occurs. The electrostatic discharge protection circuit 100 can be configured to generate a control signal for controlling the main bipolar junction transistor 107 and / or the additional bipolar junction transistor 108, 308, 408 based on the signal at the detection node 103, in particular based on the voltage level. To this end, the electrostatic discharge protection circuit 100 may include an inverter unit 140, which is configured to generate a control signal based on the signal at the detection node 103, in particular the voltage level. In this way, particularly effective and reliable electrostatic discharge protection can be provided.

[0031] The electrostatic discharge protection circuit 100 may include a second clamping unit 230, which is configured to provide a second discharge path between the first rail and the second rail in response to an electrostatic discharge event detected by the detection unit 120. The second clamping unit 230 may include a MOS transistor 207 for providing a second discharge path. Therefore, the electrostatic discharge protection circuit 100 may include a plurality of clamping units 130, 230, thereby further improving the reliability of electrostatic discharge protection. In addition, the latch immunity of the electrostatic discharge protection circuit 100 may be improved.

[0032] The electrostatic discharge protection circuit 100 may include one or more first inverter units, which are used to generate a control signal for controlling the main bipolar junction transistor 107 based on the signal at the detection node 103. In addition, the electrostatic discharge protection circuit 100 may include a second inverter unit 140, which is used to generate a control signal for controlling the MOS transistor 207 based on the signal at the detection node 103.

[0033] The one or more first inverter units may be configured to generate a control signal for controlling the main bipolar junction transistor 107 based on a control signal for controlling the MOS transistor 207 provided by the second inverter unit 140. Alternatively, the second inverter unit 140 may be configured to generate a control signal for controlling the MOS transistor 207 based on a control signal for controlling the main bipolar junction transistor 107 generated by the one or more first inverter units. Therefore, the plurality of clamping units 130, 230 may be efficiently and reliably controlled.

[0034] Furthermore, an integrated circuit is described, the integrated circuit comprising a circuit having, for example, one or more MOS transistors. The integrated circuit comprises an electrostatic discharge protection circuit 100 as described herein for protecting the circuit.

[0035] It should be noted that the description and drawings illustrate only the principles of the proposed system. Those skilled in the art will be able to implement various arrangements that, although not explicitly described or shown herein, embody the principles of the present invention and are included within the spirit and scope of the present invention. In addition, all examples and embodiments outlined herein are primarily for explanatory purposes only to help the reader understand the principles of the proposed method and system. In addition, all statements of the principles, aspects, and embodiments of the present invention and specific examples thereof provided herein are intended to encompass their equivalents.

Claims

1. An electrostatic discharge protection circuit, the electrostatic discharge protection circuit being configured to provide electrostatic discharge protection between a first rail at an operating potential and a second rail at a reference potential; The electrostatic discharge protection circuit comprises: a detection unit configured to detect an electrostatic discharge event between the first rail and the second rail; and a clamping unit configured to provide a discharge path between the first rail and the second rail in response to an electrostatic discharge event detected by the detection unit; The clamping unit includes a main bipolar junction transistor with a common source and gate with an additional bipolar junction transistor to provide the discharge path.

2. The electrostatic discharge protection circuit according to claim 1, wherein the additional bipolar junction transistor is a part of a silicon controlled rectifier, so that the main bipolar junction transistor and the silicon controlled rectifier are communicated to provide the discharge path. 3 . The ESD protection circuit of claim 1 , wherein the additional bipolar junction transistor is a PNP bipolar junction transistor. 4 . The electrostatic discharge protection circuit according to claim 3 , wherein the base of the PNP type bipolar junction transistor is directly coupled to the emitter of the PNP type bipolar junction transistor. 5 . The ESD protection circuit of claim 1 , wherein the additional bipolar junction transistor is an NPN bipolar junction transistor. 6 . The ESD protection circuit according to claim 1 , wherein the main bipolar junction transistor is an NPN type bipolar junction transistor.

7. The electrostatic discharge protection circuit according to claim 1, wherein: The main bipolar junction transistor and the additional bipolar junction transistor are arranged in series between the first rail at the operating potential and the second rail at the reference potential; and The electrostatic discharge protection circuit is configured to close the main bipolar junction transistor and the additional bipolar junction transistor to provide the discharge path in response to an electrostatic discharge event detected by the detection unit.

8. The electrostatic discharge protection circuit according to claim 1, wherein: The detection unit includes a detection node; The detection unit is configured to cause the signal at the detection node to change when an electrostatic discharge event occurs; and The electrostatic discharge protection circuit is configured to generate a control signal for controlling the main bipolar junction transistor and the additional bipolar junction transistor based on the signal at the detection node. 9 . The ESD protection circuit according to claim 8 , wherein the ESD protection circuit comprises an inverter unit configured to generate the control signal according to the signal at the detection node.

10. The electrostatic discharge protection circuit according to claim 1, wherein: The electrostatic discharge protection circuit includes a second clamping unit configured to provide a second discharge path between the first rail and the second rail in response to an electrostatic discharge event detected by the detection unit; as well as The second clamping unit includes a MOS transistor for providing the second discharge path.

11. The electrostatic discharge protection circuit according to claim 10, wherein: The detection unit is configured to provide a signal indicating an electrostatic discharge event at a detection node; The electrostatic discharge protection circuit includes one or more first inverter units, the first inverter unit is used to generate a control signal for controlling the main bipolar junction transistor based on the signal at the detection node; and The electrostatic discharge protection circuit includes a second inverter unit for generating a control signal for controlling the MOS transistor based on the signal at the detection node.

12. The electrostatic discharge protection circuit according to claim 11, wherein: The one or more first inverter units are configured to generate the control signal for controlling the main bipolar junction transistor based on the control signal for controlling the MOS transistor provided by the second inverter unit; or The second inverter unit is configured to generate the control signal for controlling the MOS transistor based on the control signal for controlling the main bipolar junction transistor generated by the one or more first inverter units.

13. The electrostatic discharge protection circuit according to claim 1, wherein: The detection unit includes a resistor and a capacitor arranged in series between the first rail and the second rail; and A signal at a sense node between the resistor and the capacitor is indicative of an electrostatic discharge event.

14. An integrated circuit comprising: A circuit having one or more MOS transistors; as well as The electrostatic discharge protection circuit according to claim 1, wherein the electrostatic discharge protection circuit is configured to protect the circuit using the one or more MOS transistors.

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