Manufacturing method of back-contact battery, back-contact battery and battery module thereof

Abstract

The present invention belongs to the technical field of back-contact batteries, and particularly relates to a manufacturing method of a back-contact battery, the back-contact battery and a battery module thereof, comprising the following steps: S2, sequentially forming a first semiconductor layer and a mask layer on the back surface of a silicon wafer; S3, performing a first etching opening on the back surface obtained in S2 to form a second semiconductor opening region; S4, performing texturing cleaning; S5, sequentially forming a passivation layer and an antireflection layer on the front surface of the silicon wafer, and the antireflection layer contains carbon-doped silicon nitride; S6, then performing annealing oxidation to oxidize at least part of the antireflection layer; S7, removing the backside wrap-around plating layer, and then using an HF-containing solution to clean the second semiconductor opening region; the mass concentration of HF in the HF-containing solution is reduced to 0.1% - 2%; S8, depositing a second semiconductor layer on the back surface. The present invention can ensure the stability of the battery manufacturing process and reduce the solution cost; meanwhile, it is beneficial to improve the passivation effect of the second semiconductor layer and enhance the battery efficiency.

Description

Technical Field

[0001] The present invention belongs to the technical field of back-contact batteries, and particularly relates to a manufacturing method of a back-contact battery, the back-contact battery, and a battery module thereof. Background Art

[0002] In the existing post-texturing process of back-contact batteries, a first semiconductor layer is formed on a silicon wafer, then openings are formed to form a second semiconductor opening region, and then texturing and cleaning are performed. Subsequently, a passivation layer and an anti-reflection layer are deposited on the front side of the silicon wafer. After the passivation layer and the anti-reflection layer are formed on the front side of the silicon wafer, there will be a certain amount of overplating on the back side, which needs to be cleaned by wet chemistry to make the surface of the second semiconductor opening region free of overplating and residual damage layers caused by laser scribing. At the same time, it is necessary to prevent the first semiconductor layer from being damaged by solution corrosion in the cleaning solution. Therefore, it is required that the corrosiveness of the wet chemical cleaning solution is not too weak, otherwise the second semiconductor opening region cannot be cleaned thoroughly, nor too strong, otherwise the first semiconductor layer is easily damaged during the cleaning process, resulting in the passivation and conductivity performance being affected. In short, there is currently a problem that the instability of cleaning leads to the instability of the battery manufacturing process and the inability to balance the battery efficiency.

[0003] CN118658933A discloses a preparation method of a back-contact battery, which performs oxygen annealing after depositing the passivation layer, then cleans the generated overplating, and then deposits the anti-reflection layer. The oxygen annealing of the passivation layer in this method will cause the hydrogen in the amorphous silicon to overflow, resulting in poor passivation performance and unable to solve the above problem of the instability of the battery manufacturing process.

[0004] It should be noted that this part of the content of the present invention only provides the background technology related to the present invention, and does not necessarily constitute the prior art or the well-known technology. Summary of the Invention

[0005] The purpose of the present invention is to overcome the defect that the stability of the battery manufacturing process and the battery efficiency cannot be balanced in the existing post-texturing process of back-contact batteries, and to provide a manufacturing method of a back-contact battery, the back-contact battery, and a battery module thereof, which can ensure the stability of the battery manufacturing process, reduce the solution cost; at the same time, it is beneficial to improve the passivation effect of the second semiconductor layer and enhance the battery efficiency.

[0006] To achieve the above purpose, in the first aspect, the present invention provides a manufacturing method of a back-contact battery, including the following steps:

[0007] S1. Provide a silicon wafer;

[0008] S2. Sequentially form a first semiconductor layer and a mask layer on the back side of the silicon wafer;

[0009] S3. Perform a first etching opening on the back side obtained in S2 to form a second semiconductor opening region;

[0010] S4. Through texturing cleaning, form a textured surface at least on the second semiconductor opening region, and then perform or not perform the step of removing the mask layer;

[0011] S5. Sequentially form a passivation layer and an anti-reflection layer on the front side of the silicon wafer. The anti-reflection layer contains carbon-doped silicon nitride;

[0012] S6. Then perform annealing oxidation to at least oxidize part of the anti-reflection layer. During the annealing oxidation process, control the thickness D1 of the oxidized part of the carbon-doped silicon nitride contained in the anti-reflection layer to be 10%-60% of the total thickness D0 of the carbon-doped silicon nitride;

[0013] S7. Remove the backside overplating, and then use a solution containing HF to clean the second semiconductor opening region; the mass concentration of HF in the solution containing HF is reduced to 0.1%-2%;

[0014] S8. Deposit a second semiconductor layer on the backside.

[0015] In some preferred embodiments of the present invention, the oxygen doping concentration of the oxidized part of the carbon-doped silicon nitride in S6 is 1×10 20 cm -3 -9×10 21 cm -3 。

[0016] Preferably, the total thickness D0 of the carbon-doped silicon nitride is 30-80 nm, and / or the carbon doping concentration of the carbon-doped silicon nitride is 1×10 18 cm -3 -9×10 19 cm -3 。

[0017] In some preferred embodiments of the present invention, the anti-reflection layer in S5 further includes an inner film layer disposed between the passivation layer and the carbon-doped silicon nitride. The inner film layer is selected from silicon nitride and / or silicon oxynitride. Among them, the thickness of the silicon nitride is 50-100 nm, and / or the thickness ratio of the silicon nitride to the carbon-doped silicon nitride is 1:(0.3-1.6).

[0018] In some preferred embodiments of the present invention, the passivation layer in S5 includes at least one film layer selected from amorphous silicon, oxygen-doped amorphous silicon, phosphorus-doped amorphous silicon, silicon oxide, and aluminum oxide.

[0019] In some preferred embodiments of the present invention, the passivation layer in S5 includes a silicon oxide film layer and an aluminum oxide film layer deposited sequentially. The thickness of the silicon oxide film layer is 1-2 nm, and the thickness of the aluminum oxide film layer is 3-10 nm.

[0020] In some preferred embodiments of the present invention, the conditions for annealing oxidation in S6 include: introducing a mixed gas containing oxygen and a protective gas during annealing, and the volume flow ratio of oxygen to the protective gas in the mixed gas containing oxygen and the protective gas is (0.033 - 0.30):1, and the flow rate of the protective gas is 2000 - 90000 sccm.

[0021] In some preferred embodiments of the present invention, the conditions for annealing oxidation in S6 include: the annealing temperature is 700 - 950 °C, the annealing pressure is 100 - 800 mbar, and the annealing time is 15 - 80 min.

[0022] In some preferred embodiments of the present invention, the process of annealing oxidation in S6 includes: controlling the furnace inlet temperature to be 200 - 700 °C, introducing the protective gas to heat up during the process of rising from the furnace inlet temperature to the annealing temperature, and introducing the mixed gas containing oxygen and the protective gas when the temperature reaches the set annealing temperature.

[0023] In some preferred embodiments of the present invention, the second semiconductor layer is a stack of an intrinsic hydrogenated amorphous silicon layer and a second doped silicon layer, or a stack of a second tunneling silicon oxide layer and a second doped polysilicon layer.

[0024] In some preferred embodiments of the present invention, the first semiconductor layer includes a first tunneling silicon oxide layer and a first doped polysilicon layer.

[0025] In some preferred embodiments of the present invention, the second semiconductor layer is a stack of an intrinsic hydrogenated amorphous silicon layer and a second doped silicon layer, the thickness of the intrinsic hydrogenated amorphous silicon layer is thinned to 2 - 5 nm, and the thickness of the second doped silicon layer is thinned to 5 - 10 nm.

[0026] In some preferred embodiments of the present invention, the deposition temperature of the second semiconductor layer is 150 - 250 °C.

[0027] In some preferred embodiments of the present invention, the conditions for cleaning in S7 include: the treatment temperature is 20 °C - 30 °C, and the cleaning time is 30 - 300 s.

[0028] In some preferred embodiments of the present invention, the manufacturing method of the back contact battery further includes:

[0029] S9. Perform a second etching opening on a part of the second semiconductor layer on the back of the silicon wafer to form a first semiconductor opening area arranged at intervals with the second semiconductor opening area;

[0030] S10. Deposit a conductive film layer on the back obtained in S9;

[0031] S11. Perform a third etching opening on the partial conductive film layer located between the first semiconductor opening region and the second semiconductor opening region to form an isolation groove;

[0032] S12. Form metal electrodes on the outer surfaces of the corresponding conductive film layers in the regions where the first semiconductor opening region and the second semiconductor opening region are located, respectively.

[0033] In a second aspect, the present invention provides a back contact battery, which is obtained by the manufacturing method of the back contact battery described in the first aspect. The back contact battery includes a silicon wafer and a passivation layer and an antireflection layer sequentially provided on the front surface of the silicon wafer. The antireflection layer contains carbon-doped silicon nitride. At least part of the carbon-doped silicon nitride contained in the antireflection layer is doped with oxygen, and the thickness D1 of the oxygen-doped part is 10%-60% of the total thickness D0 of the carbon-doped silicon nitride. The oxygen doping concentration of the oxygen-doped part of the carbon-doped silicon nitride is 1×10 20 cm -3 -9×10 21 cm -3 .

[0034] In a third aspect, the present invention provides a battery module, including the back contact battery described in the second aspect.

[0035] Advantageous effects:

[0036] Through the above technical solutions, especially by performing appropriate partial annealing oxidation on the carbon-doped silicon nitride of the antireflection layer, the present invention not only improves the corrosion resistance of the front antireflection layer in subsequent cleaning solutions and the like, but also the wrap-around coating in the second semiconductor opening area on the back and the local velvet peak body silicon in this opening area will undergo oxidation reactions during the annealing oxidation process, enabling the concentration of the cleaning solution for S7 to be reduced (the HF mass concentration is reduced by 60%-98% compared with the existing process) and the corrosion destructiveness to be significantly reduced, thereby avoiding damage to the first semiconductor layer in the cleaning solution, ensuring the stability of the battery manufacturing process, and reducing the solution cost. At the same time, the local velvet peak body silicon in the second semiconductor opening area is oxidized in the oxygen during the annealing oxidation to form an oxide layer. In the subsequent cleaning solution, the oxide layer will be quickly removed. After removal, the pyramid velvet surface in the second semiconductor opening area will be more rounded and the interface state will be cleaner, which is beneficial to improving the passivation effect of the second semiconductor layer and enhancing the battery efficiency. Compared with the process of oxygen annealing the passivation layer on the front in the prior art, the present invention performs appropriate partial annealing oxidation on the carbon-doped silicon nitride of the antireflection layer, enabling hydrogen ions in the antireflection layer to enter the interface between the passivation layer and the silicon wafer, further repairing the dangling bonds at the interface and improving the passivation level of the front film layer. At the same time, during the annealing process, part of the carbon-doped silicon nitride is oxidized and there are unoxidized parts and oxidized parts. The corrosion rates are quite different. After oxidation, the corrosion rate of the oxidized part will be significantly accelerated. Retaining a certain unoxidized layer can resist solution corrosion, improve the corrosion resistance of the unoxidized part in the antireflection layer, improve its anti-corrosion performance in the solution, and is beneficial to improving the performance of the battery and the stability of the manufacturing process. Under the same conditions, if the carbon-doped silicon nitride is replaced by silicon nitride or silicon oxynitride, considering the light absorption effect, the refractive index of the outer silicon nitride or silicon oxynitride is smaller, and the difference in corrosion rate between the oxidized and unoxidized parts is not obvious, and they are both easily corroded, so it is not easy to control the retained thickness and cannot resist solution corrosion.

[0037] Among them, the present invention specifically controls the thickness D1 of the oxidized part of the carbon-doped silicon nitride contained in the antireflection layer to be 10%-60% of the total thickness D0 of the carbon-doped silicon nitride, which is beneficial to the full oxidation of the second semiconductor opening area on the back, and thus beneficial to improving the passivation effect of the second semiconductor layer. At the same time, during the subsequent cleaning process, at least part of the carbon-doped silicon nitride of the front antireflection layer can be retained to play the best antireflection role, thereby enhancing the battery efficiency.

[0038] In the preferred embodiment of the present invention, the second semiconductor layer is a stack of an intrinsic hydrogenated amorphous silicon layer and a second doped silicon layer. Since the second semiconductor opening area has a good rounded velvet surface effect and a clean state after oxidation, which is beneficial to the passivation of the intrinsic hydrogenated amorphous silicon layer, the film thickness of the second semiconductor layer can be reduced by 10%-20% compared with the prior art, which is beneficial to reducing the parasitic absorption of the second semiconductor layer and beneficial to increasing the current density of the battery. Description of the Drawings

[0039] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for the embodiments will be briefly introduced below. It should be understood that the following accompanying drawings only show some embodiments of the present invention, and therefore should not be regarded as a limitation of the scope. For those of ordinary skill in the art, without creative efforts, other related accompanying drawings can also be obtained based on these drawings.

[0040] Figure 1 It is a schematic structural diagram of a specific implementation manner of the back-contact battery of the present invention.

[0041] Figure 2 It is a SEM image of the sharp surface of the backside pyramid texture without oxidation in an embodiment of the present invention.

[0042] Figure 3 It is a SEM image of the rounded surface of the backside pyramid texture after annealing oxidation in an embodiment of the present invention.

[0043] Explanation of the reference numerals

[0044] Silicon wafer 1, first tunneling oxide layer 2, N-type doped polysilicon layer 3, passivation layer 5, silicon nitride 6.1, carbon-doped silicon nitride 6.2, intrinsic hydrogenated amorphous silicon layer 7, P-type doped amorphous silicon layer 8, transparent conductive film layer 9, metal electrode 10. Second semiconductor opening region W2, first semiconductor opening region W1, isolation groove W3. Specific implementation manner

[0045] In the present invention, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "a plurality" means two or more, unless otherwise specifically defined.

[0046] In the present invention, unless otherwise clearly specified and defined, the first feature being "on" or "under" the second feature may be that the first and second features are in direct contact, or the first and second features are indirectly in contact through an intermediate medium. Moreover, the first feature being "above", "over" and "on top of" the second feature may be that the first feature is directly above or obliquely above the second feature, or merely indicates that the first feature has a higher horizontal height than the second feature. The first feature being "under", "below" and "beneath" the second feature may be that the first feature is directly below or obliquely below the second feature, or merely indicates that the first feature has a lower horizontal height than the second feature.

[0047] The endpoints and any values ​​of the ranges disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges. For numerical ranges, the endpoint values ​​of each range, the endpoint values ​​of each range and the individual point values, and the individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed in this article. Among them, the terms "optional" and "optional" all mean that they may be included or not included (or may be present or not).

[0048] In the present invention, the area close to the silicon wafer is referred to as the inside, and the area far from the silicon wafer is referred to as the outside.

[0049] In a first aspect, the present invention provides a method for manufacturing a back contact battery, comprising the following steps:

[0050] S1, provide silicon wafers;

[0051] S2, forming a first semiconductor layer and a mask layer in sequence on the back side of the silicon wafer;

[0052] S3, performing a first etching opening on the back surface obtained in S2 to form a second semiconductor opening region;

[0053] S4, forming a texture surface at least on the second semiconductor opening region by texturing and cleaning, and then performing or not performing a step of removing the mask layer;

[0054] S5, forming a passivation layer and an anti-reflection layer in sequence on the front side of the silicon wafer; the anti-reflection layer comprises carbon-doped silicon nitride;

[0055] S6, then performing annealing oxidation to oxidize at least part of the anti-reflection layer, and during the annealing oxidation process, controlling the thickness D1 of the oxidized portion of the carbon-doped silicon nitride contained in the anti-reflection layer to be 10%-60% of the total thickness D0 of the carbon-doped silicon nitride;

[0056] S7, removing the back side coating, and then using a HF-containing solution to clean the second semiconductor opening region; the mass concentration of HF in the HF-containing solution is reduced to 0.1%-2%;

[0057] S8. Depositing a second semiconductor layer on the back side.

[0058] During the annealing oxidation process, the thickness D1 of the oxidized portion of the carbon-doped silicon nitride contained in the antireflection layer is 10% - 60% of the total thickness D0 of the carbon-doped silicon nitride. For example, specifically, it can be 10%, 11%, 12%, 13%, 14%, 15%, 16%, 17%, 18%, 19%, 20%, 21%, 22%, 25%, 27%, 30%, 32%, 35%, 37%, 40%, 42%, 45%, 48%, 50%, 52%, 55%, 58%, 59%, 60% and the range between any two point values. In some specific embodiments, 10% - 55% can be preferably selected, and further preferably 18% - 55%.

[0059] In the present invention, the thickness of the oxidized portion of the carbon-doped silicon nitride contained in the antireflection layer is obtained by testing the change in thickness of the film layer before and after etching in the HF solution at S7.

[0060] The mass concentration of HF in the HF-containing solution is reduced to 0.1% - 2%. For example, specifically, it can be 0.1%, 0.2%, 0.5%, 0.7%, 1.0%, 1.2%, 1.5%, 1.7%, 1.9%, 2% and the range between any two point values.

[0061] In S4 of the present invention, the texturing cleaning can also form a textured surface on the front side of the silicon wafer. In S4, the mask layer can be removed or not removed, which can be selected according to actual needs. The method for removing the mask layer can refer to the prior art and will not be elaborated here.

[0062] In the present invention, the carbon-doped silicon nitride is the corresponding film layer of the outermost layer of the antireflection layer. The total thickness of the carbon-doped silicon nitride refers to the thickness of the carbon-doped silicon nitride formed in S5.

[0063] Preferably, in the present invention, the oxygen doping concentration of the oxidized portion of the carbon-doped silicon nitride is 1×10 20 cm -3 -9×10 21 cm -3 . Using a part of the carbon-doped silicon nitride with an appropriate oxygen doping concentration is more conducive to ensuring sufficient oxygen content and fully oxidizing both the front and back sides.

[0064] Further preferably, the total thickness D0 of the carbon-doped silicon nitride is 30 - 80 nm. For example, specifically, it can be 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm and the range between any two point values. For example, 30 - 70 nm can be preferably selected.

[0065] Preferably, in the present invention, the carbon doping concentration of the carbon-doped silicon nitride is 1×10 18 cm -3 -9×10 19 cm-3 。

[0066] The present invention uses carbon-doped silicon nitride with an appropriate thickness and / or an appropriate carbon doping concentration, which is more conducive to taking into account corrosion resistance and optical properties.

[0067] In some preferred embodiments of the present invention, the antireflection layer in S5 further includes an inner film layer disposed between the passivation layer and the carbon-doped silicon nitride, and the inner film layer is selected from silicon nitride and / or silicon oxynitride. The inner film layer can be a single film layer or a stacked layer including silicon nitride and silicon oxynitride.

[0068] Further preferably, the thickness of the inner film layer is 50-100 nm.

[0069] Further preferably, the thickness ratio of the inner film layer to the carbon-doped silicon nitride is 1:(0.3-1.6), preferably 1:(0.3-1.2). Using a combination of silicon nitride and carbon-doped silicon nitride with an appropriate thickness ratio as the antireflection layer is more conducive to increasing the current density of the battery.

[0070] In some preferred embodiments of the present invention, the passivation layer in S5 includes at least one film layer selected from amorphous silicon, oxygen-doped amorphous silicon, phosphorus-doped amorphous silicon, silicon oxide, and aluminum oxide.

[0071] In some preferred embodiments of the present invention, the passivation layer in S5 includes a silicon oxide film layer and an aluminum oxide film layer deposited in sequence. Further preferably, the thickness of the silicon oxide film layer is 1-2 nm, and the thickness of the aluminum oxide film layer is 3-10 nm. Using the combination of the preferred silicon oxide film layer and aluminum oxide film layer of the present invention as the passivation layer is more conducive to improving the passivation level of the battery.

[0072] In some preferred embodiments of the present invention, the conditions for annealing oxidation in S6 include: introducing a mixed gas containing oxygen and a protective gas during annealing, and the volume flow ratio of oxygen to the protective gas in the mixed gas containing oxygen and the protective gas is (0.033-0.30):1, preferably (0.10-0.30):1. Using an appropriate low flow ratio of oxygen and the protective gas is more conducive to controlling the uniformity of annealing and oxidation.

[0073] Further preferably, the flow rate of the protective gas is 2000-90000 sccm. The protective gas can be an inert gas such as argon or helium, or a non-reactive protective gas such as nitrogen.

[0074] In some preferred embodiments of the present invention, the conditions for annealing oxidation in S6 include: the annealing temperature is 700-950 °C, and the annealing time is 15-80 min.

[0075] In some preferred embodiments of the present invention, the conditions for annealing oxidation in S6 include: the pressure for annealing is 100 - 800 mbar.

[0076] In some preferred embodiments of the present invention, the process of annealing oxidation in S6 includes: controlling the furnace inlet temperature to be 200 - 700 °C. During the process of rising from the furnace inlet temperature to the annealing temperature, a protective gas is introduced for heating. When the temperature reaches the set annealing temperature, a mixed gas containing oxygen and the protective gas is then introduced. The furnace inlet temperature refers to the temperature of the furnace body when entering the furnace.

[0077] In some preferred embodiments of the present invention, the second semiconductor layer is a stack of an intrinsic hydrogenated amorphous silicon layer and a second doped silicon layer, or a stack of a second tunneling silicon oxide layer and a second doped polysilicon layer. The thickness of the second doped polysilicon layer can be, for example, 10 - 90 nm.

[0078] In some preferred embodiments of the present invention, the first semiconductor layer includes a first tunneling silicon oxide layer and a first doped polysilicon layer. The thicknesses and corresponding doping concentrations of the first tunneling silicon oxide layer and the first doped polysilicon layer can respectively refer to the corresponding ranges of the prior art and can all be used in the present invention. Exemplarily, the thickness of the first tunneling silicon oxide layer is 1 - 2 nm, the thickness of the first doped polysilicon layer is 80 - 150 nm, and the effective doping concentration is 1×10 19 cm -3 -9×10 20 cm -3 。

[0079] In the first doped polysilicon layer and the second doped silicon layer or the second doped polysilicon layer in the second semiconductor layer, one is N-type and the other is P-type. The second doped silicon layer can be, for example, doped amorphous silicon or microcrystalline silicon. The effective doping concentration of the second doped silicon layer or the second doped polysilicon layer can refer to the range of the prior art. For example, the effective doping concentration can be 1×10 18 cm -3 -9×10 19 cm -3 。

[0080] In the present invention, the thickness of the mask layer can be, for example, 50 - 100 nm, and the types of the mask layer can be at least one of silicon nitride, silicon oxide, silicon oxynitride, or nitrogen-containing polysilicon.

[0081] In some preferred embodiments of the present invention, the second semiconductor layer is a stack of an intrinsic hydrogenated amorphous silicon layer and a second doped silicon layer. Using a semiconductor layer with combined passivation, in combination with the manufacturing method of the present invention, is more conducive to improving the conversion efficiency of the battery.

[0082] Further preferably, the thickness of the intrinsic hydrogenated amorphous silicon layer is thinned to 2 - 5 nm, and the thickness of the second doped silicon layer is thinned to 5 - 10 nm. The present invention can ensure the battery efficiency and the stability of the battery manufacturing process while using a thinner second semiconductor layer, and at the same time reduce the parasitic absorption of the second semiconductor layer, which is beneficial to improving the current density of the battery.

[0083] The formation method of the second semiconductor layer can refer to the methods of the prior art. For example, it can be deposited by a plate CVD method, and all can be used in the present invention. In some preferred embodiments of the present invention, the deposition temperature of the second semiconductor layer is 150 - 250 °C. The present invention can deposit the second semiconductor layer at a lower temperature, which is more conducive to improving the passivation effect of the second semiconductor layer.

[0084] The method for removing the back wrap plating in the present invention S7 can refer to the prior art. For example, the back wrap plating can be removed using an HF acid solution, and the removal conditions are: the temperature is 20 - 50 °C, and the time is 15 - 300 s, as long as the target wrap plating can be removed.

[0085] In some preferred embodiments of the present invention, the cleaning conditions in S7 include: the treatment temperature is 20 °C - 30 °C, and the cleaning time is 30 - 300 s.

[0086] The manufacturing method of the present invention may further include other conventional steps. In some preferred embodiments of the present invention, the manufacturing method of the back contact battery further includes:

[0087] S9. Perform a second etching opening on a part of the second semiconductor layer on the back of the silicon wafer to form a first semiconductor opening area arranged at intervals with the second semiconductor opening area;

[0088] S10. Deposit a conductive film layer on the back obtained in S9;

[0089] S11. Perform a third etching opening on a part of the conductive film layer located between the first semiconductor opening area and the second semiconductor opening area to form an isolation groove;

[0090] S12. Form metal electrodes on the outer surfaces of the corresponding conductive film layers in the areas where the first semiconductor opening area and the second semiconductor opening area are located, respectively.

[0091] In a second aspect, the present invention provides a back contact battery, which is obtained by the manufacturing method of the back contact battery described in the first aspect.

[0092] The back-contact battery of the present invention includes a silicon wafer and a passivation layer and an antireflection layer sequentially disposed on the front surface of the silicon wafer. The antireflection layer contains carbon-doped silicon nitride. At least part of the carbon-doped silicon nitride contained in the antireflection layer is doped with oxygen, and the thickness D1 of the oxygen-doped part is 10%-60% of the total thickness D0 of the carbon-doped silicon nitride. The oxygen-doped antireflection layer of the present invention can reduce the concentration of the cleaning solution used for cleaning the second semiconductor opening area on the back surface during manufacturing (the HF mass concentration is reduced by 60%-98% compared with the existing process) and can greatly reduce the corrosive damage, thereby avoiding damage to the first semiconductor layer in the cleaning solution and ensuring high battery efficiency and the stability of its battery manufacturing process.

[0093] Preferably, the oxygen doping concentration of the oxygen-doped part of the carbon-doped silicon nitride is 1×10 20 cm -3 -9×10 21 cm -3 。

[0094] Preferably, the back-contact battery further includes a first semiconductor layer and a second semiconductor layer alternately disposed on the back surface of the silicon wafer. Both ends of the second semiconductor layer extend outward to cover part of the back surface of the adjacent first semiconductor layer, and a first semiconductor opening area that does not cover the second semiconductor layer is formed on the back surface of the first semiconductor layer. A second semiconductor opening area is formed between adjacent first semiconductor layers. The second semiconductor opening area and the first semiconductor opening area are arranged at intervals, and the area between them is an interval area; in the interval area, a mask layer is provided or not provided between the first semiconductor layer and the second semiconductor layer.

[0095] Preferably, the back-contact battery further includes a metal electrode and a conductive film layer laid on the outer surfaces of the first semiconductor layer and the second semiconductor layer. An isolation groove is formed in the part of the conductive film layer located in the interval area; the metal electrode is provided on the outer surfaces of the conductive film layers corresponding to the second semiconductor opening area and the first semiconductor opening area respectively.

[0096] In a third aspect, the present invention provides a battery assembly including the back-contact battery described in the second aspect. The battery assembly can be any form of assembly such as a battery module containing the back-contact battery of the present invention.

[0097] The embodiments of the present invention are described in detail below. They are exemplary and are only used to explain the present invention and should not be construed as a limitation to the present invention.

[0098] Example 1

[0099] A back-contact battery, as Figure 1 shown, its manufacturing method is specifically as follows:

[0100] S1. Double-side polishing and cleaning of the silicon wafer 1 (N-type single-crystalline silicon wafer);

[0101] S2. Form a first semiconductor layer and a mask layer on the back surface of the silicon wafer 1:

[0102] The first semiconductor layer includes a first tunneling oxide layer 2 and an N-type doped polysilicon layer 3 (i.e., the first doped polysilicon layer). The mask layer is silicon nitride with a thickness of 70 nm. The thickness of the first tunneling oxide layer 2 is 1.5 nm, the thickness of the N-type doped polysilicon layer 3 is 120 nm, and the effective doping concentration is 2×10 20 cm -3 .

[0103] S3. Etch an opening on the back surface of the silicon wafer 1 for the first time to form a second semiconductor opening region W2;

[0104] S4. Perform texturing cleaning on the front and back surfaces of the silicon wafer 1 in the second semiconductor opening region W2. During the texturing cleaning process, the mask layer on the back surface of the silicon wafer 1 is also removed by the final cleaning solution;

[0105] S5. Form a passivation layer 5 and an antireflection layer on the front surface of the silicon wafer 1 in sequence:

[0106] The passivation layer 5 is a combination of a sequentially deposited silicon oxide film layer and an aluminum oxide film layer. The thickness of the silicon oxide film layer is 1.5 nm, and the thickness of the aluminum oxide film layer is 6 nm;

[0107] The antireflection layer is a laminated combination of sequentially deposited silicon nitride 6.1 and carbon-doped silicon nitride 6.2. Among them, the thickness of the silicon nitride 6.1 is 60 nm, the thickness D0 of the carbon-doped silicon nitride 6.2 is 60 nm, and the carbon doping concentration is 5.6×10 19 cm -3 ; After conversion, the thickness ratio of the silicon nitride 6.1 to the carbon-doped silicon nitride 6.2 is 1:1.

[0108] S6. Then perform annealing oxidation:

[0109] The annealing temperature is 800 °C. The gas introduced during annealing is a mixed gas of oxygen and nitrogen containing oxygen and nitrogen. Among them, the oxygen-to-nitrogen flow ratio is 0.15:1, the nitrogen flow rate is 10000 sccm, and the annealing pressure is 500 mbar. The furnace inlet temperature during annealing is 600 °C. When rising from the furnace inlet temperature to the annealing temperature, nitrogen is introduced for heating. When the temperature reaches the set annealing temperature, a mixed gas of oxygen and nitrogen is introduced. The annealing time is 30 min. During annealing, control the thickness D1 of the oxidized part of the top-layer carbon-doped silicon nitride 6.2 on the front surface to be 20% of the total thickness D0 of the top-layer carbon-doped silicon nitride 6.2. The oxygen doping concentration of the oxidized part of the top-layer carbon-doped silicon nitride 6.2 is 1.3×10 20 cm -3 . After annealing oxidation, the texture of the second semiconductor opening region W2 is as shown in Figure 3 shown, compared with the unoxidizedFigure 2 , more rounded;

[0110] S7. Remove the backside wrap plating layer, and then clean the second semiconductor opening region W2; wherein, the second semiconductor opening region W2 is cleaned with an HF solution, the mass concentration of HF in the HF solution is 2%, the balance is deionized water, the treatment temperature is 25°C, and the cleaning time is 100 s;

[0111] S8. Deposit a second semiconductor layer on the backside of the silicon wafer 1 by plate CVD, and the deposition temperature is 230°C; the second semiconductor layer is a stack of an intrinsic hydrogenated amorphous silicon layer 7 and a P-type doped amorphous silicon layer 8 (i.e., the second doped silicon layer). The thickness of the intrinsic hydrogenated amorphous silicon layer 7 is 5 nm, the thickness of the P-type doped amorphous silicon layer 8 is 10 nm, and the effective doping concentration is 1.4×10 19 cm -3 .

[0112] S9. Perform a second etching opening on the second semiconductor layer on the backside of the silicon wafer 1 to form a first semiconductor opening region W1;

[0113] S10. Deposit a transparent conductive film layer 9 (ITO) on the backside of the silicon wafer 1;

[0114] S11. Perform a third etching opening on the transparent conductive film layer 9 on the backside of the silicon wafer 1 to form an isolation groove W3; after etching, the resistance between the first semiconductor and the second semiconductor is greater than 1 kΩ.

[0115] S12. Form metal electrodes 10 on the corresponding outer surfaces at the first semiconductor opening region W1 and the second semiconductor opening region W2 on the backside of the silicon wafer 1.

[0116] Example 2

[0117] Refer to Example 1, the difference is that during the annealing oxidation process of S6, the thickness D1 of the oxidized part of the carbon-doped silicon nitride contained in the antireflection layer is controlled such that the thickness D1 is 60% of the total thickness D0 of the carbon-doped silicon nitride. The process parameters that need to be adjusted to meet this condition are: extend the annealing oxidation time to 65 min.

[0118] Example 3

[0119] Refer to Example 1, the difference is that the total deposition thickness D0 of the carbon-doped silicon nitride in S5 is adjusted to 80 nm, and the thickness of its oxidized part remains unchanged. After calculation, the thickness ratio of silicon nitride to carbon-doped silicon nitride is 1:1.33. The process parameters that need to be adjusted to meet this thickness condition are: extend the coating time by 25%.

[0120] Example 4

[0121] Performed with reference to Example 1, except that the flow rate of methane during the S5 carbon-doped silicon nitride deposition was adjusted so that the carbon doping concentration was 8.2×10 19 cm -3 .

[0122] Example 5

[0123] Performed with reference to Example 1, except that the oxygen flow rate during the annealing oxidation was adjusted so that the volume flow ratio of oxygen to nitrogen was 0.09:1. In this case, during the annealing oxidation process, the thickness D1 of the oxidized portion of the carbon-doped silicon nitride contained in the antireflection layer was controlled so that the thickness D1 was 12% of the total thickness D0 of the carbon-doped silicon nitride, and the oxygen doping concentration of the oxidized portion of the carbon-doped silicon nitride was 1.3×10 20 cm -3 .

[0124] Example 6

[0125] Performed with reference to Example 1, except that the second semiconductor layer was adjusted to a stack of a second tunneling silicon oxide layer with a thickness of 1.2 nm and a P-type doped polysilicon layer with a thickness of 50 nm and a boron doping concentration of 1.9×10 19 cm -3 .

[0126] Comparative Example 1

[0127] Performed with reference to Example 1, except that the annealing oxidation of S6 was not performed, and the unoxidized matte surface in the second semiconductor opening region was as Figure 2 shown; and the mass concentration of HF in the HF-containing solution in S7 was 10%.

[0128] Comparative Example 2

[0129] Performed with reference to Example 1, except that during the annealing oxidation of S6, the thickness D1 of the oxidized portion of the carbon-doped silicon nitride contained in the antireflection layer was controlled to be 85% of the total thickness D0 of the carbon-doped silicon nitride. The process parameters that needed to be adjusted to meet this condition were: extending the oxidation time to 122 min.

[0130] Comparative Example 3

[0131] Performed with reference to Example 1, except that the timing of introducing the annealing oxidation was different. Specifically, the annealing oxidation of S6 was performed after forming the passivation layer, and then the antireflection layer was deposited.

[0132] Test Example

[0133] The back-contact batteries obtained from the above-mentioned examples and comparative examples were subjected to performance tests, and the results are shown in Table 1. Among them, each performance index of each example and comparative example was converted with Example 1 as the reference benchmark. The data of Example 1 was the normalization benchmark of 1.000, and other examples were converted based on Example 1. For example, the anti-reflection layer thickness uniformity of Comparative Example 1 / the anti-reflection layer thickness uniformity of Example 1 was 3.619. Among them, the test method for the anti-reflection layer thickness uniformity was: the film thickness at 5 locations (a total of five locations including the four locations around the silicon wafer and the center) of any silicon wafer was measured by an ellipsometer. The test value of the uniformity = (the maximum film thickness - the minimum film thickness) / (the maximum film thickness + the minimum film thickness). The smaller the test value of the anti-reflection layer thickness uniformity, the better its uniformity and the more stable the battery manufacturing process.

[0134] Table 1

[0135]

[0136] From the above results, it can be seen that compared with the comparative examples, by adopting the example scheme of the present invention, an anti-reflection layer with more uniform thickness can be obtained, which is beneficial to ensuring the stability of the battery manufacturing process and reducing the solution cost; at the same time, it is beneficial to improving the passivation effect of the second semiconductor layer and enhancing the battery efficiency.

[0137] Furthermore, according to Example 1 and Examples 2-6, it can be seen that by adopting the preferred scheme of the present invention, it is more beneficial to improve the battery efficiency and the stability of its battery manufacturing process.

[0138] The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited thereto. Within the technical concept scope of the present invention, various simple modifications can be made to the technical solutions of the present invention, including any other suitable combination of each technical feature. These simple modifications and combinations should also be regarded as the content disclosed by the present invention and fall within the protection scope of the present invention.

Claims

1. A method for manufacturing a back contact battery, characterized in that: The steps include: S1, provide silicon wafer; S2, forming a first semiconductor layer and a mask layer in sequence on the back side of the silicon wafer; S3, performing a first etching opening on the back surface obtained in S2 to form a second semiconductor opening region; S4, forming a texture surface at least on the second semiconductor opening region by texturing and cleaning, and then performing or not performing a step of removing the mask layer; S5, forming a passivation layer and an anti-reflection layer on the front side of the silicon wafer in sequence, wherein the anti-reflection layer comprises carbon-doped silicon nitride; in S5, the anti-reflection layer further comprises an inner film layer disposed between the passivation layer and the carbon-doped silicon nitride, wherein the inner film layer is selected from silicon nitride and / or silicon oxynitride; S6, then performing annealing oxidation to oxidize at least part of the anti-reflection layer, during which the thickness D1 of the oxidized portion of the carbon-doped silicon nitride contained in the anti-reflection layer is controlled to be 10%-60% of the total thickness D0 of the carbon-doped silicon nitride; the annealing oxidation conditions in S6 include: an annealing temperature of 700-950° C., an annealing pressure of 100-800 mbar, and an annealing time of 15-80 min; S7, removing the back side coating, and then using a HF-containing solution to clean the second semiconductor opening region; the mass concentration of HF in the HF-containing solution is reduced to 0.1%-2%; S8. Depositing a second semiconductor layer on the back side.

2. The method for manufacturing a back contact battery according to claim 1, characterized in that: The oxygen doping concentration of the oxidized part of the carbon-doped silicon nitride in S6 is 1×10 20 cm -3 -9×10 21 cm -3 and / or, The total thickness D0 of the carbon-doped silicon nitride in S5 is 30-80 nm; and / or, The carbon doping concentration of carbon-doped silicon nitride in S5 is 1×10 18 cm -3 -9×10 19 cm -3 .

3. The method for manufacturing a back contact battery according to claim 1, characterized in that: The thickness of the inner film layer is 50-100 nm, and / or the ratio of the thickness of the inner film layer to that of the carbon-doped silicon nitride is 1:(0.3-1.6).

4. The method for manufacturing a back contact battery according to any one of claims 1 to 3, characterized in that: The passivation layer in S5 includes at least one film layer selected from amorphous silicon, oxygen-doped amorphous silicon, phosphorus-doped amorphous silicon, silicon oxide and aluminum oxide.

5. The method for manufacturing a back contact battery according to claim 4, characterized in that: The passivation layer in S5 includes a silicon oxide film layer and an aluminum oxide film layer deposited in sequence, wherein the thickness of the silicon oxide film layer is 1-2 nm, and the thickness of the aluminum oxide film layer is 3-10 nm.

6. The method for manufacturing a back contact battery according to any one of claims 1 to 3, characterized in that: The annealing oxidation conditions described in S6 include: introducing a mixed gas containing oxygen and protective gas during annealing, the volume flow ratio of oxygen to protective gas in the mixed gas containing oxygen and protective gas is (0.033-0.30):1, and the flow rate of the protective gas is 2000-90000sccm.

7. The method for manufacturing a back contact battery according to claim 1, characterized in that: The annealing and oxidation process in S6 includes: controlling the furnace temperature to be 200-700°C, introducing a protective gas to increase the temperature from the furnace temperature to the annealing temperature, and introducing a mixed gas containing oxygen and protective gas when the temperature reaches the set annealing temperature.

8. The method for manufacturing a back contact battery according to claim 1, characterized in that: The second semiconductor layer is a stack of an intrinsic hydrogenated amorphous silicon layer and a second doped silicon layer, or a stack of a second tunneling silicon oxide layer and a second doped polysilicon layer; And / or, the first semiconductor layer includes a first tunneling silicon oxide layer and a first doped polysilicon layer.

9. The method for manufacturing a back contact battery according to claim 8, characterized in that: The second semiconductor layer is a stack of an intrinsic hydrogenated amorphous silicon layer and a second doped silicon layer, the thickness of the intrinsic hydrogenated amorphous silicon layer is reduced to 2-5 nm, and the thickness of the second doped silicon layer is reduced to 5-10 nm; And / or, the deposition temperature of the second semiconductor layer is 150-250°C.

10. The method for manufacturing a back contact battery according to claim 1, characterized in that: The cleaning conditions in S7 include: a treatment temperature of 20°C-30°C and a cleaning time of 30-300s; And / or, the method for manufacturing a back contact battery further comprises: S9, performing a second etching opening on a portion of the second semiconductor layer on the back side of the silicon wafer to form a first semiconductor opening region spaced apart from the second semiconductor opening region; S10, depositing a conductive film layer on the back surface obtained in S9; S11, performing a third etching opening on a portion of the conductive film layer between the first semiconductor opening region and the second semiconductor opening region to form an isolation groove; S12, forming metal electrodes on the outer surfaces of the corresponding conductive film layers in the areas where the first semiconductor opening region and the second semiconductor opening region are located.

11. A back contact battery, characterized in that: The back contact cell is made by the manufacturing method of any one of claims 1 to 10, wherein the back contact cell comprises a silicon wafer and a passivation layer and an anti-reflection layer sequentially arranged on the front side of the silicon wafer, the anti-reflection layer comprises carbon-doped silicon nitride, the carbon-doped silicon nitride contained in the anti-reflection layer is at least partially doped with oxygen, and the thickness D1 of the oxygen-doped part is 10%-60% of the total thickness D0 of the carbon-doped silicon nitride, and the oxygen doping concentration of the oxygen-doped part of the carbon-doped silicon nitride is 1×10 20 cm -3 -9×10 21 cm -3 .

12. A battery assembly, characterized in that: Comprising a back contact cell as claimed in claim 11.

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