Patterned passivation contact solar cell and manufacturing method thereof

Abstract

The invention belongs to the technical field of crystalline silicon solar cells, and relates to a patterned passivation contact solar cell and a manufacturing method thereof.The patterned passivation contact solar cell comprises a substrate, a front passivation layer and a back passivation layer are arranged on the front face and the back face of the substrate respectively, front metal grid lines are arranged on the front face of the substrate, and back metal grid lines are arranged on the back face of the substrate; an ultra-thin tunneling oxide layer and a doped polycrystalline silicon layer are sequentially arranged between the substrate and the back metal grid lines, the doped polycrystalline silicon layer is connected with the back metal grid lines, the ultra-thin tunneling oxide layer and the doped polycrystalline silicon layer are the same in shape, and a blank area is further arranged between every two adjacent back metal grid lines. And the edge shape of the blank area is matched with the edge shape of the ultrathin tunneling oxide layer or the doped polycrystalline silicon layer. The passivation contact structure with the patterned back face is adopted, carrier recombination of a metal contact area can be reduced, and meanwhile good contact performance is achieved.

Description

[0001] This application is a divisional application for application number: CN202011184322.8 (name of invention: Patterned passivated contact solar cell and its manufacturing method, application date: October 29, 2020). Technical Field

[0002] The invention belongs to the technical field of crystalline silicon solar cells and relates to a patterned passivation contact solar cell and a manufacturing method thereof. Background Art

[0003] In crystalline silicon solar cells, the serious recombination in the metal and semiconductor contact areas restricts the improvement of solar cell efficiency. Passivation contact technology is a technology that has significantly improved the photoelectric conversion efficiency of photovoltaic cells in recent years. The passivation contact (or contact passivation) structure is a structure formed by superimposing an ultra-thin tunneling oxide layer and a doped polysilicon layer on crystalline silicon, in which silicon oxide is used as a passivation layer and doped polysilicon is used as a carrier selective contact material, which can significantly reduce the carrier recombination in the metal contact area and has good contact performance, thereby greatly improving the efficiency of solar cells.

[0004] However, the inherent disadvantage of passivation contact technology is that the absorption coefficient of the doped polysilicon layer is large. If the entire surface is used on a crystalline silicon cell, it will result in a large current loss and cannot maximize the conversion efficiency of the solar cell. Therefore, the industry is currently studying the method of local passivation contact, which can take into account both passivation contact and light absorption. Summary of the invention

[0005] The object of the present invention is to provide a method for manufacturing a patterned passivation contact solar cell in view of the above problems.

[0006] Another object of the present invention is to provide a patterned passivated contact solar cell.

[0007] In order to achieve the above object, the present invention adopts the following technical solutions:

[0008] A method for manufacturing a patterned passivated contact solar cell, characterized by comprising the following steps:

[0009] A single crystal silicon wafer is subjected to texturing, diffusion bonding, etching and polishing or secondary processing to obtain a substrate, and an ultra-thin tunneling silicon oxide layer is simultaneously prepared on the front and back sides of the substrate;

[0010] A layer of amorphous silicon is further formed on the tunneling silicon oxide layer on the front and back sides of the substrate, or a layer of amorphous silicon is further formed only on the ultra-thin tunneling silicon oxide layer on the back side of the substrate;

[0011] A mask is deposited on the amorphous silicon layer, and a corrosion-resistant ink is printed on the mask on the back of the substrate. The mask in the area where the corrosion-resistant ink is not printed is then removed with hydrofluoric acid, and the ink is then removed with a mixed aqueous solution of ammonia and hydrogen peroxide;

[0012] The amorphous silicon layer in the non-mask protected area on the back side of the substrate and the amorphous silicon layer on the front side are removed, and then the tunnel oxide layer in the non-amorphous silicon area and the remaining mask are removed with hydrofluoric acid to obtain a process wafer;

[0013] The process wafer is subjected to boron diffusion or phosphorus diffusion at high temperature to activate the doping atoms and simultaneously convert all amorphous silicon into polysilicon to form a doped polysilicon layer;

[0014] A passivation layer is prepared on the front and back of the substrate respectively, and metal grid lines are printed. After screen printing and sintering, a finished solar cell is obtained.

[0015] Furthermore, the thickness of the tunneling silicon oxide layer does not exceed 2 nm, and the thickness of the amorphous silicon layer is 100-400 nm.

[0016] A method for manufacturing a patterned passivated contact solar cell comprises the following steps:

[0017] 1) Texturing: P-type or N-type single crystal silicon wafer is used as the substrate, placed in a texturing liquid to form a pyramid texture surface, and then the surface of the silicon wafer is cleaned in a hydrofluoric acid solution with a volume concentration of 1-10%;

[0018] 2) Diffusion junction: Phosphorus or boron is diffused on both sides of the textured silicon substrate to form a pn junction;

[0019] 3) Etching: Use single-sided etching equipment to remove the phosphosilicate glass layer or borosilicate glass layer on the back and edge of the substrate;

[0020] 4) Back polishing or secondary texturing: The back is polished or texturing is performed to remove the diffusion layer on the back and form a polished surface or a velvet surface, and then the phosphosilicate glass layer or borosilicate glass layer on the front is removed;

[0021] 5) Preparation of tunneling oxide layer: preparing an ultra-thin tunneling silicon oxide layer on both the front and back sides of the substrate;

[0022] 6) Preparing a doped amorphous silicon layer: using LPCVD or PECVD equipment to deposit an intrinsic amorphous silicon layer, a boron-doped or phosphorus-doped amorphous silicon layer on both sides or the back side of the substrate;

[0023] 7) Preparing a patterned mask: using APCVD or PECVD to deposit a mask on the back of the substrate, then printing a corrosion-resistant ink on the back mask of the substrate, then removing the mask in the non-ink protection area in a hydrofluoric acid solution with a volume concentration of 1-5%, and then using a mixed aqueous solution of ammonia and hydrogen peroxide to remove the ink material;

[0024] 8) Preparing a patterned passivation contact area: removing the doped amorphous silicon layer in the unprotected area on the back side and the amorphous silicon layer on the front side in an etching solution, and then removing the tunneling oxide layer in the area without the amorphous silicon layer and the remaining mask in a hydrofluoric acid solution with a volume concentration of 1-10%, to obtain a process wafer;

[0025] 9) High temperature activation and diffusion: Place the process wafer obtained in step 8 at 850-1050°C for boron diffusion or phosphorus diffusion to activate the doping atoms, so that all amorphous silicon is converted into polysilicon to form a doped polysilicon layer;

[0026] 10) Passivation: preparing a passivation layer on the front and back sides of the substrate, respectively, wherein the passivation layer is composed of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, aluminum oxide, gallium oxide, zinc oxide or titanium oxide;

[0027] 11) Laser grooving: For P-type substrates, the back side needs to be laser ablated to open the passivation layer, and then the metal grid lines are printed. For N-type substrates, the metal grid lines are directly printed.

[0028] 12) Screen printing and sintering: Screen printing and sintering are performed on the process wafer after completing step 11 to obtain a finished solar cell.

[0029] Furthermore, the texturing solution includes a KOH solution with a weight ratio of 1-20%, the texturing temperature is about 80 degrees Celsius, and the etching solution includes a KOH solution with a weight ratio of 1-20%.

[0030] Furthermore, in step 5, the ultra-thin tunneling silicon oxide layer has a thickness not exceeding 2 nm and is prepared by a thermal oxidation method, a wet chemical method, a PECVD method or a quasi-molecular source dry oxygen method.

[0031] Further, in step 6, the thickness of the amorphous silicon layer is 100-400 nm.

[0032] Furthermore, in step 7, the printed pattern is a plurality of interconnected triangles, the plurality of triangles are of the same shape and size, and the bases are on the same straight line.

[0033] A patterned passivation contact solar cell comprises a substrate, wherein a front passivation layer and a back passivation layer are respectively provided on the front and back sides of the substrate, a front metal grid line is provided on the front side of the substrate, and a back metal grid line is provided on the back side of the substrate, an ultra-thin tunneling oxide layer and a doped polysilicon layer are provided in sequence between the substrate and the back metal grid line, the doped polysilicon layer is connected to the back metal grid line, the ultra-thin tunneling oxide layer and the doped polysilicon layer have the same shape, a blank area is also provided between each two adjacent back metal grid lines, and the edge shape of the blank area is consistent with the edge shape of the ultra-thin tunneling oxide layer or the doped polysilicon layer.

[0034] Furthermore, the doped polysilicon layer includes a metal contact area and a non-metal contact area, the shape and size of the metal contact area are the same as the shape and size of the back metal gate line, and the non-metal contact area includes a plurality of interconnected triangles.

[0035] Furthermore, the thickness of the tunneling silicon oxide does not exceed 2 nm, and the thickness of the doped polysilicon layer is 100-400 nm.

[0036] Compared with the prior art, the advantages of the present invention are:

[0037] The present invention adopts a back-patterned passivation contact structure, in which an ultra-thin tunneling oxide layer is superimposed on the back side of the crystalline silicon substrate, i.e., the side not exposed to light, to passivate the crystalline silicon surface, and then a doped polysilicon layer is superimposed as a carrier selective contact material to reduce carrier recombination in the metal contact area while having good contact performance.

[0038] In addition, while taking into account the passivation contact, in order to reduce the absorption of light by the doped polysilicon layer and reduce current loss, a local passivation contact structure is used. This structure uses a patterned local contact tunneling oxide layer and polysilicon layer. This pattern includes the contact area between the metal gate line and the crystalline silicon substrate, but is not limited to this, and can achieve a good balance between the passivation contact and light absorption loss.

[0039] Other advantages, objectives and features of the present invention will be embodied in part through the following description, and in part will be understood by those skilled in the art through study and practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 It is a schematic structural diagram of the solar cell of the present invention.

[0041] Figure 2 It is a schematic diagram of the graphical local passivation contact structure of the present invention.

[0042] In the figure: substrate 11, ultra-thin tunneling oxide layer 12, doped polysilicon layer 13, front passivation layer 14, back passivation layer 15, back metal gate line 16, front metal gate line 17, blank area 18, non-metal contact area 21, metal contact area 22. DETAILED DESCRIPTION

[0043] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0044] Example 1

[0045] A method for manufacturing a patterned passivated contact solar cell comprises the following steps:

[0046] like Figure 1 and Figure 2 As shown, a single crystal silicon wafer is subjected to texturing, diffusion bonding, etching and polishing to obtain a substrate 11, and an ultra-thin tunneling silicon oxide layer 12 is simultaneously prepared on the front and back sides of the substrate 11, and the thickness of the ultra-thin tunneling silicon oxide layer 12 does not exceed 2nm.

[0047] An amorphous silicon layer is further prepared on the ultra-thin tunneling silicon oxide layer 12 on the front and back sides of the substrate 11, or an amorphous silicon layer is further prepared only on the ultra-thin tunneling silicon oxide layer 12 on the back side of the substrate 11, and the thickness of the amorphous silicon layer is 100-400nm.

[0048] A mask is deposited on the amorphous silicon layer, and corrosion-resistant ink is printed on the mask on the back of the substrate 11. The mask in the area where the corrosion-resistant ink is not printed is then removed with hydrofluoric acid, and the ink is then removed with a mixed aqueous solution of ammonia and hydrogen peroxide.

[0049] The amorphous silicon layer in the unprotected area on the back side of the substrate 11 and the amorphous silicon layer on the front side are removed, and then the tunnel oxide layer in the area without amorphous silicon and the remaining mask are removed with hydrofluoric acid to obtain a process wafer.

[0050] The process wafer is subjected to boron diffusion or phosphorus diffusion at high temperature to activate the doping atoms and simultaneously convert all amorphous silicon into polysilicon to form a doped polysilicon layer 13 .

[0051] A passivation layer is prepared on the front and back sides of the substrate 11, and metal grid lines are printed. After screen printing and sintering, a finished solar cell is obtained.

[0052] Example 2

[0053] A method for manufacturing a patterned passivation contact solar cell comprises the following steps: Figure 1 and Figure 2 As shown,

[0054] 1) Texturing: A P-type or N-type single crystal silicon wafer is used as the substrate 11, and is placed in a texturing liquid to form a pyramid texture surface. The surface of the silicon wafer is then cleaned in a hydrofluoric acid solution with a volume concentration of 1-10%.

[0055] 2) Diffusion junction: Phosphorus or boron is diffused on both sides of the textured silicon substrate to form a pn junction.

[0056] 3) Etching: Using a single-sided etching device, remove the phosphosilicate glass layer or borosilicate glass layer on the back and edge of the substrate 11.

[0057] 4) Back side polishing: The back side is polished to remove the diffusion layer on the back side and form a polished surface, and then the phosphosilicate glass layer or borosilicate glass layer on the front side is removed.

[0058] 5) Preparation of tunneling oxide layer: a layer of ultra-thin tunneling silicon oxide is prepared on the front and back sides of the substrate 11 at the same time.

[0059] 6) Preparation of doped amorphous silicon layer: using LPCVD or PECVD equipment to deposit an intrinsic amorphous silicon layer, a boron-doped or phosphorus-doped amorphous silicon layer on both sides or the back side of the substrate 11.

[0060] 7) Prepare a patterned mask: Use APCVD or PECVD to deposit a mask on the back of the substrate, then print corrosion-resistant ink on the mask on the back of the substrate, then remove the mask in the non-ink protection area in a hydrofluoric acid solution with a volume concentration of 1-5%, and then use a mixed aqueous solution of ammonia and hydrogen peroxide to remove the ink material.

[0061] 8) Prepare a patterned passivation contact area: remove the doped amorphous silicon layer in the unprotected area on the back side and the amorphous silicon layer on the front side in an etching solution, and then remove the ultra-thin tunneling oxide layer in the area without the amorphous silicon layer and the remaining mask in a hydrofluoric acid solution with a volume concentration of 1-10% to obtain a process wafer.

[0062] 9) High temperature activation and diffusion: The process wafer obtained in step 8 is placed at 850-1050° C. for boron diffusion or phosphorus diffusion to activate the doped atoms, so that all amorphous silicon is converted into polysilicon, forming a doped polysilicon layer 13.

[0063] 10) Passivation: A passivation layer is prepared on the front and back sides of the substrate 11, respectively. The passivation layer is composed of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, aluminum oxide, gallium oxide, zinc oxide or titanium oxide.

[0064] 11) Laser grooving: For a P-type substrate, the back side needs to be laser ablated to open the passivation layer, and then the metal gate line is printed. For an N-type substrate, the metal gate line is directly printed, and the doped polysilicon layer 13 contacts the metal gate line.

[0065] 12) Screen printing and sintering: Screen printing and sintering are performed on the process wafer after completing step 11 to obtain a finished solar cell.

[0066] The texturing solution includes a KOH solution with a weight ratio of 1-20%, the texturing temperature is about 80 degrees Celsius, and the etching solution includes a KOH solution with a weight ratio of 1-20%. Both the texturing solution and the etching solution can be commercially available products.

[0067] In step 5, the ultra-thin tunneling silicon oxide 12 layer has a thickness not exceeding 2 nm, and in this embodiment is 0.5-1.5 nm, and is prepared by thermal oxidation, wet chemical method, PECVD method or excimer source dry oxygen method.

[0068] In step 6, the thickness of the amorphous silicon layer is 100-400 nm.

[0069] In step 7, the printed pattern is a plurality of interconnected triangles, the plurality of triangles are of the same shape and size, and the bases are on the same straight line.

[0070] Among them, the back metal grid line, such as the P-type substrate is an aluminum grid line, the N-type substrate is a silver grid line, and the front metal grid line, such as the P-type substrate is a silver grid line, the N-type substrate is a silver-aluminum grid line.

[0071] The patterned passivated contact solar cell proposed in this embodiment, compared with the grid-line localized passivated contact solar cell, only needs to change the screen pattern used for the back printing ink, and the other processes remain almost unchanged, which is suitable for large-scale industrial applications. By adjusting the area ratio of the non-metallic contact area, a better balance can be achieved between the passivated contact and the light absorption loss, further improving the conversion efficiency of the crystalline silicon solar cell.

[0072] Example 3

[0073] A patterned passivated contact solar cell, the specific implementation and preparation method are as follows:

[0074] Use P-type or N-type single crystal silicon wafers as substrates for conventional texturing. After cleaning with hydrofluoric acid and RCA standards, phosphorus diffusion or boron diffusion is performed to form a pn junction. Post-cleaning removes the phosphorus silicon glass layer or borosilicate glass layer on the back of the silicon substrate. The back is then polished to remove the diffusion layer on the back. Next, a layer of ultra-thin tunneling silicon oxide with a thickness of 1-2nm is prepared on both the front and back sides of the silicon substrate by thermal oxidation, and then a layer of boron-doped or phosphorus-doped amorphous silicon layer with a thickness of 100-300nm is deposited on both the front and back sides of the silicon substrate by LPCVD equipment. Use APCVD or PECVD to deposit a mask on the back side of the silicon substrate, and then print corrosion-resistant ink on the mask. The printed pattern is such as Figure 2As shown. The mask of the non-ink protection area is removed in a hydrofluoric acid solution with a volume concentration of 1-5%, and then the ink material is removed using a mixed aqueous solution of ammonia and hydrogen peroxide. The doped amorphous silicon in the non-mask protection area on the back and the amorphous silicon on the front are removed in a mixed aqueous solution of KOH and etching additives. Then the tunneling oxide layer and the remaining mask material in the non-amorphous silicon area are removed in a hydrofluoric acid solution with a volume concentration of 1-10%. Under the condition of 850-1050 degrees Celsius, the doped atoms are subjected to high-temperature activation treatment, and the amorphous silicon layer is completely converted into a polycrystalline silicon layer. The corresponding passivation films are prepared on the front and back of the process wafer respectively. For P-type silicon substrates, laser ablation is required to open the back passivation film, but it is not required for N-type silicon substrates. Then conventional screen printing and sintering are carried out to form electrical contacts to obtain finished solar cells.

[0075] The patterned passivated contact solar cell proposed in this embodiment, compared with the grid-line localized passivated contact solar cell, only needs to change the screen pattern used for the back printing ink, and the other processes remain almost unchanged, which is suitable for large-scale industrial applications. By adjusting the area ratio of the non-metallic contact area, a better balance can be achieved between the passivated contact and the light absorption loss, further improving the conversion efficiency of the crystalline silicon solar cell.

[0076] Example 4

[0077] A patterned passivation contact solar cell comprises a substrate 11, wherein a front passivation layer 14 and a back passivation layer 15 are respectively provided on the front and back sides of the substrate 11, a front metal grid line 17 is provided on the front side of the substrate 11, and a back metal grid line 16 is provided on the back side of the substrate 11, an ultra-thin tunneling oxide layer 12 and a doped polysilicon layer 13 are provided in sequence between the substrate 11 and the back metal grid line 16, the doped polysilicon layer 13 is connected to the back metal grid line 16, the ultra-thin tunneling oxide layer 12 and the doped polysilicon layer 13 have the same shape, a blank area 18 is further provided between each two adjacent back metal grid lines 16, and the edge shape of the blank area 18 is consistent with the edge shape of the ultra-thin tunneling oxide layer 12 or the doped polysilicon layer 13.

[0078] In this embodiment, the blank area 18 is a region on the back side of the substrate where the ultra-thin tunneling oxide layer and the doped polysilicon layer are removed.

[0079] The doped polysilicon layer 13 includes a metal contact region 22 and a non-metal contact region 21. The shape and size of the metal contact region 22 are the same as those of the back metal gate line 16. The non-metal contact region 21 includes a plurality of interconnected triangles.

[0080] The non-metallic contact area 21 is designed to be triangular, which can better collect the current between the two gate lines and reduce the series resistance loss. By adjusting the area ratio of the tunneling oxide layer / doped polysilicon layer in the non-metallic contact area 21, a better balance can be achieved between the passivation contact and the light absorption loss. Therefore, this back-patterned passivation contact structure can reduce the absorption of light by the doped polysilicon layer and reduce current loss while taking into account the passivation contact.

[0081] The thickness of the tunneling silicon oxide is no more than 2 nm, and in this embodiment is 0.5-1.5 nm, and the thickness of the doped polysilicon layer 13 is 100-400 nm.

[0082] The specific embodiments described herein are merely examples of the spirit of the present invention. Those skilled in the art may make various modifications or additions to the specific embodiments described or replace them in similar ways without departing from the spirit of the present invention.

Claims

1. A method for manufacturing a patterned passivated contact solar cell, characterized in that: The following steps are involved: A substrate is obtained by texturing, diffusion bonding, etching and polishing or secondary texturing of a single crystal silicon wafer, and an ultra-thin tunneling silicon oxide layer is simultaneously prepared on the front and back sides of the substrate; A layer of amorphous silicon is further formed on the tunneling silicon oxide layer on the front and back sides of the substrate, or a layer of amorphous silicon is further formed only on the ultra-thin tunneling silicon oxide layer on the back side of the substrate; A mask is deposited on the amorphous silicon layer, and a corrosion-resistant ink is printed on the mask on the back of the substrate. The mask in the area where the corrosion-resistant ink is not printed is then removed with hydrofluoric acid, and the ink is then removed with a mixed aqueous solution of ammonia and hydrogen peroxide; The amorphous silicon layer in the non-mask protected area on the back side of the substrate and the amorphous silicon layer on the front side are removed, and then the tunnel oxide layer in the non-amorphous silicon area and the remaining mask are removed with hydrofluoric acid to obtain a process wafer; The process wafer is subjected to boron diffusion or phosphorus diffusion at high temperature to activate the doping atoms and simultaneously convert all amorphous silicon into polysilicon to form a doped polysilicon layer; A passivation layer is prepared on the front and back of the substrate respectively, and a metal grid line is printed, and a finished solar cell is obtained after screen printing and sintering; wherein the metal grid line on the back of the substrate is a back metal grid line; the shape of the orthographic projection of the tunneling silicon oxide layer on the substrate is the same as the shape of the orthographic projection of the doped polysilicon layer on the substrate, and a blank area is provided between each two adjacent back metal grid lines, and the edge shape of the orthographic projection of the blank area on the substrate is consistent with the edge shape of the orthographic projection of the tunneling silicon oxide layer or the doped polysilicon layer on the substrate; the doped polysilicon layer includes a metal contact area and a non-metal contact area, and the orthographic projection of the non-metal contact area on the substrate is located on the side of the orthographic projection of the metal contact area on the substrate close to the blank area; the shape of the orthographic projection of the non-metal contact area on the substrate includes a plurality of interconnected figures, and the plurality of the figures are arranged along the length direction of the back metal grid line; a part of the orthographic projection of the blank area on the substrate is located between two adjacent figures.

2. The method for manufacturing a patterned passivated contact solar cell according to claim 1, characterized in that: The thickness of the tunneling silicon oxide layer does not exceed 2 nm, and the thickness of the amorphous silicon layer is 100-400 nm.

3. A method for manufacturing a patterned passivated contact solar cell, characterized in that: The following steps are involved: 1) Texturing: P-type or N-type single crystal silicon wafer is used as the substrate, placed in a texturing liquid to form a pyramid texture surface, and then the surface of the silicon wafer is cleaned in a hydrofluoric acid solution with a volume concentration of 1-10%; 2) Diffusion junction: Phosphorus or boron is diffused on both sides of the textured silicon substrate to form a pn junction; 3) Etching: Use single-sided etching equipment to remove the phosphosilicate glass layer or borosilicate glass layer on the back and edge of the substrate; 4) Back polishing: Polishing or secondary texturing of the back to remove the diffusion layer on the back and form a polished surface or a velvet surface, and then remove the phosphosilicate glass layer or borosilicate glass layer on the front; 5) Preparation of tunneling oxide layer: preparing a layer of ultra-thin tunneling silicon oxide on the front and back sides of the substrate at the same time; 6) Preparing a doped amorphous silicon layer: using LPCVD or PECVD equipment to deposit an intrinsic amorphous silicon layer, a boron-doped or phosphorus-doped amorphous silicon layer on both sides or the back side of the substrate; 7) Preparing a patterned mask: using APCVD or PECVD to deposit a mask on the back of the substrate, then printing a corrosion-resistant ink on the back mask of the substrate, then removing the mask in the non-ink protection area in a hydrofluoric acid solution with a volume concentration of 1-5%, and then using a mixed aqueous solution of ammonia and hydrogen peroxide to remove the ink material; 8) Preparing a patterned passivation contact area: removing the doped amorphous silicon layer in the unprotected area on the back side and the amorphous silicon layer on the front side in an etching solution, and then removing the tunneling oxide layer in the area without the amorphous silicon layer and the remaining mask in a hydrofluoric acid solution with a volume concentration of 1-10%, to obtain a process wafer; 9) High temperature activation and diffusion: Place the process wafer obtained in step 8 at 850-1050°C for boron diffusion or phosphorus diffusion to activate the doping atoms, so that all amorphous silicon is converted into polysilicon to form a doped polysilicon layer; 10) Passivation: preparing a passivation layer on the front and back sides of the substrate, respectively, wherein the passivation layer is composed of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, aluminum oxide, gallium oxide, zinc oxide or titanium oxide; 11) Laser grooving: For P-type substrates, the back side needs to be laser ablated to open the passivation layer, and then the metal grid lines are printed. For N-type substrates, the metal grid lines are directly printed. 12) Screen printing and sintering: Screen printing and sintering are performed on the process wafer that has completed step 11 to obtain a finished solar cell; wherein the metal grid line on the back side of the substrate is a back side metal grid line; the shape of the orthographic projection of the tunneling oxide layer on the substrate is the same as the shape of the orthographic projection of the doped polysilicon layer on the substrate, and a blank area is provided between each two adjacent back side metal grid lines, and the edge shape of the orthographic projection of the blank area on the substrate is consistent with the edge shape of the orthographic projection of the tunneling oxide layer or the doped polysilicon layer on the substrate; the doped polysilicon layer includes a metal contact area and a non-metal contact area, and the orthographic projection of the non-metal contact area on the substrate is located on the side of the orthographic projection of the metal contact area on the substrate close to the blank area; the shape of the orthographic projection of the non-metal contact area on the substrate includes a plurality of interconnected figures, and the plurality of the figures are arranged along the length direction of the back side metal grid line; a part of the orthographic projection of the blank area on the substrate is located between two adjacent figures.

4. The method for manufacturing a patterned passivated contact solar cell according to claim 3, characterized in that: The texturing solution includes a KOH solution with a weight ratio of 1-20%, the texturing temperature is about 80 degrees Celsius, and the etching solution includes a KOH solution with a weight ratio of 1-20%.

5. The method for manufacturing a patterned passivated contact solar cell according to claim 3, characterized in that: In step 5, the ultra-thin tunneling silicon oxide layer has a thickness not exceeding 2 nm and is prepared by a thermal oxidation method, a wet chemical method, a PECVD method or a quasi-molecular source dry oxygen method.

6. The method for manufacturing a patterned passivated contact solar cell according to claim 3, characterized in that: In step 6, the thickness of the amorphous silicon layer is 100-400 nm.

7. The method for manufacturing a patterned passivated contact solar cell according to claim 3, characterized in that: In step 7, the printed pattern is a plurality of interconnected triangles, the plurality of triangles are of the same shape and size, and the bases are on the same straight line.

8. A patterned passivation contact solar cell, comprising a substrate, a front passivation layer and a back passivation layer are provided on the front and back of the substrate respectively, a front metal grid line is provided on the front of the substrate, and a back metal grid line is provided on the back of the substrate, characterized in that: An ultra-thin tunneling oxide layer and a doped polysilicon layer are sequentially arranged between the substrate and the back metal gate line, the doped polysilicon layer is connected to the back metal gate line, the shape of the orthographic projection of the ultra-thin tunneling oxide layer on the substrate is the same as the shape of the orthographic projection of the doped polysilicon layer on the substrate, and a blank area is also arranged between each two adjacent back metal gate lines, and the edge shape of the orthographic projection of the blank area on the substrate is consistent with the edge shape of the orthographic projection of the ultra-thin tunneling oxide layer or the doped polysilicon layer on the substrate; The doped polysilicon layer comprises a metal contact region and a non-metal contact region, wherein the orthographic projection of the non-metal contact region on the substrate is located on a side of the orthographic projection of the metal contact region on the substrate close to the blank region; The shape of the orthographic projection of the non-metallic contact area on the substrate includes a plurality of interconnected figures, and the plurality of the figures are arranged along the length direction of the back metal grid line; the partial orthographic projection of the blank area on the substrate is located between two adjacent figures.

9. A patterned passivated contact solar cell according to claim 8, characterized in that: The shape and size of the metal contact area are the same as those of the back metal grid line, and the non-metal contact area includes a plurality of interconnected triangles.

10. A patterned passivated contact solar cell according to claim 8, characterized in that: The thickness of the ultra-thin tunneling oxide layer does not exceed 2 nm, and the thickness of the doped polysilicon layer is 100-400 nm.

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