Display device and manufacturing method thereof

Abstract

A display device includes a substrate including a display area having a through hole and a non-display area adjacent to the display area; an insulating layer disposed on the substrate; a light emitting stack disposed on the insulating layer; an electrode extending from a display area to a non-display area and disposed on the light emitting stack; and an electrode patterned material layer in contact with one end of the electrode and disposed on the light emitting stack. One end of the light emitting stack may coincide with one end of the electrode patterned material layer. A display device capable of preventing or reducing lateral moisture penetration due to the presence of a light emitting stack may be provided.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0157172 filed on November 14, 2023, which is incorporated herein by reference for all purposes as if fully set forth herein. Technical Field

[0003] Embodiments of the present disclosure relate to a display device and a method for manufacturing the same. Background Art

[0004] Nowadays, the use of display devices is becoming diversified. In addition, as display devices become thinner and lighter, their use is expanding to various fields of economic activities.

[0005] As the size of a display area for displaying an image in a display device increases, various functions linked to or combined with the display device are added to the display apparatus to obtain greater flexibility in use.

[0006] As so-called frameless or borderless designs in which a display area appears full become more and more common, research is required on display devices having an area within the display area that is not used for displaying images but for adding various functions to have greater flexibility in use.

[0007] Therefore, a display device referred to as a hole-in-display (HID) or a hole-in-active-area (HiAA) has been proposed, in which at least a portion of a substrate is removed in a display area of ​​a display panel.

[0008] However, there is a problem that cracks may occur during the process of removing a portion of the substrate, or moisture may penetrate into the area where the substrate is removed, resulting in degradation of display quality and defects in the display device. Therefore, there is a need to solve this problem in order to produce a reliable display device. Summary of the invention

[0009] There is a problem that when moisture or the like penetrates into the area where the substrate is removed in the display area, the display quality deteriorates. Therefore, the inventors of the present disclosure have invented a display device that prevents or reduces lateral moisture penetration by a light emitting stack.

[0010] Embodiments of the present disclosure are directed to providing a display device and a method for manufacturing the same, the display device being capable of blocking a lateral moisture permeation path through a light emitting stack by patterning the light emitting stack.

[0011] Embodiments of the present disclosure are directed to providing a display device and a method for manufacturing the same, the display device being capable of preventing or reducing lateral moisture penetration paths and micro cracks of a light emitting stack by patterning the light emitting stack and arranging a dam structure.

[0012] Embodiments of the present disclosure are directed to providing a display device and a method for manufacturing the same, the display device being capable of increasing lifespan by preventing or reducing lateral moisture penetration, thereby achieving low power consumption.

[0013] According to an embodiment of the present disclosure, a display device may include: a substrate, the substrate including a non-display area and a display area surrounding the non-display area, the non-display area including a through hole; an insulating layer, the insulating layer being arranged on the substrate; a light-emitting stack, the light-emitting stack being arranged on the insulating layer; a second electrode, the second electrode extending from the display area to the non-display area to be arranged on the light-emitting stack; and an electrode patterned material layer, the electrode patterned material layer contacting one end of the second electrode and being arranged on the light-emitting stack, wherein one end of the light-emitting stack and one end of the electrode patterned material layer are arranged to overlap.

[0014] According to an embodiment of the present disclosure, a display device may include: a substrate, the substrate including a non-display area and a display area surrounding the non-display area, the non-display area including a through hole; an insulating layer, the insulating layer is arranged on the substrate; a plurality of dams, the plurality of dams are located between the display area and the through hole and are arranged on the insulating layer; a light-emitting stack, the light-emitting stack is arranged on an insulating film and the plurality of dams; a second electrode, the second electrode extends from the display area to the non-display area to be arranged on the light-emitting stack; an electrode patterned material layer, the electrode patterned material layer contacts one end of the second electrode and is arranged on the light-emitting stack; and a groove, at which each of the light-emitting stack and the electrode patterned material layer is cut.

[0015] According to an embodiment of the present disclosure, a method for manufacturing a display device may include: forming a substrate including a display area and a non-display area, forming a sacrificial layer and a dam in the non-display area, forming a light-emitting stack to cover the sacrificial layer and the dam, forming an electrode patterned material layer on the light-emitting stack to be located in the non-display area, forming a second electrode on the light-emitting stack to contact the electrode patterned material layer, forming a covering layer on the second electrode and the electrode patterned material layer, and forming a groove by irradiating a laser to the sacrificial layer.

[0016] According to an embodiment of the present disclosure, a display device capable of blocking a lateral moisture permeation path due to the presence of a light emitting stack by patterning the light emitting stack and a method of manufacturing the same may be provided.

[0017] According to an embodiment of the present disclosure, a display device capable of preventing or reducing a lateral moisture penetration path and micro cracks of a light emitting stack by patterning the light emitting stack and providing a dam structure and a method for manufacturing the same may be provided.

[0018] According to an embodiment of the present disclosure, a display device capable of increasing lifespan by preventing or reducing lateral moisture penetration, thereby achieving low power consumption, and a method of manufacturing the same may be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a system configuration diagram of a display device according to an embodiment of the present disclosure.

[0020] Figure 2 is an equivalent circuit diagram of a sub-pixel in a display panel according to an embodiment of the present disclosure.

[0021] Figure 3 is a plan view showing a structure of an optical region of a display panel according to an embodiment of the present disclosure.

[0022] Figure 4 is along Figure 3 An example of a cross-sectional view taken along line II'.

[0023] Figure 5 is along Figure 3 An example of a cross-sectional view taken along line II-II'.

[0024] Figure 6 is along Figure 3 Another example of a cross-sectional view taken along line II-II'.

[0025] Figure 7 , 8 , 9, 10, 11, 12A and 12B are diagrams illustrating a process of forming an optical area of ​​a display panel according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0026] In the following description of examples or embodiments of the present disclosure, reference will be made to the accompanying drawings in which specific examples or embodiments that can be implemented are illustrated by way of illustration, and in the accompanying drawings, the same reference numerals and symbols may be used to represent the same or similar parts even when they are shown in different drawings from each other. In addition, in the following description of examples or embodiments of the present disclosure, a detailed description of the well-known functions and components incorporated herein will be omitted when it is determined that the description may make the subject matter in some embodiments of the present disclosure quite unclear. The terms "including", "having", "comprising", "constituting", "comprising" and "forming" used herein are generally intended to allow the addition of other components unless these terms are used together with the term "only". As used herein, the singular form shall include the plural form unless the context clearly indicates otherwise.

[0027] Terms such as "first", "second", "A", "B", "(A)" or "(B)" may be used to describe elements of the present disclosure. Each of these terms is not used to define the nature, order, sequence, quantity, etc. of an element, but is only used to distinguish the corresponding element from other elements.

[0028] When it is mentioned that a first element is “connected or coupled”, “contacting or overlapping”, etc. with a second element, it should be understood that not only the first element may be “directly connected or coupled to” or “directly contacting or overlapping” the second element, but a third element may also be “interposed” between the first and second elements, or the first and second elements may be “connected or coupled”, “contacting or overlapping”, etc. with each other via a fourth element. Here, the second element may be included in at least one element of the two or more elements that are “connected or coupled”, “contacting or overlapping”, etc. with each other.

[0029] When time-related terms such as “after,” “subsequently,” “next,” “before,” etc. are used to describe a process or operation of an element or configuration, or a process or step in an operation, process, or method of manufacture, these terms may be used to describe non-sequential or non-sequential processes or operations unless the terms “directly” or “immediately” are used together.

[0030] Furthermore, when referring to any dimension, relative dimension, etc., it should be considered that the numerical value or corresponding information (e.g., level, range, etc.) of an element or feature includes a tolerance or error range that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.), even in the absence of any relevant description. In addition, the word "may" fully includes all the meanings of the word "can".

[0031] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0032] Figure 11 is a system structure diagram of a display device 100 according to an embodiment of the present disclosure. All components of each display device according to all embodiments of the present disclosure are operably coupled and configured.

[0033] refer to Figure 1 , the display device 100 may include a display panel 110 and a display driving circuit as components for displaying an image.

[0034] The display driving circuit, which is a circuit for driving the display panel 110 , may include a data driving circuit 120 , a gate driving circuit 130 , and a display controller 140 .

[0035] The display panel 110 may include a display area AA in which an image is displayed and a non-display area NA in which no image is displayed. The non-display area NA may be an area outside the display area AA, and may also be referred to as a bezel area. All or a portion of the non-display area NA may be an area visible on the front surface of the display device 100, or an area that is curved and not visible on the front surface of the display device 100.

[0036] The display panel 110 may include a substrate SUB and a plurality of sub-pixels SP disposed on the substrate SUB. In order to drive the plurality of sub-pixels SP, the display panel 110 may further include various types of signal lines.

[0037] The display device 100 according to an embodiment of the present disclosure may be a liquid crystal display device or the like, or may be a self-luminous display device in which the display panel 110 emits light by itself. When the display device 100 according to an embodiment of the present disclosure is a self-luminous display device, each of the plurality of sub-pixels SP may include a light-emitting element. However, the embodiments of the present disclosure are not limited thereto.

[0038] For example, the display device 100 according to an embodiment of the present disclosure may be an organic light-emitting display device, wherein the light-emitting element is implemented by an organic light-emitting diode (OLED). For example, the display device 100 according to an embodiment of the present disclosure may be an inorganic light-emitting display device, wherein the light-emitting element is implemented by an inorganic-based light-emitting diode. As another example, the display device 100 according to an embodiment of the present disclosure may be a quantum dot display device, wherein the light-emitting element is implemented by quantum dots as self-luminous semiconductor crystals.

[0039] The structure of each of the plurality of sub-pixels SP may vary according to the type of the display device 100. For example, when the display device 100 is a self-luminous display device in which each sub-pixel SP emits light by itself, each sub-pixel SP may include a self-luminous element, at least one transistor, and at least one capacitor. However, the embodiments of the present disclosure are not limited thereto.

[0040] For example, the various types of signal lines may include a plurality of data lines DL transmitting data signals (also referred to as data voltages or image signals) and a plurality of gate lines GL transmitting gate signals (also referred to as scan signals).

[0041] The plurality of data lines DL and the plurality of gate lines GL may cross each other. Each of the plurality of data lines DL may be disposed to extend in the first direction. Each of the plurality of gate lines GL may be disposed to extend in the second direction.

[0042] The first direction may be a column direction, and the second direction may be a row direction. The first direction may be a row direction, and the second direction may be a column direction.

[0043] The data driving circuit 120, which is a circuit configured to drive a plurality of data lines DL, may output data signals to the plurality of data lines DL. The gate driving circuit 130, which is a circuit configured to drive a plurality of gate lines GL, may output gate signals to the plurality of gate lines.

[0044] The display controller 140 may be a device configured to control the data driving circuit 120 and the gate driving circuit 130. The display controller 140 may control a driving timing of a plurality of data lines DL and a driving timing of a plurality of gate lines GL.

[0045] To control the data driving circuit 120, the display controller 140 may provide the data driving circuit control signal DCS to the data driving circuit 120. To control the gate driving circuit 130, the display controller 140 may provide the gate driving circuit control signal GCS to the gate driving circuit 130.

[0046] The display controller 140 may receive input image data from the host system 150 , and may provide image data Data to the data driving circuit 120 based on the input image data.

[0047] The data driving circuit 120 may provide data signals to the plurality of data lines DL according to the driving timing control of the display controller 140 .

[0048] The data driving circuit 120 may receive the digital type image data Data from the display controller 140 , may convert the received image data Data into an analog type data signal, and may output the data signal to a plurality of data lines DL.

[0049] The gate driving circuit 130 may provide gate signals to the plurality of gate lines GL according to the timing control of the display controller 140. The gate driving circuit 130 may be provided with a first gate voltage corresponding to an on-level voltage and a second gate voltage corresponding to an off-level voltage together with various gate driving circuit control signals GCS, may generate gate signals, and may provide the generated gate signals to the plurality of gate lines GL.

[0050] For example, the data driving circuit 120 may be connected to the display panel 110 in a tape automated bonding (TAB) method, may be connected to a bonding pad of the display panel 110 in a chip on glass (COG) or chip on panel (COP) method, or may be connected to the display panel 110 by being implemented in a chip on film (COF) method. However, the embodiments of the present disclosure are not limited thereto.

[0051] The gate drive circuit 130 may be connected to the display panel 110 in a tape automated bonding (TAB) method, may be connected to a bonding pad of the display panel 110 in a chip on glass (COG) or chip on panel (COP) method, or may be connected to the display panel 110 according to a chip on film (COF) method. Alternatively, the gate drive circuit 130 may be formed in a non-display area NA of the display panel 110 in a gate-in-panel (GIP) type. The gate drive circuit 130 may be disposed on the substrate SUB or may be connected to the substrate SUB. That is, in the case of the gate-in-panel (GIP) type, the gate drive circuit 130 may be disposed in the non-display area NA of the substrate SUB. In the case of the chip on glass (COG) type or the chip on film (COF) type, the gate driver circuit 130 may be connected to the substrate SUB.

[0052] At least one of the data driving circuit 120 and the gate driving circuit 130 may be disposed in the display area AA of the display panel 110. For example, at least one of the data driving circuit 120 and the gate driving circuit 130 may be disposed so as not to overlap with the sub-pixel SP, or may be disposed so as to partially or completely overlap with the sub-pixel SP. However, the embodiments of the present disclosure are not limited thereto.

[0053] The data driving circuit 120 may be connected to one side (e.g., the upper side or the lower side) of the display panel 110. The data driving circuit 120 may be connected to both sides (e.g., the upper side and the lower side) of the display panel 110, or may be connected to at least two of the four sides of the display panel 110, depending on a driving method, a panel design method, etc.

[0054] The gate driving circuit 130 may be connected to one side (e.g., the left side or the right side) of the display panel 110. Depending on a driving method, a panel design method, etc., the gate driving circuit 130 may be connected to both sides (e.g., the left side and the right side) of the display panel 110, or may be connected to at least two of the four sides of the display panel 110.

[0055] The display controller 140 may be implemented as a separate component from the data driving circuit 120 , or may be implemented as an integrated circuit by being integrated with the data driving circuit 120 .

[0056] The display controller 140 may be a timing controller used in general display technology, a control device including a timing controller and capable of further performing other control functions, a control device different from a timing controller, or a circuit in a control device. The display controller 140 may be implemented by various circuits or electronic components, such as an integrated circuit (IC), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), and a processor.

[0057] The display controller 140 may be electrically connected to the data driving circuit 120 and the gate driving circuit 130 through a printed circuit board (PCB), a flexible printed circuit board, or the like.

[0058] The display controller 140 may send and receive signals to and from the data driving circuit 120 according to at least one predetermined interface. For example, the interface may include a low voltage differential signaling (LVDS) interface, an EPI interface, a serial peripheral interface (SPI), etc. However, the embodiments of the present disclosure are not limited thereto.

[0059] refer to Figure 1 The display device 100 according to an embodiment of the present disclosure may include at least one optical area OA, for example, a first optical area OA1 and a second optical area OA2, from which at least a portion of the substrate SUB is removed.

[0060] At least one component (not shown) for providing various functions may be disposed in an area at least partially overlapping the optical area OA. The at least one component may be, for example, an optical electronic device, a clock hand, etc. However, the embodiments of the present disclosure are not limited thereto.

[0061] For example, the optical electronic device may include at least one of a photographing device (image sensor) such as a camera and a detection sensor such as a proximity sensor and a light sensor. However, the embodiments of the present disclosure are not limited thereto.

[0062] For example, a photographing device such as a camera may be located in the first optical area OA1, and a detection sensor may be located in the second optical area OA2. However, embodiments of the present disclosure are not limited thereto.

[0063] The component may be located under the substrate SUB to at least partially overlap the optical area OA.

[0064] The first optical area OA1 and the second optical area OA2 may have various shapes, such as a circle, an ellipse, a quadrangle, a hexagon, and an octagon. The shapes of the first optical area OA1 and the second optical area OA2 may be the same or different. The area of ​​the first optical area OA1 may be the same as or different from the area of ​​the second optical area OA2.

[0065] Hereinafter, for convenience of explanation, description will be made assuming that the first optical area OA1 and the second optical area OA2 have a circular shape and the same area, but the present disclosure is not limited thereto.

[0066] The at least one optical area OA may be located in a region where the substrate SUB is removed. The optical area OA may be a non-display area NA in which the sub-pixel SP is not disposed.

[0067] The optical area OA located in the display area AA is also referred to as a "hole in the display (HID)" or "hole in the active area (HiAA)".

[0068] Signal lines (eg, data lines DL and gate lines GL) disposed on the substrate SUB may be disposed to detour (or bypass) the optical area OA.

[0069] In order to further provide touch sensing function as well as image display function, the display device 100 according to an embodiment of the present disclosure may include a touch sensor and a touch sensing circuit, which detects whether a touch event has occurred by a touch object such as a finger or a pen, or detects a touch position by sensing the touch sensor.

[0070] The touch sensing circuit may include a touch driving circuit 160 and a touch controller 170 . The touch driving circuit 160 generates and outputs touch sensing data by driving and sensing the touch sensor, and the touch controller 170 can detect the occurrence of a touch event or detect a touch position using the touch sensing data.

[0071] The touch sensor may include a plurality of touch electrodes. The touch sensor may also include a plurality of touch lines for electrically connecting the plurality of touch electrodes and the touch driving circuit 160 .

[0072] The touch sensor may exist outside the display panel 110 in the form of a touch panel, or may exist inside the display panel 110 .

[0073] In the case where the touch sensor exists in the form of a touch panel outside the display panel 110, the touch sensor may be referred to as an external type. When the touch sensor is an external type, the touch panel and the display panel 110 may be manufactured separately and coupled during the assembly process. The external type touch panel may include a substrate for a touch panel and a plurality of touch electrodes on the substrate for the touch panel.

[0074] When the touch sensor exists inside the display panel 110 , the touch sensor may be formed on the substrate SUB together with signal lines and electrodes related to display driving during the process of manufacturing the display panel 110 .

[0075] The touch driving circuit 160 may provide a touch driving signal to at least one of the plurality of touch electrodes, and may generate touch sensing data by sensing at least one of the plurality of touch electrodes.

[0076] The touch sensing circuit may perform touch sensing in a self-capacitance sensing method or a mutual capacitance sensing manner.

[0077] In the case where the touch sensing circuit performs touch sensing in a self-capacitance sensing method, the touch sensing circuit may perform touch sensing based on capacitance between each touch electrode and a touch object (eg, a finger, a pen, etc.).

[0078] According to the self-capacitance sensing method, each of the plurality of touch electrodes may be used as a driving touch electrode and a sensing touch electrode. The touch driving circuit 160 may drive all or some of the plurality of touch electrodes, and may sense all or some of the plurality of touch electrodes.

[0079] In the case where the touch sensing circuit performs touch sensing in a mutual capacitance sensing method, the touch sensing circuit may perform touch sensing based on capacitance between touch electrodes.

[0080] According to the mutual capacitance sensing method, a plurality of touch electrodes are divided into driving touch electrodes and sensing touch electrodes. The touch driving circuit 160 may drive the driving touch electrodes and sense the sensing touch electrodes.

[0081] The touch driving circuit 160 and the touch controller 170 included in the touch sensing circuit may be implemented as separate devices or may be implemented as a single device. In addition, the touch driving circuit 160 and the data driving circuit 120 may be implemented as separate devices or may be implemented as a single device.

[0082] The display device 100 may further include a power circuit that provides various types of power to the display driving circuit and / or the touch sensing circuit.

[0083] The display device 100 according to an embodiment of the present disclosure may be a mobile terminal of various sizes, such as a smart phone and a tablet computer or a monitor or a television (TV). However, the display device 100 according to an embodiment of the present disclosure is not limited thereto, and may be a display device of various types and sizes capable of displaying information or images.

[0084] Figure 2 1 is an equivalent circuit diagram of a sub-pixel SP in the display panel 110 according to an embodiment of the present disclosure. Figure 1 Describes the same or similar content.

[0085] refer to Figure 2 , each sub-pixel SP disposed in the display area AA of the display panel 110 may include a light emitting element ED, a driving transistor DRT for driving the light emitting element ED, a scanning transistor SCT for transmitting a data voltage Vdata to a first node N1 of the driving transistor DRT, and a storage capacitor Cst for maintaining a constant voltage during one frame.

[0086] The driving transistor DRT may include a first node N1 to which a data voltage Vdata is applied, a second node N2 electrically connected to the light emitting element ED, and a third node N3 to which a high potential common voltage ELVDD is applied from a driving voltage line DVL. In the driving transistor DRT, the first node N1 may be a gate node, the second node N2 may be any one of a source node or a drain node, and the third node N3 may be the other of the source node or the drain node.

[0087] The light emitting element ED may include an anode electrode AE ​​as a first electrode, a light emitting layer EL, and a cathode electrode CE as a second electrode. The anode electrode AE ​​may be a pixel electrode provided in each sub-pixel SP, and may be electrically connected to the second node N2 of the driving transistor DRT of each sub-pixel SP. The cathode electrode CE may be a common electrode provided in common in a plurality of sub-pixels SP, and may be applied with a low potential common voltage ELVSS.

[0088] For example, the anode electrode AE ​​may be a pixel electrode, and the cathode electrode CE may be a common electrode. Conversely, the anode electrode AE ​​may be a common electrode, and the cathode electrode CE may be a pixel electrode. Hereinafter, for ease of explanation, it is assumed that the anode electrode AE ​​is a pixel electrode, and the cathode electrode CE is a common electrode. However, the embodiments of the present disclosure are not limited thereto.

[0089] For example, the light emitting element ED may be an organic light emitting diode (OLED), an inorganic light emitting diode or a quantum dot light emitting element. When the light emitting element ED is an organic light emitting diode, the light emitting layer EL in the light emitting element ED may include an organic light emitting layer including an organic material.

[0090] The scanning transistor SCT is on-off controlled by a scanning signal SCAN as a gate signal applied through the gate line GL. The scanning transistor SCTT can switch the electrical connection between the first node N1 of the driving transistor DRT and the data line DL. However, the embodiments of the present disclosure are not limited thereto.

[0091] The storage capacitor Cst may be electrically connected between the first node N1 and the second node N2 of the driving transistor DRT.

[0092] like Figure 2 As shown, each sub-pixel SP may have a 2T (transistor) 1C (capacitor) structure including two transistors DRT and SCT and one capacitor Cst. Depending on the circumstances, each sub-pixel SP may further include at least one transistor, or may further include at least one capacitor.

[0093] The storage capacitor Cst may not be a parasitic capacitor (eg, Cgs or Cgd) as an internal capacitor that may exist between the first node N1 and the second node N2 of the driving transistor DRT, but an external capacitor intentionally designed outside the driving transistor DRT.

[0094] Each of the driving transistor DRT and the scanning transistor SCT may be an n-type transistor or a p-type transistor.

[0095] Since the circuit elements (especially the light emitting element ED) in each sub-pixel SP are easily affected by external moisture or oxygen, an encapsulation layer ENCAP for preventing external moisture or oxygen from penetrating into the circuit elements (especially the light emitting element ED) may be provided in the display panel 110. The encapsulation layer ENCAP may be provided in a shape covering the light emitting element ED.

[0096] Figure 3 1 is a plan view showing the structure of the optical region OA of the display panel 110 according to an embodiment of the present disclosure. Figure 1 and Figure 2 Describes the same or similar content.

[0097] Reference Figure 3The optical area OA is disposed in the display area AA. The sub-pixel SP may be disposed around the optical area OA. The optical area OA may be any one of the first optical area OA1 or the second optical area OA2 described above.

[0098] Reference Figure 3 The optical area OA may include a through hole TH and a frame area surrounding the through hole TH. The frame area between the through hole TH and the display area AA is also referred to as a "HiAA frame area HBA".

[0099] The HiAA frame area HBA is an area surrounding the outside of the through hole TH. The HiAA frame area HBA can prevent interconnection damage when irradiating laser for forming the through hole TH. The HiAA frame area HBA can be continuously maintained and have a minimum width.

[0100] In the HiAA frame area HBA, a dam area 200 may be provided in which a dam structure for preventing moisture from penetrating from the outside through the trimming line and microcracks may be provided. At least one dam may be provided in the dam area 200. The sub-pixel SP for displaying an image may not be located in the optical area OA. That is, the optical area OA including the HiAA frame area HBA may be a non-display area NA that does not display an image.

[0101] The through hole TH may be formed when the substrate SUB is removed along the trimming line. The through hole TH may have a Figure 3 The circular shape shown in the figure may have various shapes such as an ellipse, a quadrangle, a hexagon, and an octagon. However, the embodiments of the present disclosure are not limited thereto.

[0102] The bank region 200 may include at least one bank. For example, in the bank region 200, a first bank 230, a second bank 220, and a third bank 210 may be sequentially disposed and adjacent to the display region AA between the display region AA and the through hole TH.

[0103] Each of the dams 210, 220, and 230 has a closed curve shape corresponding to the shape of the through hole TH and surrounding the through hole TH. The dams 210, 220, and 230 and the through hole TH may have different closed curve shapes, but may have the same closed curve shape with different sizes. For example, the dams 210, 220, and 230 and the through hole TH may have concentric circle shapes or be nested in series, and may be arranged to be spaced apart from each other by a predetermined interval. However, the embodiments of the present disclosure are not limited thereto.

[0104] Each sub-pixel SP disposed in the display area AA may include a light emitting element. A light emitting stack (not shown) including a light emitting layer may be located in the display area AA. When the light emitting element is an organic light emitting element, the light emitting stack may be an organic light emitting stack including an organic material. However, the embodiments of the present disclosure are not limited thereto.

[0105] The organic light emitting stack may be disposed up to at least a portion of the optical area OA.

[0106] When moisture penetrates into the organic light emitting stack, defect phenomena such as dark spots of sub-pixels may occur. There is a possibility that moisture may penetrate into the region where the through hole TH is located.

[0107] The inorganic encapsulation layer may be located on the dam area 200. Moisture may penetrate the inorganic encapsulation layer, and the dam area 200 may have the effect of extending the path of moisture penetration through the inorganic encapsulation layer. According to this effect, the dam area 200 may prevent moisture introduced into the through hole TH from reaching the light emitting layer located in the display area AA.

[0108] Figure 4 is along Figure 3 An example of a cross-sectional view taken along line II' of FIG. Figure 4 It is shown Figure 3 In the following description, the cross-sectional structure of the sub-pixel SP will be omitted or simply described. Figures 1 to 3 Describes the same or similar content.

[0109] refer to Figure 4 According to an embodiment of the present disclosure, the display device 100 includes a substrate 301. The substrate 301 may be a glass substrate or a plastic substrate. The plastic substrate may be made of, for example, polyimide (PI), polymethyl methacrylate (PMMA), or polyethylene (PE) or include the above materials to have a flexible property. However, the embodiments of the present disclosure are not limited thereto.

[0110] A plurality of insulating layers may be provided on the substrate 301. The buffer layer 302 may be provided on the substrate 301. The buffer layer 302 may include a multi-buffer layer 302a and a lower buffer layer 302b. The first transistor 320 may be provided on the lower buffer layer 302b. A first semiconductor layer 323 constituting the first transistor 320 may be provided, and a lower gate insulating layer 304 for insulating from the first gate electrode 322 may be provided on the first semiconductor layer 323. A lower interlayer insulating layer 305 may be provided on the first gate electrode 322. As the lower interlayer insulating layer 305, a first lower interlayer insulating layer 305a and a second lower interlayer insulating layer 305b may be sequentially provided. An upper buffer layer 307 may be provided on the lower interlayer insulating layer 305. However, the embodiments of the present disclosure are not limited thereto.

[0111] The multi-buffer layer 302a may delay diffusion of moisture or oxygen penetrating into the substrate 301, and may be formed as silicon nitride (SiNx) and silicon oxide (SiOx) alternately stacked at least once. However, the embodiments of the present disclosure are not limited thereto.

[0112] The lower buffer layer 302b may protect the first semiconductor layer 323 and may perform a function of blocking various types of defects introduced from the substrate 301. The lower buffer layer 302b may be formed of amorphous silicon (a-Si), silicon nitride (SiNx), or silicon oxide (SiOx). However, the embodiments of the present disclosure are not limited thereto.

[0113] The first semiconductor layer 323 of the first transistor 320 may be composed of a polycrystalline semiconductor layer. However, the embodiments of the present disclosure are not limited thereto. The first semiconductor layer 323 may include a channel region, a source region, and a drain region.

[0114] A polycrystalline semiconductor layer has higher mobility than an amorphous semiconductor layer and an oxide semiconductor layer, resulting in low power consumption and excellent reliability. Due to these advantages, a polycrystalline semiconductor layer can be used in a driving transistor. However, the embodiments of the present disclosure are not limited thereto.

[0115] The first gate electrode 322 may be disposed on the lower gate insulating layer 304 , and may be disposed to overlap the first semiconductor layer 323 .

[0116] The second transistor 330 may be disposed on the upper buffer layer 307 , and the light blocking layer 336 may be disposed under a region corresponding to the second transistor 330 .

[0117] Reference Figure 4 , a light blocking layer 336 may be disposed on the first lower interlayer insulating layer 305a below a region corresponding to the second transistor 330, and a second semiconductor layer 333 of the second transistor 330 may be disposed on the second lower interlayer insulating layer 305b and the upper buffer layer 307 to overlap the light blocking layer 336. An upper gate insulating layer 337 for insulating the second gate electrode 332 and the second semiconductor layer 333 may be disposed on the second semiconductor layer 333, and an upper interlayer insulating layer 308 may be disposed on the second gate electrode 332. The first gate electrode 322 and the second gate electrode 332 may be a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or alloys thereof, but are not limited thereto.

[0118] The first lower interlayer insulating layer 305a and the second lower interlayer insulating layer 305b may be formed as an inorganic layer having a higher hydrogen particle content than the upper interlayer insulating layer 308. For example, the first lower interlayer insulating layer 305a and the second lower interlayer insulating layer 305b may be made of silicon nitride (SiNx) formed by a deposition process using NH3 gas, and the upper interlayer insulating layer 308 may be formed of silicon oxide (SiOx). However, the embodiments of the present disclosure are not limited thereto. During the hydrogenation process, the hydrogen particles included in the first lower interlayer insulating layer 305a and the second lower interlayer insulating layer 305b may diffuse into the polycrystalline semiconductor layer to fill the voids in the polycrystalline semiconductor with hydrogen. Therefore, the polycrystalline semiconductor layer may be stabilized to prevent the characteristics of the first transistor 320 from deteriorating.

[0119] After the activation and hydrogenation process of the first semiconductor layer 323 of the first transistor 320, the second semiconductor layer 333 of the second transistor 330 may be formed. The second semiconductor layer 333 may be formed of an oxide semiconductor. Since the second semiconductor layer 333 is not exposed to the high temperature atmosphere of the activation and hydrogenation process of the first semiconductor layer 323, damage to the second semiconductor layer 333 may be prevented to improve reliability.

[0120] After setting the upper interlayer insulating layer 308, a first source contact hole 325S and a first drain contact hole 325D can be formed to correspond to the source and drain regions of the first transistor 320, respectively, and a second source contact hole 335S and a second drain contact hole 335D can be formed to correspond to the source region and the drain region of the second transistor 330, respectively.

[0121] Reference Figure 4 , the first source contact hole 325S and the first drain contact hole 325D may be continuously formed from the upper interlayer insulating layer 308 to the lower gate insulating layer 304, and the second source contact hole 335S and the second drain contact hole 335D may also be formed for the second transistor 330. The first source electrode 321 and the first drain electrode 324 corresponding to the first transistor 320 and the second source electrode 331 and the second drain electrode 334 corresponding to the second transistor 330 may be formed at the same time, and by this, the number of processes for forming the source and the drain of each of the first transistor 320 and the second transistor 330 may be reduced.

[0122] The first source electrode 321 and the first drain electrode 324 and the second source electrode 331 and the second drain electrode 334 may be a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or an alloy thereof, but are not limited thereto.

[0123] The first source electrode 321 and the first drain electrode 324 and the second source electrode 331 and the second drain electrode 334 may have a three-layer structure. The first source electrode 321 may be sequentially composed of a first electrode layer 321a, a second electrode layer 321b, and a third electrode layer 321c.

[0124] The first electrode layer 321a, the second electrode layer 321b, and the third electrode layer 321c may include materials with relatively different etching rates. The second electrode layer 321b may include a material with a relatively fast etching rate, and the first electrode layer 321a and the third electrode layer 321c may include a material with a relatively slow etching rate. For example, the second electrode layer 321b may include aluminum (Al) with a relatively fast etching rate, and the first electrode layer 321a and the third electrode layer 321c may include titanium (Ti) with a relatively slow etching rate. The first source electrode 321 may have a three-layer structure of Ti / Al / Ti. However, the embodiments of the present disclosure are not limited thereto.

[0125] Other sources and drains may also have the same structure as the first source electrode 321 .

[0126] The storage capacitor 340 may be disposed between the first transistor 320 and the second transistor 330. Figure 4 As shown, the storage capacitor 340 may be formed such that a storage lower electrode 341 and a storage upper electrode 342 overlap with the first lower interlayer insulating layer 305 a interposed therebetween.

[0127] The storage lower electrode 341 may be located on the lower gate insulating layer 304 and may be formed of the same material at the same layer as the first gate electrode 322. The storage upper electrode 342 may be electrically connected to the pixel circuit through the storage supply line 343. The storage upper electrode 342 may be formed of the same material at the same layer as the light blocking layer 336. The storage upper electrode 342 is exposed through a storage contact hole 344 passing through the second lower interlayer insulating layer 305b, the upper buffer layer 307, the upper gate insulating layer 337, and the upper interlayer insulating layer 308 to be connected to the storage supply line 343. Figure 4 As shown, the storage upper electrode 342 is spaced apart from the light blocking layer 336, but they may be integrally formed to be connected to each other. The storage supply line 343 may be formed of the same material on the same plane as the first source electrode 321 and the first drain electrode 324 and the second source electrode 331 and the second drain electrode 334. Due to this fact, the storage supply line 343 may be formed simultaneously with the first source electrode 321 and the first drain electrode 324 and the second source electrode 331 and the second drain electrode 334 using the same mask process.

[0128] When an inorganic insulating material such as SiNx or SiOx is deposited on the entire surface of the substrate 301 on which the first source electrode 321 and the first drain electrode 324, the second source electrode 331 and the second drain electrode 334, and the storage supply line 343 are formed, the protective layer 309 may be formed. The first planarization layer 311 may be formed on the substrate 301 on which the protective layer 309 is formed. Specifically, when an organic insulating material such as an acrylic resin is applied to the entire surface of the substrate 301 on which the protective layer 309 is formed, the first planarization layer 311 may be provided. However, the embodiments of the present disclosure are not limited thereto.

[0129] After providing the protective layer 309 and the first planarization layer 311, a contact hole exposing the first source electrode 321 or the first drain electrode 324 of the first transistor 320 may be formed by a photolithography process. The connection electrode 345 may be provided in a region of the contact hole exposing the first drain electrode 324.

[0130] The connection electrode 345 may be a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or an alloy thereof, but the embodiments of the present disclosure are not limited thereto.

[0131] The connection electrode 345 may have a three-layer structure. The connection electrode 345 may be sequentially composed of a first connection electrode layer 345a, a second connection electrode layer 345b, and a third connection electrode layer 345c.

[0132] The first connection electrode layer 345a, the second connection electrode layer 345b, and the third connection electrode layer 345c may include materials having relatively different etching rates. The second connection electrode layer 345b may include a material having a relatively fast etching rate, and the first connection electrode layer 345a and the third connection electrode layer 345c may include a material having a relatively slow etching rate. For example, the second connection electrode layer 345b may include aluminum (Al) having a relatively fast etching rate, and the first connection electrode layer 345a and the third connection electrode layer 345c may include titanium (Ti) having a relatively slow etching rate. The connection electrode 345 may have a three-layer structure of Ti / Al / Ti. However, the embodiments of the present disclosure are not limited thereto.

[0133] The second planarization layer 312 may be disposed on the connection electrode 345 , and by forming a contact hole exposing the connection electrode 345 in the second planarization layer 312 , the light emitting element 350 connected to the first transistor 320 may be disposed.

[0134] The light emitting element 350 may include a first electrode 351 connected to the first drain electrode 324 of the first transistor 320 , at least one light emitting stack 352 formed on the first electrode 351 , and a second electrode 353 formed on the light emitting stack 352 .

[0135] The light-emitting stack 352 may include a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer. However, the embodiments of the present disclosure are not limited thereto. In a series structure in which a plurality of light-emitting layers overlap, a charge generation layer may be additionally disposed between the light-emitting layer and the light-emitting layer. In the case of a light-emitting layer, there may be a situation in which the light-emitting layer emits different colors for each sub-pixel. For example, a light-emitting layer for red, a light-emitting layer for green, and a light-emitting layer for blue may be formed for each sub-pixel, respectively. However, a common light-emitting layer may be formed to emit white light in each sub-pixel without color differentiation, and a color filter for distinguishing colors may be provided separately. Thus, RGB type (real RGB type) and WOLED (white OLED) may be classified. Each light-emitting layer may be formed separately, but the injection layer and the transport layer may be provided as a common layer and disposed in each sub-pixel in the same manner.

[0136] The first electrode 351 may be connected to the connection electrode 345 exposed by the contact hole passing through the second planarization layer 312. The first electrode 351 may be formed into a multilayer structure including a transparent conductive layer and an opaque conductive layer having high reflection efficiency. The transparent conductive layer may be made of a material having a relatively high work function value, such as indium tin oxide (ITO) or indium zinc oxide (IZO), and the opaque conductive layer may be made of a single layer or multilayer structure including Al, Ag, Cu, Pb, Mo, Ti or an alloy thereof. However, the embodiments of the present disclosure are not limited thereto. For example, the first electrode 351 may be formed into a structure in which a transparent conductive layer, an opaque conductive layer and a transparent conductive layer are sequentially stacked, or may be formed into a structure in which a transparent conductive layer and an opaque conductive layer are sequentially stacked. Since the first electrode 351 is disposed on the second planarization layer 312 to overlap not only the light emitting area defined by the bank 354, but also the pixel circuit area in which the first transistor 320 and the second transistor 330 and the storage capacitor 340 are disposed, the light emitting area may be increased. The first electrode 351 may be an anode electrode. However, the embodiments of the present disclosure are not limited thereto.

[0137] The light emitting stack 352 may be formed as a hole transport layer, an organic light emitting layer, and an electron transport layer stacked in this order or in reverse order on the first electrode 351. The light emitting stack 352 may further include a charge generation layer, or may include first and second light emitting stacks facing each other with the charge generation layer interposed therebetween. However, the embodiments of the present disclosure are not limited thereto.

[0138] The bank 354 may be formed to expose the first electrode 351. The bank 354 may be made of an organic material such as photo acrylic and may be a translucent material, but the embodiments of the present disclosure are not limited thereto and may be made of an opaque material to prevent light interference between sub-pixels. A spacer may be formed on the bank 354. The spacer may include an organic insulating material. The spacer may include the same material as the bank 354. The bank 354 and the spacer may be formed together in a mask process using a half-tone mask or the like. In another embodiment, the spacer may include a material different from the bank 354.

[0139] The second electrode 353 may be formed on the upper surface of the light emitting stack 352 to face the first electrode 351 with the light emitting stack 352 interposed therebetween. When applied to a top emission type organic light emitting display device, the second electrode 353 may be formed as a transparent conductive layer by forming a thin indium tin oxide (ITO), indium zinc oxide (IZO) or magnesium silver (Mg-Ag). However, the embodiments of the present disclosure are not limited thereto.

[0140] A capping layer 355 may be disposed on the second electrode 353 .

[0141] The cover layer 355 can be used to protect the light emitting element 350 and help the light generated in the light emitting stack 352 to be effectively emitted to the outside. For example, the cover layer 355 can be made of an inorganic material or an organic material to prevent the light emitted from the light emitting stack 352 to the outside from being lost through total reflection. The cover layer 355 can be made of an organic material or an inorganic material to prevent the introduction of moisture and oxygen.

[0142] The capping layer 355 may include a single layer or multiple layers. For example, the capping layer 355 may be formed as a single layer of an organic capping layer including an organic material or an inorganic capping layer including an inorganic material, or may be formed as a multilayer in which an organic capping layer and an inorganic capping layer are alternately deposited. When the capping layer 355 is formed as a multilayer, the organic capping layer and the inorganic capping layer may be sequentially formed on the second electrode 353. However, the embodiments of the present disclosure are not limited thereto.

[0143] The organic capping layer may include a material constituting any one layer of the light emitting stack 352. For example, the organic capping layer may be formed using a material selected from a host material of the light emitting layer and a material constituting a hole transport layer or an electron transport layer, or may be formed using a single organic material.

[0144] In order to increase the transmittance of light from the light emitting stack 352, the inorganic capping layer may be formed using materials such as LiF, LiO, MgF2, NaF, CaO, KF, Bi2S3, Na5Al3F14, and SiO2, but the embodiments of the present disclosure are not limited thereto.

[0145] An encapsulation layer 360 for protecting the light emitting element 350 may be formed on the cover layer 355. Due to the organic nature of the light emitting stack 352, the light emitting element 350 may react with external moisture or oxygen, resulting in dark spots or pixel shrinkage. To prevent this, the encapsulation layer 360 may be disposed on the cover layer 355.

[0146] The encapsulation layer 360 may have a single-layer structure or a multi-layer structure. Figure 4 As shown, the encapsulation layer 360 may include a first encapsulation layer 361, a second encapsulation layer 362, and a third encapsulation layer 363. However, the embodiments of the present disclosure are not limited thereto.

[0147] The encapsulation layer 360 may include an inorganic layer including an inorganic insulating material. The encapsulation layer 360 may include an organic layer including an organic material. The encapsulation layer 360 may include an inorganic layer and an organic layer.

[0148] For example, the first encapsulation layer 361 and the third encapsulation layer 363 may be inorganic layers, and the second encapsulation layer 362 may be an organic layer. Among the first encapsulation layer 361, the second encapsulation layer 362, and the third encapsulation layer 363, the second encapsulation layer 362 may be the thickest. According to this fact, the second encapsulation layer 362 may be used as a planarization layer. The first encapsulation layer 361 is also referred to as a first inorganic encapsulation layer, the second encapsulation layer 362 is also referred to as an organic encapsulation layer, and the third encapsulation layer 363 is also referred to as a second inorganic encapsulation layer. However, the embodiments of the present disclosure are not limited thereto.

[0149] The first encapsulation layer 361 may be disposed on the capping layer 355 and may be disposed closest to the light emitting element 350. The first encapsulation layer 361 may be formed of an inorganic insulating material capable of low temperature deposition. For example, the first encapsulation layer 361 may be silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3). However, the embodiments of the present disclosure are not limited thereto. Since the first encapsulation layer 361 is deposited in a low temperature atmosphere, the first encapsulation layer 362 may prevent the light emitting stack 352 including an organic material susceptible to a high temperature atmosphere from being damaged during the deposition process.

[0150] The second encapsulation layer 362 may be formed to have a smaller area than the first encapsulation layer 361. In this case, the second encapsulation layer 362 may be formed to expose both ends of the first encapsulation layer 361. The second encapsulation layer 362 may be used to perform a buffer function to alleviate the interlayer stress caused by the warping of the display device 100, and may also be used to enhance the planarization performance. The second encapsulation layer 362 may be referred to as a foreign matter compensation layer. For example, the second encapsulation layer 362 may include an acrylic resin, an epoxy resin, a polyimide, a polyethylene, or a silicon oxide (SiOC), and may be formed of an organic insulating material. However, the embodiments of the present disclosure are not limited thereto. For example, the second encapsulation layer 362 may be formed using an inkjet method.

[0151] The third encapsulation layer 363 may be formed on the substrate 301 formed with the second encapsulation layer 362 to cover the upper surface and the side surface of each of the second encapsulation layer 362 and the first encapsulation layer 361. The third encapsulation layer 363 may minimize or prevent external moisture or oxygen from penetrating into the first encapsulation layer 361 and the second encapsulation layer 362. For example, the third encapsulation layer 363 is formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3). However, the embodiments of the present disclosure are not limited thereto.

[0152] The materials of the first encapsulation layer 361 and the third encapsulation layer 363 may be different from each other. The thicknesses of the first encapsulation layer 361 and the third encapsulation layer 363 may be different from each other. The thickness of the first encapsulation layer 361 may be greater than the thickness of the third encapsulation layer 363. Alternatively, the thickness of the third encapsulation layer 363 may be greater than the thickness of the first encapsulation layer 361, or the thicknesses of the first encapsulation layer 362 and the third encapsulation layer 363 may be the same as each other.

[0153] Figure 5 is along Figure 3 An example of a cross-sectional view taken along line II-II'. For example, Figure 5 It is shown Figure 3 In the following description, the cross-sectional structure of the optical region OA will be omitted or simply described. Figures 1 to 4 Describes the same or similar content.

[0154] refer to Figure 3 and Figure 5 In the display device 100 according to the embodiment of the present disclosure, the optical area OA may include the through hole TH and the HiAA frame area HBA, and the display area AA may be located outside the HiAA frame area HBA. The HiAA frame area HBA may be the non-display area NA.

[0155] Observing the cross section of the HiAA frame area HBA, various insulating layers present in the display area AA and the HiAA frame area HBA may be provided. For example, a buffer layer 302, a lower interlayer insulating layer 305, an upper buffer layer 307, and an upper interlayer insulating layer 308 may be sequentially stacked on the substrate 301. However, the embodiments of the present disclosure are not limited thereto.

[0156] Reference Figure 3 and Figure 5 , the dam area 200 including a 'dam structure' such as a dam may be located between the display area AA and the through hole TH.

[0157] The dam structure may have a layer structure of at least two layers formed perpendicularly to the substrate 301. For example, the dam structure may include a first layer formed by the planarization layer 310 and a second layer formed by the dam 354. Specifically, the dam structure may include a first layer formed by the second planarization layer 312 and a second layer formed by the dam 354. The dam structure may include a first layer formed by the second planarization layer 312, a second layer formed by the dam 354, and a third layer formed by a spacer. The dam structure may have a structure further including a first planarization layer 311 below the second planarization layer 312, or a structure stacked to further include another layer. However, the embodiments of the present disclosure are not limited thereto.

[0158] The bank region 200 may include at least one bank. For example, in the bank region 200, a first bank 230, a second bank 220, and a third bank 210 may be sequentially arranged adjacent to the display region AA between the display region AA and the through hole TH.

[0159] Reference Figure 5 In the HiAA frame region HBA as the non-display region NA, the light emitting stack 352 may be disposed on the upper interlayer insulating layer 308 as an insulating layer. The light emitting stack 352 may also be disposed on the dams 210, 220, and 230 disposed in the dam region 200. The light emitting stack 352 may be an organic light emitting stack. However, the embodiments of the present disclosure are not limited thereto.

[0160] The second electrode 353 may extend from the display area AA to the HiAA bezel area HBA as the non-display area NA, and may be disposed on the light emitting stack 352. The second electrode 353 may be a cathode electrode. However, the embodiments of the present disclosure are not limited thereto.

[0161] The electrode patterned material layer 420 capable of improving light transmittance may be disposed in the HiAA border area HBA. The electrode patterned material layer 420 may be disposed on the light emitting stack 352, and may be disposed to extend from one end of the second electrode 353 to the through hole TH. One end of the electrode patterned material layer 420 and one end of the light emitting stack 352 may be disposed to coincide. However, the embodiments of the present disclosure are not limited thereto.

[0162] The electrode patterning material layer 420 may be formed using an electrode patterning material (EPM) including an organic material. For example, the electrode patterning material layer 420 may be formed by depositing the electrode patterning material (EPM) using a fine metal mask (FMM) to cover at least a portion of the HiAA border area HBA. For example, as the electrode patterning material, Ir(ppy)3 (tris(2-phenylpyridine)iridium(III)) may be used. However, the embodiments of the present disclosure are not limited thereto.

[0163] The electrode patterning material (EPM) may be used to improve the light transmittance of the optical area OA while effectively patterning the second electrode 353 formed on the entire surface of the display area AA and a portion of the non-display area NA.

[0164] After forming the electrode patterning material (EPM) in the optical area OA using the FMM, the second electrode 353 is deposited on the entire surface of the display area AA and a portion of the non-display area NA using the open metal mask (OMM), and the second electrode 353 can be effectively formed on the entire surface of the display area AA and the portion of the non-display area NA except the electrode patterning material (EPM). Therefore, the electrode patterning material layer 420 and the second electrode 353 can be located on the same plane.

[0165] The thickness of the second electrode 353 may be not less than the thickness of the electrode patterning material layer 420. For example, the thickness of the second electrode 353 may be the same as the thickness of the electrode patterning material layer 420, or may be greater than the thickness of the electrode patterning material layer 420.

[0166] For example, after the electrode patterning material layer 420 is formed by depositing an electrode patterning material (EPM) on the light emitting stack 352 of the optical area OA using an FMM, in the case where a metal material as the second electrode 353 is completely deposited, since the metal material is not deposited on the electrode patterning material layer 420, the second electrode 353 may be selectively formed only on the entire surface of the display area AA and the light emitting stack 352 of the non-display area NA except the electrode patterning material layer 420. However, the embodiments of the present disclosure are not limited thereto.

[0167] Since the electrode patterning material (EPM) itself has low surface energy or low adhesion characteristics, the interface energy between the metal and the electrode patterning material layer 420 is very high, so when the metal is deposited, the probability of metal desorption on the surface of the electrode patterning material layer 420 is significantly increased, and metal nucleation does not occur. Therefore, since the metal is selectively deposited only in the high adhesion area with relatively low interface energy, a self-aligned patterned metal can be formed.

[0168] Reference Figure 5 , the light emitting stack 352 and the electrode patterned material layer 420 may be arranged by sequentially stacking in the HiAA border area HBA. For example, the light emitting stack 352 and the electrode patterned material layer 420 may be arranged by sequentially stacking on the dams 210, 220, and 230 located in the dam area 200. The light emitting stack 352 and the electrode patterned material layer 420 may be arranged by sequentially stacking between the display area AA and the first dam 230. The light emitting stack 352 and the electrode patterned material layer 420 may be arranged by sequentially stacking between the dams 210, 220, and 230 in the dam area 200. The light emitting stack 352 and the electrode patterned material layer 420 may be arranged by sequentially stacking between the third dam 210 and the through hole TH.

[0169] At least one groove may be provided between the display area AA and the through hole TH. The groove may be formed when each of the light emitting stack 352 and the electrode patterning material layer 420 is cut.

[0170] The groove 434 may be located between the display area AA and the bank area 200. For example, the groove 434 may be located between the display area AA and the first bank 230.

[0171] The groove may be located between the banks. For example, the groove 433 may be located between the first bank 230 and the second bank 220 , and the groove 432 may be located between the second bank 220 and the third bank 210 .

[0172] The groove 431 may be located between the bank region 200 and the through hole TH. For example, the groove 431 may be provided between the third bank 210 and the through hole TH.

[0173] The grooves 431 , 432 , 433 , and 434 may be formed when each of the light emitting stack 352 and the electrode patterning material layer 420 is cut.

[0174] Reference Figure 5When the grooves 431, 432, 433, and 434 are not formed, the light emitting stack 352 may be disposed to extend to the through hole TH. Therefore, the light emitting stack 352 may become a lateral moisture penetration path on the cut surface of the through hole TH and may cause a rising phenomenon due to moisture penetration.

[0175] Reference Figure 5 , when the light emitting stack 352 is cut at the grooves 431 , 432 , 433 , and 434 , a moisture penetration path of the light emitting stack 352 may be blocked, and thus, lateral moisture penetration due to the lifting phenomenon may be prevented or reduced.

[0176] At the grooves 431 , 432 , 433 , and 434 , one end of the electrode patterning material layer 420 and one end of the light emitting stack 352 may be arranged to coincide with each other. However, the embodiments of the present disclosure are not limited thereto.

[0177] Reference Figure 5 , the capping layer 355 may be disposed on the second electrode 353 and the electrode patterning material layer 420. The capping layer 355 may be cut at the grooves 431, 432, 433, and 434.

[0178] In other words, each of the light emitting stack 352, the electrode patterning material layer 420, and the cover layer 355 may be cut at the grooves 431, 432, 433, and 434. At the grooves 431, 432, 433, and 434, one end of the light emitting stack 352, one end of the electrode patterning material layer 420, and one end of the cover layer 355 may be arranged to overlap.

[0179] The encapsulation layer 360 may be disposed on the cover layer 355 .

[0180] The encapsulation layer 360 may contact the upper interlayer insulating layer 308 as an insulating layer without being cut at the grooves 431 , 432 , 433 , and 434 .

[0181] The encapsulation layer 360 may be a single layer or multiple layers.

[0182] For example, the encapsulation layer 360 may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer. The first encapsulation layer and the third encapsulation layer may be inorganic layers, and the second encapsulation layer may be an organic layer. That is, the first encapsulation layer may be a first inorganic encapsulation layer 361, the second encapsulation layer may be an organic encapsulation layer 362, and the third encapsulation layer may be a second inorganic encapsulation layer 363.

[0183] The first inorganic encapsulating layer 361 may contact the upper interlayer insulating layer 308 as an insulating layer without being cut at the grooves 431 , 432 , 433 , and 434 .

[0184] The organic encapsulating layer 362 may be disposed between the first inorganic encapsulating layer 361 and the second inorganic encapsulating layer 363. The organic encapsulating layer 362 may be disposed between the display area AA and the first bank 230.

[0185] The first and second inorganic encapsulating layers 361 and 363 may be disposed in contact with each other around the first bank 230 and extend to the through hole TH.

[0186] The first and second inorganic encapsulating layers 361 and 363 may be disposed to be exposed to the through holes TH.

[0187] refer to Figure 5 , the lower shield metal 410 may be disposed between the substrate 301 and the buffer layer 302 as an insulating layer.

[0188] One end of the lower shield metal 410 may be disposed to overlap the electrode patterning material layer 420, and the other end of the lower shield metal 410 may be arranged to overlap the second electrode 353. For example, one end of the lower shield metal 410 may be located between one end of the second electrode 353 and the groove 434.

[0189] Figure 6 is along Figure 3 Another example of a cross-sectional view taken along line II-II'. For example, Figure 6 It is shown Figure 3 FIG. 1 is another example of a cross-sectional structure of an optical region OA of FIG. In the following description, the cross-sectional structure of the optical region OA of FIG. 1 is omitted or simply described in the above reference. Figures 1 to 5 Describes the same or similar content.

[0190] Reference Figure 6 ,and Figure 5 Compared to the example of the cross section shown in FIG. 1 , there is a difference in the arrangement of the first inorganic encapsulating layer 361 and the second inorganic encapsulating layer 363 only in the region of the through hole TH, and thus, description of other configurations will be omitted.

[0191] refer to Figure 6 The organic encapsulating layer 362 may be disposed between the first inorganic encapsulating layer 361 and the second inorganic encapsulating layer 363 . The organic encapsulating layer 362 may be disposed between the display area AA and the first bank 230 .

[0192] The first inorganic encapsulation layer 361 and the second inorganic encapsulation layer 363 may be disposed in contact with each other around the first dam 230 and extend to the through hole TH. The second inorganic encapsulation layer 363 may cover one end of the first inorganic encapsulation layer 361 at the through hole TH. For example, one end 363a of the second inorganic encapsulation layer 363 may cover one end of the first inorganic encapsulation layer 361 at the through hole TH.

[0193] In various embodiments of the present disclosure, the number, size, arrangement and shape of the grooves 431, 432, 433 and 434 may vary. Figure 5 and Figure 6 As shown in the figure, the number of grooves can be 4, but the embodiments of the present disclosure are not limited thereto. For example, the number of grooves can be greater than 4 or less than 4. Figure 5 and Figure 6 In the illustrated embodiment, the number of grooves 431, 432, 433 and 434 is set to be one more than the number of dams 210, 220 and 230, but in other embodiments, the number of grooves may be the same as, greater than, or less than the number of dams.

[0194] Furthermore, the size of one or more of the grooves 431, 432, 433, and 434 may vary. Figure 5 and Figure 6 , the size of each of the grooves 431, 432, 433 and 434 is shown as being smaller than the width of the interval between adjacent dams. For example, the groove 433 is shown as being narrower than the interval or recess between the first baffle 230 and the second baffle 220. In this regard, the other grooves 434, 432 and 431 are shown as having the same or similar width or size. However, the embodiments of the present disclosure are not limited thereto. For example, the width or size of one or more of the grooves 431, 432, 433 and 434 may be the same as the interval or recess between adjacent dams (such as the first dam 230 and the second dam 220). In this case, the groove 433 may extend from the planarization layer 310 at the first dam 230 to the planarization layer 310 at the second dam 220. One or more of the other grooves 434, 432 and 431 may have the same or similar width or size as the groove 433.

[0195] Furthermore, the arrangement of one or more grooves 431, 432, 433, and 434 may vary. Figure 5 and Figure 6 , showing a groove between adjacent dams. For example, between the adjacent first dam 230 and the second dam 220, there is a groove 433. However, the embodiments of the present disclosure are not limited thereto. For example, there may be two or more grooves between the first dam 230 and the second dam 220 and between the other dams. In other embodiments, any one of the grooves 431, 432, 433, and 434 may be formed as a plurality of grooves, while the rest may be formed as a single groove. In other embodiments of the present disclosure, there may be a plurality of grooves between a first pair of dams (e.g., the first dam 230 and the second dam 220), but there may be no groove between the second dam 200 and the third dam 210. In other embodiments of the present disclosure, each of the grooves 434 and 431 may be a plurality of grooves.

[0196] In addition, the shapes of the grooves 431, 432, 433 and 434 may vary. Figure 3 , Figure 5 and Figure 6 , the shape of the grooves 431, 432, 433 and 434 in the plan view may be circular, or may correspond to the shape of the through hole, but the embodiments of the present disclosure are not limited thereto. For example, the shape of one or more of the grooves 431, 432, 433 and 434 in the plan view does not need to be a smooth curve, but may be wavy, or may have other shapes at one of the outer wall and the inner wall of the grooves 431, 432, 433 and 434, such as a herringbone, a square wave, a semicircle or other shapes, but the embodiments of the present disclosure are not limited thereto.

[0197] Reference Figure 5 , Figure 6 and Figure 7 The number, size, arrangement, and shape of the sacrificial layer 440 may correspond to the number, size, arrangement, and shape of the grooves 431 , 432 , 433 , and 434 .

[0198] Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig. 12A and Fig. 12B is a diagram illustrating a process of forming an optical area of ​​a display panel according to an embodiment of the present disclosure.

[0199] Reference Figure 7 , a sacrificial layer 440 and banks 210 ′, 220 ′, and 230 ′ may be formed on the substrate 301 in the non-display area NA.

[0200] For example, the lower shield metal 410 may be disposed on the substrate 301 .

[0201] A plurality of insulating layers may be provided on the substrate 301 and the lower shield metal 410. For example, a buffer layer 302, a lower interlayer insulating layer 305, an upper buffer layer 307, and an upper interlayer insulating layer 308 may be provided. On the upper interlayer insulating layer 308, a planarization layer 310 may be formed by patterning.

[0202] The sacrificial layer 440 is formed by patterning a metal material on the upper interlayer insulating layer 308. The sacrificial layer 440 may be formed of the same material as the first electrode material. However, the embodiments of the present disclosure are not limited thereto.

[0203] The banks 210', 220' and 230' may be formed by patterning the bank 354 on the planarization layer 310. The light emitting stack 352 may be formed on the bank 354, the upper interlayer insulating layer 308, the sacrificial layer 440 and the banks 210', 220' and 230' to cover the sacrificial layer 440 and the banks 210', 220' and 230'.

[0204] Reference Figure 8 , an electrode patterning material layer 420 may be formed on the light emitting stack using an electrode patterning material (EPM) to be located in the HiAA border area HBA as the non-display area NA. The electrode patterning material (EPM) may be deposited using FMM to cover at least a portion of the HiAA border area HBA. The electrode patterning material layer 420 may be formed to overlap the lower shielding metal 410.

[0205] Reference Fig. 9 , a second electrode 353 may be formed on the light emitting stack 352 to contact the electrode patterning material layer 420 by depositing metal on the entire surface of the display area AA and a portion of the non-display area NA using an OMM. The second electrode 353 may be effectively formed on the entire surface of the display area AA and a portion of the non-display area NA, which is a region other than the electrode patterning material layer 420. Therefore, the electrode patterning material layer 420 and the second electrode 353 may be located on the same plane.

[0206] Reference Fig.10 , the capping layer 355 may be, for example, completely formed on the second electrode 353 and the electrode patterning material layer 420. However, the embodiments of the present disclosure are not limited thereto.

[0207] Reference Fig.11 , the grooves 431', 432', 433', and 434' can be formed by irradiating the laser 500 from the lower side of the substrate 301 to the sacrificial layer 440. The laser 500 can travel from the lower surface of the substrate 301 in the thickness direction of the substrate 301, and can irradiate the lower surface of the sacrificial layer 440. The laser 500 can have an infrared wavelength. However, the embodiments of the present disclosure are not limited thereto. When the laser 500 is infrared, the transmittance of the laser 500 to the substrate 301 and the insulating layers 302, 305, 307, and 308 is high, and therefore, the laser 500 can effectively reach the sacrificial layer 440.

[0208] The sacrifice layer 440 may absorb the laser 500, and thermal expansion of the sacrifice layer 440 occurs. Therefore, the sacrifice layer 440 irradiated with the laser 500 may be peeled off from the insulating layers 302, 305, 307, and 308.

[0209] As the sacrificial layer 440 is stripped, the light emitting stack 352, the electrode patterning material layer 420, and the capping layer 355 disposed on the stripped sacrificial layer 440 may also be removed together with the sacrificial layer 440. Thus, grooves 431', 432', 433', and 434' defined by openings of the light emitting stack 352, the electrode patterning material layer 420, and the capping layer 355 may be formed.

[0210] The lower shield metal 410 may be located between one end of the second electrode 353 and one end of the sacrificial layer 440. Since one end of the lower shield metal 410 is located between one end of the second electrode 353 and one end of the sacrificial layer 440, the lower shield metal 410 may prevent the laser 500 from being irradiated to the second electrode 353 even when the laser 500 is irradiated from the lower surface of the substrate 310. Therefore, by reducing the distance between the second electrode 353 and the grooves 431', 432', 433', and 434', the width of the HiAA bezel area HBA may be reduced.

[0211] Reference Fig. 12A , after forming the grooves 431', 432', 433', and 434', the first inorganic encapsulation layer 361, the organic encapsulation layer 362, and the second inorganic encapsulation layer 363 may be formed in a stacking order. In this case, the first inorganic encapsulation layer 361 and the second inorganic encapsulation layer 363 may be formed to extend to the region of the through hole TH. Thereafter, the through hole TH may be formed along the trimming line using a laser. The first inorganic encapsulation layer 361 and the second inorganic encapsulation layer 363 may be disposed to be exposed to the through hole TH.

[0212] Reference Fig. 12B , after forming the grooves 431', 432', 433' and 434', the first inorganic encapsulation layer 361, the organic encapsulation layer 362 and the second inorganic encapsulation layer 363 are sequentially formed by stacking. In this case, the first inorganic encapsulation layer 361 may be formed to not extend to the region of the through hole TH, and the second inorganic encapsulation layer 363 may be formed to extend to the region of the through hole TH to form a region 363a surrounding the first inorganic encapsulation layer 361. Thereafter, the through hole TH may be formed along the trimming line using a laser. One end 363a of the second inorganic encapsulation layer 363 may be formed to cover one end of the first inorganic encapsulation layer 361 at the through hole TH.

[0213] Reference Figures 5 to 12BOnce the sacrificial layer 440 is stripped to remove the light emitting stack 352, the electrode patterning material layer 420, and the capping layer 355, portions of the upper interlayer insulating layer 308 are exposed at the grooves 431, 432, 433, and 434. Thereafter, once the first encapsulation layer 361 and the third encapsulation layer 363 are formed in the grooves 431, 432, 433, and 434, a sealing structure of multiple stacked inorganic layers may be formed. The sealing structure may include two or more of the upper interlayer insulating layer 308, the first encapsulation layer 361, and the third encapsulation layer 363 in direct contact.

[0214] Two or more of the upper interlayer insulating layer 308, the first encapsulation layer 361 and the third encapsulation layer 363 may include the same material or be formed of the same material, such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiO2) or aluminum oxide (Al2O3), but the embodiments of the present disclosure are not limited thereto.

[0215] In various embodiments of the present invention, when two or more of the grooves 431, 432, 433 and 434 are covered by the first encapsulation layer 361 and the third encapsulation layer 353, they seal each portion of the light emitting stack 352, the electrode patterning material layer 420 and the covering layer 355 between the upper interlayer insulating layer 308 and the first encapsulation layer 362.

[0216] A brief description of the embodiments of the present disclosure described above is as follows.

[0217] According to an embodiment of the present disclosure, a display device may include a substrate, the substrate including a non-display area and a display area surrounding the non-display area, the non-display area including a through hole; an insulating layer arranged on the substrate; a light-emitting stack arranged on the insulating layer; a second electrode extending from the display area to the non-display area to be arranged on the light-emitting stack; and an electrode patterned material layer contacting one end of the second electrode and arranged on the light-emitting stack, wherein one end of the light-emitting stack and one end of the electrode patterned material layer are arranged to overlap.

[0218] The display device according to an embodiment of the present disclosure may include a dam disposed between the display area and the through hole.

[0219] In the display device according to the embodiment of the present disclosure, the light emitting stack and the electrode patterning material layer may be sequentially disposed on the bank.

[0220] The display device according to an embodiment of the present disclosure may include a groove between the display area and the bank, and each of the light emitting stack and the electrode patterning material layer is cut at the groove.

[0221] The display device according to an embodiment of the present disclosure may include a cover layer disposed on the second electrode and the electrode patterning material layer.

[0222] In the display device according to the embodiment of the present disclosure, the cover layer may be cut at the groove.

[0223] In the display device according to the embodiment of the present disclosure, the dam may include a plurality of dams which are disposed to be spaced apart from each other.

[0224] In a display device according to an embodiment of the present disclosure, the plurality of dams may include a first dam and a second dam, and the display device may include a groove located between the first dam and the second dam, and each of the light-emitting stack and the electrode patterning material layer is cut at the groove.

[0225] The display device according to an embodiment of the present disclosure may include a groove between the display area and the first bank, and each of the light emitting stack and the electrode patterning material layer is cut at the groove.

[0226] The display device according to an embodiment of the present disclosure may include a lower shield metal disposed between a substrate and an insulating layer, one end of the lower shield metal may overlap the electrode patterning material layer, and the other end of the lower shield metal may overlap the second electrode.

[0227] In the display device according to the embodiment of the present disclosure, one end of the lower shield metal may be located between one end of the second electrode and one end of the electrode patterning material layer.

[0228] The display device according to an embodiment of the present disclosure may include an encapsulation layer disposed on the cover layer, and the encapsulation layer may not be cut at the groove and contact the insulating layer.

[0229] In the display device according to the embodiment of the present disclosure, the encapsulation layer may include a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer, and the first inorganic encapsulation layer may not be cut at the groove and contact the insulating layer.

[0230] In the display device according to the embodiment of the present disclosure, the first inorganic encapsulation layer and the second inorganic encapsulation layer may be exposed to the through hole.

[0231] In the display device according to the embodiment of the present disclosure, the second inorganic encapsulation layer may cover one end of the first inorganic encapsulation layer at the through hole.

[0232] In the display device according to the embodiment of the present disclosure, the thickness of the second electrode may be not less than the thickness of the electrode patterning material layer.

[0233] According to an embodiment of the present disclosure, a display device may include a substrate, the substrate including a non-display area and a display area surrounding the non-display area, the non-display area including a through hole; an insulating layer arranged on the substrate; a plurality of dams located between the display area and the through hole and arranged on the insulating layer; a light-emitting stack arranged on the insulating film and the plurality of dams; a second electrode extending from the display area to the non-display area to be arranged on the light-emitting stack; an electrode patterned material layer contacting one end of the second electrode and arranged on the light-emitting stack; and a groove cutting each of the light-emitting stack and the electrode patterned material layer.

[0234] In the display device according to the embodiment of the present disclosure, the groove may be provided in at least one of a region between the display region and the plurality of banks, a region between the plurality of banks, and a region between the plurality of banks and the through hole.

[0235] The display device according to an embodiment of the present disclosure may include a cover layer disposed on the second electrode and the electrode patterning material layer, and the cover layer may be cut at the groove.

[0236] The display device according to the embodiment of the present disclosure may include a lower shield metal disposed between the substrate and the insulating layer, and one end of the lower shield metal may be located between one end of the second electrode and one end of the electrode patterning material layer.

[0237] In the display device according to the embodiment of the present disclosure, the encapsulation layer may be disposed on the cover layer, the encapsulation layer may include a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer, and the first inorganic encapsulation layer may not be cut at the groove and contact the insulating layer.

[0238] In the display device according to the embodiment of the present disclosure, the thickness of the second electrode may be not less than the thickness of the electrode patterning material layer.

[0239] According to an embodiment of the present disclosure, a method for manufacturing a display device may include forming a substrate including a display area and a non-display area, forming a sacrificial layer and a dam in the non-display area, forming a light-emitting stack to cover the sacrificial layer and the dam, forming an electrode patterned material layer on the light-emitting stack to be located in the non-display area, forming a second electrode on the light-emitting stack to contact the electrode patterned material layer, forming a covering layer on the second electrode and the electrode patterned material layer, and forming a groove by irradiating a laser to the sacrificial layer.

[0240] In the method of manufacturing a display device according to an embodiment of the present disclosure, when forming the groove, the light emitting stack may be cut at the groove.

[0241] In the method of manufacturing a display device according to an embodiment of the present disclosure, when forming the second electrode, the second electrode may be formed at the same layer as the electrode patterning material layer.

[0242] The method of manufacturing a display device according to an embodiment of the present disclosure may include forming an encapsulation layer to cover the cover layer and the groove.

[0243] In the method of manufacturing a display device according to an embodiment of the present disclosure, when forming an encapsulation layer, the encapsulation layer may include a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer, and the second inorganic encapsulation layer may be formed to cover the organic encapsulation layer and contact the first inorganic encapsulation layer.

[0244] In the method of manufacturing the display device according to an embodiment of the present disclosure, the second inorganic encapsulating layer may be formed to cover one end of the first inorganic encapsulating layer.

[0245] The display device and the manufacturing method thereof according to the embodiments of the present disclosure may block a lateral moisture permeation path due to the presence of the light emitting stack by patterning the light emitting stack.

[0246] The display device and the manufacturing method thereof according to the embodiments of the present disclosure may prevent or reduce a lateral moisture penetration path and micro cracks caused by the light emitting stack by patterning the light emitting stack and providing a dam structure.

[0247] The display device and the manufacturing method thereof according to the embodiments of the present disclosure can increase the lifespan by preventing or reducing lateral moisture penetration, thereby achieving low power consumption.

[0248] The above description is provided to enable any person skilled in the art to make and use the technical ideas of the present disclosure, and is provided in the context of specific applications and their requirements. Various modifications, additions, and substitutions to the described embodiments will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present disclosure. The above description and accompanying drawings provide examples of the technical ideas of the present disclosure for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical ideas of the present disclosure.

Claims

1. A display device, comprising: A substrate, the substrate comprising a display area having a through hole and a non-display area adjacent to the display area; an insulating layer, wherein the insulating layer is disposed on the substrate; A light emitting stack, wherein the light emitting stack is disposed on the insulating layer; an electrode extending from the display area to the non-display area and disposed on the light emitting stack; and an electrode patterning material layer, the electrode patterning material layer is in contact with one end of the electrode and is disposed on the light emitting stack, One end of the light emitting stack and one end of the electrode patterning material layer are arranged to overlap.

2. The display device according to claim 1, further comprising: A dam is provided between the display area and the through hole. 3 . The display device according to claim 2 , wherein the light emitting stack and the electrode patterning material layer are sequentially disposed on the bank.

4. The display device according to claim 3, further comprising: A groove is located between the display area and the dam, and each of the light emitting stack and the electrode patterning material layer is disconnected at the groove.

5. The display device according to claim 4, further comprising: A covering layer is disposed on the electrode and the electrode patterning material layer. The display device according to claim 5 , wherein the cover layer is disconnected at the groove. 7 . The display device according to claim 2 , wherein the bank comprises a plurality of banks, and the plurality of banks are disposed to be spaced apart from each other.

8. The display device according to claim 7, wherein the plurality of banks include a first bank and a second bank, and The display device further comprises: A first groove is provided, wherein the first groove is located between the first dam and the second dam, and each of the light emitting stack and the electrode patterning material layer is disconnected at the first groove.

9. The display device according to claim 8, further comprising: A second groove is located between the display area and the first bank, and each of the light emitting stack and the electrode patterning material layer is disconnected at the second groove.

10. The display device according to claim 1, further comprising: a lower shielding metal disposed between the substrate and the insulating layer, One end of the lower shielding metal overlaps with the electrode patterning material layer, and the other end of the lower shielding metal overlaps with the electrode. 11 . The display device according to claim 10 , wherein the one end of the lower shielding metal is located between one end of the electrode and one end of the electrode patterning material layer.

12. The display device according to claim 5, further comprising: an encapsulation layer, the encapsulation layer being arranged on the covering layer, The encapsulation layer is not disconnected at the groove and contacts the insulating layer.

13. The display device according to claim 12, wherein: The encapsulation layer includes a first inorganic encapsulation layer, an organic encapsulation layer and a second inorganic encapsulation layer, and The first inorganic encapsulation layer is not disconnected at the groove and contacts the insulating layer. 14 . The display device of claim 13 , wherein the first inorganic encapsulation layer and the second inorganic encapsulation layer are exposed to the through hole. 15 . The display device of claim 13 , wherein the second inorganic encapsulating layer covers one end of the first inorganic encapsulating layer at the through hole.

16. The display device according to claim 1, wherein: The thickness of the electrode is not less than the thickness of the electrode patterning material layer.

17. A display device, comprising: A substrate, the substrate comprising a display area having a through hole and a non-display area adjacent to the display area; an inorganic insulating layer, wherein the inorganic insulating layer is located on the substrate; A light emitting stack, wherein the light emitting stack is located on the inorganic insulating layer; a common electrode extending from the display area to the non-display area and disposed on the light emitting stack; an electrode patterning material layer, the electrode patterning material layer being in contact with one end of the common electrode and being disposed on the light emitting stack; at least one groove formed in the light emitting stack and surrounding the through hole; and An inorganic encapsulation layer is located on the common electrode and in the at least one groove. 18 . The display device of claim 17 , wherein the inorganic insulating layer and the inorganic encapsulation layer are in direct contact in the at least one groove.

19. A method for manufacturing a display device, the method comprising: forming a substrate including a display area and a non-display area; forming a sacrificial layer and a bank in the non-display area; forming a light emitting stack to cover the sacrificial layer and the bank; forming an electrode patterning material layer on the light emitting stack to be located in the non-display area; forming a second electrode on the light emitting stack to contact the electrode patterning material layer; forming a covering layer on the second electrode and the electrode patterning material layer; and The grooves are formed by irradiating the sacrificial layer with laser. 20 . The method according to claim 19 , wherein when the groove is formed, the light emitting stack is cut at the groove. 21 . The method according to claim 19 , wherein when forming the second electrode, the second electrode is formed at the same layer as the electrode patterning material layer.

22. The method of claim 19, further comprising: An encapsulation layer is formed to cover the cover layer and the groove. 23 . The method of claim 22 , wherein when forming the encapsulation layer, the encapsulation layer comprises a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer, and the second inorganic encapsulation layer is formed to cover the organic encapsulation layer and contact the first inorganic encapsulation layer. 24 . The method of claim 23 , wherein the second inorganic encapsulation layer is formed to cover one end of the first inorganic encapsulation layer.

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