Silicon adapter plate structure of integrated memristor switch array and preparation method of silicon adapter plate structure

Abstract

The invention discloses a silicon adapter plate structure of an integrated memristor switch array and a preparation method of the silicon adapter plate structure, and belongs to the technical field of advanced packaging integrated chips. Preparing a memristor bottom electrode on the surface of the protective layer; preparing a memristor functional layer on the bottom electrode, and preparing a memristor top electrode on the memristor functional layer; preparing an interconnection insulating layer, and preparing an interconnection opening; and depositing a seed layer on the interconnection opening, and preparing interconnection wiring. According to the invention, the switch array of the memristor is integrated in the silicon adapter plate, so that after the silicon adapter plate is prepared or the core particles are integrated with the silicon adapter plate, the resistance state of the memristor is changed by applying voltage to the memristor, the connection and disconnection of an interconnection circuit are controlled, and an interconnection circuit network in the core particle integration is changed; and the function switching of the integrated chip can be realized.

Description

Technical Field

[0001] The present invention belongs to the technical field of advanced packaged integrated chips, and in particular relates to a silicon adapter plate structure of an integrated memristor switch array and a preparation method thereof. Background Art

[0002] For existing silicon adapters used for advanced packaging integration, the circuit structure in the wiring layer of the silicon adapter is designed according to the integration requirements. After the silicon adapter manufacturing process is completed, the interconnection circuit of the silicon adapter cannot be changed. However, with the increasing demand for integrated chips with higher integration and higher intelligence, silicon adapters with multiple functions have become a hot topic. Among them, the silicon adapter with variable interconnection circuits can change the interconnection relationship between core particles after chip integration, which is conducive to the functional switching of integrated chips and systems. Memristor is currently a device that can realize resistance conversion, with a switching ratio of up to 10 7 -10 8 , and it has good compatibility with chip technology, and can be used as artificial neurons, switching devices, etc. At present, memristors are more than an independent electronic component, used to prepare memristor chips, such as patent CN101593810A discloses a nanostructure fast switching memristor and its manufacturing method, which can be used as an independent switching element, but it is difficult to implement in an integrated chip, and its preparation process is also difficult to integrate with 2.5D and 3D. For example, patent CN114203756A discloses a back-end integrated structure of a memristor unit and a CMOS circuit and its preparation method. By using a back-end process integration method based on the standard CMOS process, the hybrid integration of memristors and CMOS circuits is realized. However, for now, the preparation process of using memristors for advanced packaging integrated chips is still not perfect, and the molded products need to be further optimized in realizing the functional switching of the entire integrated chip. Summary of the invention

[0003] The present invention provides a silicon adapter plate structure of an integrated memristor switch array and a preparation method thereof, aiming to solve the problem that the preparation process of using memristors for advanced packaged integrated chips is still not perfect, and the molded products need to be further optimized in realizing the function switching of the entire integrated chip.

[0004] In order to achieve the above object, the present invention adopts the following technical scheme: A method for preparing a silicon adapter plate structure with an integrated memristor switch array comprises the following steps: S1, depositing a protective layer on the surface of the silicon adapter plate; S2, preparing a first photoresist mask layer on the surface of the protective layer, exposing the protective layer at the position where the memristor switch array is to be prepared and preparing a memristor bottom electrode, and removing the first photoresist mask layer; S3, preparing a memristor functional layer on the protective layer and the bottom electrode, then preparing a second photoresist mask layer, exposing the functional layer except the bottom electrode and removing the exposed functional layer, and then removing the second photoresist mask layer; S4, preparing a third photoresist mask layer on the memristor functional layer, exposing the memristor functional layer and preparing a memristor top electrode, and removing the third photoresist mask layer; S5, preparing an interconnection insulating layer on the outer layer of the protective layer and the top electrode of the memristor, and preparing an interconnection opening at a position where interconnection is required; S6. Depositing a seed layer on the interconnect opening, and preparing interconnect wiring by electroplating process, so as to realize electrical interconnection between the memristor switch array and external wires and silicon through vias.

[0005] In some embodiments, in S1, before depositing the protective layer, the silicon adapter plate for preparing the memristor switch array is subjected to surface planarization treatment; The roughness of the prepared area is controlled to be 1-10nm; The surface planarization process adopts chemical mechanical polishing or photolithography and plasma etching process. After the surface planarization, the wafer is cleaned with chemical reagents, deionized water or plasma.

[0006] In some embodiments, in S1, the material of the protective layer is SiO2, Si3N4 or polyimide.

[0007] In some embodiments, in S2, the memristor bottom electrode is prepared by electron beam evaporation or magnetron sputtering technology, and the memristor bottom electrode includes a bottom electrode adhesion layer and a bottom electrode functional layer, wherein: The material of the electrode adhesion layer is Ni, Ti, Cr or TiW, and the material of the bottom electrode functional layer is Au, Pt, Pd or Ru.

[0008] In some embodiments, in S3 , the material of the memristor functional layer is a transition metal oxide, a metal halide material, a two-dimensional material, or an organic material.

[0009] In some embodiments, in S3, the memristor functional layer is prepared by chemical vapor deposition, molecular beam epitaxy, atomic deposition or coating; The thickness of the memristor functional layer is controlled to be 1-100nm.

[0010] In some embodiments, in S3, after the memristor functional layer is prepared, the memristor functional layer is cleaned; Thermal oxidation, plasma treatment, electron beam irradiation, chemical doping, laser irradiation or ozone oxidation technology are used to dope, thin, induce oxidation and phase change the memristor functional layer.

[0011] In some embodiments, in S4, the memristor top electrode includes a top electrode functional layer and a top electrode conductive layer, the top electrode functional layer is made of Ti, Al, Ag or Cu, and the top electrode conductive layer is made of Au, Pd or Pt.

[0012] In some embodiments, in S5, the interconnection insulating layer is made of polyimide or silicon dioxide; In the case of using polyimide, spin coating and photolithography techniques are used to form interconnection openings for interconnecting with wires and through silicon vias; In the case of using silicon dioxide, chemical vapor deposition is used for preparation, a SiO2 etching photoresist mask layer is prepared using a photolithography process, and plasma etching is used to prepare interconnection openings.

[0013] The present invention also provides a silicon adapter plate structure of an integrated memristor switch array, which is prepared based on the preparation method of the silicon adapter plate structure of an integrated memristor switch array, and the silicon adapter plate structure includes a silicon adapter plate unit and a memristor switch array integrated on the silicon adapter plate unit, wherein: The memristor switch array includes a protection layer, a memristor bottom electrode, a memristor functional layer, a memristor top electrode and an interconnection insulating layer from the inside to the outside.

[0014] Compared with the prior art, the silicon adapter plate structure of the integrated memristor switch array and the preparation method thereof of the present invention have the following beneficial effects: The present invention discloses a method for preparing a silicon adapter plate structure with an integrated memristor switch array, which realizes the integration of a memristor-based switch array in a silicon adapter plate, so that after the silicon adapter plate is prepared, or after the core particle is integrated with the silicon adapter plate, in subsequent operations, by applying a voltage to the memristor, its configuration is changed, thereby controlling the conduction and disconnection of the interconnection line, changing the interconnection circuit network in the core particle integration, and facilitating the switching of the integrated chip function. The method of the present invention is adopted, which is conducive to reducing the volume of the device, improving the integration density, and facilitating integration and expansion on the existing production line. The present invention can optimize the electrical performance of the memristor by controlling the process steps, and enhance the reliability of the device by preparing structures such as a protective layer and an interconnection insulating layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The drawings in the specification are used to provide further understanding of the present invention and constitute a part of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute improper limitations on the present invention.

[0016] Figure 1 It is a schematic diagram of the structure after the conductive material is filled and the surface is smoothed in the method for preparing the silicon adapter plate structure of the integrated memristor switch array of the present invention; Figure 2 It is a structural schematic diagram of a method for preparing a silicon adapter plate structure of an integrated memristor switch array according to the present invention after a protective layer is prepared on the silicon adapter plate; Figure 3 It is a structural schematic diagram of a method for preparing a silicon adapter plate structure of an integrated memristor switch array according to the present invention after preparing a memristor bottom electrode; Figure 4 It is a top view schematic diagram of a memristor bottom electrode in a method for preparing a silicon adapter plate structure with an integrated memristor switch array according to the present invention; Figure 5 It is a structural schematic diagram after preparing a memristor functional layer on a bottom electrode in a method for preparing a silicon adapter plate structure of an integrated memristor switch array of the present invention; Figure 6 It is a structural schematic diagram of a method for preparing a silicon adapter plate structure of an integrated memristor switch array according to the present invention after selectively removing a memristor functional layer; Figure 7 It is a structural schematic diagram after preparing the memristor top electrode in a method for preparing a silicon adapter plate structure of an integrated memristor switch array of the present invention; Figure 8 It is a schematic top view of a memristor top electrode in a method for preparing a silicon adapter plate structure with an integrated memristor switch array according to the present invention; Fig. 9 It is a structural schematic diagram after preparing a memristor functional layer in a method for preparing a silicon adapter plate structure of an integrated memristor switch array of the present invention; Fig.10 It is a schematic structural diagram of a method for preparing a silicon adapter plate structure of an integrated memristor switch array according to the present invention after removing a protective layer on a filling conductive material; Fig.11 It is a structural schematic diagram of a method for preparing a silicon adapter plate structure of an integrated memristor switch array according to the present invention after preparing an interconnection insulating layer; Fig.12 It is a top view schematic diagram of a method for preparing a silicon adapter plate structure with an integrated memristor switch array according to the present invention after preparing an interconnection insulating layer; Fig.13 A schematic diagram of a silicon adapter plate structure with an integrated memristor switch array according to the present invention; Fig.14 It is a schematic diagram of the structure of a 2.5D integrated chip in the application of a silicon adapter plate structure with an integrated memristor switch array according to the present invention; Fig.15 The present invention is a schematic top view of a silicon adapter plate structure with an integrated memristor switch array, which realizes the conduction states of different interfaces by controlling the memristor switch array in application.

[0017] In the figure, 101, silicon substrate, 102, through silicon via, 103, insulating layer, 104, filling conductive material, 201, protective layer, 301, bottom electrode adhesion layer, 302, bottom electrode functional layer, 401, memristor functional layer, 501, top electrode functional layer, 502, top electrode conductive layer, 601, interconnection insulating layer, 602, interconnection opening, 701, Cu interconnection wiring, 702, multi-layer wiring layer, 703, interconnection pad, 801, core particle, 802, interconnection solder ball or micro bump. DETAILED DESCRIPTION

[0018] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0019] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0020] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0021] In the description of the embodiments of the present invention, it should be noted that if the terms "upper", "lower", "horizontal", "inner", etc. indicate an orientation or positional relationship based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the product of the invention is usually placed when in use, it is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. In addition, the terms "first", "second", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0022] In addition, if the term "horizontal" appears, it does not mean that the component must be absolutely horizontal, but can be slightly tilted. For example, "horizontal" only means that its direction is more horizontal than "vertical", which does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0023] In the description of the embodiments of the present invention, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "set", "install", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal connection of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0024] Based on this, the present invention provides a method for preparing a silicon adapter plate structure of an integrated memristor switch array, comprising the following steps: S1, depositing a protective layer on the surface of the silicon adapter plate; S2, preparing a first photoresist mask layer on the surface of the protective layer, exposing the protective layer at the position where the memristor switch array is to be prepared and preparing a memristor bottom electrode, and removing the first photoresist mask layer; S3, preparing a memristor functional layer on the protective layer and the bottom electrode, then preparing a second photoresist mask layer, exposing the functional layer except the bottom electrode and removing the exposed functional layer, and then removing the second photoresist mask layer; S4, preparing a third photoresist mask layer on the memristor functional layer, exposing the memristor functional layer and preparing a memristor top electrode, and removing the third photoresist mask layer; S5, preparing an interconnection insulating layer on the outer layer of the protective layer and the top electrode of the memristor, and preparing an interconnection opening at a position where interconnection is required; S6. Depositing a seed layer on the interconnect opening, and preparing interconnect wiring by electroplating process, so as to realize electrical interconnection between the memristor switch array and external wires and silicon through vias.

[0025] The present invention integrates a switch array of memristors on a silicon adapter board. In application, the local interconnection circuit in the integrated chip can be turned on and off under the control of voltage, thereby changing the interconnection relationship between different integrated core particles, which is further conducive to changing the function of an integrated chip composed of multiple core particles without changing the type and number of integrated core particles and most of the interconnection circuit structure, thereby achieving function switching. The product prepared by the method of the present invention is conducive to realizing 2.5D, 3D integrated chips and microelectronic systems with different function switching. At the same time, the convenient variable interconnection is conducive to the rapid manufacturing of integrated chips, and has certain application prospects in the field of advanced electronic packaging.

[0026] The memristor switch array in the present invention can be prepared on the front or back of the silicon adapter board, and can be located between the front and back multilayer wiring and the silicon substrate, or between the wiring layers of the multilayer wiring. Take the preparation of the memristor switch array between the silicon substrate and the wiring layer on the front of the silicon adapter board as an example.

[0027] like Figure 1-13 As shown, in some embodiments, a silicon adapter plate structure of an integrated memristor switch array and a preparation method thereof of the present invention are specifically as follows: S1: Preparation of conductive silicon vias. The surface of the silicon substrate 101 is cleaned. The cleaning may be, but not limited to, chemical reagents or deionized water. The silicon via 102 is prepared by a deep silicon etching process. The insulating layer 103 is prepared by one or more mixed processes such as thermal oxidation, atomic deposition, and chemical vapor deposition. The material of the insulating layer 103 may be, but not limited to, SiO2, Si3N4, polyimide (PI), etc. The conductive material 104 is prepared and filled in the silicon via 102 by physical vapor deposition, low-pressure chemical vapor deposition, electroplating, etc. The conductive material 104 may be copper, tungsten, polysilicon, etc. Finally, the surface is polished by chemical mechanical polishing.

[0028] S2: Surface planarization. The surface of the memristor switch array to be prepared is planarized. As an option, the roughness of the preparation area is ensured to be 1-10nm. The planarization method can use chemical mechanical polishing to polish the entire silicon substrate. Photolithography and plasma etching processes can also be used. By coating photoresist and performing exposure and development processes, only a local area of ​​the memristor switch array to be prepared is exposed, and this area is chemically corroded or plasma etched to reduce the surface roughness, and then the photoresist is removed. After the surface is planarized, the wafer is cleaned. The cleaning can be but is not limited to chemical reagents, deionized water cleaning, and plasma cleaning.

[0029] S3: Deposition of protective layer. Prepare a protective layer 201 on the silicon adapter. On the one hand, the protective layer 201 is used to protect the insulating layer 103 and the filling conductive material 104 on the silicon adapter to prevent corrosion and removal in subsequent processes. On the other hand, the protective layer 201 can be used as a stop layer in the material etching process in the subsequent process to prevent excessive etching and removal. The material of the protective layer 201 can be but not limited to insulating materials such as SiO2, Si3N4, PI, etc. As an option, the preparation method of the protective layer 201 can be but not limited to chemical vapor deposition, atomic deposition, material coating, etc.

[0030] S4: Preparation of memristor bottom electrode. Using photolithography technology, prepare a first photoresist mask layer on the surface of the protective layer 201, and expose the protective layer 201 only at the position where the memristor switch array needs to be prepared, and the rest of the positions are covered with the first photoresist mask layer. Subsequently, electron beam evaporation technology or magnetron sputtering technology is used to sequentially prepare the bottom electrode adhesion layer 301 and the bottom electrode functional layer 302. The bottom electrode adhesion layer 301 is used to increase the bonding force between the bottom electrode functional layer 302 and the protective layer 201, and can be but not limited to metal materials such as Ni, Ti, Cr, TiW, etc. The bottom electrode functional layer 302 is the bottom electrode that forms the memristor function, and its material can be but not limited to inert metal materials such as Au, Pt, Pd, Ru, etc. After preparing the bottom electrode, a degumming solution is used to remove the photoresist mask layer, and optionally, a chemical reagent cleaning or plasma cleaning is used to clean the surface to reduce photoresist residue.

[0031] S5: Preparation of functional layer based on memristor material. The memristor functional layer 401 is the key layer for forming the memristor characteristics. Its material may include but is not limited to transition metal oxides, metal halide materials, two-dimensional materials, organic materials, etc., and may be selected according to the performance requirements of the memristor switch in terms of switching ratio, response time, carrying current, etc. The thickness of the memristor functional layer 401 is generally controlled to be 1-100nm, and its preparation may be but is not limited to chemical vapor deposition, molecular epitaxy, coating and other technologies directly on the silicon adapter. For some preparation processes that require growth substrates or the growth process will damage the silicon adapter, it can be prepared on other substrates and then transferred to the surface of the silicon substrate using wafer-level transfer technology.

[0032] S6: Post-processing of the functional layer. After the preparation or transfer of the memristor functional layer 401, organic glue and other contaminants will remain on its surface, and it needs to be treated to improve the contact mechanics and electrical properties between the material and the top electrode. The treatment process includes chemical reagent cleaning, plasma cleaning, etc. In addition, in order to improve the switching ratio, response time, carrying current and other performance of the memristor, the lattice structure and element composition of the memristor functional layer 401 need to be regulated. The functional layer material can be doped, thinned, induced to oxidize and phase change, etc. by, but not limited to, thermal oxidation, plasma treatment, electron beam irradiation, chemical doping, laser irradiation, ozone oxidation and other technologies to improve the performance of the entire array of switching devices.

[0033] S7: Selective removal of the functional layer. A second photoresist mask layer is prepared using photolithography technology to protect the memristor functional layer 401 above and around the bottom electrode of the memristor. The excess material is removed using chemical corrosion and plasma etching processes. The protective layer 201 can ensure that the insulating layer 103 and the filled conductive material 104 are not damaged when the excess material is removed. The photoresist is then removed and the silicon adapter is cleaned.

[0034] S8: Preparation of memristor top electrode. Using photolithography technology, prepare a third photoresist mask layer on the protective layer 201 and the memristor functional layer 401. Only the memristor functional layer 401 is exposed, and the rest of the positions are covered with the third photoresist mask layer. Subsequently, electron beam evaporation technology or magnetron sputtering technology is used to sequentially prepare the top electrode functional layer 501 and the top electrode conductive layer 502. The top electrode functional layer 501 is the top electrode that forms the memristor function, and its material can be but is not limited to active metal materials such as Ti, Al, Ag, and Cu. The positions of the top electrode functional layer 501 and the bottom electrode functional layer 302 can be interchanged, and the voltage polarity that controls the memristor switch will be opposite after the interchange. The top electrode conductive layer 501 is used for the top electrode interconnect layer 401 to realize electrical interconnection with external interconnection. On the one hand, it can cover the active metal of the top electrode functional layer 501 to prevent it from being oxidized and damaged by subsequent processes. On the other hand, it can use metals with good conductivity and stability to improve the conductivity of the device and reduce the resistance of the device. It can be but not limited to Au, Pd, Pt and other metal materials. After preparing the bottom electrode, the photoresist mask layer is removed by using a degumming liquid, and optionally, the surface is cleaned by chemical reagent cleaning or plasma cleaning to reduce photoresist residue.

[0035] S9: Preparation of interconnection wire insulation layer. In order to realize the interconnection between the memristor switch array and the external wires and silicon through vias, and to facilitate the preparation of the multi-layer wiring on the subsequent silicon adapter board, it is necessary to prepare an interconnection insulation layer 601 with a relatively flat surface. The interconnection insulation layer 601 can be prepared by spin coating and photolithography technology to prepare a PI layer, and the PI layer contains an interconnection opening 602 for interconnection with the wires and silicon through vias. It is also possible to prepare a SiO2 layer by chemical vapor deposition, and prepare a SiO2 etching photoresist mask layer by photolithography, and then prepare the interconnection opening 602 by plasma etching.

[0036] S10: Protective layer etching: Using a photoresist mask and plasma etching, the protective layer 201 on the filled conductive material 104 is removed to facilitate the subsequent electrical interconnection between the through silicon via 102 and the conductive wire and the memristor switch array.

[0037] S11: Preparation of interconnection wiring. Ti and Cu seed layers are deposited on the interconnection opening 602 by physical vapor deposition. Subsequently, Cu interconnection wiring 701 is prepared by electroplating process, which can realize electrical interconnection between the electrodes of the memristor switch array and the silicon through-hole 102 or other wiring and interconnection structures. As an option, chemical mechanical polishing can be used to flatten the surface of the silicon substrate to facilitate the preparation of subsequent multi-layer wiring.

[0038] S12: Preparation of multi-layer wiring layers and interconnect pads on the front side. Physical vapor deposition and Cu electroplating process are used to prepare interconnect wires, and spin coating and photolithography are used to prepare PI layers, and then a wiring layer is prepared. The interconnect wire and PI layer preparation process is repeated to achieve the preparation of multi-layer wiring layers 702 and interconnect pads 703.

[0039] S13: Preparation of multi-layer wiring layer and interconnect pad on the back side. The back side of the silicon substrate (the side of the memristor switch array) is subjected to mechanical thinning, plasma silicon etching, and chemical mechanical polishing in sequence, so that the back side is exposed to the filled conductive material 104 and has a flat surface. The multi-layer wiring layer 702 and the interconnect pad 703 on the back side of the silicon substrate 101 are prepared by the process in S12. It can also be prepared by the Damascus wiring process.

[0040] The present invention further provides a silicon adapter plate structure with an integrated memristor switch array, comprising a silicon adapter plate unit and a memristor switch array integrated on the silicon adapter plate unit, wherein: The memristor switch array includes, from the inside to the outside, a protective layer 201, a memristor bottom electrode (including a bottom electrode adhesion layer 301 and a bottom electrode functional layer 302), a memristor functional layer 401, a memristor top electrode (including a top electrode functional layer 501 and a top electrode conductive layer 502), and an interconnect insulating layer 601.

[0041] like Fig.14 As shown, in application, the silicon adapter plate structure of the integrated memristor switch array prepared by the present invention can realize the integrated interconnection of multiple core particles by using the conventional 2.5D silicon adapter plate integration process. Fig.14 The invention is a 2.5D integrated chip based on a silicon adapter board with an integrated memristor switch array, and the structure includes a core particle 801 and interconnection solder balls or micro bumps 802. The memristor switch array is integrated between the multi-layer wiring on the front side of the silicon adapter board and the silicon substrate, and can also be integrated between two wiring layers in the multi-layer wiring layer 702. The memristor switch array can also be integrated at the corresponding position on the back side of the silicon adapter board. The example shows a 3×3 array of memristor switches. When a DC voltage or a pulse voltage of different directions or different voltages is applied to the memristor, a single memristor can be switched between a high resistance state and a low configuration, thereby realizing the control of the switch state. For example, for a bipolar memristor, by applying a positive voltage to the active electrode and a negative voltage to the inert electrode, when the voltage reaches a certain threshold, the memristor changes from a high resistance state to a low resistance state. When the voltage direction is opposite, the memristor changes from a low resistance state to a high resistance state at a certain voltage value. The configuration transformation of the memristor can realize the conduction between different interconnected circuits.

[0042] like Fig.15As shown, for example, the conduction and disconnection of the interconnection interfaces A1, A2, A3 and B1, B2, B3 are controlled by the resistance states of 3×3 memristors 11, 12, 13, 21, 22, 23, 31, 32, 33. When all memristors are in a high resistance state, A1, A2, A3 and B1, B2, B3 are not conducting. When a voltage is applied between A1 and B1 to change the memristor to a low resistance state, A1 is conducting with B1. Similarly, when memristors 22 and 33 are changed to a low resistance state, A2 is conducting with B2, and A3 is conducting with B3. Subsequently, when the interconnection structure needs to be changed, the resistance state of the relevant memristor is adjusted. For example, memristors 11, 22, and 33 that have been changed to low resistance are adjusted back to high resistance, and memristors 12, 23, and 31 are adjusted to low resistance, so that A1 and B2 are interconnected, A2 and B3 are interconnected, and A3 and B1 are interconnected. Therefore, the configuration change of the memristor has a switching effect, which can realize the change of the interconnection circuit, thereby affecting the interconnection relationship between the core particles, which is conducive to realizing the function switching of the entire integrated structure.

[0043] In summary, the present invention provides a silicon adapter plate structure with an integrated memristor switch array and a preparation method thereof. The present invention realizes flexible on and off of local interconnection circuits in an integrated chip under voltage control by integrating a switch array of memristors on a silicon adapter plate, which not only allows the interconnection relationship between different integrated core particles to change dynamically, but also enables rapid switching of integrated chip functions without changing the type, quantity and most interconnection circuit structures of the integrated core particles. In addition, in practical applications, the present invention provides a convenient variable interconnection solution for 2.5D, 3D integrated chips and microelectronic systems, promotes rapid manufacturing and functional diversification of integrated chips, and has a certain degree of applicability in the field of advanced electronic packaging.

[0044] Finally, it should be noted that the above is only a preferred embodiment of the present invention and does not limit the present invention in any form. Any ordinary technician in the industry can smoothly implement the present invention as shown in the specification and described above, and any equivalent changes, modifications and evolutions made by using the technical content disclosed above are all equivalent embodiments of the present invention. At the same time, any equivalent changes, modifications and evolutions made to the above embodiments based on the essential technology of the present invention are still within the protection scope of the technical solution of the present invention.

Claims

1. A method for preparing a silicon adapter plate structure with an integrated memristor switch array, characterized in that: The steps include: S1, depositing a protective layer on the surface of the silicon adapter plate; S2, preparing a first photoresist mask layer on the surface of the protective layer, exposing the protective layer at the position where the memristor switch array is to be prepared and preparing a memristor bottom electrode, and removing the first photoresist mask layer; S3, preparing a memristor functional layer on the protective layer and the bottom electrode, then preparing a second photoresist mask layer, exposing the functional layer except the bottom electrode and removing the exposed functional layer, and then removing the second photoresist mask layer; S4, preparing a third photoresist mask layer on the memristor functional layer, exposing the memristor functional layer and preparing a memristor top electrode, and removing the third photoresist mask layer; S5, preparing an interconnection insulating layer on the outer layer of the protective layer and the top electrode of the memristor, and preparing an interconnection opening at a position where interconnection is required; S6. Depositing a seed layer on the interconnect opening, and preparing interconnect wiring by electroplating process, so as to realize electrical interconnection between the memristor switch array and external wires and silicon through vias.

2. The method for preparing the silicon adapter plate structure of the integrated memristor switch array according to claim 1, characterized in that: In the S1, before depositing the protective layer, the silicon adapter plate for preparing the memristor switch array is subjected to surface planarization treatment; The roughness of the prepared area is controlled to be 1-10nm; The surface planarization process adopts chemical mechanical polishing or photolithography and plasma etching process. After the surface planarization, the wafer is cleaned with chemical reagents, deionized water or plasma.

3. The method for preparing the silicon adapter plate structure of the integrated memristor switch array according to claim 1, characterized in that: In the above S1, the material of the protective layer is SiO2, Si3N4 or polyimide.

4. The method for preparing the silicon adapter plate structure of the integrated memristor switch array according to claim 1, characterized in that: In S2, the memristor bottom electrode is prepared by electron beam evaporation or magnetron sputtering technology, and the memristor bottom electrode includes a bottom electrode adhesion layer and a bottom electrode functional layer, wherein: The material of the electrode adhesion layer is Ni, Ti, Cr or TiW, and the material of the bottom electrode functional layer is Au, Pt, Pd or Ru.

5. The method for preparing the silicon adapter plate structure of the integrated memristor switch array according to claim 1, characterized in that: In S3, the material of the memristor functional layer is transition metal oxide, metal halide material, two-dimensional material or organic material.

6. The method for preparing the silicon adapter plate structure of the integrated memristor switch array according to claim 1, characterized in that: In S3, the memristor functional layer is prepared by chemical vapor deposition, molecular beam epitaxy, atomic deposition or coating; The thickness of the memristor functional layer is controlled to be 1-100nm.

7. The method for preparing the silicon adapter plate structure of the integrated memristor switch array according to claim 1, characterized in that: In said S3, after preparing the memristor functional layer, the memristor functional layer is cleaned; Thermal oxidation, plasma treatment, electron beam irradiation, chemical doping, laser irradiation or ozone oxidation technology are used to dope, thin, induce oxidation and phase change the memristor functional layer.

8. The method for preparing the silicon adapter plate structure of the integrated memristor switch array according to claim 1, characterized in that: In the above S4, the memristor top electrode includes a top electrode functional layer and a top electrode conductive layer. The material of the top electrode functional layer is Ti, Al, Ag or Cu, and the material of the top electrode conductive layer is Au, Pd or Pt.

9. The method for preparing the silicon adapter plate structure of the integrated memristor switch array according to claim 1, characterized in that: In said S5, the material of the interconnection insulating layer is polyimide or silicon dioxide; In the case of using polyimide, spin coating and photolithography techniques are used to form interconnection openings for interconnecting with wires and through silicon vias; In the case of using silicon dioxide, chemical vapor deposition is used for preparation, a SiO2 etching photoresist mask layer is prepared using a photolithography process, and plasma etching is used to prepare interconnection openings.

10. A silicon adapter plate structure with an integrated memristor switch array, characterized in that: The silicon adapter plate structure of the integrated memristor switch array is prepared based on the preparation method of the silicon adapter plate structure of the integrated memristor switch array according to any one of claims 1 to 9, and the silicon adapter plate structure includes a silicon adapter plate unit and a memristor switch array integrated on the silicon adapter plate unit, wherein: The memristor switch array includes a protection layer, a memristor bottom electrode, a memristor functional layer, a memristor top electrode and an interconnection insulating layer from the inside to the outside.

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