Metadata register for memory device

Abstract

This disclosure provides systems, methods, and devices for a memory system supporting metadata. In a first aspect, a method of processing data and metadata at a memory device includes receiving data from a host into a first plurality of registers via at least one data connection; receiving metadata from the host into a second plurality of registers via at least one non-data connection; storing data in a first portion of the memory array; and storing the metadata in a second portion of the memory array. Other aspects and features are also claimed and described.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of U.S. patent application No. 18 / 047,493, filed on October 18, 2022, entitled “METADATA REGISTERS FOR AMEMORY DEVICE,” the entire text of which is expressly incorporated herein by reference. Technical Field

[0002] In general, aspects of the present disclosure relate to computer information systems, and more particularly, to memory systems for storing data. Some features may enable and provide improved memory capabilities for storing metadata, such as error correction codes (ECC) for data stored in memory. Background Art

[0003] Computing devices (e.g., laptops, mobile phones, etc.) may include one or more processors to perform various computing functions, such as telephony, wireless data access, and camera / video functions. Memory is an important component of computing devices. The processor may be coupled to the memory to perform the above-mentioned computing functions. For example, the processor may retrieve instructions from the memory to perform computing functions and / or store temporary data in the memory for processing these computing functions, etc. Summary of the invention

[0004] The following summarizes some aspects of the present disclosure to provide a basic understanding of the discussed technology. This summary is not an extensive review of all expected features of the present disclosure, and is neither intended to identify key or important elements of all aspects of the present disclosure, nor to describe the scope of any or all aspects of the present disclosure. Its sole purpose is to give some concepts of one or more aspects of the present disclosure in a summarized form as a prelude to more specific embodiments given later.

[0005] According to at least one embodiment, an apparatus includes a memory configured to communicate with a host. The memory includes a memory array configured to store data. The memory is configured to provide the data stored in the memory array to the host when performing a computing function. In some aspects, the registers of the storage device can be configured to store data and metadata separately in different sets of registers. The metadata register can temporarily store information during transmission between the host device and the storage device for retrieval from the memory array of the storage device in response to a read command, or stored in the memory array of the storage device in response to a write command.

[0006] In one aspect of the present disclosure, a memory device includes a memory array, the memory array including a first portion and a second portion; and a memory input / output (I / O) module. The memory I / O module can be coupled to the memory array and configured to communicate with a host through a channel including a plurality of connections, the plurality of connections including at least one data connection and at least one non-data connection, and including at least one first register and at least one second register. The memory I / O module can be configured to perform operations including: receiving data from the host via the at least one data connection into the at least one first register; receiving metadata from the host via the at least one non-data connection into the at least one second register; storing the data in the first portion of the memory array; and storing the metadata in the second portion of the memory array. The memory I / O module may also be configured to perform operations comprising: retrieving data from the first portion of the memory array into the at least one first register; retrieving metadata from the second portion of the memory array into the at least one second register; sending the data from the at least one first register to the host via the at least one data connection; and sending the metadata from the at least one second register to the host via the at least one non-data connection.

[0007] In additional aspects of the present disclosure, an apparatus (such as a wireless device) includes at least one processor and a memory coupled to the at least one processor. The at least one processor is configured to communicate with the memory through a memory controller, the memory controller being coupled to a channel coupling the processor to the memory. The processor may be a processor, a controller, or other logic circuit in a host.

[0008] In additional aspects of the present disclosure, a non-transitory computer-readable medium stores instructions that, when executed by a processor, cause the processor to perform the operations described herein with respect to various aspects of the present disclosure.

[0009] The term one or more error correction codes (one or more ECCs) in the present disclosure may refer to error detection, error correction, or error detection and correction codes. ECC is not limited to a specific type of decoding. In some examples, ECC may include Hamming codes and / or parity check codes.

[0010] The memory in the present disclosure may be embedded in a processor on a semiconductor die, or may be part of a different semiconductor die. The memory may be of various types. For example, the memory may be a static random access memory (SRAM), a dynamic random access memory (DRAM), a magnetic random access memory (MRAM), a NAND flash memory, or a NOR flash memory, etc.

[0011] Methods and apparatus are presented in the present disclosure by way of non-limiting examples of low power double data rate (LPDDR) synchronous dynamic random access memory (SDRAM). For example, the LPDDR memory operates according to an LPDDR specification promulgated by the Joint Electron Device Engineering Council (JEDEC). One such LPDDR specification may be LPDDR5. Another such LPDDR specification may be LPDDR6.

[0012] For those of ordinary skill in the art, other aspects, features, and implementations will become apparent after reviewing the following description of specific exemplary aspects in conjunction with the accompanying drawings. Although features may be discussed below with respect to certain aspects and figures, various aspects may include one or more of the advantageous features discussed herein. In other words, although one or more aspects may be discussed as having certain advantageous features, one or more of such features may also be used according to various aspects. In a similar manner, although exemplary aspects may be discussed below as device, system, or method aspects, exemplary aspects may be implemented in various devices, systems, and methods.

[0013] The method may be embedded in a computer readable medium as a computer program code including instructions for causing a processor to perform the steps of the method. In some embodiments, the processor may be part of a mobile device including a first network adapter configured to send data, such as an image or video in a record, or as streaming data, over a first network connection among a plurality of network connections. The processor may be coupled to the first network adapter and a memory for storing data supporting processing and communication operations performed by the processor. The network adapter may support communication over a wireless communication network such as a 5G NR communication network. The processor may cause data stored in the memory to be transmitted over the wireless communication network.

[0014] The foregoing has been fairly broadly outlined according to the features and technical advantages of the examples of the present disclosure, so that the following detailed description can be better understood. Additional features and advantages will be described hereinafter. The disclosed concepts and specific examples can be easily used as the basis for modifying or designing other structures for the same purpose of performing the present disclosure. Such equivalent constructions do not deviate from the scope of the appended claims. When considered in conjunction with the accompanying drawings, the characteristics of the concepts disclosed herein (both their organization and method of operation) together with the associated advantages will be better understood according to the following description. Each of the figures in the accompanying drawings is provided for the purpose of illustration and description, and is not intended to limit the limits of the claims.

[0015] Although various aspects and implementations are described in this application by the description of some examples, it will be understood by those skilled in the art that additional implementations and use cases may be generated in many other arrangements and scenarios. The innovations described herein can be implemented across many different platform types, devices, systems, shapes, sizes, and packaging arrangements. For example, various aspects and / or uses can be generated via integrated chip implementations and other devices based on non-module components (e.g., end-user devices, vehicles, communication devices, computing devices, industrial devices, retail / purchase devices, medical devices, devices implementing artificial intelligence (AI), etc.). Although some examples may be specifically targeted at use cases or applications, or may not be specifically targeted at use cases or applications, various applicability of the described innovations may occur. The range of implementations can range from chip-level or modular components to non-modular, non-chip-level implementations, and further to aggregated, distributed or original equipment manufacturer (OEM) devices or systems containing one or more aspects of the described innovations. In some actual settings, the device that incorporates the described aspects and features may also necessarily include additional components and features for implementing and practicing the claimed and described aspects. For example, the transmission and reception of wireless signals necessarily include multiple components for analog and digital purposes (e.g., hardware components including antennas, radio frequency (RF) chains, power amplifiers, modulators, buffers, processors, interleavers, adders / summers, etc.). The innovations described herein are intended to be implemented in a variety of devices, chip-level components, systems, distributed arrangements, end-user equipment, etc., having different sizes, shapes, and configurations. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] A further understanding of the nature and advantages of the present disclosure may be achieved by reference to the following drawings. In the drawings, similar components or features may have the same reference numerals. In addition, various components of the same type may be distinguished by following the reference numeral with a dash and a second reference numeral to distinguish between similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, without regard to the second reference numeral.

[0017] Figure 1 A block diagram of an example computing system including a host, a memory, and a channel coupling the host and the memory is shown in accordance with one or more aspects of the present disclosure.

[0018] Figure 2A A block diagram of an example computing system including a host, a memory, and a channel coupling the host and the memory with another implementation of the channel is shown in accordance with one or more aspects of the present disclosure.

[0019] Figure 2B A block diagram of an example computing system including a host, a memory, and a channel coupling the host and the memory with link error correction code (ECC) protection of the channel is shown in accordance with one or more aspects of the present disclosure.

[0020] Figure 2C A block diagram of an example computing system including a host, a memory, and a channel coupling the host and the memory with another implementation of the channel is shown in accordance with one or more aspects of the present disclosure.

[0021] Figure 3A A flow chart depicting an example method for a memory to perform a write command using metadata registers according to one or more aspects of the present disclosure is shown.

[0022] Figure 3B A flow chart depicting an example method for a memory to perform a read command using metadata registers according to one or more aspects of the present disclosure is shown.

[0023] Figure 4A A block diagram depicting an example configuration for a metadata register is shown in accordance with one or more aspects of the present disclosure.

[0024] Figure 4B A block diagram depicting an example configuration for a metadata register is shown in accordance with one or more aspects of the present disclosure.

[0025] Figure 5A-Figure 5BA timing diagram depicting a write operation to transfer metadata over a non-data connection is shown in accordance with one or more aspects of the present disclosure.

[0026] Figure 6A-6B A timing diagram depicting a read operation that transfers metadata over a non-data connection is shown in accordance with one or more aspects of the present disclosure.

[0027] Figure 7 A block diagram depicting a configuration of a memory array for use in a storage device for storing metadata is shown in accordance with one or more aspects of the present disclosure.

[0028] Figure 8 A block diagram depicting another configuration of a memory array for use in a storage device for storing metadata is shown in accordance with one or more aspects of the present disclosure.

[0029] Fig. 9 A block diagram depicting storage of data and metadata in a memory array is shown in accordance with one or more aspects of the present disclosure.

[0030] Like reference numbers and designations in the various drawings indicate like elements. DETAILED DESCRIPTION

[0031] The specific embodiments described below in conjunction with the accompanying drawings are intended as descriptions of various configurations and are not intended to limit the scope of the present disclosure. Instead, the specific embodiments include specific details for the purpose of providing a thorough understanding of the subject matter of the present invention. It will be apparent to those skilled in the art that these specific details are not required in every case, and in some instances, for clarity of presentation, well-known structures and components are shown in block diagram form.

[0032] The present disclosure provides systems, devices, methods and computer-readable media that support data processing, including technologies for supporting the transmission of data between a host and a storage device. The host can send data and accompanying metadata to be stored in a memory array of a storage device. The storage device may include registers for receiving and accumulating data and metadata for writing to the memory array. The metadata register of the storage device may be organized to associate metadata with data without using two separate addresses for data and metadata. Examples of metadata for storage with data include error correction codes (ECC) that protect data from errors and / or signatures that protect data from tampering. However, metadata may be used more than just to protect data.

[0033] Particular implementations of the subject matter described in this disclosure may be implemented to achieve one or more of the following potential advantages or benefits. In some aspects, this disclosure provides techniques for storing metadata with data in a manner that is compatible with current memory array architectures by coordinating the storage of data and metadata in pages of a memory array. In addition, in some aspects, metadata may be sent between a host and a memory device without requiring a dedicated connection in a channel between the host and the memory device for carrying the metadata.

[0034] As the demand for computing devices to perform more functions at faster and faster speeds grows, errors in data stored in memory may also increase. Errors may grow as the amount of data stored in memory and transmitted between blocks increases. One example of preventing such errors is the use of error correction codes (ECC) associated with the data. Without overburdening the host or memory, improving the error detection / correction scheme when accessing the memory is beneficial to improving system performance. ECC can be attached during transmission on the channel, such as in the case of link ECC. ECC can also be attached to be stored in the memory array, such as in the case of system ECC. In some examples, end-to-end system ECC can be implemented in the host by adding a large density on-chip SRAM to store online ECC parity bits for certain data, thereby enhancing overall data reliability. However, such high-density on-chip SRAM is very expensive in terms of overall system cost, and high-density SRAM is susceptible to soft errors associated with SRAM cells.

[0035] In the present disclosure, system ECC data or other metadata is generated inside the host and transmitted through a non-data channel between the host and the storage device (e.g., RDQS_t in a write operation and DM in a read operation). The ECC bits can be stored in a memory array (e.g., a DRAM cell array) along with the corresponding data, so that ECC protection provides a unified and consistent way to reduce overall system cost by allowing on-chip SRAM to be removed, and achieves better performance without the need for a separate memory link ECC. Therefore, the present disclosure provides a simplified and efficient ECC scheme to implement system ECC by sharing certain resources with non-data connections. In this way, the overall system cost can be reduced and performance can be improved.

[0036] Figure 1An apparatus 100 is shown including a host 110, a memory 150, and a channel 190 coupling the host 110 and the memory 150. For example, the apparatus 100 may be a device in a computing system (e.g., a server, a data center, a desktop computer), a mobile computing device (e.g., a laptop, a cell phone, a vehicle, etc.), an Internet of Things device, a virtual reality (VR) system, an augmented reality (AR) system, an automotive system (e.g., a driver assistance system, an autonomous driving system), an image capture device (e.g., a stand-alone digital camera or digital video recorder, a wireless communication device handheld device equipped with a camera (e.g., a mobile phone, a cellular or satellite radio phone), a personal digital assistant (PDA), a tablet or a tablet, a gaming device, a computing device (e.g., a webcam, a video surveillance camera), or other device with digital imaging or video capabilities), and / or a multimedia system (e.g., a television, an optical disc player, a streaming device).

[0037] The host 110 may include at least one processor, such as a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), a multimedia engine, and / or a neural processing unit (NPU). The host 110 may be configured to be coupled to and communicate with the memory 150 (e.g., memory 150-1 to 150-4) via a channel 190 (e.g., channels 190-1 to 190-4) to perform a computing function, such as one of data processing, data communication, graphic display, camera, AR or VR rendering, image processing, neural processing, etc. For example, the memory 150-1 to 150-4 may store instructions or data for the host to perform a computing function.

[0038] The host 110 may include a memory controller 130, which may include controller PHY modules 134-1 to 134-4. Each of the controller PHY modules 134-1 to 134-4 may be coupled to a corresponding one of the memories 150-1 to 150-4 via corresponding channels 190-1 to 190-4. For ease of reference, reference to read and write is made from the perspective of the host 110. For example, in a read operation, the host 110 may receive data stored in one or more memories 150-1 to 150-4 via one or more channels of the channels 190-1—190-4. In a write operation, the host 110 may provide data to be written to one or more memories 150-1—150-4 for storage via one or more channels of the channels 190-1—190-4. The memory controller 130 may be configured to control various aspects of communication to and from the memories 150-1—150-4, such as a logical layer. The controller PHY modules 134-1 - 134-4 may be configured to control electrical characteristics (eg, voltage level, phase, delay, frequency, etc.) of signals provided or received on the channels 190-1 - 190-4, respectively.

[0039] In some examples, memories 150-1-150-4 may be LPDDR DRAMs (e.g., LPDDR5, LPDDR6). In some examples, memories 150-1-150-4 may be different types of memories, such as one LPDDR5, one LPDDR6, one flash memory, and one SRAM, respectively. Host 110, memories 150-1-150-4, and / or channels 190-1-190-4 may operate according to LPDDR (e.g., LPDDR5, LPDDR6) specifications. In some examples, each of channels 190-1-190-4 may include 16 bits of data (e.g., 16 DQs). In some examples, each of channels 190-1-190-4 may operate on 32 bits of data (e.g., 32 DQs). Figure 1 In FIG. 1 , four channels are shown, however, the apparatus 100 may include more or fewer channels, such as 8 or 16 channels.

[0040] Figure 2A 1 shows in more detail the configuration of the host 110, the memory 150, and the channel 190 according to some aspects of the present disclosure. Figure 2A Shows that there is Figure 1Another representation of the device 100 of the host 110, the memory 150, and the channel 190. The channel 190 between the host 110 and the memory 150 may include multiple connections, some of which carry data (e.g., user data or application data) and some of which carry non-data (e.g., addresses and other signaling information). For example, the non-data connections in the channel 190 may include a data clock (e.g., WCK) for providing data to the corresponding memory 150 and a read data strobe (e.g., RDQS) for receiving data from the corresponding memory 150 on a byte-by-byte basis. The channel 190 may also include data mask (e.g., DM, sometimes referred to as data mask inversion DMI to indicate multiple functions performed by the signal connection) signaling, which is used to mask certain portions of the data in a write operation. The channel 190 may further include commands and addresses (e.g., CA[0:n]) and associated CA clocks to provide commands (e.g., read or write commands) to the memory 150.

[0041] The host 110 may include at least one processor 120, which may include a CPU 122, a GPU 123, and / or an NPU 124. The host 110 may also include a memory controller 130 having a controller PHY module 134. The memory controller 130 may be coupled to the at least one processor 120 via a bus system 115 when performing various computing functions. The term "bus system" may provide that elements coupled to the "bus system" may exchange information between them directly or indirectly. In different embodiments, the "bus system" may cover multiple physical connections and intervening stages such as buffers, latches, registers, etc. The module may be implemented in hardware, software, or a combination of hardware and software.

[0042] The memory controller 130 may send and / or receive data blocks to other modules, such as at least one processor 120 and / or memory 150. The memory 150 may include a memory I / O module 160 (e.g., a PHY layer) configured to control electrical characteristics (e.g., voltage level, phase, delay, frequency, etc.) to provide or receive signals on the connection of the channel 190. For example, the memory I / O module 160 may be configured to capture (e.g., sample) data, commands, and addresses from the host 110 via the channel 190, and output data to the host 110 via the channel 190. Figure 5A-Figure 5B and Figure 6A-6BAn example technique for communicating over a channel 190 between a memory I / O module 160 and a memory controller 130 is shown in the example of FIG. 150. The memory 150 may also include a memory array 175, which may include a plurality of memory cells (e.g., DRAM memory cells, MRAM memory cells, SRAM memory cells, and flash memory cells) storing values. The host 110 may read data stored in the memory array 175 and write data to the memory array 175 via the channel 190 and the memory I / O module 160. The memory array 175 may be divided into a plurality of memory banks, each of which is organized into a plurality of pages.

[0043] Application or user data may be processed by processor 120, and memory controller 130 may be directed to store and / or retrieve such data from memory 150. For example, data may be generated during execution of an application, such as a spreadsheet program that calculates values ​​based on other data. As another example, data may be generated during execution of an application by receiving user input, such as to a spreadsheet program. As another example, data may be generated during execution of a gaming application that generates information about a representation of a scene rendered by a three-dimensional (3-D) application.

[0044] Data may be associated with metadata that provides information about the data being stored. Metadata may include attributes or characteristics of the data. In one example, the metadata is an error correction code (ECC), which may be used to verify the integrity of the data and correct a limited number of errors in the data after transmission and / or storage. The ECC is metadata because it describes the characteristics of the data to which the ECC is associated (e.g., the value generated by the algorithm when the data is provided as input to the algorithm).

[0045] Information sent over channel 190 may be stored in registers in memory I / O module 160 of memory 150 as a temporary or short-term storage location prior to long-term storage in memory array 175. Memory I / O module 160 may include first and second registers for storing data (e.g., user data or application data) and metadata, respectively. A first plurality of registers 182A-K stores data; and a second plurality of registers 181A-N stores metadata. In different embodiments, K may be equal to N, or K may be different from N, where K is greater than N or K is less than N. In some embodiments, N and / or K may be 1. The contents of registers 181A-N and 182A-K may then be transferred to memory array 175. In some embodiments, the contents of registers 181A-N and 182A-K may be transferred in serial fashion shortly after receipt to complete a single write command. In some embodiments, the contents of registers 181A-N and 182A-K may be accumulated based on multiple write commands received at memory 150, and metadata is transferred to memory array 175 when certain criteria are met. In some embodiments, there may be a single register 182 and / or a single register 181. For example, to reduce hardware size, there may be a single data register 182 with multiple metadata registers 181A-N. A write command may be coupled with serial data input from the host so that the write data (e.g., 32 bytes) is temporarily stored in the 32-byte register 182. The data is then automatically written to the first portion of the memory array without any additional write commands from the host. Figure 4A-4B Some example configurations for metadata registers 181A-N are shown in FIG.

[0046] The device 100 may be configured to support processing of metadata accompanying data sent between the host 110 and the memory 150. In one example, the metadata may be an error correction code (ECC) for protecting the data from at least some errors in communication and / or storage. A separate link ECC code may be sent over the channel 190 to protect the data and / or metadata during transmission over the channel 190. Figure 2B 1 shows a configuration of host 110, memory 150, and channel 190 according to some aspects of the present disclosure to support link ECC. Figure 2B Shows that there is Figure 1 and / or Figure 2A Another representation of device 100 of host 110, memory 150, and channel 190.

[0047] The host 110 may be configured to perform a plurality of ECC functions. To support the system ECC function, the host 110 may include a system ECC memory 137. The memory controller 130 may be coupled to the system ECC memory 137 via the bus system 116. The memory controller 130 may further include a system ECC decoder 131 and a system ECC encoder 132. The controller PHY module 134 may include a link ECC decoder 135 and a link ECC encoder 136.

[0048] The device 100 may implement a system ECC function to detect / correct errors that occur when performing a computing function (e.g., operating with at least one processor 120). The system ECC function may be particularly useful for applications with low fault tolerance (e.g., automotive applications). In some examples, the system ECC encoder 132 may generate a system ECC for a data block and an ECC associated with the data block, for example, by appending ECC bits to the data block. The memory controller 130 may send the data block along with the system ECC to other modules, such as at least one processor 120 and / or memory 150. For example, the system ECC may be sent to the memory 150, and the memory 150 may store the system ECC in the same manner as the data. In some embodiments, the memory 150 does not perform an ECC function based on the system ECC. In some examples, the memory controller 130 may receive a data block and an associated system ECC from, for example, the processor 120 and / or the memory 150. Then, the memory controller 130 may use the system ECC to detect / correct errors in the data block.

[0049] The host 110 is coupled to the memory 150 via a channel 190, which is shown for the byte DQ[0:7] of the data. The channel 190 and the signaling between the host 110 and the memory 150 can be implemented according to the JEDEC DRAM specification (e.g., LPDDR5, LPDDR6). As shown, the channel 190 includes a signal connection for DQ, a read data strobe (RDQS), a data mask (DM), a data clock (WCK), a command and address (CA[0:n]), and a command and address clock (CK). The host 110 can use the read data strobe RDQS in a read operation to strobe (e.g., clock) the data to receive the data on the DQ. The memory 150 can use the data mask DM to mask certain parts of the data to prevent being written in a write operation. The memory 150 can use the data clock WCK to sample the data on the DQ for a write operation. The memory 150 can use the command and address clock CK to clock (e.g., receive) the CA. The signal connections for each signaling may include pins at the host 110, pins at the memory 150, and one or more conductive traces electrically connecting the pins. The one or more conductive traces may be part of a single integrated circuit (IC) on a silicon chip containing the processor 120 and the memory 150, may be part of a package-on-package (PoP) containing the processor 120 and the memory 150, or may be part of a printed circuit board (PCB) coupled to both the processor 120 and the memory 150.

[0050] The memory 150 may include a memory I / O module 160 (e.g., a PHY layer) configured to control electrical characteristics (e.g., voltage level, phase, delay, frequency, etc.) to provide or receive signals on the channel 190. For example, the memory I / O module 160 may be configured to capture (e.g., sample) data, commands, and addresses from the host 110 via the channel 190, and output data to the host 110 via the channel 190.

[0051] The memory 150 may also include a memory array 175, which may include a plurality of memory cells (e.g., DRAM memory cells) storing information. The host 110 may read data stored in the memory array 175 and write data to the memory array 175 via the channel 190. In addition, the memory array 175 may be configured to store metadata, such as an ECC (e.g., a system or array ECC) associated with the stored data. For example, a data block (e.g., a word) in the first portion 176A of the memory array 175 may be associated with a system ECC stored in the second portion 176B via a shared address. For example, reading (or writing) a shared address at the memory array 175 may read (or write) both the data block at the address and the system ECC associated with the data block.

[0052] The device 100 may include a link ECC function to detect / correct errors caused by data transmission in the channel 190. The memory I / O module 160 may include a memory link ECC decoder 161 and a memory link ECC encoder 162. The link ECC information may be appended during transmission on the channel 190, and verified at the host 110 or the memory 150, and then discarded. For example, in a write operation, the link ECC encoder 136 may generate a link ECC associated with a data block (e.g., write data) to be written to the memory 150. The host 110 may provide the write data to the memory 150 via a DQ signal connection (e.g., a data connection in the channel 190), and provide the link ECC to the memory 150 via a signal connection of a read data strobe RDQS (e.g., a non-data connection in the channel 190). At the memory 150, the memory link ECC decoder 161 may use the link ECC to detect / correct errors in the write data. The link ECC may not be stored in the memory array 175 because the link ECC function is resolved at the memory I / O module 160. In a read operation, the memory link ECC encoder 162 can receive data (e.g., read data) stored in the memory array 175 (e.g., via the node 174, the array ECC decoder 171, and the node 164) and generate a link ECC associated with the read data. The memory I / O module 160 can provide the read data to the host 110 via the signal connection of DQ and provide the link ECC to the host 110 via the signal connection of the data mask DM. At the host 110, the link ECC decoder 135 can use the link ECC to detect / correct errors in the read data.

[0053] Referring to the metadata registers 181A-N, a plurality of metadata registers may be located in the memory I / O module 160 of the memory 150 and associated with a memory space divided out of a memory bank (e.g., in the second portion 176B) in the memory array 175 (e.g., in the first portion 176A). For example, column addresses "0x3C" to "0x3F" on each page may be reserved for metadata such as ECC. For 32-byte data, a write operation is performed to a target page and column position in the first portion 176A of the memory array 175 (data stored in the data registers 182A-K), and for associated 2-byte metadata, a write operation is performed to a predetermined area of ​​the second portion 176B of the memory array 175 (metadata stored in the metadata registers 181A-N). In a memory 150 configured to support such a write operation, a memory internal data bus (e.g., a read bus 163) may remain configured for a word size for data without separately considering metadata. In some embodiments, when an earlier read command is executed to retrieve metadata from the memory array into a metadata register based on a read command to the metadata memory space (e.g., "0x3C" - "0x3F"), a read command to the normal memory space (e.g., "0x00" - "0x3B") is executed to simultaneously retrieve normal 32-byte read data from the first portion 176A and 2-byte metadata from the second portion 176B.

[0054] exist Figure 2C Another configuration of a channel 190 for transmitting metadata is shown in FIG. Figure 2C In the example of , channel 190 includes a dedicated system metadata bus. The data bus ("data bus [0:k-1]") transmits, for example, 32 bytes of data, while the system metadata bus ("system metadata [0:p-1]") simultaneously transmits, for example, 2 bytes of metadata to accompany the data for a write or read operation. The data bus is an example of a data connection within channel 190, while the system metadata bus is an example of a non-data connection within channel 190.

[0055] The data and metadata sent via channel 190 may be sent via a combination of data and non-data connections. For example, user data may be sent via data connections DQ[0:7], while metadata may be sent via non-data connections (e.g., data mask DM connections or read strobe RDQS connections). Figure 3A Operations for executing a write command involving data and metadata by a storage device are described in the accompanying drawings.

[0056] The write command issued by the host to the memory device in method 300 causes the memory device to perform an operation at block 302 in which the memory device receives data from the host via at least one data connection into a first plurality of registers. For example, the data may be stored in data registers 182A-K by processing signals received on the data DQ[0:7] channel. In addition, at block 304, the memory device receives metadata from the host into a second plurality of registers via at least one non-data connection. For example, the metadata may be stored in metadata registers 181A-N by processing signals received on the non-data read strobe RDQS channel. A data channel may be any channel that carries user or application data for at least temporary storage in a memory array. A non-data channel may be any channel that carries data different from user or application data.

[0057] After certain conditions are met, the write command may be completed by executing blocks 306 and 308. At block 306, data is stored from the first plurality of registers to a first portion of the memory array corresponding to the write address specified in the write command received for the received data of block 302. For example, the contents of the data registers 182A-K may be stored in an area of ​​the first portion 176A of the memory array 175 based on the write address. At block 308, metadata is stored from the second plurality of registers to a second portion of the memory array. For example, the contents of the metadata registers 181A-N may be stored in an area of ​​the second portion 176B of the memory array 175 corresponding to the write address (e.g., an area reserved for metadata corresponding to the data at the write address). In some examples, execution of blocks 306 and 308 may be triggered by certain criteria, such as the filling of registers 181A-N or 182A-K with a specific number of bytes of data for storage in a single page. In some examples, data may be accumulated in registers 181A-N and / or 182A-K from two or more write commands before the write command is completed by executing blocks 306 and 308. In some examples, data may be accumulated in registers 181A-N and / or 182A-K while receiving a sequence of write commands having addresses corresponding to the same page of memory. When a subsequent write command directed to a different page of memory is received, registers 181A-N and / or 182A-K may be written to memory array 176. In some embodiments of a memory device having a single register 182A, the data portion (e.g., corresponding to columns 0x00-0x3B) may be written to the memory array without any delay, such that only additional write commands to the metadata portion of the memory array (e.g., corresponding to columns 0x3C-0x3F) are used to store metadata to the memory array.

[0058] exist Figure 3B, operations for executing a read command involving data and metadata by a storage device are described in . The read command issued by the host to the storage device in method 300 causes the memory 150 to perform a read operation. At box 352, metadata corresponding to the read address is received from the memory array into a second plurality of registers. At box 354, data corresponding to the read address is received from the memory array into a first plurality of registers. In some embodiments, metadata is loaded into a second set of registers before accessing normal data (e.g., data located in columns 0x00 to 0x3B). In some embodiments, box 352 and box 356 can be performed sequentially during a read operation to retrieve data and metadata from the storage device to the host simultaneously. When a certain amount of data is accumulated in the register, for example, the register is full or the requested data is stored in the register, the data can be sent from the register to the host via channel 190. At box 356, data from the first plurality of registers is sent to the host via at least one data connection. For example, the contents of the data registers 182A-K may be modulated onto the data DQ[0:7] connections of the channel 190 and received at the memory controller 130 of the host 110. At block 358, data from the second plurality of registers is sent to the host over at least one non-data connection. For example, the contents of the metadata registers 181A-N may be modulated onto the non-data read strobe RDQS connection of the channel 190 and received at the memory controller 130 of the host 110. The memory controller 130 of the host 110 may process the electrical signals received on the channel 190 and provided to the processor 120 and / or the ECC memory 137.

[0059] According to various techniques, metadata registers 181A-N may be associated with memory addresses of memory array 175. Figure 4A An example memory address map is shown in . Certain addresses in the page can be allocated to metadata, for example, by partitioning out column spaces corresponding to 0x3C–0x3F. Metadata registers 181A-N may include n metadata registers dedicated to each column position. That is, column space 0x3C has a first set 481A of n metadata registers, column space 0x3D has a second set 481B of n metadata registers, column space 0x3E has a third set 481C of n metadata registers, and column space 0x3F has a fourth set 481D of n metadata registers. In this example configuration, metadata registers 181A-N may have a total of 4n registers, where the column address of each memory bank is fully associated with n metadata registers.

[0060] exist Figure 4BAnother example memory address mapping is shown in . N metadata registers 181A-N can be coupled to all column locations of all memory banks. Any metadata from the reserved metadata column locations 0x3C–0x3F can be stored or retrieved to any of the n metadata registers during a write or read operation, respectively. An example command protocol for selecting one of the n metadata registers is a “CAS” + “WRITE / READ” command set that selects one of the n metadata registers by a target column address. The “CAS” command selects one of the n metadata registers, and the “WRITE / READ” command passes a target column address (“0x3C” or “0x3D” or “0x3E” or “0x3F”) for storing the metadata in a specific register in registers 181A-n.

[0061] Figure 5A and Figure 5B Waveforms for transmitting data and metadata through an example channel in a write operation according to certain aspects of the present disclosure are shown. The command and address clock CK can be a differential signal having CK_t and CK_c signals connected. The data clock WCK can be a differential signal having WCK0_t and WCK0_c signals connected. The read data strobe RDQS can be a differential signal having RDQS_t and RDQS_c signals connected. The data mask is marked as DM0 to indicate that DM0 corresponds to the lower byte of DQ (DQ[0:7]). At T0 (the rising edge of CK_c and the falling edge of CK_t), the host 110 can provide a CAS command for a write operation to the memory 150. At T1, a write command can be provided by the host 110 to the memory 150.

[0062] After a time period of write latency (WL), the host 110 may switch data clocks WCK0_t and WCK0_c to provide a clock for receiving data for writing to the memory 150 on the DQ signal connection. At Tc0-Tc2, the memory 150 may serially receive 16 bytes of data on each of the DQ[0:7] signal connections and be timed by the data clocks WCK0_t and WCK0_c. The memory 150 may serially (e.g., based on the data clocks WCK0_t and WCK0_c) receive 16 bits of the data mask DM0 to mask certain portions of the data received from the write operation. In some examples, the memory 150 may receive 16 bytes of data and a 16-bit data mask DM0, wherein each bit of the data mask DM0 masks a corresponding byte of the received data.

[0063] At Tc0-Tc2, the memory 150 may receive, for example, 8 bits of ECC or other metadata on the RDQS_t signal connection based on the data clocks WCK0_t and WCK0_c. In a read operation, the RDQS_t signal connection may be configured to provide a read data strobe (RDQS) from the memory 150 to the host 110. In some examples, in addition to metadata containing the system ECC, ECC link data may also be included on the RDQS connection. Reference Figure 2B , the memory link ECC decoder 161 can use the received link ECC to detect and / or correct errors in the received 16-byte data.

[0064] Fig. 6A and Figure 6B Waveforms for reading data and metadata in the device 100 of FIG. 2 in a read operation according to certain aspects of the present disclosure are shown. The command and address clock CK may be a differential signal having CK_t and CK_c signals connected. The data clock WCK may be a differential signal having WCK0_t and WCK0_c signals connected. The read data strobe RDQS may be a differential signal having RDQS_t and RDQS_c signals connected. The data mask is marked as DM0 to indicate that DM0 corresponds to the lower byte of DQ (DQ[0:7]). At T0 (the rising edge of CK_c and the falling edge of CK_t), the host 110 may provide a CAS command for a read operation to the memory 150. At T1, a read command may be provided to the memory 150 by the host 110.

[0065] After a period of time read latency (RL), the memory 150 may toggle the read data strobe RDQS to provide a clock to the host 110 to receive data for a read operation on the DQ signal connection. At Tc0-Tc2, the host 110 may receive 16 bytes of data serially on each of the DQ[0:7] signal connections and clocked by the read data strobes RDQS_t and RDQS_c. Thus, in this example, the host 110 receives 16 bytes of data.

[0066] At Tc0-Tc2, the host 110 may receive, for example, 8 bits of metadata, such as a system ECC, on a data mask DM0 signal connection based on (e.g., timed by) the read data strobes RDQS_t and RDQS_c. In a write operation, the DM signal connection may be configured to provide a data mask from the host 110 to the memory 150. In some examples, a link ECC may also be inserted into the DM signal connection.

[0067] Figure 7A first address space 742 for accessing the first portion 176A of the memory array 175 and a second address space 744 for accessing the second portion 176B of the memory array 175 are shown according to certain aspects of the present disclosure. In some examples, each of the first address space 742 and the second address space 744 may include row addresses and column addresses received from the CA of the channel 190. For example, the first address space 742 may correspond to row addresses 0000h to FFFFh and column addresses 00h to 3Ah, and the second address space 744 may correspond to row addresses 0000h to FFFFh and column addresses 3Bh to 3Fh. Thus, the total address space of the memory array 175 ranges from row address 0000h and column address 00h to row address FFFFh and column address 3Fh.

[0068] The first portion 176A may be addressed by a first address (e.g., an address in the first address space 742), and the second portion 176B may be addressed by a second address (e.g., an address in the second address space 744). Thus, the first address and the second address may differ in column addressing. Although the present disclosure utilizes examples of first address space 742 and second address space 744 varying in column space, other examples are possible, such as Figure 8 A row-based example of .

[0069] Figure 8 An example of a first address space 842 and a second address space 844 that are different in line space according to certain aspects of the present disclosure is shown. Figure 8 , the first portion 176A may be accessed via a first address space 842, which corresponds to row addresses 0000h through FFFDh. The second portion 176B may be accessed via a second address space 844, which corresponds to row addresses FFFEh through FFFFh. In this example, the first address space 842 and the second address space 844 may differ in row space, and therefore, the first address used to access the first portion 176A and the second address used to access the second portion 176B may differ in row addressing.

[0070] Fig. 9 Examples of data and address mappings in accordance with certain aspects of the present disclosure are shown. Fig. 9For example, the data (written to or read from the first portion 176A; marked as normal data) can be 32 bytes, and the ECC (written to or read from the second portion 176B) can be 16 bits or less. Unused address space (marked as "empty") is gathered within the column address 3Fh space, while in other examples, the unused address space is distributed between the column address spaces. In the execution of each read or write command, a total of 34 bytes (32 bytes of data and 2 bytes of system ECC or other metadata) can be sent between the host 110 and the memory 150 (e.g., via at least one data connection and at least one non-data connection). In such a configuration, a 2-byte ECC can be implemented without a loss of memory bandwidth. In addition, an additional 2 bytes of ECC ("c") can be implemented to further protect the 32 bytes of data ("n") and the two-byte system ECC ("s").

[0071] An example mapping for a portion of a memory array is shown in the following table. The column address for metadata is associated with the column address of the corresponding data. The column address for metadata is associated with a portion of the memory array reserved for metadata, such as Figure 2A-2B The second portion 176B of the memory array 175 in FIG.

[0072] The wireless communication device may include a memory configured to receive and output data (e.g., at least Figure 2A-2C ), and according to any aspect disclosed herein, the wireless communication device may be provided in or integrated in any processor-based device. Examples include, but are not limited to, a set-top box, an entertainment unit, a navigation device, a communication device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smart phone, a session initiation protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device (e.g., a smart watch, a health or fitness tracker, glasses, etc.), a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio unit, a satellite radio unit, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, an avionics system, a drone, and a multirotor aircraft.

[0073] In one or more aspects, the technology for memory storage and retrieval may include additional aspects, such as any single aspect or any combination of aspects described below or in conjunction with one or more other processes or devices described elsewhere herein. In a first aspect, supporting data operations may include a device configured to store and retrieve data from a memory array of a storage device. The device may respond to commands from a host device, such as read commands and write commands, and in response, provide certain data from the memory array on a channel that couples the storage device to the host device. The device may include a memory array and a memory I / O module, the memory I / O module is coupled to the memory array and is configured to communicate with the host through a channel including multiple connections, the multiple connections including at least one data connection and at least one non-data connection. In some implementations, the storage device is included in a wireless device such as a UE. In some implementations, the device includes a remote server, such as a cloud-based computing solution, which includes the storage device.

[0074] In some implementations, the device may include at least one processor and a memory coupled to the processor. The processor may be configured to perform the operations described herein with respect to the device. In some other implementations, the device may include a non-transitory computer-readable medium having a program code recorded thereon, and the program code may be executable by a computer for causing the computer to perform the operations described herein with reference to the device. In some implementations, the device may include one or more units configured to perform the operations described herein. In some implementations, a method of accessing (including writing or reading) data in a memory array may include: one or more operations described herein with reference to the device.

[0075] In a second aspect, in combination with the first aspect, the device is further configured to: receive data from the host via at least one data connection into at least one first register; receive metadata from the host via at least one non-data connection into at least one second register; store the data in a first portion of the memory array; and store the metadata in a second portion of the memory array.

[0076] In a third aspect, in combination with one or more of the first or second aspects, data and metadata are received simultaneously during a single write command.

[0077] In a fourth aspect, in combination with one or more aspects of the first to third aspects, the device can be configured to receive a first address through at least one second non-data connection corresponding to data, wherein storing the data in a first portion of the memory array is based on the first address; and storing the metadata in a second portion of the memory array is to a second address corresponding to the first address.

[0078] In the fifth aspect, in combination with one or more aspects of the first to fourth aspects, receiving metadata from the host into a second plurality of registers via at least one non-data connection includes: receiving multiple metadata including first metadata corresponding to a first write operation and second metadata corresponding to a second write operation into at least one second register, the multiple metadata corresponding to multiple memory addresses of a page of a memory array; and storing the metadata in a second portion of the memory array includes: writing the multiple metadata from the at least one second register to a page of the memory array to complete the first write operation and the second write operation.

[0079] In a sixth aspect, in combination with one or more of the first to fifth aspects, the metadata includes an error correction code (ECC).

[0080] In a seventh aspect, in combination with one or more of the first to sixth aspects, the metadata includes a signature for authenticating data corresponding to the metadata.

[0081] In an eighth aspect, in combination with one or more aspects of the first to seventh aspects, at least one non-data connection includes a data mask inversion (DMI) portion of a channel, wherein the number of connections of the data mask inversion (DMI) portion is less than the number of connections of at least one data connection.

[0082] In a ninth aspect, in combination with one or more aspects of the first to eighth aspects, at least one non-data connection includes a read data enable (RDQS) portion of the channel, wherein the number of connections of the read data enable (RDQS) portion is less than the number of connections of at least one data connection.

[0083] In the tenth aspect, in combination with one or more aspects of the first to ninth aspects, at least one second register includes a first part associated with a first column address and a second part associated with a second column address, and receiving metadata includes: receiving the metadata into the first part or the second part based on a memory address for data associated with the metadata specified by a write command corresponding to the data received by the memory I / O module.

[0084] In an eleventh aspect, in combination with one or more of the first to tenth aspects, at least one second register comprises a first portion and a second portion, and

[0085] Receiving the metadata includes receiving the metadata into the first portion or the second portion based on an indicator specified by a write command received by the memory I / O module.

[0086] In a twelfth aspect, in combination with one or more aspects of the first to eleventh aspects, the memory I / O module may be configured to: retrieve data from a first portion of a memory array into at least one first register; retrieve metadata from a second portion of the memory array into at least one second register; send data from at least one first register to a host via at least one data connection; and send metadata from at least one second register to a host via at least one non-data connection.

[0087] In a thirteenth aspect, in combination with one or more of the first to twelfth aspects, data and metadata are retrieved simultaneously during a single read command.

[0088] In a fourteenth aspect, in combination with one or more aspects of the first to thirteenth aspects, the memory I / O module is further configured to perform operations, the operations comprising: receiving a first address through at least one second non-data connection corresponding to data, wherein retrieving data from a first portion of the memory array is based on the first address; and retrieving metadata from a second portion of the memory array is from a second address corresponding to the first address.

[0089] In the fifteenth aspect, in combination with one or more aspects of the first to fourteenth aspects, retrieving metadata from a second portion of the memory array to at least one second register includes: during a single page operation, retrieving multiple metadata, the multiple metadata including first metadata corresponding to a first read operation and second metadata corresponding to a second read operation, the multiple metadata corresponding to multiple memory addresses of a page of the memory array; and sending metadata from the second multiple registers to the host via at least one non-data connection includes: sending multiple metadata.

[0090] In a sixteenth aspect, in combination with one or more aspects of the first to fifteenth aspects, an apparatus includes a host device, the host device is configured to communicate with a storage device through a channel, the host device includes a memory controller coupled to the channel, the memory controller is configured to perform operations, the operations including: sending data between the memory controller and at least one first register of the storage device through at least one data connection of the channel; and sending metadata between the memory controller and at least one second register of the storage device through at least one non-data connection of the channel.

[0091] In a seventeenth aspect, in combination with one or more of the first to sixteenth aspects, the host device is configured to signal a read command on the channel, the read command specifying a read address for retrieving data and retrieving metadata from the storage device.

[0092] In an eighteenth aspect, in combination with one or more of the first to seventeenth aspects, the read address identifies a set of at least one second register for storing metadata.

[0093] In a nineteenth aspect, in combination with one or more of the first to eighteenth aspects, the read command includes an indicator specifying a set of at least one second register for storing metadata.

[0094] In a twentieth aspect, in combination with one or more of the first to nineteenth aspects, the host device is configured to: signal a write command on a channel, the write command specifying a write address for storing data and sending the data to the storage device.

[0095] In a twenty-first aspect, in combination with one or more of the first to twentieth aspects, the write address identifies a set of at least one second register for storing metadata.

[0096] In a twenty-second aspect, in combination with one or more of the first to twenty-first aspects, the write command includes an indicator specifying one of the at least one second register for storing metadata.

[0097] In the description of the embodiments herein, a large amount of specific details (e.g., examples of specific components, circuits, and processes) are set forth to provide a thorough understanding of the present disclosure. As used herein, the term "coupling" means directly connected or connected by one or more intermediate components or circuits. In addition, in the following description and for the purpose of explanation, specific terms are set forth to provide a thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that these specific details may not be needed to implement the teachings disclosed herein. In other examples, in order to avoid blurring the teachings of the present disclosure, known circuits and equipment are shown in block diagram form.

[0098] Some portions of the following detailed description are presented in terms of programs, logic blocks, processes, and other symbolic representations of operations on data bits within a computer memory. In the present disclosure, programs, logic blocks, processes, etc. are conceived as a self-consistent sequence of steps or instructions leading to a desired result. These steps are steps requiring physical manipulations of physical quantities. Typically, although not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated in a computer system.

[0099] In the figure, a single block can be described as performing one or more functions. The one or more functions performed by the block can be performed in a single component or across multiple components, and / or can be performed using a combination of hardware, software, or hardware and software. In order to clearly represent the interchangeability between hardware and software, the following generally describes each illustrative component, frame, module, circuit, and step around its function. Whether such functionality is implemented as hardware or software depends on specific application and the design constraints imposed on the overall system. The technician can implement the described functionality in a changing manner for each specific application, but such implementation decision should not be interpreted as causing a departure from the scope of the present disclosure. Moreover, the example device may include components outside those components shown, including known components such as processors, memory, etc.

[0100] Unless otherwise specifically stated, it should be apparent from the following discussion that throughout this application, discussions using terms such as "access," "receive," "send," "use," "select," "determine," "normalize," "multiply," "average," "monitor," "compare," "apply," "update," "measure," "derive," "set," "generate," and the like refer to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's registers, memories, or other such information storage, transmission, or display devices.

[0101] The terms "device" and "apparatus" are not limited to one or a specific number of physical objects (e.g., a smartphone, a camera controller, a processing system, etc.). As used herein, a device can be any electronic device having one or more parts that can implement at least some parts of the present disclosure. Although the description and examples herein use the term "device" to describe various aspects of the present disclosure, the term "device" is not limited to a specific configuration, type, or number of objects. As used herein, an apparatus may include a device or a portion of a device for performing the described operations.

[0102] Certain components in a device or apparatus are described as “a unit for accessing,” “a unit for receiving,” “a unit for sending,” “a unit for using,” “a unit for selecting,” “a unit for determining,” “a unit for normalizing,” “a unit for multiplying,” or other terms of similar names, referring to one or more operations on data (e.g., image data) that may refer to a processing circuit (e.g., an application specific integrated circuit (ASIC), a digital signal processor (DSP), a graphics processing unit (GPU), a central processing unit (CPU)) configured to perform the functions through hardware, software, or a combination of hardware configured by software.

[0103] Those skilled in the art will appreciate that information and signals may be represented using any of a variety of different techniques and methods. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof.

[0104] This article is about Figure 1-2C The components, functional blocks, and modules described may include processors, electronic devices, hardware devices, electronic components, logical circuits, memories, software codes, firmware codes, and other examples or any combination thereof. Software should be broadly interpreted to mean instructions, instruction sets, codes, code segments, program codes, programs, subroutines, software modules, applications, software applications, software packages, routines, subroutines, objects, executable programs, execution threads, processes, and / or functions and other examples, whether referred to as software, firmware, middleware, microcode, hardware description languages, or other. In addition, the features discussed herein may be implemented via dedicated processor circuits, via executable instructions, or a combination thereof.

[0105] Those skilled in the art may refer to Figure 1 and Figure 2A-2C One or more blocks (or operations) described in the accompanying drawings may be combined with one or more blocks (or operations) described in another drawing with reference to the accompanying drawings. Figure 3A-3B One or more boxes (or operations) of Figure 1 and Figure 2A-2C As another example, with Figure 5A-Figure 5B and Figure 6A-6B One or more boxes can be associated with Figure 1 and Figure 2A-2C One or more boxes (or operations) that are associated are combined.

[0106] Those of ordinary skill in the art will also understand that the various illustrative logic boxes, modules, circuits and algorithm steps described in conjunction with the disclosure herein can all be implemented as electronic hardware, computer software or a combination of the two. In order to clearly illustrate this interchangeability of hardware and software, various illustrative components, boxes, modules, circuits and steps have been generally described above in terms of their functionality. Whether such functionality is implemented as hardware or software depends on specific applications and the design constraints imposed on the overall system. Technicians can implement the described functionality in a changing manner for each specific application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure. Technicians will also easily recognize that the order or combination of components, methods or interactions described herein are only examples, and components, methods or interactions of various aspects of the present disclosure can be combined or performed in a manner different from that shown and described herein.

[0107] The various illustrative logics, logical blocks, modules, circuits, and algorithmic processes described in conjunction with the implementations disclosed herein may be implemented as electronic hardware, computer software, or a combination of both. The interchangeability of hardware and software has been generally described in terms of functionality and illustrated in the various illustrative components, blocks, modules, circuits, and processes described above. Whether such functionality is implemented in hardware or software depends on the specific application and the design constraints imposed on the overall system.

[0108] The hardware and data processing apparatus for implementing the various illustrative logics, logic blocks, modules and circuits described in conjunction with the aspects disclosed herein may be implemented or executed using a general purpose single-chip or multi-chip processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, or any conventional processor, controller, microcontroller or state machine. In some implementations, a processor may be implemented as a combination of computing devices, for example, a combination of a DSP and a microprocessor, a plurality of microprocessors, a combination of one or more microprocessors and a DSP core, or any other such configuration. In some implementations, specific processes and methods may be performed by circuits specific to a given function.

[0109] In one or more aspects, the functions described may be implemented in hardware, digital electronic circuitry, computer software, firmware (including the structures disclosed in this specification and their structural equivalents), or any combination thereof. Implementations of the subject matter described in this specification may also be implemented as one or more computer programs (which are one or more modules of computer program instructions) encoded on computer storage media for execution by, or to control the operation of, data processing apparatus.

[0110] If implemented in software, the function can be stored on a computer-readable medium or transmitted through a computer-readable medium as one or more instructions or codes. The process of the method or algorithm disclosed herein can be implemented in a processor executable software module residing on a computer-readable medium. Computer-readable media include both computer storage media and communication media, and the communication media include any medium that can be implemented to transfer a computer program from one place to another. The storage medium can be any available medium that can be accessed by a computer. By way of example and not limitation, such a computer-readable medium may include a random access memory (RAM), a read-only memory (ROM), an electrically erasable programmable read-only memory (EEPROM), a CD-ROM or other optical disk storage, a disk storage or other magnetic storage device, or any other medium that can be used to store a desired program code in the form of an instruction or data structure and can be accessed by a computer. In addition, any connection can be appropriately referred to as a computer-readable medium. As used herein, disks and optical disks include compact disks (CDs), laser optical disks, optical disks, digital versatile disks (DVDs), floppy disks, and blue-ray disks, wherein disks usually copy data magnetically, and optical disks use lasers to optically copy data. The combination of the above should also be included within the scope of computer-readable media. Additionally, the operations of a method or algorithm may reside as one or any combination or set of codes and instructions on a machine-readable medium and a computer-readable medium, which codes and instructions may be incorporated into a computer program product.

[0111] Various modifications to the implementations described in this disclosure may be apparent to those skilled in the art, and the general principles defined herein may be applied to some other implementations without departing from the spirit or scope of the disclosure. Therefore, the claims are not intended to be limited to the implementations shown herein, but are to be given the broadest scope consistent with the disclosure, the principles and novel features disclosed herein.

[0112] In addition, one of ordinary skill in the art will readily understand that, for the convenience of describing the drawings, opposing terms such as "up" and "down", or "front" and "back", or "top" and "bottom", or "forward" and "backward" are sometimes used and indicate relative positions corresponding to the orientation of the drawings on a correctly oriented page, and may not reflect the correct orientation of any device implemented.

[0113] As used herein, the term "coupled to" in various tenses of the verb "couple" may mean that element A is directly connected to element B, or that other elements may be connected between elements A and B (i.e., element A is indirectly connected to element B) to operate certain intended functions. In the case of electrical components, the term "coupled to" may also be used herein to mean the use of wires, traces, or other conductive materials to electrically connect elements A and B (and any elements electrically connected therebetween). In some examples, the term "coupled to" means the transfer of electrical energy between elements A and B to operate certain intended functions.

[0114] In some examples, the term "electrically connected" means having or being configurable to have current flowing between elements A and B. For example, in addition to wires, traces, or other conductive materials and components, elements A and B may be connected via resistors, transistors, or inductors. Additionally, for radio frequency functions, elements A and B may be "electrically connected" via capacitors.

[0115] The terms "first", "second", and "third", etc., are used for ease of reference and may not carry substantive meaning. Likewise, the names of components / modules may be used for ease of reference and may not limit the components / modules. For example, such non-limiting names may include a "read ECC" signal connection and a "write ECC" signal connection.

[0116] Certain features described in this specification in the context of separate implementations may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented in multiple implementations, either individually or in any suitable subcombination. Furthermore, while features are described above as operating in certain combinations and even initially claimed as such, in some cases one or more features in a claimed combination may be separated from the combination, and a claimed combination may be directed to a subcombination or variations of a subcombination.

[0117] Similarly, although the operations are depicted in a specific order in the accompanying drawings, this should not be understood as requiring such operations to be performed in the specific order shown or in a sequential order, or requiring the execution of all the operations shown to achieve the desired result. Further, the accompanying drawings may schematically depict one or more example processes in the form of a flow chart. However, other operations not depicted may be incorporated into the schematically illustrated example process. For example, one or more additional operations may be performed before, after, simultaneously or between any illustrated operations. In some cases, multitasking and parallel processing may be advantageous. In addition, the separation of various system components in the implementation described above should not be understood as requiring such separation in all implementations, but it should be understood that the described program components and systems can generally be integrated together in a single software product, or encapsulated in multiple software products. In addition, some other implementations are within the scope of the claims that follow. In some cases, the actions recorded in the claims can be performed in different orders and still achieve the desired result.

[0118] As used herein, including in the claims, the term "or," when used in a list of two or more items, means that any one of the listed items may be taken individually, or any combination of two or more of the listed items may be taken. For example, if a composition is described as containing components A, B, or C, the composition may contain: only A; only B; only C; a combination of A and B; a combination of A and C; a combination of B and C; or a combination of A, B, and C. Furthermore, as used herein, including in the claims, "or," as used in a list of items ending with "at least one of," indicates a disjunctive list, so that, for example, a list of "at least one of A, B, or C" means any one of A or B or C or AB or AC or BC or ABC (i.e., A and B and C), or any combination thereof.

[0119] As understood by one of ordinary skill in the art, the term "substantially" is defined as being largely, but not necessarily completely, the specified object (and including the specified object; for example, substantially 90 degrees includes 90 degrees, and substantially parallel includes parallel). In any disclosed implementation, the term "substantially" may be replaced with "within a specified [percentage]", where the percentage includes 0.1, 1, 5, or 10%.

[0120] The foregoing description of the present disclosure is provided to enable those skilled in the art to implement or use the present disclosure. Various modifications to the present disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the examples and designs described herein, but to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A device comprising: A memory array including a first portion and a second portion; Memory I / O modules: coupled to the memory array; configured to communicate with a host via a channel comprising a plurality of connections, the plurality of connections comprising at least one data connection and at least one non-data connection; as well as comprising at least one first register and at least one second register, The memory I / O module is further configured to perform operations, the operations comprising: receiving data from the host into the at least one first register via the at least one data connection; receiving metadata from the host into the at least one second register via the at least one non-data connection; storing the data in the first portion of the memory array; and The metadata is stored in the second portion of the memory array.

2. The device according to claim 1, wherein: The data and the metadata are received simultaneously during a single write command.

3. The device according to claim 1, wherein: The memory I / O module is further configured to perform operations including: receiving a first address via at least one second non-data connection corresponding to the data, in: storing the data in the first portion of the memory array is based on the first address; and Storing the metadata in the second portion of the memory array is to a second address corresponding to the first address.

4. The device according to claim 1, wherein: Receiving metadata from the host into the at least one second register via the at least one non-data connection includes: receiving a plurality of metadata including first metadata corresponding to a first write operation and second metadata corresponding to a second write operation into the at least one second register, the plurality of metadata corresponding to a plurality of memory addresses of pages of the memory array; and Storing the metadata in the second portion of the memory array includes writing the plurality of metadata from the at least one second register into the page of the memory array to complete the first write operation and the second write operation.

5. The device according to claim 1, wherein: The metadata includes an error correction code (ECC).

6. The device according to claim 1, wherein: The metadata includes a signature for authenticating the data corresponding to the metadata.

7. The device according to claim 1, wherein: The at least one non-data connection includes: a data mask inversion (DMI) portion of the channel, wherein a number of connections of the data mask inversion (DMI) portion is less than a number of connections of the at least one data connection.

8. The device according to claim 1, wherein: The at least one non-data connection includes a read data strobe (RDQS) portion of the channel, wherein the number of connections of the read data strobe (RDQS) portion is less than the number of connections of the at least one data connection.

9. The device according to claim 1, wherein: The at least one second register includes a first portion associated with the first column address and a second portion associated with the second column address, and Receiving the metadata includes receiving the metadata into the first portion or the second portion based on a memory address for the data associated with the metadata specified by a write command corresponding to the data received by the memory I / O module.

10. The device according to claim 1, wherein: The at least one second register comprises a first portion and a second portion, and Receiving the metadata includes receiving the metadata into the first portion or the second portion based on an indicator specified by a write command received by the memory I / O module.

11. A method comprising: At the storage device, receiving data from a host via at least one data connection into at least one first register; receiving, at the storage device, metadata from the host via at least one non-data connection into at least one second register; storing, by the storage device, the data from the at least one first register in a first portion of a memory array; as well as The metadata from the at least one second register is stored, by the storage device, in a second portion of the memory array.

12. The method according to claim 11, further comprising: fetching the data from the memory array into the at least one first register; fetching the metadata from the memory array into the at least one second register; sending the data from the at least one first register to the host via the at least one data connection; as well as The metadata is sent from the at least one second register to the host via the at least one non-data connection.

13. The method according to claim 11, further comprising: receiving a first address via at least one second non-data connection corresponding to the data, in: storing the data in the first portion of the memory array is based on the first address; and Storing the metadata in the second portion of the memory array is to a second address corresponding to the first address.

14. The method according to claim 11, wherein: Receiving metadata from the host into the at least one second register via the at least one non-data connection includes: receiving a plurality of metadata including first metadata corresponding to a first write operation and second metadata corresponding to a second write operation into the at least one second register, the plurality of metadata corresponding to a plurality of memory addresses of pages of the memory array; and Storing the metadata in the second portion of the memory array includes writing the plurality of metadata from the at least one second register into the page of the memory array to complete the first write operation and the second write operation.

15. The method according to claim 11, wherein: The metadata includes an error correction code (ECC).

16. The method according to claim 11, wherein: The metadata includes a signature for authenticating the data corresponding to the metadata.

17. The method according to claim 11, wherein: The at least one non-data connection includes: a data mask inversion (DMI) portion of a channel, wherein a number of connections of the data mask inversion (DMI) portion is less than a number of connections of the at least one data connection.

18. The method according to claim 11, wherein: The at least one non-data connection includes a read data strobe (RDQS) portion of a channel, wherein the number of connections of the read data strobe (RDQS) portion is less than the number of connections of the at least one data connection.

19. The method of claim 11, wherein: at least one second register includes a first portion associated with the first column address and a second portion associated with the second column address, and Receiving the metadata includes receiving the metadata into the first portion or the second portion based on a memory address for the data associated with the metadata specified by a write command corresponding to the data.

20. The method of claim 11, wherein: The at least one second register comprises a first portion and a second portion, and Receiving the metadata includes receiving the metadata into the first portion or the second portion based on an indicator specified by a write command.

21. An apparatus comprising: A memory array including a first portion and a second portion; Memory I / O modules: coupled to the memory array; configured to communicate with a host via a channel comprising a plurality of connections, the plurality of connections comprising at least one data connection and at least one non-data connection; as well as comprising at least one first register and at least one second register, The memory I / O module is further configured to perform operations, the operations comprising: fetching data from said first portion of said memory array into said at least one first register; fetching metadata from the second portion of the memory array into the at least one second register; sending the data from the at least one first register to the host via the at least one data connection; and The metadata is sent from the at least one second register to the host via the at least one non-data connection.

22. The device according to claim 21, wherein The data and the metadata are retrieved simultaneously during a single read command.

23. The device according to claim 21, wherein The memory I / O module is further configured to perform operations including: receiving a first address via at least one second non-data connection corresponding to the data, in: Retrieving the data from the first portion of the memory array is based on the first address; and Retrieving the metadata from the second portion of the memory array is from a second address corresponding to the first address.

24. The apparatus of claim 21, wherein: Retrieving metadata from the second portion of the memory array into the at least one second register includes: retrieving a plurality of metadata during a single page operation, the plurality of metadata including first metadata corresponding to a first read operation and second metadata corresponding to a second read operation, the plurality of metadata corresponding to a plurality of memory addresses of a page of the memory array; Sending metadata from the at least one second register to the host via the at least one non-data connection includes sending the plurality of metadata.

25. The device according to claim 21, wherein The metadata includes an error correction code (ECC).

26. The device according to claim 21, wherein The metadata includes a signature for authenticating the data corresponding to the metadata.

27. The device according to claim 21, wherein The at least one non-data connection includes: a data mask inversion (DMI) portion of the channel, wherein a number of connections of the data mask inversion (DMI) portion is less than a number of connections of the at least one data connection.

28. The device according to claim 21, wherein The at least one non-data connection includes a read data strobe (RDQS) portion of the channel, wherein the number of connections of the read data strobe (RDQS) portion is less than the number of connections of the at least one data connection.

29. The apparatus of claim 21, wherein: The at least one second register includes a first portion associated with the first column address and a second portion associated with the second column address, and Retrieving the metadata includes retrieving the metadata into the first portion or the second portion based on a memory address for the data associated with the metadata specified by a read command corresponding to the data received by the memory I / O module.

30. The apparatus of claim 21, wherein: The at least one second register comprises a first portion and a second portion, and Retrieving the metadata includes retrieving the metadata into the first portion or the second portion based on an indicator specified by a read command received by the memory I / O module.

31. A method comprising: fetching data from a first portion of a memory array into at least one first register; retrieving metadata from a second portion of the memory array into at least one second register; sending the data from the at least one first register to a host via at least one data connection; as well as The metadata is sent from the at least one second register to the host via at least one non-data connection.

32. The method according to claim 31, wherein: The data and the metadata are retrieved simultaneously during a single read command.

33. The method of claim 31 , further comprising: receiving a first address via at least one second non-data connection corresponding to the data, in: Retrieving the data from the first portion of the memory array is based on the first address; and Retrieving the metadata from the second portion of the memory array is from a second address corresponding to the first address.

34. The method of claim 31, wherein: Retrieving metadata from the second portion of the memory array into the at least one second register includes: retrieving a plurality of metadata during a single page operation, the plurality of metadata including first metadata corresponding to a first read operation and second metadata corresponding to a second read operation, the plurality of metadata corresponding to a plurality of memory addresses of a page of the memory array; Sending metadata from the at least one second register to the host via the at least one non-data connection includes sending the plurality of metadata.

35. The method of claim 31, wherein: The metadata includes an error correction code (ECC).

36. The method of claim 31, wherein: The metadata includes a signature for authenticating the data corresponding to the metadata.

37. The method of claim 31, wherein: The at least one non-data connection includes: a data mask inversion (DMI) portion of a channel, wherein a number of connections of the data mask inversion (DMI) portion is less than a number of connections of the at least one data connection.

38. The method of claim 31, wherein: The at least one non-data connection includes a read data strobe (RDQS) portion of a channel, wherein the number of connections of the read data strobe (RDQS) portion is less than the number of connections of the at least one data connection.

39. The method of claim 31, wherein: The at least one second register includes a first portion associated with the first column address and a second portion associated with the second column address, and Retrieving the metadata includes retrieving the metadata into the first portion or the second portion based on a memory address for the data associated with the metadata specified by a read command corresponding to the data.

40. The method of claim 31, wherein: The at least one second register comprises a first portion and a second portion, and Retrieving the metadata includes retrieving the metadata into the first portion or the second portion based on an indicator specified by a read command.

41. An apparatus comprising: A host device configured to communicate with the storage device via a channel, The host device includes a memory controller coupled to the channel, the memory controller configured to perform operations including: transmitting data between the memory controller and at least one first register of the memory device via at least one data connection of the channel; as well as Metadata is transmitted between the memory controller and at least one second register of the memory device over at least one non-data connection of the channel.

42. The device according to claim 41, wherein The operations include: A read command is signaled over the channel, the read command specifying at least one read address for retrieving the data from the storage device and retrieving the metadata.

43. The device according to claim 42, wherein: The at least one read address identifies a set of the at least one second registers for storing the metadata.

44. The device according to claim 42, wherein: The read command includes an indicator specifying a set of the at least one second register for storing the metadata.

45. The apparatus of claim 41, wherein: The operations include: A write command is signaled over the channel, the write command specifying a write address for storing the data and sending the data to the storage device.

46. ​​The device according to claim 45, wherein The write address identifies a set of the at least one second registers for storing the metadata.

47. The device according to claim 45, wherein The write command includes an indicator designating one of the at least one second register for storing the metadata.

48. A method comprising: sending, by a memory controller of a host device coupled to the memory device via a channel, data to at least one first register of the memory device via at least one data connection of the channel; as well as Metadata is sent, by the memory controller of the host device, to at least one second register of the memory device via at least one non-data connection of the channel.

49. The method of claim 48, further comprising: A read command is signaled by the memory controller on the channel, the read command specifying a read address for retrieving the data from the storage device and for retrieving the metadata.

50. The method of claim 49, wherein: The read address identifies a set of the at least one second registers for storing the metadata.

51. The method of claim 49, wherein: The read command includes an indicator specifying a set of the at least one second register for storing the metadata.

52. The method of claim 48, further comprising: A write command is signaled over the channel, the write command specifying a write address for storing the data and sending the data to the storage device.

53. The method of claim 52, wherein: The write address identifies a set of the at least one second registers for storing the metadata.

54. The method of claim 52, wherein: The write command includes an indicator designating one of the at least one second register for storing the metadata.

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