Method for manufacturing semiconductor device

Abstract

The invention provides a method for manufacturing a semiconductor device capable of improving characteristics. According to one embodiment, a method of manufacturing a semiconductor device includes forming a first metal layer including a first metal element on a first surface of a structure including a substrate including SiC and the first surface. The manufacturing method includes injecting a first element including at least one selected from the group consisting of He, Ne, Ar, Kr, Xe, Rn, and Si into the first surface via the first metal layer. The manufacturing method includes irradiating the first surface with laser light via the first metal layer after the injection.

Description

Technical Field

[0001] An embodiment of the present invention relates to a method for manufacturing a semiconductor device. Background Art

[0002] Improvement in characteristics is desired for semiconductor devices.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2023-40706 Summary of the invention

[0006] Problems to be solved by the invention

[0007] An embodiment provides a method for manufacturing a semiconductor device capable of improving characteristics.

[0008] Means for solving problems

[0009] According to an embodiment, a method for manufacturing a semiconductor device includes: forming a first metal layer including a first metal element on the first surface of a structure including a substrate including SiC and including a first surface. The manufacturing method includes: injecting a first element including at least one selected from He, Ne, Ar, Kr, Xe, Rn, Si, N, P, As, B, Al, and Ga into the first surface via the first metal layer. The manufacturing method includes: after the injection, irradiating the first surface with a laser via the first metal layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 This is a flowchart illustrating a method for manufacturing a semiconductor device according to the first embodiment.

[0011] Figure 2 It is a schematic cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment.

[0012] Figure 3 It is a schematic cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment.

[0013] Figure 4 It is a schematic cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment.

[0014] Figure 5 It is a schematic cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment.

[0015] Figure 6 It is a schematic cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment.

[0016] Figure 7 It is a schematic cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment.

[0017] Figure 8 It is a schematic cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment.

[0018] Fig. 9 This is a flowchart illustrating a method for manufacturing a semiconductor device according to the second embodiment.

[0019] Fig.10 It is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to the second embodiment.

[0020] Fig.11 It is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to the second embodiment.

[0021] Fig.12 It is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to the second embodiment.

[0022] Fig.13 It is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to the second embodiment.

[0023] Fig.14 It is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to the second embodiment.

[0024] Fig.15 is a schematic cross-sectional view illustrating a semiconductor device according to a third embodiment. DETAILED DESCRIPTION

[0025] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0026] The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the size between parts, etc. are not necessarily the same as in reality. Even when the same part is shown, the sizes and ratios may be shown differently depending on the drawings.

[0027] In the present specification and each drawing, the same elements as those in the above-mentioned drawings are denoted by the same reference numerals, and detailed description thereof will be appropriately omitted.

[0028] (First Embodiment)

[0029] Figure 1 This is a flowchart illustrating a method for manufacturing a semiconductor device according to the first embodiment.

[0030] Figure 2 to Figure 8 It is a schematic cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment.

[0031] like Figure 1 and Figure 2 As shown, for example, a structure 18 is prepared (step S105). Figure 2 As shown, the structure 18 includes a substrate 15. The substrate 15 may be, for example, a semiconductor substrate. The substrate 15 includes SiC. The substrate 15 includes a first surface 15a. The substrate 15 may be, for example, at least a portion of a SiC wafer.

[0032] like Figure 1 and Figure 2 As shown, a first metal layer 61 is formed on the first surface 15a of the structure 18 (step S110). The first metal layer 61 contains a first metal element.

[0033] like Figure 1 and Figure 3 As shown, the first element 81 is injected into the first surface 15a via the first metal layer 61 (step S120). The first element 81, for example, includes at least one selected from He, Ne, Ar, Kr, Xe, Rn, Si, N, P, As, B, Al, and Ga. The first element 81, for example, may include at least one selected from He, Ne, Ar, Kr, Xe, Rn, and Si. The injection is, for example, ion injection. For example, ions of the first element 81 are injected.

[0034] like Figure 1 and Figure 5 As shown, after the injection, the laser 80L is irradiated to the first surface 15a through the first metal layer 61 (step S130). For example, laser annealing is performed. Figure 6 As shown, a silicide layer 61S is formed from at least a portion of the first metal layer 61 .

[0035] In the embodiment, after the first metal layer 61 is formed, the first element 81 is injected through the first metal layer 61. Thus, a low-resistance ohmic contact can be stably obtained. This is considered to be because a portion of the first metal element contained in the first metal layer 61 is introduced into the substrate 15 due to the injection of the first element 81. For example, a knockon phenomenon is considered to occur.

[0036] For example, the first metal element is introduced relatively uniformly and stably near the first surface 15a of the substrate 15. Thus, a mixed layer (mixed region 15M described later) having a fast reaction rate of silicide reaction is uniformly formed. By subsequent annealing based on laser irradiation, the highly reactive mixed layer is efficiently silicided. Thus, a uniform silicide layer 61S is stably formed. Thus, low resistance can be obtained. High flatness can be obtained. For example, high flatness and low resistance can be obtained. According to an embodiment, a method for manufacturing a semiconductor device capable of improving characteristics is provided. For example, a silicide layer 61S with high flatness can be obtained. The surface morphology can be improved.

[0037] In the embodiment, laser annealing is performed after the first element 81 is injected through the first metal layer 61. Thus, a stable silicide layer 61S can be obtained even by low-power laser irradiation. For example, a laser 80L with a low energy density can be applied. Thus, the laser irradiation process can be made more efficient. For example, a high throughput can be obtained. For example, energy consumption can be reduced.

[0038] like Figure 2 As shown, the substrate 15 may include a second surface 15 b. The structure 18 may include a semiconductor layer 10 in addition to the substrate 15. The structure 18 may include a conductive layer 50 and an insulating component 40.

[0039] For example, a semiconductor layer 10 is provided between the substrate 15 and the insulating member 40. A conductive layer 50 is provided between the semiconductor layer 10 and the insulating member 40. The conductive layer 50 may be, for example, an electrode layer. The insulating member 40 may be, for example, a passivation layer, etc. The second surface 15b is located between the semiconductor layer 10 and the first surface 15a. The first surface 15a corresponds to, for example, a surface where an ohmic electrode is provided. For example, the semiconductor layer 10 includes SiC.

[0040] For example, at least a portion of the semiconductor layer 10 may be epitaxially grown on a base (SiC wafer) serving as the substrate 15. The conductive layer 50 and the insulating member 40 are formed on the semiconductor layer 10. Thereafter, the base may be thinned. For example, grinding or the like may be performed. Thus, the preparation of the structure 18 (step S105) may include thinning the thickness of the base serving as the substrate 15.

[0041] like Figure 2 and Figure 3 As shown, during the injection of the first element 81, the structure 18 can be fixed to the support member 60. The mechanical strength is increased, and stable processing can be performed.

[0042] like Figure 3 and Figure 4As shown, a mixed region 15M is formed by the injection of the first element 81. The mixed region 15M includes, for example, Si, C, and the first metal element. For example, the injection of the first element 81 may include moving a portion of the first metal element to a region including the first surface 15a of the substrate 15. For example, by the injection of the first element 81, a mixed region 15M is formed in a region including the first surface 15a of the substrate 15. As described above, the formation of the mixed region 15M is caused by the collision phenomenon.

[0043] The first metal element includes, for example, at least one selected from Ti, Co, Ni, Mo, Ta, W, and Pt. A mixed region 15M including such a first metal element, Si, and carbon is formed. For example, the first metal element is uniformly introduced near the first surface 15a. The mixed region 15M may further include a first element 81. Ti, Co, Ni, Mo, Ta, W, and Pt can react with Si to form silicide.

[0044] like Figure 5 As shown in FIG. 8 , the first metal layer 61 and the mixed region 15M are irradiated with laser 80L. Figure 6 As shown, a silicide layer 61S is formed. Thus, the irradiation includes forming a silicide layer 61S from the first metal layer 61. After the silicide layer 61S is formed, the mixed region 15M may remain. At least a portion of the mixed region 15M may be amorphous. At least a portion of the mixed region 15M may include crystals (including polycrystalline).

[0045] In an embodiment, the thickness of the first metal layer 61 is preferably greater than or equal to 10 nm and less than or equal to 100 nm. If the thickness of the first metal layer 61 is too thin, it is difficult to obtain a uniform silicide layer 61S, for example. If the thickness of the first metal layer 61 is too thick, for example, during the injection of the first element 81 and / or laser irradiation, the energy becomes too large.

[0046] In an embodiment, the first element 81 may include at least one selected from Ar, B, P, and As. Thus, it is easy to form a mixed region 15M of appropriate thickness. The integration with other processes is good. For example, an ion implantation device for imparting conductivity may be used.

[0047] The implantation of the first element 81 may also include the implantation of the first metal element.

[0048] In an embodiment, the first element 81 may include Si. For example, a Si-rich mixed region 15M is obtained. For example, silicon is easily introduced into the first metal layer 61. Thus, a uniform silicide layer 61S can be formed efficiently. For example, a portion of silicon is introduced into the first metal layer 61. Thus, a region in which the substrate 15, the region formed by the impact, and the region into which silicon is injected into the first metal layer 61 are continuous is formed.

[0049] like Figure 1 and Figure 7 As shown, after irradiating the laser 80L, the first conductive layer 51 can be formed on the silicide layer 61S (step S140). The first conductive layer 51 functions as an electrode, for example. The first conductive layer 51 can include a metal such as aluminum, copper, or gold. The first conductive layer 51 is in ohmic contact with the substrate 15 via the silicide layer 61S with low resistance.

[0050] like Figure 1 As shown, a second metal layer 62 (see Figure 8 )(Step S125). Figure 8 As shown, the second metal layer 62 is formed on the first metal layer 61. The second metal layer 62 includes a second metal element. The second metal element may include, for example, at least one selected from Ti, Co, Ni, Mo, Ta, W, and Pt. The second metal element may be the same as or different from the first metal element.

[0051] For example, a thin first metal layer 61 is formed, and the first element 81 is implanted. Thus, the target mixed region 15M is efficiently formed. Then, the second metal layer 62 is formed. By laser irradiation, the silicide layer 61S can be efficiently formed from the first metal layer 61 and the second metal layer 62. The silicide layer 61S of the target thickness can be stably formed.

[0052] The second metal element may be the same as the first metal element or different from the first metal element.

[0053] As already described, the structure 18 may further include a semiconductor layer 10 containing SiC. By providing the semiconductor layer 10, a higher quality can be obtained. The semiconductor layer 10 is an epitaxial growth layer. In an embodiment, laser irradiation is performed to form a silicide layer 61S. Thus, the target area (the area including the first metal layer 61 and the mixed area 15M) can be locally and effectively heated. Damage to the surface device structure (semiconductor layer 10 and conductive layer 50) is suppressed. The temperature of the surface device structure (semiconductor layer 10 and conductive layer 50) that rises by laser irradiation is, for example, above 50°C and below 1000°C. The temperature can be, for example, below 100°C.

[0054] In the embodiment, the power of the laser 80L is, for example, 1.0 J / cm 2 Above and 3.0J / cm 2 The following steps can suppress damage to the surface device structure (semiconductor layer 10 and conductive layer 50 ) and obtain good ohmic contact.

[0055] (Second Embodiment)

[0056] Fig. 9 This is a flowchart illustrating a method for manufacturing a semiconductor device according to the second embodiment.

[0057] Figure 10 to Figure 14 It is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to the second embodiment.

[0058] like Fig. 9 As shown, in the second embodiment, after the injection (step S210), the first metal layer 61 is formed (step S220). Thereafter, the laser 80L is irradiated (step S230). In addition to the order of the steps, the configuration described in the first embodiment can be applied to the second embodiment.

[0059] For example, Fig.10 As shown, for example, a structure 18 is prepared (step S105). Fig.10 As shown, the structure 18 includes a substrate 15. The substrate 15 includes SiC and includes a first surface 15a.

[0060] like Fig.10 As shown, the metal element 85 for implantation is implanted into the first surface 15a of the structure 18 (step S210). The metal element 85 for implantation includes, for example, at least one selected from Ti, Co, Ni, Mo, Ta, W, and Pt.

[0061] like Fig.11 As shown, a mixed region 15M is formed near the first surface 15a by implanting the metal element 85. The mixed region 15M is a region including the first surface 15a. The mixed region 15M contains Si, C, and the metal element 85 for implantation.

[0062] like Fig.12 As shown, after the implantation, a first metal layer 61 containing a first metal element is formed on the first surface 15a (step S220). Fig.13 As shown, the first surface 15 a is irradiated with laser light 80L via the first metal layer 61 (step S230 ).

[0063] In the second embodiment, before forming the first metal layer 61, the mixed region 15M is formed by injecting the metal element 85. By injecting the metal element 85 with low energy, the mixed region 15M can be formed efficiently. By irradiating the mixed region 15M including the metal element 85 and the first metal layer 61 including the first metal element with the laser 80L, the silicide layer 61S can be efficiently formed. At least a portion of the silicide layer 61S can be formed by at least a portion of the first metal layer 61. A portion of the silicide layer 61S can be formed by at least a portion of the mixed region 15M. In this way, the irradiation of the laser 80L (step S230) can include forming at least a portion of the silicide layer 61S by the first metal layer 61.

[0064] For example, consider a first reference example in which the first metal layer 61 is formed after Ar ions are injected, and then laser irradiation is performed. In the first reference example, an amorphous region is formed by the injection of Ar ions, etc. Thus, silicide can be formed by a low-power laser 80L. However, in the first reference example, a mixed region 15M is not formed. In the first reference example, in the silicide reaction, metal elements are supplied only from the first metal layer 61 formed on the surface. The reaction region is only near the first metal layer 61. Therefore, for example, there is a limit to the reduction of resistance.

[0065] In contrast, in the embodiment, the mixed region 15M is formed by injecting the metal element 85. Thereafter, the first metal layer 61 is formed, and then the laser 80L is irradiated. The laser 80L is irradiated to the mixed region 15M and the first metal layer 61 to form the silicide layer 61S. The mixed region 15M functions as a transition region, for example. When the silicide layer 61S is formed, stress and the like are relaxed. For example, good film quality can be maintained, and the silicide layer 61S can be formed efficiently. For example, a good morphology can be obtained. For example, a surface with good flatness can be obtained.

[0066] like Fig. 9 as well as Fig.14 As shown, the first conductive layer 51 may be formed on the silicide layer 61S after the irradiation with the laser light 80L (step S230 ).

[0067] In the second embodiment, the first metal element also includes at least one selected from Ti, Co, Ni, Mo, Ta, W and Pt. In the second embodiment, the thickness of the first metal layer 61 can be greater than 10 nm and less than 500 nm. In the second embodiment, the structure 18 can further include a semiconductor layer 10 containing SiC. In the second embodiment, the structure 18 can include a conductive layer 50 and an insulating member 40.

[0068] In the first and second embodiments, after laser irradiation or after formation of the first conductive layer 51, the structural body 18 may be separated from the supporting member 60. Thus, a semiconductor device is obtained.

[0069] (Third Embodiment)

[0070] The third embodiment relates to a semiconductor device.

[0071] Fig.15 is a schematic cross-sectional view illustrating a semiconductor device according to a third embodiment.

[0072] like Fig.15 As shown, the semiconductor device 110 of the embodiment includes a first conductive layer 51, a semiconductor layer 10, a substrate 15, a silicide layer 61S, and a mixed region 15M. The semiconductor layer 10 includes SiC. The substrate 15 includes SiC. The substrate 15 is provided between the first conductive layer 51 and the semiconductor layer 10. The silicide layer 61S is provided between the first conductive layer 51 and the substrate 15. The silicide layer 61S includes a first metal element and silicon. The mixed region 15M is provided between the silicide layer 61S and the substrate 15. The mixed region 15M includes a first metal element, silicon, and carbon.

[0073] The first metal element includes at least one selected from Ti, Co, Ni, Mo, Ta, W, and Pt. Good ohmic contact is obtained between the first conductive layer 51 and the substrate 15. Low resistance can be obtained. For example, low on-resistance can be obtained.

[0074] like Fig.15 As shown, in this example, the semiconductor device 110 includes a second conductive layer 52 and a third conductive layer 53. The semiconductor layer 10 includes a first semiconductor region 11, a second semiconductor region 12, a third semiconductor region 13, and a fourth semiconductor region 14. A first direction D1 from the first conductive layer 51 to the second conductive layer 52 is set as the Z-axis direction. A direction perpendicular to the Z-axis direction is set as the X-axis direction. A direction perpendicular to the Z-axis direction and the X-axis direction is set as the Y-axis direction.

[0075] The first semiconductor region 11 is of the first conductivity type (e.g., n-type). The first semiconductor region 11 includes a first partial region 11a, a second partial region 11b, and a third partial region 11c. A second direction D2 from the first partial region 11a to the second partial region 11b intersects the first direction D1. The second direction D2 may be the X-axis direction. The third partial region 11c is disposed between the first partial region 11a and the third conductive layer 53 in the first direction D1.

[0076] The second semiconductor region 12 is of the second conductivity type (e.g., p-type). The third semiconductor region 13 is of the first conductivity type. The fourth semiconductor region 14 is of the second conductivity type. The first conductivity type impurity concentration in the third semiconductor region 13 is higher than the first conductivity type impurity concentration in the first semiconductor region 11. The second conductivity type impurity concentration in the fourth semiconductor region 14 is higher than the second conductivity type impurity concentration in the second semiconductor region 12.

[0077] A portion 12p of the second semiconductor region 12 is located between the second partial region 11b and the third semiconductor region 13 in the first direction D1. Another portion 12q of the second semiconductor region 12 is located between the third partial region 11c and the fourth semiconductor region 14 in the second direction D2. The third semiconductor region 13 is located between another portion 12q of the second semiconductor region 12 and the fourth semiconductor region 14 in the second direction D2.

[0078] The second conductive layer 52 is electrically connected to the third semiconductor region 13 and the fourth semiconductor region 14. The insulating component 40 may include a first insulating region 41 and a second insulating region 42. At least a portion of the first insulating region 41 is disposed between the third partial region 11c and the third conductive layer 53. The second conductive layer 52 is disposed between the semiconductor layer 10 and the second insulating region 42. The third conductive layer 53 may extend along a third direction D3 intersecting a plane including the first direction D1 and the second direction D2. The third direction D3 may be, for example, the Y-axis direction.

[0079] The current flowing between the first conductive layer 51 and the second conductive layer 52 can be controlled by the potential of the third conductive layer 53. The semiconductor device 110 is, for example, a transistor. The first conductive layer 51 can be, for example, a drain electrode. The second conductive layer 52 can be a source electrode. The third conductive layer 53 can be a gate electrode.

[0080] The semiconductor device 110 of the embodiment may be, for example, a diode. The first conductive layer 51 may be any electrode layer. In the semiconductor device 110 of the embodiment, a good ohmic contact can be obtained. A semiconductor device with improved characteristics can be provided. For example, low resistance can be obtained. For example, high flatness can be obtained. For example, high flatness and low resistance can be obtained.

[0081] In an embodiment, for example, the substrate 15 may include at least one selected from 4H—SiC, 6H—SiC, and 3C—SiC.

[0082] For example, the first conductivity type impurity includes at least one selected from N, P, and As. For example, the second conductivity type impurity includes at least one selected from B, Al, and Ga.

[0083] In the embodiment, information on the length and thickness is obtained by electron microscope observation, etc. Information on the composition of the material is obtained by SIMS (Secondary Ion Mass Spectrometry) or EDX (Energy dispersive X-ray spectroscopy), etc.

[0084] The implementation method may include the following technical solutions.

[0085] (Technical Solution 1)

[0086] A method for manufacturing a semiconductor device, comprising the following steps:

[0087] forming a first metal layer including a first metal element on the first surface of a structure including a substrate including SiC and including a first surface;

[0088] injecting a first element including at least one selected from the group consisting of He, Ne, Ar, Kr, Xe, Rn, Si, N, P, As, B, Al, and Ga into the first surface through the first metal layer;

[0089] After the implantation, the first surface is irradiated with laser light through the first metal layer.

[0090] (Technical Solution 2)

[0091] The method for manufacturing a semiconductor device according to claim 1, wherein the implanting includes moving a portion of the first metal element to a region of the substrate including the first surface.

[0092] (Technical Solution 3)

[0093] The method for manufacturing a semiconductor device according to technical solution 1, wherein, by the implantation, a mixed region is formed in a region of the substrate including the first surface,

[0094] The mixed region includes Si, C and the first metal element.

[0095] (Technical Solution 4)

[0096] The method for manufacturing a semiconductor device according to Technical Solution 2 or 3, wherein the first metal element includes at least one selected from Ti, Co, Ni, Mo, Ta, W and Pt.

[0097] (Technical Solution 5)

[0098] The method for manufacturing a semiconductor device according to any one of claims 2 to 4, wherein the first element includes at least one selected from the group consisting of Ar, B, P, and As.

[0099] (Technical Solution 6)

[0100] The method for manufacturing a semiconductor device according to any one of technical solutions 2 to 4, wherein the first element includes Si.

[0101] (Technical Solution 7)

[0102] The method for manufacturing a semiconductor device according to any one of technical solutions 2 to 6, wherein the irradiating includes forming a silicide layer from the first metal layer.

[0103] (Technical Solution 8)

[0104] The method for manufacturing a semiconductor device according to Technical Solution 7, wherein, after the irradiation, a first conductive layer is formed on the silicide layer.

[0105] (Technical Solution 9)

[0106] The method for manufacturing a semiconductor device according to any one of technical solutions 1 to 8, wherein the thickness of the first metal layer is greater than or equal to 10 nm and less than or equal to 100 nm.

[0107] (Technical Solution 10)

[0108] The method for manufacturing a semiconductor device according to any one of technical solutions 1 to 9, wherein a second metal layer including a second metal element is formed on the first metal layer between the implantation and the irradiation.

[0109] (Technical Solution 11)

[0110] A method for manufacturing a semiconductor device according to Technical Solution 10, wherein the second metal element is the same as the first metal element.

[0111] (Technical Solution 12)

[0112] The method for manufacturing a semiconductor device according to any one of technical solutions 1 to 11, wherein the structure further includes a semiconductor layer containing SiC,

[0113] The substrate further comprises a second surface,

[0114] The second surface is located between the first surface and the semiconductor layer.

[0115] (Technical Solution 13)

[0116] The method for manufacturing a semiconductor device according to claim 12, wherein the temperature of the semiconductor layer increased by the irradiation is 100° C. or less.

[0117] (Technical Solution 14)

[0118] A method for manufacturing a semiconductor device, comprising the following steps:

[0119] implanting a metal element for implantation into the first surface of a structure including a substrate containing SiC;

[0120] After the implantation, forming a first metal layer including a first metal element on the first surface;

[0121] The first surface is irradiated with laser light through the first metal layer.

[0122] (Technical Solution 15)

[0123] The method for manufacturing a semiconductor device according to technical solution 14, wherein the implantation includes forming a mixed region in a portion of the substrate,

[0124] The mixed region includes the first surface,

[0125] The mixed region contains Si, C, and the metal element for the implantation.

[0126] (Technical Solution 16)

[0127] A method for manufacturing a semiconductor device according to technical solution 14 or 15, wherein the metal element used for the injection includes at least one selected from Ti, Co, Ni, Mo, Ta, W and Pt.

[0128] (Technical Solution 17)

[0129] The method for manufacturing a semiconductor device according to any one of technical solutions 14 to 16, wherein the first metal element includes at least one selected from Ti, Co, Ni, Mo, Ta, W and Pt.

[0130] (Technical Solution 18)

[0131] The method for manufacturing a semiconductor device according to any one of Technical Solutions 14 to 17, wherein the irradiation includes forming a silicide layer from the first metal layer.

[0132] (Technical Solution 19)

[0133] The method for manufacturing a semiconductor device according to any one of technical solutions 1 to 18 further comprises preparing the structure,

[0134] The preparation of the structure includes reducing the thickness of a base body serving as the substrate.

[0135] (Technical Solution 20)

[0136] A semiconductor device comprising:

[0137] a first conductive layer;

[0138] a semiconductor layer comprising SiC;

[0139] a substrate disposed between the first conductive layer and the semiconductor layer and comprising SiC;

[0140] a silicide layer disposed between the first conductive layer and the substrate and comprising a first metal element and silicon; and

[0141] The mixed region is disposed between the silicide layer and the substrate and includes the first metal element, silicon and carbon.

[0142] According to the embodiment, it is possible to provide a method for manufacturing a semiconductor device capable of improving characteristics.

[0143] The embodiments of the present invention are described above with reference to specific examples. However, the present invention is not limited to these specific examples. For example, as long as a person skilled in the art can implement the present invention in the same manner and obtain the same effect by appropriately selecting from the known range, the specific configuration of each element such as a substrate, a semiconductor layer, and a silicide layer included in a semiconductor device or a structure is included in the scope of the present invention.

[0144] Furthermore, embodiments in which two or more elements of the specific examples are combined within a technically possible range are also included in the scope of the present invention as long as they include the gist of the present invention.

[0145] Furthermore, all semiconductor device manufacturing methods that can be implemented by those skilled in the art with appropriate design changes based on the semiconductor device manufacturing method described above as an embodiment of the present invention also belong to the scope of the present invention as long as they include the gist of the present invention.

[0146] Furthermore, within the scope of the concept of the present invention, a person skilled in the art can conceive of various changes and modifications, and such changes and modifications also belong to the scope of the present invention.

[0147] Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the subject matter of the invention. These embodiments or their variations are included in the scope or subject matter of the invention, and are included in the invention described in the claims and their equivalents.

[0148] Description of Reference Numerals

[0149] 10: semiconductor layer; 11~14: first semiconductor region~fourth semiconductor region; 11a~11c: first partial region~third partial region; 12p: one part; 12q: another part; 15: substrate; 15M: mixed region; 15a, 15b: first surface, second surface; 18: structure; 40: insulating component; 41, 42: first insulating region, second insulating region; 50: conductive layer; 51~53: first conductive layer~third conductive layer; 60: supporting component; 61, 62: first metal layer, second metal layer; 61S: silicide layer; 80L: laser; 81: first element; 85: metal element; 110: semiconductor device; D1~D3: first direction~third direction.

Claims

1. A method for manufacturing a semiconductor device, comprising the following steps: forming a first metal layer including a first metal element on the first surface of a structure including a substrate including SiC and including a first surface; injecting a first element including at least one selected from the group consisting of He, Ne, Ar, Kr, Xe, Rn, Si, N, P, As, B, Al, and Ga into the first surface through the first metal layer; After the implantation, the first surface is irradiated with laser light through the first metal layer.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The implanting includes moving a portion of the first metal element to a region of the substrate including the first surface.

3. The method for manufacturing a semiconductor device according to claim 1, wherein: By the implantation, a mixed region is formed in a region of the substrate including the first surface, The mixed region includes Si, C and the first metal element.

4. The method for manufacturing a semiconductor device according to claim 2, wherein: The first metal element includes at least one selected from the group consisting of Ti, Co, Ni, Mo, Ta, W, and Pt.

5. The method for manufacturing a semiconductor device according to claim 2, wherein: The first element includes at least one selected from the group consisting of Ar, B, P, and As.

6. The method for manufacturing a semiconductor device according to claim 2, wherein: The first element includes Si.

7. The method for manufacturing a semiconductor device according to any one of claims 1 to 6, wherein: Between the implanting and the irradiating, a second metal layer including a second metal element is formed on the first metal layer.

8. A method for manufacturing a semiconductor device, comprising the following steps: implanting a metal element for implantation into the first surface of a structure including a substrate containing SiC; After the implantation, forming a first metal layer including a first metal element on the first surface; The first surface is irradiated with laser light through the first metal layer.

9. The method for manufacturing a semiconductor device according to claim 8, wherein: The implanting comprises forming a mixed region in a portion of the substrate, The mixed region includes the first surface, The mixed region contains Si, C, and the metal element for the implantation.

10. The method for manufacturing a semiconductor device according to claim 8, wherein: The metal element for the implantation includes at least one selected from the group consisting of Ti, Co, Ni, Mo, Ta, W, and Pt.

11. The method for manufacturing a semiconductor device according to any one of claims 8 to 10, wherein: The first metal element includes at least one selected from the group consisting of Ti, Co, Ni, Mo, Ta, W, and Pt.

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