Semiconductor device

Abstract

The purpose of the present disclosure is to provide a technique that, in a semiconductor device provided with a plurality of semiconductor elements, increases the degree of freedom in layout, performs temperature detection of the semiconductor elements taking into account the heat generation distribution in the semiconductor device, and can maximize the effective area of the semiconductor elements. The semiconductor device includes a base plate, a plurality of semiconductor elements, and a plurality of wiring elements disposed on the base plate so as to be adjacent to each of the plurality of semiconductor elements. A diode for detecting the temperature of adjacent semiconductor elements among the plurality of semiconductor elements is disposed in each wiring element. The lead pad of each wiring element is disposed so as to face the lead pad of an adjacent semiconductor element. The diode of each wiring element is disposed on the side of an adjacent semiconductor element. The lead pad of each semiconductor element and the lead pad of each wiring element adjacent to each semiconductor element are connected via a lead.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device. Background Art

[0002] In a semiconductor device mounted on a power converter such as an inverter, a structure is adopted in which a plurality of semiconductor elements are connected in parallel and driven in order to conduct a large current. In a semiconductor device having a plurality of semiconductor elements, as a method for maximizing the effective area of ​​the semiconductor elements, for example, Patent Document 1 discloses a structure in which wiring elements are provided separately from the semiconductor elements. Prior art literature Patent Literature

[0003] Patent Document 1: International Publication No. 2020 / 110170 Summary of the invention Technical problem to be solved by the invention

[0004] In the technology described in Patent Document 1, a wiring element is arranged in the center of a base plate, and a plurality of semiconductor elements are arranged so as to surround the wiring element, thereby making the lead lengths of the semiconductor elements and the wiring element uniform. Therefore, since the arrangement of the semiconductor elements and the wiring element and the detour of the external electrodes are restricted, there is a problem of low layout freedom.

[0005] In addition, in order to monitor overheating and overcurrent conditions in semiconductor devices, it is necessary to provide temperature detection elements for detecting the temperature of the semiconductor elements for multiple semiconductor elements, so it is difficult to maximize the effective area of ​​all semiconductor elements. In the case where a temperature detection element is provided for any of the multiple semiconductor elements, only the temperature of the semiconductor element provided with the temperature detection element can be detected, so it is impossible to select the semiconductor element for temperature detection in consideration of the heat generation distribution in the semiconductor device.

[0006] Therefore, an object of the present disclosure is to provide a technology that can improve the layout freedom in a semiconductor device including a plurality of semiconductor elements, detect the temperature of the semiconductor elements in consideration of the heat generation distribution in the semiconductor device, and maximize the effective area of ​​the semiconductor elements. Technical solutions to technical problems

[0007] The semiconductor device involved in the present disclosure includes: a base plate; a plurality of semiconductor elements, which are mounted on the base plate and each have a lead pad; and a plurality of wiring elements, which are arranged on the base plate in a manner adjacent to the plurality of semiconductor elements and each have a lead pad, wherein a temperature sensor for detecting the temperature of the adjacent semiconductor elements among the plurality of semiconductor elements is arranged in each of the wiring elements, the lead pad of each of the wiring elements is arranged to be opposite to the lead pad of the adjacent semiconductor element, the temperature sensor of each of the wiring elements is arranged on the side of the adjacent semiconductor element, and the lead pad of each of the semiconductor elements and the lead pad of each of the wiring elements adjacent to each of the semiconductor elements are connected via leads. Effects of the Invention

[0008] According to the present disclosure, a plurality of wiring elements are arranged adjacent to a plurality of semiconductor elements, respectively, and the lead pads of each wiring element are arranged opposite to the lead pads of the adjacent semiconductor element, so that the leads between the semiconductor element and the wiring element do not interfere with each other, and wiring can be performed with a certain lead length or less. As a result, it is not necessary to arrange the semiconductor element in a manner surrounding the wiring element, and the layout freedom of the semiconductor device is improved compared with the past.

[0009] Furthermore, since a temperature sensor corresponding to each semiconductor element is disposed in each wiring element, it is possible to select a semiconductor element for temperature detection in consideration of heat generation distribution in the semiconductor device.

[0010] In addition, since the temperature sensor of each wiring element is arranged on the side of the adjacent semiconductor element, the thermal coupling with the semiconductor element is good, and the temperature detection accuracy of the semiconductor element is good. Therefore, the temperature sensor can be reduced from the semiconductor element, so that the effective area of ​​the semiconductor element can be maximized.

[0011] The objects, features, aspects and advantages of the present disclosure will become more apparent from the following detailed description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 This is a top view of the semiconductor device according to the first embodiment. Figure 2 This is a cross-sectional view of the semiconductor device according to the first embodiment. Figure 3 This is a plan view of a wiring element included in the semiconductor device according to the first embodiment. Figure 4 yes Figure 3 AA line section view. Figure 5 yes Figure 3 BB line cross-sectional view. Figure 6 This is an equivalent circuit diagram of the semiconductor device according to the first embodiment. Figure 7 It is a top view of the semiconductor device involved in Embodiment 2. Figure 8 It is a top view of a wiring element included in the semiconductor device according to the second embodiment. Fig. 9 This is an equivalent circuit diagram of the semiconductor device according to the second embodiment. Fig.10 It is a top view of the semiconductor device involved in Embodiment 3. Fig.11 It is a top view of a wiring element included in the semiconductor device according to the third embodiment. Fig.12 yes Fig.11 CC line section view. Fig.13 This is an equivalent circuit diagram of a semiconductor device and a control substrate when a high withstand voltage diode is provided on the control substrate. Fig.14 This is an equivalent circuit diagram of a semiconductor device and a control substrate when a high withstand voltage diode is provided in the semiconductor device according to the third embodiment. Fig.15 It is a top view of a wiring element included in the semiconductor device according to the fourth embodiment. Fig.16 This is an equivalent circuit diagram of a wiring element included in the semiconductor device according to the fourth embodiment. Fig.17 It is a top view of the semiconductor device involved in Embodiment 5. Fig.18 This is a cross-sectional view of a semiconductor device according to a fifth embodiment. Fig.19 It is a top view of the semiconductor device involved in Embodiment 6. DETAILED DESCRIPTION

[0013] <Implementation method 1> <Overall Structure of Semiconductor Device> Embodiment 1 will be described below using the drawings. Figure 1 1 is a plan view of the semiconductor device 100 according to the first embodiment. Figure 2 It is a cross-sectional view of the semiconductor device 100 according to the first embodiment. Figure 3 It is a plan view of the wiring element 10 included in the semiconductor device 100 according to the first embodiment. Figure 4 yes Figure 3AA line section view. Figure 5 yes Figure 3 BB line cross-sectional view. Figure 6 is an equivalent circuit diagram of the semiconductor device 100 according to the first embodiment. Figure 2 In the figure, the extending directions of the external electrodes 20 and the control terminals 22 are changed to make the connection relationship between the components easier to see.

[0014] like Figure 1 and Figure 2 As shown, the semiconductor device 100 includes a base plate 1 , a plurality of (eg, three) semiconductor elements 2 , a plurality of (eg, three) wiring elements 10 , an external electrode 20 , and four control terminals 22 .

[0015] The bottom plate 1 is mainly made of metal such as Cu and Al. The bottom plate 1 is formed in a rectangular shape in a plan view and functions as a drain terminal. Hereinafter, the bottom plate 1 is also referred to as a drain terminal 1.

[0016] A plurality of semiconductor elements 2 are mounted on a base plate 1 by bonding the back surface with a conductive bonding material 5 such as solder, Ag paste or Cu paste. Each semiconductor element 2 is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The surface electrode of each semiconductor element 2 is divided into two areas: an area where a main terminal electrode 3 is arranged for the main current to flow, and an area where a lead pad 4 is arranged for transmitting a driving voltage, temperature and overcurrent signal of each semiconductor element 2. The area where the lead pad 4 is arranged is Figure 1 The area where the main terminal electrode 3 is arranged is located on the right side (the wiring element 10 side). Figure 1 Center is on the left.

[0017] The main terminal electrode 3 is bonded to the external electrode 20 via the conductive bonding material 5, and the lead pad 4 is connected to the lead pad 12 of the adjacent wiring element 10 via the lead 21. In addition, each semiconductor element 2 may be a semiconductor switching element such as an IGBT (Insulated Gate Bipolar Transistor) or a reverse conducting IGBT other than a MOSFET.

[0018] A plurality of wiring elements 10 are arranged on the base plate 1 so as to be adjacent to the plurality of semiconductor elements 2. The plurality of wiring elements 10 are arranged on the base plate 1 by bonding the back surfaces via the conductive bonding material 5. A resistor 14 for suppressing the oscillation action of the adjacent semiconductor element 2 among the plurality of semiconductor elements 2 and a diode 13 as a temperature sensor for detecting the temperature of the adjacent semiconductor element 2 are arranged in each wiring element 10. The diode 13 of each wiring element 10 is arranged on the adjacent semiconductor element 2 side.

[0019] The external electrode 20 is made of Cu, and is disposed on the main terminal electrodes 3 of the plurality of semiconductor elements 2 to connect the plurality of semiconductor elements 2. The main terminal electrode 3 functions as a source terminal, and the external electrode 20 disposed on the main terminal electrode 3 also functions as a source terminal. Hereinafter, the external electrode 20 is also referred to as the source terminal 20.

[0020] like Figure 1 and Figure 6 As shown, the plurality of semiconductor elements 2 are connected in parallel, and the plurality of wiring elements 10 are connected to the plurality of semiconductor elements 2 in a state where they are adjacent to each other.

[0021] The four control terminals 22 are terminals for inputting and outputting signals related to the control of each semiconductor element 2. The four control terminals 22 are a current sensing terminal 22a, a Kelvin source terminal 22b, a gate terminal 22c, and a temperature sensing anode terminal 22d, and are connected to each semiconductor element 2 through each wiring element 10. In the first embodiment, a current sensing method is adopted as a short-circuit detection method for detecting a short-circuit state of the semiconductor element 2.

[0022] <Structure of Wiring Components> Next, the structure of each wiring element 10 will be described. Figure 3 , Figure 4 and Figure 5 As shown, each wiring element 10 uses a Si substrate 11 as a base material, and a back electrode 15 composed of Al, Ti, Ni or Au is formed on the back of the Si substrate 11. The back of each wiring element 10 is bonded to the base plate 1 via a conductive bonding material 5, similarly to the semiconductor element 2.

[0023] A thermal oxide film 16 is formed on the surface of the Si substrate 11, and passive elements such as a resistor 14 composed of polysilicon (Poly-Si) 18 and a diode 13 composed of polysilicon (P type) 18a and polysilicon (N type) 18b are formed on the thermal oxide film 16. In order to insulate the signal terminals of the resistor 14 and the diode 13 on the surface side of the Si substrate 11, an insulating interlayer film 17 is formed on the thermal oxide film 16 and the polysilicon 18, 18a, and 18b. Furthermore, a lead pad 12 as a surface electrode composed of Al is formed on the insulating interlayer film 17.

[0024] A contact portion 17a for electrically connecting the resistor 14 and the diode 13 to the lead pad 12 as a surface electrode is provided in a portion of the insulating interlayer film 17. Figure 1 As shown in FIG. 1 , the lead pad 4 of the semiconductor element 2 is connected to the control terminal 22 via the wiring element 10, and the wiring element 10 has a relay wiring function. Figure 1 , Figure 4 and Figure 5 As shown in FIG. 1 , lead pads 12 for connecting the lead pads 4 of the semiconductor element 2 and the control terminal 22 by the lead wires 21 are provided on the surface of the wiring element 10. The lead pads 12 of each wiring element 10 are arranged to face the lead pads 4 of the adjacent semiconductor element 2 and are also arranged at other locations. The lead pads 4 of each semiconductor element 2 and the lead pads 12 of each wiring element 10 adjacent to each semiconductor element 2 are connected via the lead wires 21.

[0025] In order to ensure insulation, the interior of the semiconductor device 100 is sealed with a sealing material (not shown) made of epoxy resin or the like.

[0026] <Effect> Next, the effects of the semiconductor device 100 according to Embodiment 1 will be described in comparison with the technology described in Patent Document 1 (International Publication No. 2020 / 110170).

[0027] In the technology described in Patent Document 1, a wiring element is arranged in the center of a base plate and a plurality of semiconductor elements are arranged so as to surround the wiring element, thereby making the lead lengths of the semiconductor elements and the wiring element uniform. As a result, there are restrictions on the arrangement of the semiconductor elements and the wiring element and the detour of the external electrodes, so there is a problem of low layout freedom.

[0028] In contrast, the semiconductor device 100 according to the first embodiment includes: a base plate 1; a plurality of semiconductor elements 2 mounted on the base plate 1 and each having a lead pad 4; and a plurality of wiring elements 10 arranged on the substrate 1 so as to be adjacent to the plurality of semiconductor elements 2 and each having a lead pad 12. A diode 13 is arranged in each wiring element 10 as a temperature sensor for detecting the temperature of the adjacent semiconductor element 2 among the plurality of semiconductor elements 2. The lead pad 12 of each wiring element 10 is arranged to be opposite to the lead pad 4 of the adjacent semiconductor element 2. The diode 13 as the temperature sensor of each wiring element 10 is arranged on the side of the adjacent semiconductor element 2. The lead pad 4 of each semiconductor element 2 and the lead pad 12 of each wiring element 10 adjacent to each semiconductor element 2 are connected via a lead 21.

[0029] Therefore, the plurality of wiring elements 10 are arranged adjacent to the plurality of semiconductor elements 2, respectively, and the lead pads 12 of each wiring element 10 are arranged opposite to the lead pads 4 of the adjacent semiconductor element 2, so that the leads 21 between the semiconductor element 2 and the wiring element 10 do not interfere with each other, and wiring can be performed with a certain lead length or less. As a result, it is not necessary to arrange the semiconductor element 2 so as to surround the wiring element 10, and the layout freedom of the semiconductor device 100 is improved compared with the past.

[0030] Furthermore, since the diode 13 as the temperature sensor corresponding to each semiconductor element 2 is arranged in each wiring element 10 , the semiconductor element 2 for temperature detection can be selected in consideration of the heat generation distribution in the semiconductor device 100 .

[0031] In addition, since the diode 13 as the temperature sensor of each wiring element 10 is arranged on the side of the adjacent semiconductor element 2, the thermal coupling with the semiconductor element 2 is good, and the temperature detection accuracy of the semiconductor element 2 is good. As a result, the temperature sensor can be reduced from the semiconductor element 2, so that the effective area of ​​the semiconductor element 2 can be maximized.

[0032] In addition, when a plurality of semiconductor elements 2 are driven in parallel, a transient surge voltage and current may be generated due to the variation in characteristics of the semiconductor elements 2 and the floating inductance of the main terminals and the lead 21 in the semiconductor device 100, which may cause malfunction and destruction of the semiconductor element 2. Generally, in order to suppress the gate oscillation of the semiconductor element 2 caused by the transient surge at the time of shutdown, a balancing resistor for the purpose of suppressing oscillation is provided on the gate wiring of the semiconductor element 2. In the present embodiment, since the resistor 14 for suppressing the oscillation of the adjacent semiconductor element 2 is also arranged in each wiring element 10, it is not necessary to provide a balancing resistor for the semiconductor element 2, and it is possible to suppress malfunction and destruction of the semiconductor device 100 at a low cost.

[0033] <Implementation method 2> Next, a semiconductor device 100A according to the second embodiment will be described. Figure 7 It is a top view of a semiconductor device 100A according to the second embodiment. Figure 8 It is a plan view of a wiring element 10A included in a semiconductor device 100A according to the second embodiment. Fig. 9 1 is an equivalent circuit diagram of a semiconductor device 100A according to Embodiment 2. In Embodiment 2, the same components as those described in Embodiment 1 are denoted by the same reference numerals and their description is omitted.

[0034] like Figure 7 , Figure 8 and Fig. 9 As shown, in the second embodiment, the short-circuit detection method for detecting the short-circuit state of the semiconductor element 2 is changed from the current sensing method to the non-saturated voltage detection method. Therefore, as the control terminal 22, instead of the current sensing terminal 22a (refer to Figure 1 ), a non-saturated voltage detection output terminal 22e is provided for taking out the non-saturated voltage (drain voltage) of each semiconductor element 2 to the outside. The non-saturated voltage detection output terminal 22e is connected to the drain terminal 1. By changing the short-circuit detection method from the current sensing method to the non-saturated voltage detection method, as shown in FIG. Figure 1 As shown in FIG. 1 , the current sensing element 4a formed in each semiconductor element 2 and the current sensing path formed in the wiring element 10 are reduced. Here, the current sensing path is from Figure 1 The current sensing element 4 a shown is formed in a portion of the wiring component 10 in a path from the lead 21 and the lead pad 12 to the current sensing terminal 22 a .

[0035] As described above, the semiconductor device 100A according to the second embodiment further includes the control terminal 22 for inputting and outputting signals related to control of each semiconductor element 2 , and the control terminal 22 includes the non-saturated voltage detection output terminal 22 e for externally extracting the drain voltage of each semiconductor element 2 .

[0036] Therefore, since the current sensing element 4 a of each semiconductor element 2 and the current sensing path of the wiring element 10 can be reduced, the cost of the semiconductor device 100A can be reduced without impairing the protection function of the semiconductor element 2 .

[0037] <Implementation method 3> Next, a semiconductor device according to Embodiment 3 will be described. Fig.10 It is a top view of a semiconductor device 100B according to the third embodiment. Fig.11It is a plan view of a wiring element 10B included in a semiconductor device 100B according to the third embodiment. Fig.12 yes Fig.11 In the third embodiment, the same components as those described in the first and second embodiments are denoted by the same reference numerals and their description is omitted.

[0038] like Fig.10 , Fig.11 and Fig.12 As shown, in the third embodiment, a high withstand voltage diode 19 is arranged in each wiring element 10B to insulate the non-saturated voltage detection output terminal 22e for extracting the drain voltage of the adjacent semiconductor element 2 to the outside. - Layer 29, N + Layer 30, P - Layer 31, P + Layer 32.

[0039] Next, the effect of arranging the high withstand voltage diode 19 in each wiring element 10B will be described in comparison with the case where the high withstand voltage diode 19 is arranged on a control substrate for controlling a semiconductor device. Fig.13 This is an equivalent circuit diagram of a semiconductor device and a control substrate when a high withstand voltage diode 19 is provided on the control substrate. Fig.14 This is an equivalent circuit diagram of the semiconductor device 100B and the control substrate when the high withstand voltage diode 19 is provided in the semiconductor device 100B according to the third embodiment.

[0040] like Fig.13 As shown, in addition to the control IC 33, the resistor 34, and the capacitor 35, a high withstand voltage diode 19 is also provided on the control substrate. On the control substrate, a high voltage wiring needs to be provided at a location connected to the non-saturated voltage detection output terminal 22e.

[0041] In contrast, Fig.14 As shown, when a high-voltage diode 19 is configured in each wiring element 10B, since the output terminal 22e for non-saturated voltage detection is electrically insulated in the semiconductor device 100B, there is no need to set up high-voltage wiring on the control substrate, and it can be foreseen that the control substrate can be miniaturized and the layout freedom can be improved.

[0042] In addition, if the charging current is set to I CHG , the value of resistor 34 is R DESAT , the forward voltage V of the high withstand voltage diode 19 F , the saturation voltage V of the semiconductor element 2 as MOSFET DS , then the over-current judgment threshold V of control IC33 DESAT Use VDESAT =I CHG ×R DESAT +V F +V DS express.

[0043] Since the MOSFET’s saturation voltage V DS It has a positive temperature characteristic that the higher the temperature, the larger the absolute value. Therefore, the higher the ambient temperature, the higher the overcurrent judgment threshold V DESAT The higher the value, the higher the control IC33 monitors the overcurrent judgment threshold V DESAT When the voltage reaches a certain level or above, the overcurrent protection is activated. However, since the monitoring range of the control IC 33 is limited, the overcurrent judgment threshold V DESAT When it is too high, it will affect the operating temperature range of the overcurrent protection circuit.

[0044] In addition, if Fig.14 As shown in FIG. 1 , a high withstand voltage diode 19 is arranged in each wiring element 10B near the semiconductor element 2 serving as a heat source. Fig.13 Compared with the case of , the temperature of the high withstand voltage diode 19 rises. The forward voltage V of the high withstand voltage diode 19 F It has a negative temperature characteristic that decreases as the temperature rises. Since it works in the direction of eliminating the saturation voltage temperature characteristic of the MOSFET, the overcurrent judgment threshold V DESAT The detection accuracy is improved.

[0045] <Implementation method 4> Next, a semiconductor device according to a fourth embodiment will be described. Fig.15 It is a plan view of a wiring element 10C included in the semiconductor device according to the fourth embodiment. Fig.16 It is an equivalent circuit diagram of a wiring element 10C included in a semiconductor device according to Embodiment 4. In Embodiment 4, the same components as those described in Embodiments 1 to 3 are denoted by the same reference numerals and their description is omitted.

[0046] In the fourth embodiment, a protection diode 24 is added to the first embodiment. Specifically, Fig.15 and Fig.16 As shown, a protection diode 24 is arranged in each wiring element 10C to protect the adjacent semiconductor element 2 from electrostatic damage. Specifically, in each wiring element 10C, a protection diode 24 is arranged between the gate terminal G and the Kelvin source terminal KS, and between the current sense terminal CS and the Kelvin source terminal KS. Here, Fig.15 and Fig.16The gate terminal G, the Kelvin source terminal KS, the current sensing terminal CS and the temperature sensing anode terminal A are connected to the Figure 1 The gate terminal 22c, the Kelvin source terminal 22b, the current sensing terminal 22a and the temperature sensing anode terminal 22d are connected.

[0047] This can suppress electrostatic destruction of the semiconductor element 2 , thereby improving the reliability and assemblability of the semiconductor device.

[0048] <Implementation method 5> Next, a semiconductor device 100D according to the fifth embodiment will be described. Fig.17 It is a top view of a semiconductor device 100D according to the fifth embodiment. Fig.18 It is a cross-sectional view of a semiconductor device 100D according to Embodiment 5. In Embodiment 5, the same components as those described in Embodiments 1 to 4 are denoted by the same reference numerals and their description is omitted.

[0049] like Fig.17 and Fig.18 As shown, in Embodiment 5, a plurality of wiring elements 10 are arranged at locations on the external electrode 20 corresponding to the respective semiconductor elements 2, so as to be adjacent to each other above the plurality of semiconductor elements 2 via the external electrode 20. The plurality of wiring elements 10 are arranged on the external electrode 20 by bonding the back surface via the conductive bonding material 5.

[0050] In each wiring element 10, a resistor 14 for suppressing the oscillation action of the semiconductor element 2 adjacent to the semiconductor element 2 below through the external electrode 20 among the plurality of semiconductor elements 2 and a diode 13 as a temperature sensor for detecting the temperature of the semiconductor element 2 adjacent to the semiconductor element 2 below through the external electrode 20 are arranged. The lead pad 12 of each wiring element 10 is arranged to face the lead pad 4 of the semiconductor element 2 adjacent to the semiconductor element 2 below through the external electrode 20, and is also arranged in a position other than the lead pad 4. The diode 13 of each wiring element 10 is arranged on the side of the semiconductor element 2 adjacent to the semiconductor element 2 below through the external electrode 20. The lead pad 4 of each semiconductor element 2 and the lead pad 12 of each wiring element 10 adjacent to each semiconductor element 2 above are connected via the lead 21.

[0051] As described above, in the semiconductor device 100D according to the fifth embodiment, as in the case of the first embodiment, the degree of freedom of layout can be improved, and the temperature detection of the semiconductor element 2 can be performed in consideration of the heat distribution in the semiconductor device 100D, and the effective area of ​​the semiconductor element 2 can be maximized. In addition, it is not necessary to provide a balancing resistor for the semiconductor element 2, and it is possible to suppress malfunction and destruction of the semiconductor device 100D at a low cost.

[0052] Furthermore, since the plurality of wiring elements 10 are arranged at locations corresponding to the respective semiconductor elements 2 on the external electrodes 20 so as to be adjacent to each other above the plurality of semiconductor elements 2 via the external electrodes 20, the area of ​​the base plate 1 can be reduced compared to the case of the first embodiment. Thus, the semiconductor device 100D can be miniaturized.

[0053] <Implementation method 6> Next, a semiconductor device 100E according to the sixth embodiment will be described. Fig.19 It is a plan view of a semiconductor device 100E according to Embodiment 6. In Embodiment 6, the same components as those described in Embodiments 1 to 5 are denoted by the same reference numerals, and description thereof is omitted.

[0054] In the fifth embodiment, a plurality of wiring elements 10 are arranged on the upper surface of the external electrode 20 arranged in the region where the main terminal electrode 3 is arranged in each semiconductor element 2 .

[0055] In contrast, Fig.19 As shown, in the sixth embodiment, the main terminal electrode 3 as the surface electrode of each semiconductor element 2 is divided into two regions 3a and 3b. A plurality of wiring elements 10 are arranged in one region 3a, and an external electrode 20 is arranged in the other region 3b.

[0056] Specifically, the plurality of wiring elements 10 are bonded to one region 3a of each semiconductor element 2 via a conductive bonding material (not shown) so as to be adjacent to each other above the plurality of semiconductor elements 2. In addition, the external electrode 20 is bonded to another region 3b of each semiconductor element 2 via a conductive bonding material (not shown).

[0057] In each wiring element 10, a resistor 14 for suppressing the oscillation action of the semiconductor element 2 adjacent to the lower side among the plurality of semiconductor elements 2 and a diode 13 as a temperature sensor for detecting the temperature of the semiconductor element 2 adjacent to the lower side are arranged. The lead pad 12 of each wiring element 10 is arranged to face the lead pad 4 of the semiconductor element 2 adjacent to the lower side, and is also arranged at a position other than the lead pad 4. The diode 13 of each wiring element 10 is arranged on the side of the semiconductor element 2 adjacent to the lower side. The lead pad 4 of each semiconductor element 2 and the lead pad 12 of each wiring element 10 adjacent to the upper side of each semiconductor element 2 are connected via a lead 21.

[0058] As described above, in the semiconductor device 100E according to the sixth embodiment, as in the case of the first embodiment, the degree of freedom of layout can be improved, and the temperature detection of the semiconductor element 2 can be performed in consideration of the heat distribution in the semiconductor device 100E, and the effective area of ​​the semiconductor element 2 can be maximized. In addition, it is not necessary to provide a balancing resistor for the semiconductor element 2, and it is possible to suppress malfunction and destruction of the semiconductor device 100E at a low cost.

[0059] In addition, since the main terminal electrode 3 of each semiconductor element 2 is divided into two areas 3a and 3b, each wiring element 10 is arranged in one area 3a, and the external electrode 20 is arranged in the other area 3b, the thermal coupling between the wiring element 10 and the semiconductor element 2 is improved compared with the case of embodiment 5, and the temperature detection accuracy of the semiconductor element 2 is improved.

[0060] <Variations of Embodiments 1 to 6> In the first to sixth embodiments, the number of the plurality of semiconductor elements 2 and the plurality of wiring elements 10 , 10A, 10B, 10C is described as three each, but the present invention is not limited thereto and the number of the plurality of semiconductor elements 2 and wiring elements 10 , 10A, 10B, 10C may be two or more and the same number.

[0061] In addition, in embodiments 1 to 6, the same number of wiring elements 10, 10A, 10B, and 10C as the semiconductor elements 2 are configured, but the number of wiring elements 10, 10A, 10B, and 10C may not be the same as the semiconductor elements 2, and more than two wiring elements 10, 10A, 10B, and 10C may be constituted by one Si substrate 11.

[0062] In the first to sixth embodiments, a capacitor made of a silicon oxide film or an insulating interlayer film may be formed in each wiring element 10, 10A, 10B, 10C. By forming a low-pass filter with the resistor 14 in the wiring element 10, 10A, 10B, 10C, the resistance of the semiconductor element 2 to switching noise is improved.

[0063] In addition, in the first to sixth embodiments, the resistance value of the resistor 14 disposed in each wiring element 10, 10A, 10B, 10C can also be adjusted by laser trimming. As a result, the deviation of the balancing resistor connected between the semiconductor elements 2 can be suppressed. In the case where the balancing resistor is configured for the gate to prevent gate oscillation during the turn-off of the parallel operation, if the difference in the value of the balancing resistor connected to each semiconductor element 2 is large, the oscillation risk becomes high, but since the deviation of the resistance value is reduced, the oscillation risk is reduced, and the malfunction of the semiconductor element 2 can be suppressed.

[0064] In addition, the protection diode 24 of the fourth embodiment may be used in the second and third embodiments, and the non-saturated voltage detection output terminal 22e of the second embodiment, the high withstand voltage diode 19 of the third embodiment, and the protection diode 24 of the fourth embodiment may be used in the fifth and sixth embodiments.

[0065] The present disclosure has been described in detail, but the above description is in all aspects illustrative and not restrictive, and it is understood that numerous modifications not shown are conceivable.

[0066] In addition, each embodiment can be freely combined, or each embodiment can be appropriately modified or omitted. Description of symbols

[0067] 1 Bottom plate 2 Semiconductor components 3 Main terminal electrodes Area 3a, 3b 4-lead pad 10, 10A, 10B, 10C wiring components 12 Lead pads 13 Diode 14 resistors 10High voltage diode 20 External electrodes 21 leads 22 control terminals 22e Output terminal for non-saturation voltage detection 24 protection diodes.

Claims

1. A semiconductor device, characterized in that: include: Base plate; A plurality of semiconductor elements, each of which is mounted on the base plate and has a lead pad; as well as a plurality of wiring elements, each of which is arranged on the base plate so as to be adjacent to the plurality of semiconductor elements and each of which has a lead pad; A temperature sensor for detecting the temperature of the adjacent semiconductor elements among the plurality of semiconductor elements is arranged in each of the wiring elements. The lead pad of each of the wiring elements is arranged to face the lead pad of the adjacent semiconductor element. The temperature sensor of each of the wiring elements is arranged on the adjacent semiconductor element side. The lead pads of each of the semiconductor elements and the lead pads of each of the wiring elements adjacent to the semiconductor elements are connected via wires.

2. The semiconductor device according to claim 1, wherein A resistor for suppressing an oscillation operation of the adjacent semiconductor element is further arranged in each of the wiring elements.

3. The semiconductor device according to claim 1 or 2, wherein: It also includes a control terminal, which is used to input and output signals related to the control of each of the semiconductor elements. The control terminal includes a terminal for extracting the drain voltage of each of the semiconductor elements to the outside.

4. The semiconductor device according to claim 3, wherein: A high withstand voltage diode is disposed in each of the wiring elements to insulate the terminal for extracting the drain voltage of the adjacent semiconductor element to the outside.

5. The semiconductor device according to any one of claims 1 to 4, wherein: A protection diode is disposed in each of the wiring elements to protect the adjacent semiconductor element from electrostatic damage.

6. A semiconductor device, characterized in that: include: Base plate; A plurality of semiconductor elements, each of which is mounted on the base plate and has a lead pad; An external electrode, which is disposed on the plurality of semiconductor elements and connects the plurality of semiconductor elements; as well as a plurality of wiring elements, each of which is arranged at a position corresponding to each of the semiconductor elements on the external electrode in a manner adjacent to each of the semiconductor elements above the external electrode, and each of which has a lead pad, A temperature sensor is disposed in each of the wiring elements to detect the temperature of the semiconductor element adjacent to the semiconductor element below the semiconductor elements with the external electrode interposed therebetween. The lead pads of each of the wiring elements are arranged to face the lead pads of the semiconductor element that is adjacent below with the external electrode interposed therebetween. The temperature sensor of each of the wiring elements is arranged on the semiconductor element side adjacent to the semiconductor element below with the external electrode interposed therebetween. The lead pads of each of the semiconductor elements and the lead pads of each of the wiring elements adjacent to each of the semiconductor elements are connected via wires.

7. The semiconductor device according to claim 6, wherein: A resistor is further arranged in each of the wiring elements to suppress an oscillation operation of the semiconductor element adjacent thereto below via the external electrode.

8. A semiconductor device, characterized in that: include: Base plate; A plurality of semiconductor elements, each of which is mounted on the base plate and has a lead pad and a surface electrode divided into two areas; An external electrode, which is disposed on the plurality of semiconductor elements and connects the plurality of semiconductor elements; as well as a plurality of wiring elements, each of which is arranged in a region of each of the semiconductor elements so as to be adjacent to each other above the plurality of semiconductor elements and each of which has a lead pad; The external electrode is connected to another region of each semiconductor element. A temperature sensor for detecting the temperature of the semiconductor element adjacent to the semiconductor element below among the plurality of semiconductor elements is arranged in each of the wiring elements. The lead pads of each of the wiring elements are arranged to face the lead pads of the semiconductor element adjacent thereto below. The temperature sensor of each of the wiring elements is arranged on the side of the semiconductor element adjacent thereto below. The lead pads of each of the semiconductor elements and the lead pads of each of the wiring elements adjacent to each of the semiconductor elements are connected via wires.

9. The semiconductor device according to claim 8, wherein: A resistor for suppressing an oscillation operation of the semiconductor element adjacent thereto is further arranged in each of the wiring elements.

10. The semiconductor device according to any one of claims 1 to 9, wherein: A capacitor composed of a silicon oxide film or an insulating interlayer film is formed in each of the wiring elements.

11. The semiconductor device according to any one of claims 2, 7 and 9, wherein: The resistor disposed in each of the wiring elements can have its resistance value adjusted by laser trimming.

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